Imaging element and electronic apparatus

Abstract

The light detection device includes a first substrate, a second substrate, a third substrate, a first coupling portion, and a second coupling portion. The first substrate includes a plurality of photoelectric converters. The second substrate includes a first signal processor configured to perform first signal processing, and the second substrate is stacked on the first substrate. The third substrate includes a second signal processor configured to perform second signal processing, and the third substrate is stacked on the second substrate. The first coupling portion includes a plurality of first electrodes, each first electrode coupling a circuit of the second substrate and a circuit of the third substrate. The second coupling portion includes a plurality of second electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. In a plan view, an area of the first coupling portion is different from an area of the second coupling portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Japanese Priority Patent Application JP 2022-094466 filed on Jun. 10, 2022, and Japanese Priority Patent Application JP 2022-202458 filed on Dec. 19, 2022, the entire contents of each of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an imaging element and an electronic device. Background Art

[0004] Some conventional imaging elements include a pixel array section, an AD converter, and a memory section.

[0005] [Citation List]

[0006] [Patent Document]

[0007] [Patent Document 1]

[0008] International Publication No. WO2014 / 007004 Summary of the invention

[0009] [Technical issues]

[0010] In an imaging element, it is desirable to suppress an increase in chip area. It is desirable to provide an imaging element capable of suppressing an increase in chip area.

[0011] According to aspects of the present disclosure, a light detection device is provided, comprising: a first substrate comprising a plurality of photoelectric converters, the plurality of photoelectric converters being configured to generate charges through photoelectric conversion; a second substrate comprising a first signal processor configured to perform first signal processing to generate signals based on the charges generated by the plurality of photoelectric converters, the second substrate stacked on the first substrate, a third substrate comprising a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate, a first coupling portion comprising a plurality of first electrodes, the plurality of first electrodes coupling the circuit of the second substrate and the circuit of the third substrate; and a second coupling portion comprising a plurality of second electrodes, the plurality of second electrodes coupling the circuit of the second substrate and the circuit of the third substrate, wherein in a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion.

[0012] In some embodiments, the plurality of photoelectric converters are arranged on the first substrate in a first direction and in a second direction orthogonal to the first direction. In some embodiments, a plurality of first electrodes are arranged side by side in the first direction, and a plurality of second electrodes are arranged side by side in the first direction. In some embodiments, the length of the first engaging portion in the first direction is different from the length of the second engaging portion in the first direction. In some embodiments, at least a portion of the first signal processor is arranged between the first coupling portion and the second coupling portion in a plan view. In some embodiments, the first substrate includes a plurality of pixels, each of the plurality of pixels includes a photoelectric converter in a plurality of photoelectric converters and is configured to output an analog signal based on a charge generated by photoelectric conversion, and the second substrate includes an analog-to-digital converter configured to convert an analog signal output from the pixel into a digital signal. In some embodiments, the first signal processor is configured to perform a first signal processing to generate a first digital signal based on the charge generated by the plurality of photoelectric converters, and the second signal processor is configured to perform a second signal processing to generate a second digital signal based on a signal from the first coupling portion, the signal being based on the charge generated by the plurality of photoelectric converters. In some embodiments, in a plan view, the first coupling portion is arranged between the analog-to-digital converter and the first signal processor. In some embodiments, the second coupling portion is arranged on the opposite side of the first coupling portion relative to the first signal processor in a plan view. In some embodiments, a plurality of first electrodes are arranged in two or more rows. In some embodiments, the light detection device further includes a compression portion and a decompression portion, the compression portion is arranged on the second substrate and is configured to compress the signal, the decompression portion is arranged on the third substrate and is configured to decompress the compressed signal, wherein the first coupling portion is configured to transmit the compressed signal compressed by the compression portion to the decompression portion. In some embodiments, the compression portion is arranged between the analog-to-digital converter and the first signal processor. In some embodiments, the light detection device further includes a third signal processor arranged on the third substrate, wherein the third signal processor is configured to perform a third signal processing to generate a third digital signal based on the charge generated by the plurality of photoelectric converters through the second coupling portion. In some embodiments, the third signal processor is configured to perform recognition processing based on the third digital signal. In some embodiments, the first coupling portion is arranged between the second signal processor and the third signal processor in a plan view. In some embodiments, the second coupling portion is arranged on the opposite side of the first coupling portion relative to the third signal processor in a plan view. In some embodiments, the second coupling portion includes at least one of a first converter configured to convert a serial signal into a parallel signal or a second converter configured to convert a parallel signal into a serial signal.In some embodiments, the light detection device further includes an interface portion, the interface portion being arranged on the second substrate and configured to output from the light detection device at least one of a signal output from the first signal processor or a signal output from the second signal processor, wherein in a plan view, the second coupling portion is arranged between the first signal processor and the interface portion. In some embodiments, each of the plurality of first electrodes and each of the plurality of second electrodes includes a through electrode, a first junction electrode, and a second junction electrode, the through electrode penetrating the second substrate, the first junction electrode coupled to the through electrode, and the second junction electrode coupled to the first junction electrode.

[0013] According to aspects of the present disclosure, an electronic device is provided, comprising: a first substrate comprising a plurality of photoelectric converters, the plurality of photoelectric converters being configured to generate charges through photoelectric conversion; a second substrate comprising a first signal processor configured to perform first signal processing to generate signals based on the charges generated by the plurality of photoelectric converters, the second substrate being stacked on the first substrate; a third substrate comprising a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate; a first coupling portion comprising a plurality of first electrodes, the plurality of first electrodes coupling the circuit of the second substrate and the circuit of the third substrate; and a second coupling portion comprising a plurality of second electrodes, the plurality of second electrodes coupling the circuit of the second substrate and the circuit of the third substrate, wherein in a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion.

[0014] An imaging element according to an embodiment of the present disclosure includes a first substrate, a second substrate, a third substrate, a first coupling portion, and a second coupling portion. The first substrate includes a plurality of photoelectric converters, each of which is configured to generate charges by photoelectric conversion. The second substrate includes a first signal processor configured to obtain a signal based on the charge generated by the photoelectric converter and perform signal processing, and the second substrate is stacked on the first substrate. The third substrate includes a second signal processor configured to perform signal processing and stacked on the second substrate. The first coupling portion is provided with a plurality of first electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The second coupling portion is provided with a plurality of second electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The size of the first coupling portion is different from the size of the second coupling portion.

[0015] An electronic device according to an embodiment of the present disclosure includes a first substrate, a second substrate, a third substrate, a first coupling portion, and a second coupling portion. The first substrate includes a plurality of photoelectric converters, each of which is configured to generate charges through photoelectric conversion. The second substrate includes a first signal processor configured to obtain a signal based on the charge generated by the photoelectric converter and perform signal processing, and the second substrate is stacked on the first substrate. The third substrate includes a second signal processor configured to perform signal processing and stacked on the second substrate. The first coupling portion is provided with a plurality of first electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The second coupling portion is provided with a plurality of second electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The size of the first coupling portion is different from the size of the second coupling portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram illustrating an example of a schematic configuration of an electronic device according to an embodiment of the present disclosure.

[0017] Figure 2 is a diagram illustrating an example of a schematic configuration of an imaging element according to an embodiment of the present disclosure.

[0018] Figure 3 : is a diagram showing a configuration example of an imaging element according to an embodiment of the present disclosure.

[0019] Figure 4 : is a diagram showing a configuration example of pixels of an imaging element according to an embodiment of the present disclosure.

[0020] Figure 5 is a schematic diagram of an example of a cross-sectional configuration of an imaging element according to an embodiment of the present disclosure.

[0021] Figure 6 is a diagram illustrating a configuration example of an imaging element according to an embodiment of the present disclosure.

[0022] Fig. 7A is a diagram illustrating a layout example of an imaging element according to an embodiment of the present disclosure.

[0023] Figure 7B is a diagram illustrating a layout example of an imaging element according to an embodiment of the present disclosure.

[0024] Figure 7C is a diagram illustrating a layout example of an imaging element according to an embodiment of the present disclosure.

[0025] Figure 8 2 is a diagram for describing an example of signal transmission in an imaging element according to an embodiment of the present disclosure.

[0026] Fig. 9 2 is a diagram for describing an example of signal transmission in an imaging element according to an embodiment of the present disclosure.

[0027] Fig.10 : is a diagram for describing a configuration example of a first coupling portion of an imaging element according to an embodiment of the present disclosure.

[0028] Fig.11 is a diagram illustrating an example of timing adjustment in the first coupling portion of the imaging element according to the embodiment of the present disclosure.

[0029] Fig. 12A : is a diagram showing a configuration example of a first coupling portion of an imaging element according to an embodiment of the present disclosure.

[0030] Fig. 12B is a diagram showing a configuration example of a first coupling portion of an imaging element according to a comparative example.

[0031] Fig.13 : is a diagram for describing a configuration example of an imaging element according to Modification 1 of the present disclosure.

[0032] Fig.14 : is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 2 of the present disclosure.

[0033] Fig.15A : is a diagram showing a layout example of an imaging element according to Modification 3 of the present disclosure.

[0034] Fig. 15B : is a diagram showing a layout example of an imaging element according to Modification 3 of the present disclosure.

[0035] Fig.16 : is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 4 of the present disclosure.

[0036] Fig.17 : is a diagram for describing a configuration example of an imaging element according to Modification 5 of the present disclosure.

[0037] Fig.18A 2 is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 5 of the present disclosure.

[0038] Fig.18B : is a timing chart for describing an operation example of the first coupling section of the imaging element according to Modification 5 of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0040] 1. Implementation Method

[0041] 2. Modifications

[0042] 3. Usage Examples

[0043] 4. Application Examples

[0044] The imaging element (also referred to herein as a light detecting device) may have a three-layer stacked structure, that is, a structure in which a first chip having a pixel array unit, a second chip having an AD converter, and a third chip having a storage unit are stacked (see Patent Document 1).

[0045] <1. Implementation Method>

[0046] Figure 1 2 is a diagram showing an example of a schematic configuration of an electronic device according to an embodiment of the present disclosure. The electronic device 10 includes an imaging element 1, an optical system 201, a controller 202, and a processor 203. The optical system 201 includes an optical lens, and guides light from a subject to the imaging element 1.

[0047] The imaging element 1 includes a plurality of pixels, each pixel includes a light receiving element, and is configured to perform photoelectric conversion of incident light to generate a signal. The light receiving element (light receiving unit) can convert the incident light into an electric charge. The imaging element 1 includes, for example, a CMOS (complementary metal oxide semiconductor) image sensor. The imaging element 1 captures incident light (image light) from an object through an optical system 201. The imaging element 1 captures an image of a subject formed by an optical lens. The imaging element 1 performs photoelectric conversion on the received light to generate a pixel signal.

[0048] The controller 202 is configured to be able to control the operation of the imaging element 1. The controller 202 provides a control signal to the imaging element 1, controls the imaging element 1, and causes the imaging element 1 to output a signal of each pixel. The processor 203 includes a signal processor, and is configured to perform signal processing on the signal output from the imaging element 1. The controller 202 and the processor 203 each include, for example, a processor and a memory (such as ROM or RAM), and perform signal processing (information processing) based on a program. The processor 203 can perform various types of signal processing on the signal of each pixel output from the imaging element 1 and output pixel data.

[0049] [Schematic Configuration of Imaging Element]

[0050] Figure 2 is a diagram showing an example of a schematic configuration of an imaging element according to an embodiment. Figure 2In the example shown, the imaging element 1 has a region (pixel section 100) in which a plurality of pixels P are two-dimensionally arranged in a matrix as an imaging region. The light receiving element (light receiving section) of each pixel P includes a photoelectric converter capable of generating charge by photoelectric conversion. The photoelectric converter includes, for example, a photodiode and is configured to be capable of performing photoelectric conversion of light. Figure 2 In the example shown in , the imaging element 1 includes, for example, a vertical driver 110 , a column signal processor 112 , a signal processing block 113 , and the like in a region around the pixel portion 100 .

[0051] The imaging element 1 is provided with, for example, a plurality of pixel drive lines Lread and a plurality of vertical signal lines VSL. For example, the pixel portion 100 is wired with a plurality of pixel drive lines Lread for each pixel row, each pixel row including a plurality of pixels P arranged side by side in the horizontal direction (row direction). In addition, the pixel portion 100 is wired with vertical signal lines VSL for corresponding pixel columns, each pixel column including a plurality of pixels P arranged side by side in the vertical direction (column direction). The pixel drive lines Lread are each configured to transmit a drive signal for signal reading from the pixel P. The vertical signal lines VSL are each a signal line capable of transmitting a signal from the pixel P. The vertical signal lines VSL are each configured to transmit a signal output from the pixel P.

[0052] The vertical driver 110 includes a shift register, an address decoder, etc. The vertical driver 110 is configured to drive each pixel P in the pixel portion 100. The vertical driver 110 includes a pixel driver, and generates a signal for driving the pixel P, and outputs the signal to each pixel P in the pixel portion 100 through a pixel drive line Lread. For example, the vertical driver 110 generates a signal for controlling a transfer transistor, a signal for controlling a reset transistor, etc., and provides the signal to each pixel P through a pixel drive line Lread.

[0053] The signal output from each pixel P selected and scanned by the vertical driver 110 is provided to the column signal processor 112 through the vertical signal line VSL. The column signal processor 112 is configured to perform signal processing on the input signal of each pixel. The column signal processor 112 includes, for example, a load circuit section, an AD (analog-digital) converter 20, a horizontal selection switch, etc. The signal of each pixel P transmitted through a corresponding one of the vertical signal lines VSL undergoes signal processing by the column signal processor 112 and is output to the signal processing block 113.

[0054] The signal processing block 113 is configured to perform signal processing on the input signal and output the signal. The signal processing block 113 is configured to be able to obtain the signal of each pixel converted into a digital signal from the column signal processor 112 and perform signal processing. The signal processing block 113 is also called a logic circuit part (digital circuit part) capable of performing digital signal processing.

[0055] The signal processing block 113 can perform signal processing on the signals of the pixels sequentially input from the column signal processor 112 and output the signals that have been subjected to the processing. As described later, the signal processing block 113 includes a plurality of signal processors (signal processing circuits). The signal processing block 113 can perform, for example, various types of digital signal processing such as noise reduction processing (e.g., black level adjustment, column variation correction, etc.) and interpolation processing.

[0056] Figure 3 1 is a diagram showing a configuration example of an imaging element according to an embodiment. Figure 3 As shown in FIG. 1 , the imaging element 1 includes a first substrate 101, a second substrate 102, and a third substrate 103. The first substrate 101, the second substrate 102, and the third substrate 103 are stacked on top of each other. The imaging element 1 has a structure (stacked structure) in which the first substrate 101, the second substrate 102, and the third substrate 103 are stacked in the Z-axis direction. Figure 3 As shown in the figure, the incident direction of light from the object is defined as the Z-axis direction, the left / right direction of the figure perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. Figure 3 The direction of the arrow in the figure is used to express the direction.

[0057] Each substrate may include a circuit, such as one or more of the different circuits described herein. The first substrate 101 is provided with a pixel portion 100. In the pixel portion 100, a plurality of pixels P are arranged in a horizontal direction (row direction) (a first direction) and a vertical direction (column direction) (a second direction perpendicular to the first direction). The pixel portion 100 includes a pixel array, wherein the pixels P are arranged in a matrix. The second substrate 102 is provided with a vertical driver 110 and a column signal processor 112. In addition, in the present embodiment, the signal processing block 113 includes a plurality of logic circuits and is separately arranged on a plurality of substrates.

[0058] As in Figure 3 In the example shown in , the signal processing block 113 includes a first signal processor 91, a second signal processor 92, and a third signal processor 93, and is separately arranged on the second substrate 102 and the third substrate 103. Figure 3In the example shown, the first signal processor 91 is arranged on the second substrate 102. The second signal processor 92 and the third signal processor 93 are arranged on the third substrate 103. The signal processing block 113 is arranged separately on a plurality of substrates so that an increase in chip area can be suppressed. A plurality of circuits capable of performing processing on signals from the pixel P while suppressing an increase in chip area can be provided.

[0059] [Pixel configuration]

[0060] Figure 4 1 is a diagram showing a configuration example of a pixel of an imaging element according to an embodiment. The pixels P each include a photoelectric converter 12, a transistor TGL, a floating diffusion (FD), a transistor AMP, a transistor SEL, and a transistor RST.

[0061] Each of the transistor TGL, the transistor AMP, the transistor SEL, and the transistor RST includes a MOS transistor (MOSFET) having terminals including a gate, a source, and a drain. Figure 4 In the example shown, each of the transistors TGL, AMP, SEL and RST comprises an NMOS transistor. It should be noted that the transistors of the pixel P may each comprise a PMOS transistor.

[0062] The photoelectric converter 12 is configured to generate electric charge by photoelectric conversion. Figure 4 In the example shown, the photoelectric converter 12 includes a photodiode (PD) and converts incident light into electric charge. The photoelectric converter 12 performs photoelectric conversion to generate electric charge corresponding to the amount of received light.

[0063] The transistor TGL is configured to be able to transfer the charge generated by the photoelectric conversion of the photoelectric converter 12 to the FD. Figure 4 As shown, transistor TGL is controlled by signal STGL to electrically couple or disconnect the photoelectric converter 12 and FD. Transistor TGL is a transfer transistor and can transfer charges generated and stored by photoelectric conversion of the photoelectric converter 12 to the FD.

[0064] FD is a charge storage part and is configured to be able to store the transferred charge. FD can store the charge generated by the photoelectric conversion of the photoelectric converter 12. FD is also called a holding part capable of holding the transferred charge. FD stores the transferred charge and converts the charge into a voltage corresponding to the capacitance of FD.

[0065] The transistor AMP is configured to generate and output a signal based on the charge stored in the FD. Figure 4As shown, the gate of the transistor AMP is electrically coupled to the FD, and the voltage obtained by the conversion of the FD is input to the gate of the transistor AMP. The drain of the transistor AMP is coupled to the power line to which the power supply voltage is to be supplied, and the source of the transistor AMP is coupled to the vertical signal line VSL through the transistor SEL. The transistor AMP is an amplifying transistor, and can generate a signal based on the charge stored in the FD (i.e., a signal based on the voltage of the FD), and output the signal to the vertical signal line VSL.

[0066] The transistor SEL is configured to be able to control the output of the signal of the pixel. The transistor SEL is configured to be able to output the signal from the transistor AMP to the vertical signal line VSL by being controlled by the signal SSEL. The transistor SEL is a selection transistor and can control the output timing of the signal of the pixel. It should be noted that the transistor SEL can be arranged between the power supply line to be provided with the power supply voltage and the transistor AMP. Alternatively, the transistor SEL can be omitted as needed.

[0067] The transistor RST is configured to be able to reset the voltage of FD. Figure 4 In the example shown, the transistor RST is electrically coupled to the power supply line and is configured to reset the charge of the pixel P. The transistor RST can reset the charge stored in the FD and reset the voltage of the FD by being controlled by the signal SRST. It should be noted that the transistor RST can release the charge stored in the photoelectric converter 12 through the transistor TGL. The transistor RST is a reset transistor.

[0068] Vertical driver 110 (see Figure 2 and Figure 3 ) provides a driving signal to each gate of the transistor TGL, transistor SEL, transistor RST, etc. of each pixel P to turn the transistor into a conducting state (conducting state) or a cut-off state (non-conducting state). The transistor TGL, transistor SEL, etc. are controlled to be turned on or off by the vertical driver 110. The vertical driver 110 controls the signal STGL, signal SSEL, signal SRST, etc. input to each pixel P, thereby outputting the signal from the transistor AMP of each pixel P to the vertical signal line VSL.

[0069] The signal of each pixel is output to the column signal processor 112 through the vertical signal line VSL. As described above, the column signal processor 112 includes a load circuit portion (not shown), an AD converter 20, etc. The load circuit portion is coupled to the vertical signal line VSL. For example, the load circuit portion includes a current source capable of supplying current to the transistor AMP of each pixel P. The load circuit portion and the transistor AMP of the pixel P together constitute a source follower circuit. It should be noted that the column signal processor 112 may include an amplifier circuit portion configured to amplify the signal read from the pixel P through the vertical signal line VSL.

[0070] The AD converter 20 is configured to convert the input analog signal into a digital signal. The AD converter 20 is an ADC (analog-to-digital converter). The AD converter 20 is provided for each of the plurality of vertical signal lines VSL. The AD converter 20 (AD conversion circuit) is provided for each pixel column including a plurality of pixels P arranged side by side in the vertical direction (column direction). The AD converter 20 performs AD conversion processing on the signal of each pixel as an analog signal input from each pixel P through the vertical signal line VSL. In one embodiment, the AD converter 20 includes a comparator (comparator circuit) and a counter, and converts the input signal of each pixel into a digital signal having a predetermined number of bits. The column signal processor 112 outputs the pixel signal that has undergone AD conversion to the signal processing block 113.

[0071] Figure 5 Schematic diagram of an example of a cross-sectional configuration of an imaging element according to this embodiment. The imaging element 1 has a configuration in which a first substrate 101, a second substrate 102, and a third substrate 103 are stacked in the Z-axis direction. The first substrate 101, the second substrate 102, and the third substrate 103 each include a semiconductor substrate (e.g., a silicon substrate).

[0072] like Figure 5 As shown, the first substrate 101, the second substrate 102 and the third substrate 103 respectively have first surfaces 11S1, 12S1 and 13S1, each of which is provided with a transistor, and second surfaces 11S2, 12S2 and 13S2. The first surfaces 11S1, 12S1 and 13S1 are each a component formation surface formed such as a transistor. Each of the first surfaces 11S1, 12S1 and 13S1 is provided with a gate electrode, a gate oxide film, etc. It should be noted that on the second surface 11S2 side of the first substrate 101, a lens portion 31, a color filter 32, etc. for converging light are provided for each pixel P.

[0073] like Figure 5 As shown, the first surface 11S1 of the first substrate 101 is provided with a wiring layer 111. In addition, the first surface 12S1 of the second substrate 102 is provided with a wiring layer 121, and the second surface 12S2 of the second substrate 102 is provided with a wiring layer 122. The first surface 13S1 of the third substrate 103 is provided with a wiring layer 131. The wiring layers 111, 121, 122, 131 are composed of, for example, a conductor film and an insulating film, and have a plurality of wirings, through holes, etc. The wiring layers 111, 121, 122, and 131 each include, for example, two or more layers of wiring.

[0074] The wiring layers 111, 121, 122, and 131 have a configuration in which a plurality of wirings are stacked with an interlayer insulating layer (interlayer insulating film) interposed therebetween. The wiring layer is formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), or the like. The interlayer insulating layer is formed using, for example, a single-layer film containing one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like, or a stacked film containing two or more of them.

[0075] It should be noted that the first substrate 101 and the wiring layer 111 may be collectively referred to as the first substrate 101 (or the first circuit layer). In addition, the second substrate 102 and the wiring layers 121 and 122 may be collectively referred to as the second substrate 102 (or the second circuit layer). The third substrate 103 and the wiring layer 131 may be collectively referred to as the third substrate 103 (or the third circuit layer).

[0076] The first substrate 101 and the second substrate 102 are stacked by bonding electrodes, and the first surface 11S1 and the first surface 12S1 are opposite to each other. Elements such as transistors are formed on the first surface 11S1 and the first surface 12S1. In other words, the first substrate 101 and the second substrate 102 are bonded with their respective front surfaces facing each other.

[0077] The second substrate 102 and the third substrate 103 are stacked by bonding electrodes having a second surface 12S2 and a first surface 13S1 opposite to each other. Elements such as transistors are formed on the first surface 13S1. In other words, the second substrate 102 and the third substrate 103 are bonded in a manner that the rear surface of the second substrate 102 and the front surface of the third substrate 103 opposite to each other are bonded.

[0078] In one example, the first surface 11S1 of the first substrate 101 and the first surface 12S1 of the second substrate 102 are bonded together by bonding metal electrodes each including copper (Cu) (i.e., Cu-Cu junction). In addition, for example, the second surface 12S2 of the second substrate 102 and the first surface 13S1 of the third substrate 103 are also bonded by Cu-Cu. It should be noted that the electrode for the junction may include, for example, a metal material other than copper (Cu) such as nickel (Ni), cobalt (Co), or tin (Sn), or may include other materials.

[0079] exist Figure 5In the example shown in FIG. 1 , a plurality of electrodes 15 each including the uppermost wiring in the wiring layer 111 and a plurality of electrodes 25 each including the uppermost wiring in the wiring layer 121 are joined to couple the first substrate 101 and the second substrate 102. The electrodes 15 and 25 are each a junction electrode. In addition, a plurality of electrodes 26 each including the uppermost wiring in the wiring layer 122 and a plurality of electrodes 35 each including the uppermost wiring in the wiring layer 131 are joined to couple the second substrate 102 to the third substrate 103. The electrodes 26 and 35 are each a junction electrode.

[0080] like Figure 5 As shown, the second substrate 102 and the wiring layers 121 and 122 include a plurality of through electrodes 28. The through electrodes 28 are electrodes that penetrate the second substrate 102. The through electrodes 28 are formed to extend in the Z-axis direction and reach the wiring layer 122 of the second substrate 102. The through electrodes 28 each include, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. It should be noted that the through electrodes 28 may each include another metal material.

[0081] In the imaging element 1 according to the present embodiment, the circuit provided on the first surface 12S1 side of the second substrate 102 and the circuit provided on the first surface 13S1 side of the third substrate 103 are electrically coupled through the through electrode 28 and the electrodes 26 and 35 for bonding. The through electrode 28 and the junction electrodes 26 and 35 constitute an electrode (coupling electrode 40) that connects the circuit of the second substrate 102 and the circuit of the third substrate 103, and is configured to be able to transmit a signal. The coupling electrode 40 couples the circuits provided in different layers.

[0082] Furthermore, in the imaging element 1, the circuit provided on the first surface 11S1 side of the first substrate 101 and the circuit provided on the first surface 12S1 side of the second substrate 102 are electrically coupled via the electrodes 15 and 25 for bonding. The circuit on the first surface 11S1 side of the first substrate 101 and the circuit on the first surface 12S1 side of the second substrate 102 are electrically coupled via the coupling portion 60 (see the later-described Fig. 7A and Figure 7B ). The coupling portion 60 includes a plurality of electrodes 15 and a plurality of electrodes 25 for bonding, and electrically couples the circuit of the first substrate 101 and the circuit of the second substrate 102. The coupling portion 60 may include a through electrode, a through hole, etc. The circuit of the first substrate 101 and the circuit of the second substrate 102 are coupled through a Cu-Cu junction, a through electrode, a through hole, etc.

[0083] Figure 6 : is a diagram showing a configuration example of an imaging element according to an embodiment. Figure 6 Column signal processor 112 and signal processing block 113 of imaging element 1 are shown. Figure 6As shown, the signal processing block 113 includes a first signal processor 91, a second signal processor 92, a third signal processor 93, an imaging controller 80, and an interface unit 90 (I / F unit). The imaging controller 80 includes a first imaging controller 81 and a second imaging controller 82. For example, the first signal processor 91, the first imaging controller 81, the interface unit 90, etc. are arranged on the second substrate 102. In addition, the second signal processor 92, the third signal processor 93, the second imaging controller 82, etc. may be arranged on the third substrate 103.

[0084] In addition, the signal processing block 113 of the imaging element 1 includes a first coupling section 71 and a second coupling section 72 (a second coupling section 72a and a second coupling section 72b in FIG. 7). Each of the first coupling section 71 and the second coupling section 72 is provided with the above-mentioned plurality of electrodes 40 (through electrodes 28 and electrodes 26 and 35). The first coupling section 71 and the second coupling section 72 each couple the circuit of the second substrate 102 and the circuit of the third substrate 103.

[0085] The first signal processor 91 is configured to be able to obtain a signal for each pixel and perform signal processing. Figure 6 In the example shown in , the first signal processor 91 obtains the pixel signal converted into the digital signal from the column signal processor 112. The digital signal based on the charge generated by the photoelectric converter 12 of the pixel P is input to the first signal processor 91 as the pixel signal.

[0086] The first signal processor 91 includes a circuit that performs various types of signal processing on the pixel signal. The first signal processor 91 includes an operation circuit, a memory circuit, etc. The first signal processor 91 can perform signal processing such as noise reduction processing, interpolation processing (rereading processing) or grayscale correction processing on the pixel signal that has undergone AD conversion, for example. The first signal processor 91 can perform various types of signal processing on the signal of each pixel to generate image data D1 (image signal). The first signal processor 91 can output the image data D1 obtained by processing the signal from the column signal processor 112 to the interface part 90, the second coupling part 72a, etc.

[0087] The first coupling portion 71 includes a plurality of coupling electrodes 40 and couples the circuit of the second substrate 102 and the circuit of the third substrate 103. Figure 6 In the illustrated example, the first coupling portion 71 electrically couples the column signal processor 112 and the first signal processor 91 included in the circuit of the second substrate 102 and the second signal processor 92 included in the circuit of the third substrate 103 .

[0088] The first coupling portion 71 includes a plurality of first output portions 51 and a plurality of first input portions 52, and is configured to be able to transmit signals. The first output portion 51 is provided on the second substrate 102, and the first input portion 52 is provided on the third substrate 103. The first output portion 51 is an output portion (output circuit) that outputs signals to the circuit of the third substrate 103, respectively. The first input portion 52 is an input portion (input circuit) that inputs signals from the circuit of the second substrate 102. The first output portion 51 and the first input portion 52 are also referred to as transmission portions that can transmit signals.

[0089] The first coupling section 71 includes a plurality of coupling electrodes 40 corresponding to the number of signals to be transmitted (such as the amount of data), a plurality of first output sections 51, and a plurality of first input sections 52. The first output section 51 and the first input section 52 of the first coupling section 71 each include, for example, a flip-flop (FF circuit), an inverter (INV circuit), and the like.

[0090] The first output portions 51 of the first coupling portion 71 are each electrically coupled to the column signal processor 112 and the first signal processor 91. The first input portions 52 of the first coupling portion 71 are each electrically coupled to the second signal processor 92. The pixel signal converted into a digital signal is input to the first output portion 51 from the column signal processor 112. The pixel signal input to the first output portion 51 is transmitted to the first input portion 52 through the first output portion 51 via the coupling electrode 40. The first coupling portion 71 can output the pixel signal from the first input portion 52.

[0091] The second signal processor 92 is configured to be able to obtain a signal for each pixel and perform signal processing. Figure 6 In the example shown in , the second signal processor 92 obtains the pixel signal as a digital signal from the first coupling section 71. The digital signal based on the charge generated by the photoelectric converter 12 of the pixel P is input to the second signal processor 92 as the pixel signal.

[0092] The second signal processor 92 includes a circuit that performs various types of signal processing on the pixel signal. The second signal processor 92 includes an operation circuit, a memory circuit, etc. The second signal processor 92 may perform signal processing such as noise reduction processing, interpolation processing, or cropping processing on the pixel signal, for example. The second signal processor 92 may perform various types of signal processing on the signal of each pixel to generate image data D2 (image signal). The second signal processor 92 may output the image data D2 to the second coupling portion 72a, etc.

[0093] The second coupling portion 72a includes a plurality of connection electrodes 40, and connects the circuit of the second substrate 102 and the circuit of the third substrate 103. Figure 6In the example shown in , the second coupling portion 72a electrically couples the first signal processor 91 and the third signal processor 93. Furthermore, the second coupling portion 72a electrically couples the second signal processor 92 and the interface portion 90, and electrically couples the third signal processor 93 and the interface portion 90.

[0094] The second coupling portion 72a includes a plurality of second output portions 61 and a plurality of second input portions 62, and is configured to be able to transmit signals. The second coupling portion 72a includes a plurality of coupling electrodes 40, a plurality of second output portions 61, and a plurality of second input portions 62 corresponding to the number of signals to be transmitted. For example, the second output portion 61 ( Figure 6 The second output sections 61a to 61c in the figure) and the second input section 62 (the second input sections 62a to 62c) each include a flip-flop, an inverter, etc. It should be noted that the second output section 61 and the second input section 62 are also referred to as transmission sections capable of transmitting signals.

[0095] exist Figure 6 In the example of , the second substrate 102 is provided with a second output portion 61a, a second input portion 62b and a second input portion 62c. In addition, the third substrate 103 is provided with a second input portion 62a, a second output portion 61b and a second output portion 61c. The second output portion 61a is an output portion (output circuit) that outputs a signal to the circuit of the third substrate 103, and the second input portion 62a is an input portion (input circuit) that inputs a signal from the circuit of the second substrate 102. The second output portions 61b and 61c are both output portions that output signals to the circuit of the second substrate 102. In addition, the second input portions 62b and 62c are input portions that input signals from the circuit of the third substrate 103, respectively.

[0096] The second output portion 61a of the second coupling portion 72a is electrically coupled to the first signal processor 91. The second input portion 62a of the second coupling portion 72a is electrically connected to the third signal processing portion 93. The image data D1 including each pixel that has been subjected to signal processing is input to the second output portion 61a from the first signal processor 91. The image data D1 input to the second output portion 61a is transmitted from the second output portion 61a to the second input portion 62a through the coupling electrode 40.

[0097] The second output portion 61b of the second coupling portion 72a is electrically coupled to the second signal processor 92. The second input portion 62b of the second coupling portion 72a is electrically connected to the interface portion 90. Image data D2 including the signal of each pixel after signal processing is input to the second output portion 61b from the second signal processor 92. The image data D2 input to the second output portion 61b is transmitted to the second input portion 62b through the second output portion 61b via the coupling electrode 40.

[0098] The third signal processor 93 is configured to be able to obtain a signal for each pixel and perform signal processing. Figure 6 In the example shown, the third signal processor 93 obtains the image data D1 as a digital signal from the first signal processor 91 through the second output section 61a and the second input section 62a of the second coupling section 72a. The image data D1 including the signal of each pixel subjected to signal processing is input to the third signal processor 93.

[0099] The third signal processor 93 includes a circuit that performs various types of signal processing on the pixel signal. The third signal processor 93 includes an operation circuit, a memory circuit, etc. The third signal processor 93 includes, for example, a DSP (digital signal processor), an ISP (image signal processor), etc. The third signal processor 93 can perform recognition processing based on the image data D1 including the signal of each pixel. The third signal processor 93 is also called an AI (artificial intelligence) circuit.

[0100] In one example, the third signal processor 93 performs interpolation processing, gain adjustment processing, color adjustment processing, normalization processing, etc. on the image data D1 including the signal of each pixel to generate data for recognition processing. The third signal processor 93 performs image recognition processing using DNN (deep neural network) based on the generated data to generate data D3 indicating the recognition result. The data D3 includes, for example, data (signal) indicating a specific object included in the image data D1. The third signal processor 93 can output the data D3 to the second coupling portion 72a.

[0101] The second output portion 61c of the second coupling portion 72a is electrically coupled to the third signal processor 93. The second input portion 62c of the second coupling portion 72a is electrically coupled to the interface portion 90. Data D3 is input to the second output portion 61c from the third signal processor 93. The data D3 input to the second output portion 61c is transmitted from the second output portion 61c to the second input portion 62c through the coupling electrode 40.

[0102] The interface section 90 includes a transmission circuit and is configured to be able to transmit an input signal. The interface section 90 includes an interface circuit. The image data D1 is input to the interface section 90 from the first signal processor 91. In addition, the image data D2 is input to the interface section 90 from the second signal processor 92 through the second output section 61b and the second input section 62b of the second coupling section 72a.

[0103] In addition, the data D3 is input from the third signal processor 93 to the interface unit 90 through the second output unit 61c and the second input unit 62c of the third signal processor 93. The interface unit 90 can send the image data D1, image data D2, and data D3 to the outside at a high speed. Thus, the imaging element 1 of this embodiment can generate image data D1, image data D2, and data D3 according to the signal of each pixel, and output the image data D1, image data D2, and data D3 to the outside.

[0104] The imaging control section 80 controls each component of the imaging element 1. The imaging controller 80 receives a clock or data for commanding an operation mode, etc., provided from the outside, and controls each component of the imaging element 1. The imaging controller 80 includes, for example, a processor (e.g., a CPU) and a memory, and performs various types of signal processing. The first imaging controller 81 controls the operation of the circuit of the second substrate 102, for example, the operation of the first signal processor 91, etc. The second imaging controller 82 controls the operation of the circuit of the third substrate 103, for example, the operation of the second signal processor 92, the third signal processor 93, etc.

[0105] The second coupling portion 72b includes a plurality of connection electrodes 40 and electrically connects the first imaging controller 81 and the second imaging controller 82. The second coupling portion 72b is configured to be able to transmit signals. The second coupling portion 72b includes a plurality of coupling electrodes 40 corresponding to the number of signals to be transmitted, a plurality of second output portions 61, and a plurality of second input portions 62. For example, the second output portion 61 ( Figure 6 The second output parts 61d and 61e in the figure) and the second input part 62 (the second input parts 62d and 62e) each include a trigger, an inverter, etc.

[0106] The second output portion 61d of the second coupling portion 72b is electrically coupled to the first imaging controller 81. The second input portion 62d of the second coupling portion 72b is electrically coupled to the second imaging controller 82. The signal input from the first imaging controller 81 to the second output portion 61d is transmitted to the second imaging controller 82 through the coupling electrode 40 and the second input portion 62d.

[0107] The second output portion 61e of the second coupling portion 72b is electrically coupled to the second imaging controller 82. The second input portion 62e of the second coupling portion 72b is electrically coupled to the first imaging controller 81. A signal input from the second imaging controller 82 to the second output portion 61e is transmitted to the first imaging controller 81 through the coupling electrode 40 and the second input portion 62e. The first imaging controller 81 and the second imaging controller 82 can transmit and receive signals through the second coupling portion 72b and control each component of the imaging element 1.

[0108] 7A to 7C1 and 2 are diagrams each showing a layout example of an imaging element according to an embodiment. Fig. 7A The layout example in φ represents a layout example of the first substrate 101 among the first substrate 101 to the third substrate 103 . Figure 7B The layout example in represents a layout example in the second substrate 102. In addition, Figure 7C The layout example in ⊥ represents a layout example in the third substrate 103.

[0109] exist Fig. 7A and Figure 7B In the example shown in , two coupling portions 60 are provided on each of the first substrate 101 and the second substrate 102. On the first substrate 101, two coupling portions 60 are provided around the pixel portion 100. On the second substrate 102, the coupling portions 60 are provided in an area outside the vertical driver 110 and an area outside the column signal processor 112. The coupling portions 60 each include the above-mentioned plurality of electrodes 15 corresponding to the number of signals to be transmitted and a plurality of electrodes 25 for connection. Each coupling portion 60 couples the circuit of the first substrate 101 and the circuit of the second substrate 102.

[0110] As described above, the first coupling portion 71 and the second coupling portion 72 (the second coupling portions 72a and 72b) each include a plurality of coupling electrodes 40 corresponding to the number of signals to be transmitted. In the first coupling portion 71, the plurality of coupling electrodes 40 are arranged side by side in the X-axis direction. In addition, in the second coupling portion 72, the plurality of coupling electrodes 40 are arranged side by side in the X-axis direction. In a plan view, each coupling portion may have a different area. For example, the first coupling portion 71 and the second coupling portion 72 have different sizes from each other. That is, the area where the first coupling portion 71 is provided and the area where the second coupling portion 72 is provided have different widths from each other.

[0111] like Figure 7B and Figure 7C Schematically shown, the number of coupling electrodes 40 in the first coupling portion 71 is greater than the number of coupling electrodes 40 in the second coupling portion 72. The size of the first coupling portion 71 is greater than the size of the second coupling portion 72. The length of the first coupling portion 71 in the X-axis direction is greater than the length of the second coupling portion 72 in the X-axis direction. Therefore, in the imaging element 1, a large number of signals can be transmitted simultaneously (in parallel).

[0112] In addition, if Figure 7B As shown, in a plan view, the first coupling section 71 is provided between the column signal processor 112 including the plurality of AD converters 20 and the first signal processor 91. The first coupling section 71 is arranged adjacent to the column signal processor 112 and the first signal processor 91. Therefore, in the imaging element 1 according to the present embodiment, signal transmission from the column signal processor 112 to the first signal processor 91 and the first coupling section 71 can be efficiently performed.

[0113] In addition, if Figure 7C As shown, in a plan view, the first coupling portion 71 is provided between the second signal processor 92 and the third signal processor 93. The first coupling portion 71 is provided adjacent to the second signal processor 92. Therefore, in the imaging element 1, signal transmission can be efficiently performed between the column signal processor 112 and the second signal processor 92 through the first coupling portion 71.

[0114] like Figure 7B As shown, in a plan view, the second coupling portion 72 is disposed between the first signal processor 91 and the interface portion 90. At least a portion of the first signal processor 91 is disposed between the first coupling portion 71 and the second coupling portion 72. The second coupling portion 72 is disposed on a side of the first signal processor 91 opposite to the first coupling portion 71.

[0115] In addition, if Figure 7C As shown, the second coupling portion 72 is provided on the side opposite to the first coupling portion 71 with respect to the third signal processor 93. Therefore, in the imaging element 1 of the present embodiment, signal transmission between the circuit of the second substrate 102 and the circuit of the third substrate 103 can be efficiently performed through the second coupling portion 72. In the imaging element 1, signal transmission between the first signal processor 91 and the third signal processor 93, signal transmission between the third signal processor 93 and the interface portion 90, and the like can be efficiently performed.

[0116] Figure 8 and Fig. 9 1 is a diagram for describing an example of signal transmission in an imaging element according to an embodiment. The imaging element 1 according to the embodiment can perform first mode signal transmission and second mode signal transmission. Figure 8 shows a first mode signal transmission, and Fig. 9 The second mode signal transmission is shown. The first mode signal transmission is a mode in which signal transmission is performed using a multi-cycle (i.e., a multi-cycle path type signal transmission). The second mode signal transmission is a mode in which signal transmission is performed using serial / parallel conversion and parallel-serial conversion, and is a serial / parallel-parallel-serial conversion type signal transmission.

[0117] In this embodiment, the first coupling portion 71 is configured to be able to perform first mode signal transmission. The first coupling portion 71 can perform signal transmission between the second sub-state 102 and the third substrate 103 through the first mode signal transmission. In addition, the second coupling portion 72 is configured to be able to perform second mode signal transmission. The second coupling portion 72a and the second coupling portion 72b can each perform signal transmission between the second substrate 102 and the third substrate 103 through the second mode signal transmission.

[0118] exist Figure 8In the example shown, the first output section 51 of the first coupling section 71 includes a flip-flop C11. The first input section 52 of the first coupling section 71 includes a flip-flop C12. A data signal having a frequency f1 is input to the flip-flop C11 from the flip-flop C10 of the column signal processor 112. The signal level of this data signal transitions (changes) once every multiple transitions, for example, once every four transitions of the clock signal as a reference.

[0119] The flip-flop C11 samples the data signal from the flip-flop C10 in synchronization with the clock signal having a frequency f2 (= f1 / 4), and outputs the data signal to the first input section 52. The data signal having a frequency f2 is input from the first output section 51 to the flip-flop C12 of the first input section 52 through the coupling electrode 40. The flip-flop C12 samples the data signal from the flip-flop C11 in synchronization with the clock signal having a frequency f2, and outputs the data signal to a circuit outside the first coupling section 71 (for example, the flip-flop C20 of the second signal processor 92).

[0120] The data signal having the frequency f2 is input to the flip-flop C20 of the second signal processor 92 from the first input section 52. The flip-flop C20 can sample the data signal from the flip-flop C12 in synchronization with the clock signal having the frequency f1', and capture and hold the data signal.

[0121] Therefore, in the first coupling portion 71, the transmission of the data signal is synchronized with the clock signal having a frequency f2 lower than the frequency f1 (for example, a frequency equal to one quarter of the frequency f1). This makes it possible to suppress the transmission and reception of erroneous data signals between the layers of the second substrate 102 and the third substrate 103 and to correctly transmit and receive signals. Figure 8 In the illustrated example, in the imaging element 1 , a signal of each pixel can be appropriately transmitted from the column signal processor 112 to the second signal processor 92 .

[0122] exist Fig. 9 In the example shown, the second output section 61 of the second coupling section 72 includes a serial / parallel converter 65 and a plurality of triggers C21. The second input section 62 of the second coupling section 72 includes a plurality of triggers C22 and a parallel-to-serial converter 66. The serial / parallel converter 65 includes a serial / parallel conversion circuit (serial-to-parallel converter) and is configured to be able to convert a serial signal into a parallel signal. The parallel-to-serial converter 66 includes a parallel-to-serial conversion circuit (serializer) and is configured to be able to convert a parallel signal into a serial signal. It should be noted that the serial / parallel converter 65 and the parallel-to-serial converter 66 may be provided outside the second coupling section 72.

[0123] A data signal having a frequency f1 is input from a circuit outside the second coupling section 72 (e.g., a flip-flop C15 of the first signal processor 91) to the serial / parallel converter 65. The serial / parallel converter 65 converts the data signal, which is a serial signal input from the flip-flop C15, into a parallel signal, and outputs the parallel signal to each flip-flop C21. The flip-flops C21 output the data signal from the serial / parallel converter 65 to the second input section 62 in synchronization with a clock signal having a frequency f2 (=f1 / 4), respectively.

[0124] The data signal as a parallel signal is input from the second output section 61 to the plurality of flip-flops C22 of the second input section 62 through the coupling electrode 40. The flip-flops C22 sample the data signal from the flip-flops C21 in synchronization with the clock signal having a frequency f2 and output the data signal to the parallel-to-serial converter 66.

[0125] The data signal having the frequency f2 is input to the parallel-to-serial converter 66. The parallel-to-serial converter 66 converts the data signal, which is a parallel signal input from the plurality of flip-flops C22, into a serial signal, and outputs the data signal to a circuit (e.g., flip-flop C25 of the third signal processor 93) outside the second coupling section 72. The flip-flop C25 of the third signal processor 93 can sample the data signal from the parallel-to-serial converter 66 in synchronization with the clock signal having the frequency f1', and capture and hold the data signal.

[0126] Therefore, the second coupling portion 72 performs transmission and reception of data signals in synchronization with the clock signal having a frequency f2 lower than the frequency f1 through the second mode signal transmission. This makes it possible to prevent erroneous data signals from being transmitted and received between the second substrate 102 and the third substrate 103 and to perform data transmission appropriately. By using serial / parallel conversion and parallel-to-serial conversion, data transmission can be efficiently performed. Fig. 9 In the illustrated example, in the imaging element 1 , a signal of each pixel can be appropriately transmitted from the first signal processor 91 to the third signal processor 93 .

[0127] In the imaging element 1, signal transmission between the second signal processor 92 and the interface section 90 and signal transmission between the third signal processor 93 and the interface section 90 can be appropriately performed by the second mode signal transmission in the second coupling section 72a. In addition, in the imaging element 1, signal transmission between the first imaging control section 81 and the second imaging control section 82 can be appropriately performed by the second mode signal transmission of the second coupling section 72b.

[0128] Fig.10 : is a diagram for describing a configuration example of a first coupling portion of an imaging element according to the present embodiment. Fig.11: is a diagram showing an example of timing adjustment in the first coupling portion of the imaging element according to the embodiment. Fig.10 In the example shown in FIG. 1 , the imaging element 1 includes a clock signal generator 54. The flip-flop C10 of the column signal processor 112 outputs the data signal CH_DATA to the first signal processor 91 and the first coupling section 71 in synchronization with the clock signal VCK. The signal level (voltage) of the data signal CH_DATA transitions to a high level or a low level once every four transitions of the clock signal VCK, as shown in FIG. Fig.11 shown.

[0129] The clock signal generator 54 is configured to generate and output a clock signal. The clock signal generator 54 includes a flip-flop, an inverter, etc. The clock signal IFCK1 is input to the clock signal generator 54. In addition, a signal indicating the transition time (rising edge and falling edge) of the data signal CH_DATA is input to the clock signal generator 54 as an alignment signal S1.

[0130] The clock signal generator 54 changes the phase (output timing) of the clock signal IFCK1 according to the alignment signal S1 (phase matching signal). The phase of the clock signal IFCK1 is adjusted according to the timing of the alignment signal S1. Fig.11 As shown, the clock signal generator 54 outputs the clock signal IFCK2 having a frequency f2 (=f1 / 4) as the phase-adjusted clock signal. It can be said that the clock signal generator 54 regenerates the clock signal IFCK2 according to the phase adjustment of the data signal CH_DATA. It should be noted that the first coupling section 71 may include the clock signal generator 54.

[0131] The clock signal generator 54 provides the clock signal IFCK2 to the first output section 51 and the first input section 52 of the first coupling section 71. The phase-adjusted clock signal IFCK2 having the frequency f2 is input to each flip-flop C11 of the first output section 51 and each flip-flop C12 of the first input section 52. This allows the first coupling section 71 to transmit and receive the data signal CH_DATA according to the clock signal IFCK2 having the low frequency f2 according to the first mode signal transmission. This makes it possible to avoid the difficulty of skew timing adjustment and reduce the level of setting difficulty. Signal transmission between substrates can be appropriately performed.

[0132] Furthermore, in the present embodiment, the first output section 51 and the first input section 52 of the first coupling section 71 each include a plurality of buffer circuits. Fig. 12A 1 is a diagram showing an example of the configuration of the first coupling portion of the imaging element according to the present embodiment. The first coupling portion 71 includes a buffer 55, a buffer 56 ( Fig. 12ABuffers 56a to 56c) and buffer 57. Buffer 55, buffer 56 and buffer 57 may be arranged in one or both of the first output portion 51 and the first input portion 52.

[0133] exist Fig. 12A In the example shown, a plurality of buffers 56 are provided at predetermined intervals in the first coupling portion 71 extending in the X-axis direction. The buffers 56 are arranged at predetermined intervals from the position of the buffer 55 as a reference position (starting position), for example, as in Fig. 12A The buffer 55 is electrically connected to the buffers 56a to 56c, and outputs the clock signal CLK to the buffers 56a to 56c. The buffers 56a to 56c output the clock signal CLK input from the buffer 55 to the circuit of the third substrate 103.

[0134] In the imaging element 1, the clock signal can be branched and the branched signal can be transmitted through the plurality of buffers 56, and the non-common portion (non-common path) of the clock signal path can be shortened. This makes it possible to prevent difficulty in skew timing adjustment and to appropriately perform signal transmission at the interface between the second substrate 102 and the third substrate 103.

[0135] Fig. 12B is a diagram showing a configuration example of a first coupling portion of an imaging element according to a comparative example. In the comparative example, a clock signal is transmitted by a buffer 55 and a buffer 56, and a clock signal path is not divided. In this case, as Fig. 12B As shown, the non-shared path in the region R1 indicated by the dotted line is longer, and the number of buffers arranged in the region R1 increases, which leads to difficulty in skew timing adjustment.

[0136] On the contrary, in this embodiment, if Fig. 12A As shown, the non-shared path in region R1 is shortened by dividing the clock signal path, and the number of buffers in region R1 is reduced. This enables the flip-flop C16 of the third substrate 103 to correctly receive the data signal input from the flip-flop C15 through the buffer 57 according to the clock signal input from the buffer 56c.

[0137] [Work and Effect]

[0138] The imaging element (imaging element 1) according to the present embodiment includes: a first substrate (first substrate 101) including a plurality of photoelectric converters (photoelectric converters 12) each configured to generate charge by photoelectric conversion; a second substrate (second substrate 102) including a first signal processor (first signal processor 91) configured to obtain a signal based on the charge generated by the photoelectric converter and perform signal processing, and a third substrate (third substrate 103) stacked on the first substrate, the third substrate including a second signal processor (second signal processor 92) configured to perform signal processing, and the third substrate is stacked on the second substrate, a first coupling portion (first sample portion 71) provided with a plurality of first electrodes each coupling a circuit of the second substrate and a circuit of the third substrate, and a second coupling portion (second coupling portion 72) provided with a plurality of second electrodes each coupling a circuit of the second substrate and a circuit of the third substrate. The size of the first coupling portion is different from that of the second coupling portion.

[0139] In the imaging element 1 of the present embodiment, the first signal processor 91 and the second signal processor 92 are arranged on different substrates. In addition, the imaging element 1 has the first coupling portion 71 and the second coupling portion 72 that connect the circuit of the second substrate 102 including the first signal processor 91 and the circuit of the third substrate 103 including the second signal processor 92. This makes it possible to suppress an increase in chip area compared to a case where the first signal processor 91 and the second signal processor 92 are arranged on the same substrate.

[0140] Next, a modification of the present disclosure is described. Hereinafter, components similar to those of the above-described embodiment are denoted by the same reference numerals, and description thereof is appropriately omitted.

[0141] <2. Modifications>

[0142] (2-1. Modification 1)

[0143] Fig.13 1 is a diagram for describing a configuration example of an imaging element according to Modification 1. The imaging element 1 may include a compression section 75 and a decompression section 76 (not shown). The compression section 75 includes a compression circuit and is configured to be able to compress a signal. The decompression section 76 includes a decompression circuit and is configured to be able to decompress a signal, for example, Fig.13 As shown, the compression part 75 is provided on the second substrate 102. The decompression part 76 is provided on the third substrate 103. Fig.13 In the example shown in , the compression section 75 is provided between the AD converter 20 of the column signal processor 112 and the first signal processor 91. It should be noted that the compression section 75 may be arranged between the column signal processor 112 and the first coupling section 71.

[0144] The signal of each pixel converted into a digital signal is input from the column signal processor 112 to the compression section 75. The compression section 75 performs compression processing on the signal of each pixel, and outputs image data including the processed pixel signal to the first coupling section 71. The first coupling section 71 transmits the compressed image data to the circuit of the third substrate 103. The compressed image data is input from the first coupling section 71 to the decompression section 76 of the third substrate 103. The decompression section 76 performs decompression processing on the compressed image data, and outputs image data including the pixel signal that has been subjected to the processing to the second signal processor 92.

[0145] In this modification, the signal of each pixel is compressed by the compression section 75, input to the first coupling section 71, and transmitted to the third substrate 103. This makes it possible to reduce the number of signals transmitted by the first coupling section 71, and reduce the number of coupling electrodes 40 in the first coupling section 71, the number of triggers, etc. Fig.13 In the example shown in , it is possible to reduce the area of ​​the first coupling portion 71. Reducing the number of signals to be transmitted makes it possible to avoid difficulty in skew timing adjustment and reduce the level of difficulty in setting.

[0146] (2-2. Modification 2)

[0147] Fig.14 : is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 2. Fig.14 In the example shown, the first coupling section 71 includes an inverter 58. The inverter 58 can output an inverted signal of the input signal. The inverted signal of the clock signal IFCK is input from the inverter 58 to the trigger C12 of the first input section 52. This makes it possible to improve the holding time in the trigger C12. It should be noted that the second coupling section 72 may be provided with an inverter for inverting the clock signal. Even in this modification, the difficulty of skew timing adjustment can be prevented. The difficulty of setting the imaging element 1 can be reduced.

[0148] (2-3. Modification 3)

[0149] Fig.15A and Fig. 15B 2 are diagrams each showing a layout example of an imaging element according to Modification 3. Fig.15A The layout example in 101 represents a layout example in the second substrate 102 among the first substrate 101 to the third substrate 103. In addition, Fig. 15B The layout example in FIG. 1 represents a layout example in the third substrate 103. The first coupling portion 71 may be arranged separately in two or more stages. Fig.15A and Fig. 15BIn the example shown in , the first coupling portion 71 is arranged separately in two stages. In the first coupling portion 71, two electrode blocks each including a plurality of coupling electrodes 40 arranged side by side in the X-axis direction are arranged in the Y-axis direction. It can be said that the two electrode blocks are stacked in the vertical direction.

[0150] In this modification, the flexibility of design and layout can be improved by ensuring the space on the left and right sides of the first coupling portion 71. In addition, the wiring of signal wiring (such as data signal wiring and clock signal wiring) between circuits can be reduced and signal transmission can be performed efficiently. Fig. 15B In the example shown, the area where the third signal processor 93 is provided can be expanded (enlarged). Fig. 15B In the example shown, the second signal processor 92 and the second imaging controller 82 are arranged relatively close to the second coupling portion 72. Thus, signal transmission between the second signal processor 92 and the second coupling portion 72 and signal transmission between the second imaging controller 82 and the second coupling portion 72 can be efficiently performed.

[0151] (2-4. Modification 4)

[0152] Fig.16 4 is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 4. Fig.16 In the example shown in , transmission and reception of signals between the second substrate 102 and the third substrate 103 can be performed using a clock signal generated by a PLL (Phase Locked Loop) 160 provided on the third substrate 103 of the imaging element 1 .

[0153] The PLL 160 includes a phase synchronization circuit and is configured to generate and output a clock signal, which is a signal that repeats a high level and a low level. The PLL 160 generates a clock signal CK2 having a predetermined frequency based on a reference clock signal input from the outside, and provides the clock signal CK2 to the first coupling section 71. In this modification, the first input section 52 of the first coupling section 71 is provided with a plurality of asynchronous buffers 152 ( Fig.16 The asynchronous buffers 152a and 152b in FIG. 1 ). Each of the asynchronous buffers 152 is configured to be able to asynchronously perform, for example, data writing and data reading.

[0154] exist Fig.16In the example shown, the first input unit 52 includes an asynchronous buffer 152a and an asynchronous buffer 152b. The asynchronous buffer 152a and the asynchronous buffer 152b each include, for example, an asynchronous FIFO (first in first out) circuit. The asynchronous buffers 152a and 152b are each also referred to as an asynchronous buffer memory. In addition, the first input unit 52 includes a selector 151a and a selector 151b. The selector 151a has a selection circuit configured to output an input signal to the asynchronous buffers 152a and 152b. The selector 151b has a selection circuit that outputs a signal selected from the signals input from the asynchronous buffers 152a and 152b to the trigger C12.

[0155] The clock signal IFCK is input to the asynchronous buffer 152a and the asynchronous buffer 152b via the coupling electrode 40 from the second substrate 102 side. In addition, the clock signal CK2 is input to each of the asynchronous buffers 152a and 152b from the PLL 160. The asynchronous buffers 152a and 152b can perform writing (sampling) of the data signal from the flip-flop C11 in synchronization with the clock signal IFCK. In addition, the asynchronous buffers 152a and 152b can perform reading of the data signal to the selector 151b and the flip-flop C12 in synchronization with the clock signal CK2.

[0156] In the imaging element 1 of this modification, the signal transmission between the second substrate 102 and the third substrate 103 can also be performed by asynchronous communication using the asynchronous buffer 152. This makes it possible to set the frequency of the clock signal CK2 used in the circuits of the third substrate 103 (such as the second signal processor 92, the third signal processor 93, and the second imaging controller 82) independently of the clock signal IFCK. For example, the frequency of the clock signal CK2 can be increased to be higher than the frequency of the clock signal IFCK. This makes it possible to increase the processing speed in the logic circuit of the third substrate 103, etc.

[0157] (2-5. Modification 5)

[0158] Fig.17 1 is a diagram for describing a configuration example of an imaging element according to Modification 5. The imaging element 1 is configured to be able to perform signal transmission between the second substrate 102 and the third substrate 103 by asynchronous communication. For example, one or both of the first coupling portion 71 and the second coupling portion 72 may have Fig.17 The circuit configuration is schematically shown in . The use of asynchronous communication makes it relatively easy to perform skew timing adjustments.

[0159] exist Fig.17In the example shown in , the trigger C25 of the second substrate 102 outputs the data signal to the trigger C26 of the third substrate 103 according to the clock signal CK1. The trigger C26 of the third substrate 103 receives the data signal input from the trigger C25 according to the clock signal CK2. In the imaging element 1, for example, a signal that changes (transitions) only once during one frame can be sent and received by asynchronous communication. In this modification, the area of ​​the circuit for synchronous communication, the number of through electrodes, etc. can be reduced.

[0160] Fig.18A 2 is a diagram for describing a configuration example of a first coupling portion of an imaging element according to Modification 5. Fig.18B : is a timing chart for describing an operation example of the first coupling section of the imaging element according to Modification 5. Fig.18A An example is shown in which the first coupling section 71 is configured to be able to perform asynchronous communication. Note that the second coupling section 72 may be configured to be able to perform asynchronous communication.

[0161] In the example of FIG. 18 , the flip-flop C11b of the first output section 51 samples the latch pulse (Latch_Pulse) in synchronization with the clock signal CK1 and outputs the latch pulse to the first input section 52, as shown in FIG. Fig.18B As shown by the dotted line L1 in the timing diagram of FIG. 1 . The latch pulse is input as an enable signal to the flip-flop C11a of the first output section 51. When the latch pulse is at a high level, the flip-flop C11a samples the signal Data which is a data signal synchronized with the clock signal CK1, and outputs the signal Data to the first input section 52, as shown in FIG. Fig.18B As shown by the dotted line L2 in FIG.

[0162] The signal Data is input from the flip-flop C11a of the first output section 51 to the flip-flop C12 of the first input section 52. In addition, a latch pulse is input as an enable signal from the flip-flop C11b to the flip-flop C12 through the delay circuit 153. The delay circuit 153 includes, for example, a delay buffer and includes a flip-flop. In addition, a clock signal CK2 different from the clock signal CK1 is input to the flip-flop C12.

[0163] For example, when the latch pulse is at a high level, the flip-flop C12 can sample the signal Data in synchronization with the clock signal CK2 and output the signal Data to a circuit outside the first coupling portion 71. Thus, in the imaging element 1, the latch pulse and the data signal can be sent and received between the second substrate 102 and the third substrate 103, and asynchronous communication can be performed. Using asynchronous communication makes it relatively easy to perform skew timing adjustment.

[0164] <3. Usage examples>

[0165] The above-described imaging element 1 and electronic device 10 can be used in various cases of sensing light, such as visible light, infrared light, ultraviolet light, and X-rays, as follows.

[0166] - a device for capturing images for viewing, such as a digital camera or a mobile device each having a camera function;

[0167] - Devices used in traffic, such as on-vehicle sensors that capture images of the front, rear, surroundings, interior, etc. of a car for safe driving (such as automatic stop) and for identifying the driver's state, monitoring imaging machines that monitor traveling vehicles and roads, or distance measurement sensors that measure the distance between vehicles;

[0168] - A device used in household appliances (such as televisions, refrigerators, or air conditioners) to capture images of user gestures and operate the appliance based on the gestures

[0169] - Devices for medical care and health care purposes, such as endoscopes or devices that take images of blood vessels by receiving infrared light

[0170] -Devices used for security purposes, such as surveillance cameras for crime prevention or cameras for personal authentication

[0171] - Devices for cosmetic purposes, such as skin measurement devices that take images of the skin or microscopes that take images of the scalp

[0172] -Devices for sports use, such as action cameras or wearable cameras for sports applications

[0173] -Agricultural devices, such as cameras used to monitor the condition of fields and crops

[0174] <4. Application Examples>

[0175] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the imaging element 1 and the like can be applied to any of various electronic devices (such as cameras or mobile phones) having an imaging function. Application of the technology according to the present disclosure makes it possible to miniaturize electronic devices.

[0176] Although the present disclosure has been described with reference to the embodiments, variations, use examples, and application examples, the present disclosure is not limited to the above-mentioned embodiments, etc., and can be modified in various ways. For example, the above-mentioned modifications have been described as modifications of the above-mentioned embodiments; however, the configurations of the respective modifications can be appropriately combined.

[0177] An imaging element according to an embodiment of the present disclosure includes a first substrate, a second substrate, a third substrate, a first coupling portion, and a second coupling portion. The first substrate includes a plurality of photoelectric converters, each of which is configured to generate charges by photoelectric conversion. The second substrate includes a first signal processor configured to obtain a signal based on the charge generated by the photoelectric converter and perform signal processing, and the second substrate is stacked on the first substrate. The third substrate includes a second signal processor configured to perform signal processing and is stacked on the second substrate. The first coupling portion is provided with a plurality of first electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The second coupling portion is provided with a plurality of second electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The size of the first coupling portion is different from the size of the second coupling portion. Thus, the increase in the chip area of ​​the imaging element can be suppressed.

[0178] An electronic device according to an embodiment of the present disclosure includes a first substrate, a second substrate, a third substrate, a first coupling portion, and a second coupling portion. The first substrate includes a plurality of photoelectric converters, each of which is configured to generate a charge by photoelectric conversion. The second substrate includes a first signal processor configured to obtain a signal based on the charge generated by the photoelectric converter and perform signal processing, and the second substrate is stacked on the first substrate. The third substrate includes a second signal processor configured to perform signal processing and is stacked on the second substrate. The first coupling portion is provided with a plurality of first electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The second coupling portion is provided with a plurality of second electrodes, each of which couples a circuit of the second substrate and a circuit of the third substrate. The size of the first coupling portion is different from the size of the second coupling portion. This makes it possible to realize an electronic device that can suppress the increase in chip area.

[0179] It should be noted that the effects described herein are merely exemplary and are not limited to the description, and may further include other effects. In addition, the present disclosure may also have the following configurations. (1)

[0181] A light detection device, comprising:

[0182] A first substrate including a plurality of photoelectric converters configured to generate charges by photoelectric conversion;

[0183] a second substrate including a first signal processor configured to perform first signal processing to generate a signal based on the charges generated by the plurality of photoelectric converters, the second substrate being stacked on the first substrate;

[0184] a third substrate including a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate;

[0185] A first coupling portion including a plurality of first electrodes, wherein the plurality of first electrodes couple the circuit of the second substrate and the circuit of the third substrate; and

[0186] The second coupling portion includes a plurality of second electrodes, wherein the plurality of second electrodes couple the circuit of the second substrate and the circuit of the third substrate,

[0187] In a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion. (2)

[0189] The light detecting device according to (1), wherein the plurality of photoelectric converters are arranged on the first substrate in a first direction and in a second direction orthogonal to the first direction. (3)

[0191] The light detection device according to (1) or (2), wherein:

[0192] A plurality of first electrodes are arranged side by side in a first direction, and

[0193] A plurality of second electrodes are arranged side by side in the first direction. (4)

[0195] The light detecting device according to any one of (1) to (3), wherein a length of the first coupling portion in the first direction is different from a length of the second coupling portion in the first direction. (5)

[0197] The light detecting device according to any one of (1) to (4), wherein at least a portion of the first signal processor is arranged between the first coupling portion and the second coupling portion in a plan view. (6)

[0199] The light detection device according to any one of (1) to (5), wherein:

[0200] The first substrate includes a plurality of pixels, each of the plurality of pixels including a photoelectric converter among the plurality of photoelectric converters and configured to output an analog signal based on charges generated by photoelectric conversion; and

[0201] The second substrate includes an analog-to-digital converter configured to convert an analog signal output from the pixel into a digital signal. (7)

[0203] The light detection device according to any one of (1) to (6), wherein:

[0204] The first signal processor is configured to perform first signal processing based on the charges generated by the plurality of photoelectric converters to generate a first digital signal, and

[0205] The second signal processor is configured to perform second signal processing to generate a second digital signal based on the signal from the first coupling section, the signal being based on the charges generated by the plurality of photoelectric converters. (8)

[0207] The light detection device according to (6), wherein the first coupling section is arranged between the analog-to-digital converter and the first signal processor in a plan view. (9)

[0209] The light detecting device according to any one of (1) to (7), wherein the second coupling portion is arranged on an opposite side of the first coupling portion with respect to the first signal processor in a plan view. (10)

[0211] The light detection device according to any one of (1) to (9), wherein:

[0212] The plurality of first electrodes are arranged in two or more rows. (11)

[0214] The light detection device according to any one of (1) to (10), further comprising:

[0215] a compression section disposed on the second substrate and configured to compress a signal; and

[0216] a decompression unit, arranged on the third substrate and configured to decompress the compressed signal,

[0217] The first coupling portion is configured to transmit the compressed signal compressed by the compression portion to the decompression portion. (12)

[0219] The light detection device according to (11), wherein the compression section is arranged between the analog-to-digital converter and the first signal processor. (13)

[0221] The light detection device according to any one of (1) to (12), further comprising:

[0222] a third signal processor disposed on a third substrate,

[0223] The third signal processor is configured to perform third signal processing to generate a third digital signal based on the charges generated by the plurality of photoelectric converters through the second coupling portion. (14)

[0225] The light detection device according to (13), wherein the third signal processor is configured to perform recognition processing based on the third digital signal. (15)

[0227] The light detecting device according to (13) or (14), wherein the first coupling section is arranged between the second signal processor and the third signal processor in a plan view. (16)

[0229] The light detecting device according to any one of (13) to (15), wherein the second coupling portion is arranged on a side opposite to the first coupling portion with respect to the third signal processor in a plan view. (17)

[0231] An optical detection device according to any one of (1) to (16), wherein the second coupling portion includes at least one of a first converter or a second converter, the first converter is configured to convert a serial signal into a parallel signal, and the second converter is configured to convert a parallel signal into a serial signal. (18)

[0233] The light detection device according to any one of (1) to (17), further comprising:

[0234] an interface portion disposed on the second substrate and configured to output at least one of a signal output from the first signal processor or a signal output from the second signal processor from the light detection device,

[0235] Wherein, in a plan view, the second coupling portion is arranged between the first signal processor and the interface portion. (19)

[0237] An optical detection device according to any one of (1) to (18), wherein each of a plurality of first electrodes and each of a plurality of second electrodes includes a through electrode, a first junction electrode, and a second junction electrode, the through electrode penetrates the second substrate, the first junction electrode is coupled to the through electrode, and the second junction electrode is coupled to the first junction electrode. (20)

[0239] An electronic device, comprising:

[0240] A first substrate including a plurality of photoelectric converters configured to generate charges by photoelectric conversion;

[0241] a second substrate including a first signal processor configured to perform first signal processing to generate a signal based on charges generated by the plurality of photoelectric converters, the second substrate being stacked on the first substrate;

[0242] a third substrate including a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate;

[0243] A first coupling portion including a plurality of first electrodes, wherein the plurality of first electrodes couple the circuit of the second substrate and the circuit of the third substrate; and

[0244] The second coupling portion includes a plurality of second electrodes, wherein the plurality of second electrodes couple the circuit of the second substrate and the circuit of the third substrate,

[0245] In a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion.

[0246] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0247] [Reference Numbers List]

[0248] 1 Imaging element

[0249] 10 Electronic devices

[0250] 12 Photoelectric converter

[0251] 71 first coupling portion

[0252] 72 second coupling portion

[0253] 91 First Signal Processor

[0254] 92 Second signal processor

[0255] 93 Third signal processor

[0256] 101 First Substrate

[0257] 102 Second substrate

[0258] 103 A third substrate.

Claims

1. A light detection device, comprising: a first substrate including a plurality of photoelectric converters configured to generate charges by photoelectric conversion; a second substrate including a first signal processor configured to perform first signal processing to generate a signal based on the charges generated by the plurality of photoelectric converters, the second substrate being stacked on the first substrate; a third substrate including a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate; A first coupling portion, comprising a plurality of first electrodes, wherein the plurality of first electrodes couple the circuit of the second substrate and the circuit of the third substrate; as well as a second coupling portion including a plurality of second electrodes, wherein the plurality of second electrodes couple the circuit of the second substrate and the circuit of the third substrate, In a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion.

2. The light detection device according to claim 1, wherein: The plurality of photoelectric converters are arranged on the first substrate in a first direction and a second direction orthogonal to the first direction.

3. The light detection device according to claim 1, wherein: The plurality of first electrodes are arranged side by side in a first direction, and The plurality of second electrodes are arranged side by side in the first direction.

4. The light detection device according to claim 3, wherein: A length of the first coupling portion in the first direction is different from a length of the second coupling portion in the first direction.

5. The light detection device according to claim 1, wherein: In the plan view, at least a portion of the first signal processor is arranged between the first coupling portion and the second coupling portion.

6. The light detection device according to claim 1, wherein: The first substrate includes a plurality of pixels, each of the plurality of pixels including one of a plurality of photoelectric converters and configured to output an analog signal based on the charge generated by photoelectric conversion; and The second substrate includes an analog-to-digital converter configured to convert the analog signal output from the pixel into a digital signal.

7. The light detection device according to claim 6, wherein: The first signal processor is configured to perform the first signal processing to generate a first digital signal based on the charges generated by the plurality of photoelectric converters, and The second signal processor is configured to perform the second signal processing to generate a second digital signal based on the signal from the first coupling portion, the signal being based on the charges generated by the plurality of photoelectric converters.

8. The light detection device according to claim 6, wherein: In the plan view, the first coupling portion is arranged between the analog-to-digital converter and the first signal processor.

9. The light detection device according to claim 8, wherein: The second coupling portion is arranged on an opposite side of the first coupling portion with respect to the first signal processor in the plan view.

10. The light detection device according to claim 3, wherein: The plurality of first electrodes are arranged in two or more rows.

11. The light detection device according to claim 6, further comprising: a compression section disposed on the second substrate and configured to compress a signal; as well as a decompression unit, arranged on the third substrate and configured to decompress the compressed signal, The first coupling portion is configured to transmit the compressed signal compressed by the compression portion to the decompression portion.

12. The light detection device according to claim 11, wherein The compression section is arranged between the analog-to-digital converter and the first signal processor.

13. The light detection device according to claim 1, further comprising: a third signal processor disposed on the third substrate, The third signal processor is configured to perform third signal processing to generate a third digital signal based on the charges generated by the plurality of photoelectric converters through the second coupling portion.

14. The light detection device according to claim 13, wherein: The third signal processor is configured to perform recognition processing based on the third digital signal.

15. The light detection device according to claim 13, wherein: In a plan view, the first coupling portion is arranged between the second signal processor and the third signal processor.

16. The light detection device according to claim 13, wherein: The second coupling portion is arranged on a side opposite to the first coupling portion with respect to the third signal processor in a plan view.

17. The light detection device according to claim 1, wherein: The second coupling portion includes at least one of a first converter configured to convert a serial signal into a parallel signal and a second converter configured to convert a parallel signal into a serial signal.

18. The light detection device of claim 1, further comprising: an interface section arranged on the second substrate and configured to output, from the light detection device, at least one of a signal output from the first signal processor and a signal output from the second signal processor, Wherein, in a plan view, the second coupling portion is arranged between the first signal processor and the interface portion.

19. The light detection device according to claim 1, wherein: Each of the plurality of first electrodes and each of the plurality of second electrodes includes a through electrode penetrating the second substrate, a first junction electrode coupled to the through electrode, and a second junction electrode coupled to the first junction electrode.

20. An electronic device, comprising: a first substrate including a plurality of photoelectric converters configured to generate charges by photoelectric conversion; a second substrate including a first signal processor configured to perform first signal processing to generate a signal based on the charges generated by the plurality of photoelectric converters, the second substrate being stacked on the first substrate; a third substrate including a second signal processor configured to perform second signal processing, the third substrate being stacked on the second substrate; A first coupling portion, comprising a plurality of first electrodes, wherein the plurality of first electrodes couple the circuit of the second substrate and the circuit of the third substrate; as well as a second coupling portion including a plurality of second electrodes, wherein the plurality of second electrodes couple the circuit of the second substrate and the circuit of the third substrate, In a plan view, an area of ​​the first coupling portion is different from an area of ​​the second coupling portion.

Images