Semiconductor structure, manufacturing method thereof and memory system

Abstract

A semiconductor structure and a manufacturing method thereof, and a memory system, the method comprising: forming a stack layer and a channel structure, the channel structure comprising a channel layer and a plug structure, the plug structure being located on a side of the channel layer close to a first surface and comprising an exposed surface; carrying out oxidation treatment on the exposed surface to form an oxide; forming an upper selection gate layer on the first surface; and forming an upper selection channel structure which penetrates through the upper selection gate layer along the stacking direction and extends to the plug structure.

Description

Semiconductor structure and manufacturing method thereof, and memory system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory system. Background Art

[0002] Three-dimensional memory (such as 3D NAND) is an emerging type of memory that vertically stacks multiple layers of memory cells. This technology enables the creation of storage devices with storage capacities several times greater than comparable NAND technologies. This technology allows for higher storage capacities to be accommodated in a smaller space, resulting in significant cost savings, reduced energy consumption, and significant performance improvements.

[0003] In 3D NAND, the select transistor corresponding to the upper select gate can be formed separately to accommodate a small-sized select transistor design and improve storage density. However, the bottom morphology of the select transistor manufactured by the existing method can cause potential drift, affecting the stability of the memory.

[0004] Summary of the Invention

[0005] The present application provides a semiconductor structure and a manufacturing method thereof, as well as a memory system, which can avoid potential drift caused by the bottom morphology of a selection tube, thereby improving the stability of the memory.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0007] forming a stacked layer and a channel structure, wherein the stacked layer includes a first surface, and the channel structure penetrates the stacked layer along a stacking direction and includes a channel layer and a plug structure electrically connected to the channel layer; the plug structure is located on a side of the channel layer close to the first surface and includes an exposed surface;

[0008] performing an oxidation treatment on the exposed surface to form an oxide on the exposed surface, wherein a surface of the oxide facing away from the plug structure protrudes from the first surface;

[0009] forming an upper selection gate layer on the first surface, the upper selection gate layer covering the oxide;

[0010] An upper selection channel structure is formed, wherein the upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure.

[0011] On the other hand, an embodiment of the present application further provides a semiconductor structure, including:

[0012] stacked structure;

[0013] a channel structure penetrating the stack structure along a stacking direction, the channel structure comprising a channel layer and a plug structure electrically connected to the channel layer, the plug structure being located on one side of the channel layer;

[0014] a protruding structure located on a side of the plug structure away from the channel layer, the protruding structure protruding toward the side away from the plug structure;

[0015] an upper selection gate layer located on a side of the stack structure close to the plug structure, the upper selection gate layer covering the protrusion structure;

[0016] An upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure.

[0017] On the other hand, an embodiment of the present application further provides a memory system, comprising at least one memory and a controller coupled to the memory, wherein the memory comprises at least one semiconductor structure as described above, and the controller is used to control the memory to store data.

[0018] The semiconductor structure, its manufacturing method, and memory system provided by the embodiments of the present application are formed by forming a stacked layer and a channel structure, the channel structure penetrates the stacked layer along the stacking direction, and includes a channel layer and a plug structure electrically connected to the channel layer; the plug structure is located on the side of the channel layer close to the first surface, and includes an exposed surface; the exposed surface is oxidized to form an oxide on the exposed surface, and the surface of the oxide facing away from the plug structure protrudes from the first surface; an upper selection gate layer is formed on the first surface, and the upper selection gate layer covers the oxide; an upper selection channel structure is formed, and the upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure, thereby avoiding the formation of a sharp angle between the upper selection channel structure in the upper selection gate layer and the bottom surface of the upper selection gate layer, thereby avoiding the problem of potential drift caused by excessive local electric field voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] FIG1 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0021] 2A to 2K are schematic cross-sectional views of a semiconductor structure according to an embodiment of the present application at different process steps;

[0022] FIG3A is a schematic diagram of the enlarged structure of the local area M1 in FIG2C ;

[0023] FIG3B is a schematic diagram of the enlarged structure of the local area M2 in FIG2D ;

[0024] FIG3C is a schematic diagram of the enlarged structure of the local area M3 in FIG2J ;

[0025] 4A to 4C are schematic cross-sectional views of another embodiment of the semiconductor structure according to different process steps;

[0026] 5A and 5B are schematic cross-sectional views of another semiconductor structure provided by an embodiment of the present application at different process steps;

[0027] FIG6 is a schematic diagram of the structure of an exemplary system provided in an embodiment of the present application;

[0028] FIG7 is a schematic structural diagram of an exemplary memory card provided in an embodiment of the present application;

[0029] FIG8 is a schematic structural diagram of an exemplary solid-state drive provided in an embodiment of the present application;

[0030] FIG9 is a schematic diagram of the structure of the memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The present application will be further described below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are intended only to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and are not intended to be exhaustive. All other examples obtained by persons of ordinary skill in the art without inventive effort are intended to fall within the scope of protection of this application.

[0032] In the description herein, it should be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting this application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0033] In this description, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0034] It will be understood that the meanings of “on,” “over,” and “over” in the description herein should be interpreted in the broadest manner, such that “on” not only means “on” something with no intervening features or layers (i.e., directly on something), but also includes “on” something with intervening features or layers.

[0035] The terms used herein are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural form. The meaning of "plurality" is two or more. It should also be understood that the terms "include" and / or "comprising" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0036] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, and a memory system.

[0037] Please refer to FIG1 , which is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. The method for manufacturing a semiconductor structure may include the following steps S101-S104, wherein:

[0038] Step S101. Forming a stacked layer and a channel structure, wherein the stacked layer includes a first surface, and the channel structure penetrates the stacked layer along a stacking direction and includes a channel layer and a plug structure electrically connected to the channel layer; the plug structure is located on a side of the channel layer close to the first surface and includes an exposed surface;

[0039] Step S102: performing an oxidation treatment on the exposed surface to form an oxide on the exposed surface, wherein a surface of the oxide facing away from the plug structure protrudes from the first surface;

[0040] Step S103. Forming an upper selection gate layer on the first surface, wherein the upper selection gate layer covers the oxide;

[0041] Step S104 . Form an upper selection channel structure, wherein the upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure.

[0042] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0043] Please refer to FIG. 2A to FIG. 2K , which are schematic cross-sectional views of the semiconductor structure 10 at different process steps provided in an embodiment of the present application. The above steps S101 to S104 will be further described below in conjunction with FIG. 2A to FIG. 2K , wherein:

[0044] Step S101. Form a stacked layer 11 and a channel structure 12, wherein the stacked layer 11 includes a first surface aa, the channel structure 12 penetrates the stacked layer 11 along the stacking direction Z, and includes a channel layer 121, and a plug structure 122 electrically connected to the channel layer 121; the plug structure 122 is located on a side of the channel layer 121 close to the first surface aa, and includes an exposed surface bb.

[0045] As shown in FIG. 2C , the channel layer 121 is made of polysilicon, and the plug structure 122 is made of a conductive material, such as polysilicon or any one or a combination of metal materials such as tungsten, cobalt, copper, and aluminum. The stacked layer 11 includes gate sacrificial layers 111 and gate spacer layers 112 alternately disposed with the gate sacrificial layers 111. The stacking direction z is the direction in which the gate sacrificial layers 111 and the gate spacer layers 112 are stacked.

[0046] The stacked layer 11 can be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate sacrificial layer 111 can be made of silicon nitride, and the gate spacer layer 112 can be made of silicon oxide. The gate spacer layers 112 can have different thicknesses; for example, the top gate spacer layer 112 can be thicker than the remaining gate spacer layers 112.

[0047] It is easy to understand that the stacked layer 11 is generally formed on the substrate 13, and the channel structure 12 penetrates the stacked layer 11 and extends into the substrate 13. The substrate 13 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), Group III-V compound semiconductor materials, Group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0048] In some embodiments, referring to FIG. 2A , FIG. 2B , and FIG. 2C , the above step S101 may specifically include:

[0049] forming a storage channel structure 12a penetrating the stacked layer 11 along a stacking direction z, wherein the storage channel structure 12a includes a channel layer 121 and a filling layer 123, wherein the channel layer 121 is disposed around the filling layer 123, and the stacked layer 11 includes the first surface aa;

[0050] removing a portion of the filling layer 123 close to the first surface aa in the storage channel structure 12a to obtain a gap H;

[0051] Depositing a layer of conductive material on the first surface aa, wherein the conductive material fills the gap H;

[0052] The conductive material outside the gap H is removed to form the plug structure 122 , thereby obtaining the channel structure 12 .

[0053] Among them, the filling layer 123 is located on the side of the channel layer 121 away from the stacked layer 11. The material of the filling layer 123 includes insulating materials, such as oxides such as silicon oxide, and the conductive material can be any one or a combination of metal materials such as polysilicon, tungsten, cobalt, copper, and aluminum.

[0054] Specifically, the void H can be formed by removing a portion of the filling layer 123 through dry or wet etching. The depth of the void H can be controlled by controlling the etching time and the etchant concentration. Excess conductive material can be removed through chemical mechanical polishing (CMP). The conductive material filled in the void H can serve as a plug structure 122, which is equivalent to forming the plug structure 122 at the end of the top of the storage channel structure 12a. The plug structure 122 and the storage channel structure 12a remaining after removing the portion of the filling layer 123 together serve as the channel structure 12.

[0055] It should be pointed out that, please continue to refer to Figures 2B, 2C and 3A. Figure 3A is an enlarged structural schematic diagram of the local area M1 in Figure 2C above. After the CMP process, the top of the plug structure 122 finally formed is recessed, mainly because the exposed surface bb in the plug structure 122 is recessed toward the side close to the filling layer 123.

[0056] In some embodiments, referring to FIG. 2A to FIG. 2C and FIG. 3A , the above step of “forming a storage channel structure 12 a penetrating the stacking layer 11 along the stacking direction z” may specifically include:

[0057] forming a storage channel hole penetrating the stacked layer 11 along the stacking direction z;

[0058] forming a storage function layer 124 on the inner wall of the storage channel hole;

[0059] forming a channel layer 121 on a side of the storage function layer 124 away from the inner wall;

[0060] A filling layer 123 is formed on a side of the channel layer 121 away from the storage function layer 124 , and the filling layer 123 fills the storage channel hole.

[0061] The storage function layer 124 may be an ONO film layer, i.e., its material includes silicon oxide, silicon nitride, and silicon oxide. The height of the storage function layer 124 in the channel structure 12 along the stacking direction z is greater than the height of the filling layer 123 in the channel structure 12 along the stacking direction z.

[0062] Step S102 : performing an oxidation treatment on the exposed surface bb to form an oxide Q on the exposed surface bb, wherein a surface of the oxide Q facing away from the plug structure 122 protrudes from the first surface aa.

[0063] The formation of oxide Q on the exposed surface bb primarily refers to oxidizing the exposed portion of plug structure 122 into oxide Q. Referring to Figures 2C and 2D, as well as Figure 3B, Figure 3B is an enlarged schematic diagram of the structure of local area M2 in Figure 2D. The material of oxide Q depends on the material of plug structure 122. For example, when plug structure 122 is made of polycrystalline silicon, oxide Q is silicon oxide. During the oxidation process, the volume of oxide Q continuously expands, thereby changing the top of plug structure 122 from a concave shape to a convex shape.

[0064] In some embodiments, to increase the oxidation rate, before oxidizing the exposed surface bb, the method for manufacturing the semiconductor structure 10 may further include: performing a doping treatment on the exposed surface bb. Ions that promote oxidation may be doped, and a higher doping concentration results in a faster formation of the oxide Q and a larger volume expansion.

[0065] Step S103 . Form an upper selection gate layer 14 on the first surface aa, wherein the upper selection gate layer 14 covers the oxide Q.

[0066] 2D , 2E , and 2F , the upper select gate layer 14 may indirectly cover the oxide Q, meaning that another film layer may be disposed between the upper select gate layer 14 and the oxide Q. The upper select gate layer 14 is made of a conductive material such as polysilicon and is typically thicker along the stacking direction z.

[0067] Specifically, before the above step S103, the method for manufacturing the semiconductor structure 10 may further include:

[0068] An etch stop layer 15 is formed on the first surface aa, and the etch stop layer 15 covers the oxide Q.

[0069] At this time, the oxide Q and the etch stop layer 15 between the oxide Q and the upper selection gate layer 14 can serve as the protruding structure 17 . The above step S103 can specifically include: forming the upper selection gate layer 14 on the side of the etch stop layer 15 away from the stacked layer 11 .

[0070] After forming the oxide Q, an etch stop layer 15 may be formed first, and then the upper select gate layer 14 may be formed. The material of the etch stop layer 15 may include an insulating material such as silicon oxide, which is generally different from the material of the upper select gate layer 14. Typically, the thickness of the etch stop layer 15 along the stacking direction z is relatively small, for example, its thickness is smaller than the thickness of the upper select gate layer 14 along the stacking direction z and the thickness of the top gate spacer layer 112 along the stacking direction z.

[0071] In some embodiments, the upper select gate layer 14 can directly cover the oxide Q, that is, no other film layer is disposed between the upper select gate layer 14 and the oxide Q. For example, please continue to refer to FIG. 2D and FIG. 4A to FIG. 4C , which are schematic cross-sectional views of the semiconductor structure 10 at different process steps according to an embodiment of the present application. As can be seen from FIG. 2D and FIG. 4A , the upper select gate layer 14 can be directly formed after the oxide Q is formed. In this case, the oxide Q can directly serve as the protruding structure 17.

[0072] In some embodiments, please continue to refer to Figure 2F or Figure 4A, the top surface of the oxide Q protrudes from the top surface of the storage function layer 124, that is, the spacing distance between the surface of the oxide Q close to the upper selection gate layer 14 and the surface of the plug structure 122 close to the upper selection gate layer 14 is greater than the spacing distance between the surface of the storage function layer 124 close to the upper selection gate layer 14 and the surface of the plug structure 122 close to the upper selection gate layer 14.

[0073] In some embodiments, please continue to refer to Figure 2F or Figure 4A. In the channel structure 12, the top surface of the storage function layer 124 is higher than the top surface of the filling layer 123, that is, the spacing distance between the surface of the storage function layer 124 close to the upper selection gate layer 14 and the surface of the upper selection gate layer 14 away from the stacking layer 11 is smaller than the spacing distance between the surface of the filling layer 123 close to the upper selection gate layer 14 and the surface of the upper selection gate layer 14 away from the stacking layer 11.

[0074] Step S104 : forming an upper selection channel structure 16 , wherein the upper selection channel structure 16 penetrates the upper selection gate layer 14 along the stacking direction z and extends to the plug structure 122 .

[0075] 2G to 2J , or FIG. 4A and FIG. 4B , the upper selection channel structure 16 may include an insulating layer 161 and a conductive layer 162. The conductive layer 162 is located on a side of the insulating layer 161 facing away from the upper selection gate layer 14 and is electrically connected to the plug structure 122. The insulating layer 161 may be made of an oxide such as silicon oxide, and the conductive layer 162 may be made of any one or a combination of tungsten, cobalt, copper, aluminum, silicon, or doped crystalline silicon.

[0076] In some embodiments, the upper selection channel structure 16 can be obtained by first forming an etching hole that passes through the upper selection gate layer 14 along the stacking direction z and extends to the plug structure 122, then forming an insulating layer 161 on the sidewall of the etching hole, and then filling the conductive layer 162 in the etching hole.

[0077] In some embodiments, the upper selection channel structure 16 may also be formed in other ways. For example, referring to FIG. 2G to FIG. 2J , the step S104 may specifically include:

[0078] Using a first etching process, a first hole k1 is formed penetrating the upper selection gate layer 14 along the stacking direction z;

[0079] forming an insulating layer 161 on the inner wall of the first hole k1;

[0080] By performing a second etching process, a second hole k2 is formed through the first hole k1 , penetrating the upper selection gate layer 14 and the insulating layer 161 along the stacking direction z and extending to the plug structure 122 ;

[0081] The second hole k2 is filled with a conductive layer 162 to obtain the upper selection channel structure 16 .

[0082] The first etch comprises a dry etch or a wet etch, which may use the etch stop layer 15 or the oxide Q as a stop layer for etching. The second etch comprises a punch etch. After the first etch, the first hole k1 not only penetrates the upper select gate layer 14 but also typically extends into the etch stop layer 15, as shown in FIG. 2H , or into the oxide Q, as shown in FIG. 4A and FIG. 4B .

[0083] Typically, the upper selection channel structure 16 has a maximum size in the upper selection gate layer 14, that is, the size (such as width) of the upper selection channel structure 16 along the first direction x in the upper selection gate layer 14 is greater than the size (such as width) of the rest of the upper selection channel structure 16 along the first direction x. The first direction x can be the extension direction of the stacked layer 11, which is perpendicular to the stacking direction z of the stacked layer 11.

[0084] It should be noted that, please continue to refer to Figures 2J and 3C. Figure 3C is an enlarged structural diagram of the local area M3 in Figure 2J. Since the top of the oxide Q is in a convex shape, when the upper selection gate layer 14 is formed, this convex shape will directly or indirectly affect the upper selection gate layer 14. For example, the upper selection gate layer 14 includes a second surface cc close to the first surface aa, and the second surface cc includes a recessed area corresponding to the position of the oxide Q. The second surface cc of the recessed area is recessed along the first surface aa toward the second surface cc, which is equivalent to the convex shape of the top of the oxide Q. It is transferred to the upper selection gate layer 14, so that the angle α between the upper selection channel structure 16 in the upper selection gate layer 14 and the surface of the upper selection gate layer 14 close to the stacking layer 11 is a right angle or an obtuse angle, that is, the angle α between the surface of the upper selection gate layer 14 close to the stacking layer 11 and the insulating layer 161 in the upper selection gate layer 14 is not less than 90° (see FIG. 3C for details), thereby avoiding the formation of a sharp angle (acute angle) between the upper selection channel structure 16 and the upper selection gate layer 14, and further avoiding the technical problem of excessive local electric field voltage and potential drift caused by the sharp angle.

[0085] In other embodiments, please refer to Figures 5A and 5B, which are schematic cross-sectional views of another semiconductor structure 20 provided in an embodiment of the present application, wherein the semiconductor structure 20 includes a stacked layer 21, a channel structure 22 extending through the stacked layer 21 in a stacking direction, an etch stop layer 23 located on the stacked layer 21 and covering the channel structure 22, an upper select gate layer 24 located on a side of the etch stop layer 23 facing away from the stacked layer 21, and a channel structure 22 extending through the stacked layer 21 in a stacking direction. 24 and an upper selection channel structure 25 of the etch stop layer 23, wherein the channel structure 22 includes a channel layer 221 and a plug structure 222 electrically connected to the channel layer 221, the upper selection channel structure 25 includes a conductive layer 251 and an insulating layer 252 surrounding the conductive layer 251, the plug structure 222 is located on a side of the channel structure 22 close to the etch stop layer 23, and the conductive layer 251 in the upper selection channel structure 25 extends to the plug structure 222 and is electrically connected to the plug structure 222.

[0086] As can be seen from the above step S101, when forming the plug structure 222, the wet etching in the CMP will cause a depression to be formed on the top of the plug structure 222, and this depression will be transferred to the etch stop layer 23, causing the top of the etch stop layer 23 to also form a depression, while the bottom of the etch stop layer 23 will bulge toward the plug structure 222. The depression at the top of the etch stop layer 23 will further affect the upper selection gate layer 24, causing the bottom of the upper selection gate layer 24 to protrude toward the plug structure 222, thereby causing the angle β between the upper selection channel structure 25 and the bottom surface of the upper selection gate layer 24 to be an acute angle less than 90°, that is, a sharp angle. Once voltage is subsequently applied to the upper selection gate layer 24, the source, and the drain, a large concentrated electric field is likely to be generated at the sharp corner, thereby causing potential drift, which cannot solve the technical problem raised in this application. Moreover, since the thickness of the etch stop layer 23 and the insulating layer 252 is not very thick, the large local electric field at the sharp corner is likely to break through the etch stop layer 23 and the insulating layer 252, thereby affecting the performance of the memory.

[0087] The semiconductor structure 10 in the embodiment of the present application at least partially solves the above-mentioned technical problems. Referring to Figures 2I and 4C , after the plug structure 122 is formed, a volume-expanding oxide Q is formed on the top surface of the plug structure 122 through oxidation, causing the top of the plug structure 122 to change from a concave shape to a convex shape. Consequently, when the upper select gate layer 24 is subsequently formed, this convex shape directly or indirectly affects the bottom surface of the upper select gate layer 24, causing the bottom surface of the upper select gate layer 24 to become concave in a direction away from the stacked layer 11. This, in turn, causes the angle α between the upper select channel structure 16 and the bottom surface of the upper select gate layer 14 to be a right angle or an obtuse angle (rather than the sharp angle β shown in Figure 5B ). This minimizes the potential drift caused by the sharp angle, which can lead to excessive local electric field voltage and breakdown of the etch stop layer 15 and the insulating layer 161.

[0088] It should be noted that, please continue to refer to Figures 2J and 2K, or refer to Figures 4B and 4C. Figure 4C is another cross-sectional structural schematic diagram of the semiconductor structure 10 provided in an embodiment of the present application. After the above-mentioned step S104, a gate line gap can be formed, and the gate sacrificial layer 111 can be replaced by the gate through the gate line gap to obtain a gate layer 111a, and the replaced stacked layer 11 can be used as a stacked structure 11a.

[0089] The embodiment of the present application also provides a semiconductor structure 10, please continue to refer to Figures 2K and 4C, wherein the semiconductor structure 10 includes a stacked structure 11a; a channel structure 12 that penetrates the stacked structure 11a along the stacking direction z, the channel structure 12 includes a channel layer 121, and a plug structure 122 electrically connected to the channel layer 121, the plug structure 122 is located on one side of the channel layer 121; a protruding structure 17 located on the side of the plug structure 122 away from the channel layer 121, the protruding structure 17 protrudes toward the side away from the plug structure 122; an upper selection gate layer 14 located on the side of the stacked structure 11a close to the plug structure 122, the upper selection gate layer 14 covering the protruding structure 17; and an upper selection channel structure 16 that penetrates the upper selection gate layer 14 along the stacking direction z and extends to the plug structure 122.

[0090] The channel layer 121 is made of polysilicon, and the plug structure 122 is made of a conductive material, such as polysilicon, or any one or a combination of metal materials such as tungsten, cobalt, copper, and aluminum. The stacked structure 11a includes gate layers 111a and gate spacer layers 112 alternately arranged with the gate layers 111a. The stacking direction z is the direction in which the gate layers 111a and the gate spacer layers 112 are stacked. The gate layer 111a is made of polysilicon, tungsten, copper, and the like. The upper select gate layer 14 is made of polysilicon, for example.

[0091] In some embodiments, please continue to refer to Figure 2K, the semiconductor structure 10 also includes an etch stop layer 15, the etch stop layer 15 is located on the side of the stack structure 11a close to the plug structure 122, the upper selection gate layer 14 is located on the side of the etch stop layer 15 away from the stack structure 11a, and the protruding structure 17 includes the etch stop layer 15 corresponding to the position of the plug structure 122.

[0092] The material of the etch stop layer 15 may include an insulating material such as silicon oxide, which is generally different from the material of the upper select gate layer 14. Generally, the thickness of the etch stop layer 15 along the stacking direction z is relatively small, for example, its thickness is smaller than the thickness of the upper select gate layer 14 along the stacking direction z and the thickness of the top gate spacer layer 112 along the stacking direction z.

[0093] In some embodiments, the protruding structure 17 may include oxide Q (see, for example, FIG. 4C ), and may also include an etch stop layer 15 between the oxide Q and the upper selection gate layer 14 , that is, an etch stop layer 15 corresponding to the position of the plug structure 122 (see, for example, FIG. 2K ).

[0094] In some embodiments, an angle between a surface of the protrusion structure 17 facing away from the plug structure 122 and the upper selection channel structure 16 in the upper selection gate layer 14 is not less than 90°.

[0095] In some embodiments, the upper selection channel structure 16 includes a conductive layer 162 and an insulating layer 161 arranged around the conductive layer 162, and the angle between the surface of the protruding structure 17 facing away from the plug structure 122 and the insulating layer 161 in the upper selection gate layer 14 is not less than 90°.

[0096] The material of the insulating layer 161 may include oxides such as silicon oxide, and the material of the conductive layer 162 may be any one or a combination of tungsten, cobalt, copper, aluminum, silicon, or doped crystalline silicon.

[0097] In some embodiments, the conductive layer 162 penetrates the upper selection gate layer 14 and the protruding structure 17 along the stacking direction z and extends to the plug structure 122 , and the insulating layer 161 penetrates the upper selection gate layer 14 along the stacking direction z and extends to connect with the protruding structure 17 .

[0098] In some embodiments, the dimension (e.g., width) of the upper selection channel structure 16 along the first direction x in the upper selection gate layer 14 is greater than the dimension (e.g., width) of the remaining portion of the upper selection channel structure 16 along the first direction x. The first direction x may be the extension direction of the stacking layer 11, which is perpendicular to the stacking direction z of the stacking structure 11a.

[0099] In some embodiments, the channel structure 12 also includes a storage function layer 124 and a filling layer 123, the channel layer 121 is arranged around the filling layer 123, and the storage function layer 124 is arranged around the channel layer 121, and the spacing distance between the surface of the storage function layer 124 close to the upper selection gate layer 14 and the surface of the upper selection gate layer 14 away from the stacking structure 11a is smaller than the spacing distance between the surface of the filling layer 123 close to the upper selection gate layer 14 and the surface of the upper selection gate layer 14 away from the stacking structure 11a.

[0100] The storage function layer 124 may be an ONO film layer, i.e., its material includes silicon oxide, silicon nitride, and silicon oxide. The distance between the surface of the plug structure 122 close to the upper select gate layer 14 and the surface of the upper select gate layer 14 facing away from the stacked structure 11a is greater than the distance between the surface of the storage function layer 124 close to the upper select gate layer 14 and the surface of the upper select gate layer 14 facing away from the stacked structure 11a.

[0101] In some embodiments, the spacing distance between the surface of the protrusion structure 17 close to the upper selection gate layer 14 and the surface of the plug structure 122 close to the upper selection gate layer 14 is greater than the spacing distance between the surface of the storage function layer 124 close to the upper selection gate layer 14 and the surface of the plug structure 122 close to the upper selection gate layer 14.

[0102] In some embodiments, a surface of the upper selection gate layer 14 on one side close to the stack structure 11 a includes a recessed region corresponding to the position of the protruding structure 17 , and the recessed region is recessed toward a side away from the stack structure 11 a .

[0103] It should be understood that the structures and manufacturing processes of the various components of the semiconductor structure 10 in the embodiment of the present application can refer to the above-mentioned embodiment of the manufacturing method of the semiconductor structure 10, and will not be repeated here.

[0104] In summary, the manufacturing method of the semiconductor structure 10 and the semiconductor structure 10 provided in the embodiment of the present application are formed by forming a stacked layer 11 and a channel structure 12, wherein the stacked layer 11 includes a first surface aa, and the channel structure 12 penetrates the stacked layer 11 along the stacking direction z and includes a channel layer 121 and a plug structure 122 electrically connected to the channel layer 121; the plug structure 122 is located on a side of the channel layer 121 close to the first surface aa, and includes an exposed surface bb; the exposed surface bb is oxidized to form an oxide Q on the exposed surface bb, and the The surface of the oxide Q facing away from the plug structure 122 protrudes from the first surface aa; an upper selection gate layer 14 is formed on the first surface aa, and the upper selection gate layer 14 covers the oxide Q; an upper selection channel structure 16 is formed, and the upper selection channel structure 16 passes through the upper selection gate layer 14 along the stacking direction z and extends to the plug structure 122, thereby avoiding the formation of a sharp angle between the upper selection channel structure 16 in the upper selection gate layer 14 and the bottom surface of the upper selection gate layer 14, thereby avoiding the problem of potential drift caused by excessive local electric field voltage, which is beneficial to improving the stability of the memory.

[0105] In addition, see Figure 6, Figure 6 is a structural diagram of an exemplary system 100 provided in an embodiment of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with a storage therein. As shown in Figure 6, system 100 may include a host 101 and a memory system 102, and memory system 102 includes one or more memories 1021 and a controller 1022. Host 101 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SOC) (e.g., an application processor (AP)) of an electronic device. Host 101 can be configured to send data to memory 1021 or receive data from memory 1021.

[0106] In the examples of the present application, the memory 1021 is not limited to a three-dimensional NAND memory. Without violating the disclosure or teachings of the present application, the memory 1021 can be implemented as various other types of non-volatile memories that can retain stored data when the power is disconnected.

[0107] In some embodiments, the controller 1022 is coupled to the memory 1021 and the host 101 and is configured to control the memory 1021, such as controlling the memory 1021 to perform data write and read operations. The controller 1022 can manage the data stored in the memory 1021 and communicate with the host 101. In some embodiments, the controller 1022 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 1022 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0108] The controller 1022 can be configured to control operations of the memory 1021, such as read, erase, and program operations. The controller 1022 can also be configured to manage various functions related to data stored or to be stored in the memory 1021, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 1022 is also configured to process error correction codes (ECC) on data read from or written to the memory 1021. The controller 1022 can also perform any other suitable functions, such as formatting the memory 1021. The controller 1022 can communicate with an external device (e.g., the host 101) according to a specific communication protocol. For example, the controller 1022 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Drive Electronic (IDE) protocol, Firewire protocol, etc.

[0109] The controller 1022 and one or more memories 1021 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of electronic products. In one example as shown in FIG7 , the controller 1022 and a single memory 1021 can be integrated into a memory card 200. The memory card 200 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 200 may also include a memory card connector 201 that couples the memory card 200 to a host (e.g., the host 101 in FIG6 ). In another example as shown in FIG8 , the controller 1022 and multiple memories 1021 can be integrated into an SSD 300. SSD 300 may also include an SSD connector 301 that couples SSD 300 to a host (eg, host 101 in FIG. 6 ). In some embodiments, the storage capacity and / or operating speed of SSD 300 is greater than that of memory card 200.

[0110] 9 is a schematic diagram of a memory 400 according to an embodiment of the present invention. The memory 400 includes any of the aforementioned semiconductor structures 10 and a peripheral circuit structure 401 coupled to the semiconductor structure 10. The peripheral circuit structure 401 can be configured to perform operations such as reading, writing, erasing, and verifying on the semiconductor structure 10.

[0111] In some embodiments, the peripheral circuit structure 401 may further include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, program verification logic, and an erase verification circuit, etc., which may perform the above operations according to the acquired computer program instructions. It should be noted that the peripheral circuit structure 401 and the semiconductor structure 10 may be stacked or tiled, and this is not limited here.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Forming a stacked layer and a channel structure, wherein the stacked layer includes a first surface, and the channel structure penetrates the stacked layer along a stacking direction and includes a channel layer and a plug structure electrically connected to the channel layer; The plug structure is located on a side of the channel layer close to the first surface and includes an exposed surface; performing an oxidation treatment on the exposed surface to form an oxide on the exposed surface, wherein a surface of the oxide facing away from the plug structure protrudes from the first surface; forming an upper selection gate layer on the first surface, the upper selection gate layer covering the oxide; An upper selection channel structure is formed, wherein the upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming an upper selection gate layer on the first surface, the method further includes: forming an etch stop layer on the first surface, wherein the etch stop layer covers the oxide; The forming of an upper selection gate layer on the first surface includes: forming the upper selection gate layer on a side of the etch stop layer away from the stacked layer.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: An angle between the upper selection channel structure in the upper selection gate layer and a surface of the upper selection gate layer close to the stacked layer is not less than 90°.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before the exposed surface is subjected to oxidation treatment, the method further comprises: The exposed surface is subjected to a doping treatment.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The upper selection gate layer includes a second surface close to the first surface, the second surface includes a recessed region corresponding to the position of the oxide, and the second surface of the recessed region is recessed in a direction from the first surface to the second surface.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the upper selection channel structure comprises: Using a first etching process, a first hole is formed penetrating the upper selection gate layer along the stacking direction; forming an insulating layer on an inner wall of the first hole; By using a second etching process, a second hole is formed through the first hole along the stacking direction, penetrating the upper selection gate layer and the insulating layer and extending to the plug structure; A conductive layer is filled in the second hole to obtain the upper selection channel structure.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: An angle between a surface of the upper selection gate layer close to the stacked layer and the insulating layer in the upper selection gate layer is not less than 90°.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the stacked layer and the channel structure comprises: forming a storage channel structure penetrating the stacked layer along a stacking direction, wherein the storage channel structure comprises a channel layer and a filling layer, wherein the channel layer is arranged around the filling layer, and the stacked layer comprises the first surface; Removing a portion of the filling layer close to the first surface in the storage channel structure to obtain a gap; Depositing a layer of conductive material on the first surface, wherein the conductive material fills the gap; The conductive material outside the gap is removed to form the plug structure, thereby obtaining the channel structure.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: The method of forming a storage channel structure penetrating the stacking layer along the stacking direction includes: forming a storage channel hole penetrating the stacked layer along the stacking direction; forming a storage function layer on the inner wall of the storage channel hole; forming a channel layer on a side of the storage functional layer away from the inner wall; A filling layer is formed on a side of the channel layer away from the storage function layer, and the filling layer fills the storage channel hole.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The spacing distance between the surface of the oxide close to the upper selection gate layer and the surface of the plug structure close to the upper selection gate layer is greater than the spacing distance between the surface of the storage functional layer close to the upper selection gate layer and the surface of the plug structure close to the upper selection gate layer.

11. A semiconductor structure comprising: Stacked structure; A channel structure penetrating the stack structure along a stacking direction, the channel structure comprising a channel layer and a plug structure electrically connected to the channel layer, the plug structure being located on one side of the channel layer; a protruding structure located at a side of the plug structure away from the channel layer, the protruding structure protruding toward the side away from the plug structure; an upper selection gate layer located on a side of the stack structure close to the plug structure, the upper selection gate layer covering the protrusion structure; An upper selection channel structure penetrates the upper selection gate layer along the stacking direction and extends to the plug structure.

12. The semiconductor structure according to claim 11, wherein: The semiconductor structure also includes an etch stop layer, which is located on a side of the stack structure close to the plug structure, the upper selection gate layer is located on a side of the etch stop layer away from the stack structure, and the protruding structure includes the etch stop layer corresponding to the position of the plug structure.

13. The semiconductor structure according to claim 11, wherein: An angle between a surface of the protruding structure facing away from the plug structure and the upper selection channel structure in the upper selection gate layer is not less than 90°.

14. The semiconductor structure according to claim 11, wherein: The upper selection channel structure includes a conductive layer and an insulating layer arranged around the conductive layer, and an angle between a surface of the protruding structure facing away from the plug structure and the insulating layer in the upper selection gate layer is not less than 90°.

15. The semiconductor structure according to claim 14, wherein: The conductive layer penetrates the upper selection gate layer and the protruding structure along the stacking direction and extends to the plug structure. The insulating layer penetrates the upper selection gate layer along the stacking direction and extends to connect with the protruding structure.

16. The semiconductor structure according to claim 11, wherein: A dimension of the upper selection channel structure in the upper selection gate layer along a first direction is greater than a dimension of a remaining portion of the upper selection channel structure along the first direction, and the first direction is perpendicular to the stacking direction.

17. The semiconductor structure according to claim 11, wherein: The channel structure also includes a storage functional layer and a filling layer, the channel layer is arranged around the filling layer, the storage functional layer is arranged around the channel layer, and the spacing distance between the surface of the storage functional layer close to the upper selection gate layer and the surface of the upper selection gate layer away from the stacking structure is smaller than the spacing distance between the surface of the filling layer close to the upper selection gate layer and the surface of the upper selection gate layer away from the stacking structure.

18. The semiconductor structure according to claim 17, wherein: The spacing distance between the surface of the protrusion structure close to the upper selection gate layer and the surface of the plug structure close to the upper selection gate layer is greater than the spacing distance between the surface of the storage function layer close to the upper selection gate layer and the surface of the plug structure close to the upper selection gate layer.

19. The semiconductor structure according to claim 17, wherein: The spacing distance between the surface of the plug structure close to the upper selection gate layer and the surface of the upper selection gate layer away from the stacking structure is greater than the spacing distance between the surface of the storage functional layer close to the upper selection gate layer and the surface of the upper selection gate layer away from the stacking structure.

20. The semiconductor structure according to claim 11, wherein: A surface of one side of the upper selection gate layer close to the stack structure includes a recessed area corresponding to the position of the protruding structure, and the recessed area is recessed toward a side away from the stack structure.

21. A memory system comprising at least one memory, wherein the memory comprises the semiconductor structure according to any one of claims 11 to 20, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

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