Metallized guide plate for probe card and manufacturing method thereof

Abstract

The invention discloses a metalized guide plate for a probe card and a manufacturing method thereof, and the method comprises the following steps: providing a substrate made of an insulating material, and carrying out the flattening of the two opposite side surfaces of the substrate; processing and drilling are conducted on the substrate, and a needle planting hole penetrating through the substrate is formed; performing photoetching on two opposite side surfaces of the substrate respectively to form photoresist layers; first conductive materials are deposited on the two opposite side surfaces of the substrate respectively, so that seed layers are formed on the inner wall surfaces of at least part of the needle planting holes and the two opposite side surfaces, corresponding to the at least part of the needle planting holes, of the substrate; electroplating a second conductive material on the surface of the seed layer to form an electroplated layer on the surface of the seed layer; and cleaning the substrate and removing the photoresist layer to obtain the metalized guide plate with the pattern circuit, so that the metalized guide plate has relatively high current resistance, and the stability of the probe card for high-current and high-power-consumption wafer test can be improved. The method is stable and controllable, high in yield and low in risk.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor wafer test probes, and in particular to a metallized guide plate for a probe card and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor wafer test probe technology, the probe card, as the electrical contact interface between the wafer chip to be tested and the test machine, is one of the key components that limit the performance of the test system. With the iteration of chip design technology, the demand for probe cards for testing wafers with high power consumption and high current is becoming more and more urgent. The probe card mainly includes a guide plate and a probe. The guide plate and the probe are key components that affect the current carrying capacity of the test chip. The guide plate is used to install the probe and limit the probe. The guide plate is mainly used as a template or carrier in the chip packaging process. It is used to ensure the precise alignment between the chip and the packaging material. In the integrated circuit design of semiconductor wafers, the distance between the centers of two adjacent identical elements (such as transistors, pads, contacts, etc.) on the chip (i.e., PITCH) has a direct impact on the performance, integration and production cost of the chip. Since PITCH is subject to process limitations, it cannot be reduced indefinitely, because this will lead to a significant increase in the complexity and cost of the manufacturing process. At the same time, the size of PITCH will also affect the design of the probe, because the probe needs to be precisely docked with these elements on the chip. Since the probe is a metal device that directly contacts the PAD (i.e., the pad on the chip, which is a metal area used in the test step of the chip manufacturing process and as the point where the chip is connected to the external circuit during the final packaging) on ​​the test wafer chip. If the PITCH is too small, the thickness and width of the probe will also be limited and cannot be increased indefinitely, otherwise it may affect the contact quality between the probe and the chip, and may even cause the probe to fail to properly contact the contact point on the chip. In the actual chip testing process, the probes on the probe card will contact the chip terminals on the wafer for electrical testing. These probes are usually arranged at a very narrow pitch, such as a pitch of 20 microns to 30 microns. The life of the probe depends not only on the service life, but also on the number of times the probe contacts the chip on the wafer. Therefore, the design and manufacture of the probe need to take these factors into account to ensure the accuracy and reliability of the test. Therefore, there is an urgent need for a manufacturing method for a metallized guide plate for a probe card to seek to improve the current resistance of the probe card and improve the stability of the wafer test with high power consumption and high current. Summary of the invention

[0003] In order to solve the above technical problems, an object of the present invention is to provide a method for manufacturing a metallized guide plate for a probe card and a metallized guide plate manufactured by the manufacturing method.

[0004] On the one hand, the present invention provides a method for manufacturing a metallized guide plate for a probe card, comprising the following steps: (1) providing a substrate made of an insulating material and flattening the two opposite surfaces of the substrate; (2) drilling the substrate to form a needle hole that penetrates the substrate and is used to implant a probe; (3) performing photolithography on the two opposite surfaces of the substrate to form a photoresist layer; (4) depositing a first conductive material on the two opposite surfaces of the substrate to form a seed layer on the inner wall surface of at least a portion of the needle hole and on the two opposite surfaces of the substrate corresponding to at least a portion of the needle hole; (5) electroplating a second conductive material on the surface of the seed layer to form an electroplated layer on the surface of the seed layer; and (6) cleaning the substrate and removing the photoresist layer to obtain a metallized guide plate with a graphic circuit.

[0005] According to an embodiment of the present invention, in the step (1), the insulating material includes one of sapphire, ceramic, silicon carbide and silicon nitride.

[0006] According to one embodiment of the present invention, in the step (1), the planarization process includes one of chemical mechanical polishing, glass reflow, spin coating, sputtering deposition, selective deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and thermal reflow; after the planarization treatment is performed on the surfaces of the two opposite sides of the substrate, the thickness of the substrate is 200 microns to 450 microns.

[0007] According to an embodiment of the present invention, in the step (2), the diameter of the needle implantation hole is 20 microns to 100 microns.

[0008] According to one embodiment of the present invention, in the step (3), when the two opposite surfaces of the substrate are photolithographically processed, the thickness of the photoresist layer formed is 15 micrometers, the exposure dose is 500 millijoules per square centimeter, and the development time is 50 seconds.

[0009] According to one embodiment of the present invention, in the step (4), at least one layer of the first conductive material is deposited on the two opposite surfaces of the substrate, or multiple layers of the first conductive material are deposited successively, and the first conductive material includes one or a composite of titanium, copper, gold, nickel, and chromium; the seed layer includes one of a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, and a nickel / copper / gold composite layer, and the thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers.

[0010] According to an embodiment of the present invention, in the step (5), the second conductive material includes one of rhodium, gold and silver, and the thickness of the electroplated layer is 2 microns to 5 microns.

[0011] According to one embodiment of the present invention, in the step (6), the substrate is ultrasonically cleaned using acetone, alcohol and deionized water in sequence, and each cleaning time is not less than 15 minutes.

[0012] On the other hand, the present invention also provides a metallized guide plate for a probe card manufactured by the method described in any one of the above-mentioned technical solutions, comprising: a substrate made of insulating material, the substrate being provided with a plurality of pin implanting holes penetrating the substrate and used for implanting probes; a graphic circuit comprising a conductive layer, the conductive layer being formed on at least a portion of the inner wall surface of the pin implanting holes and on the opposite side surfaces of the substrate corresponding to at least a portion of the pin implanting holes.

[0013] According to one embodiment of the present invention, the conductive layer includes a seed layer and an electroplating layer, the seed layer is made of a first conductive material, the seed layer is formed on at least a portion of the inner wall surface of the needle implanting hole and on two opposite side surfaces of the substrate corresponding to at least a portion of the needle implanting hole, and the electroplating layer is made of a second conductive material, and the electroplating layer is formed on the surface of the seed layer.

[0014] Compared with the prior art, the present invention has the following beneficial effects: By adopting the manufacturing method of the present invention, a seed layer and an electroplating layer are formed on the pin holes of the substrate and the surfaces on both sides by deposition and electroplating in sequence, so that a metallized guide plate with a preset graphic circuit can be obtained, and the process steps are stable and controllable, with high yield and low risk. The metallized guide plate obtained by the manufacturing method of the present invention connects at least part of the pin holes together through a conductive layer to form a graphic circuit, so that the part of the pin holes has a higher current resistance after the probe is implanted, which can improve the stability of the probe card for high-current, high-power wafer testing, and the part of the pin holes that the graphic circuit does not pass through are isolated and independent from each other. After the probe is implanted, the part of the pin holes can be used as a separate test probe, so that the probe card has a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 (a) to FIG. 1 (b) are schematic diagrams of step 1 of a method for manufacturing a metallized guide plate according to an embodiment of the present invention; Figure 2 is a schematic diagram of step 2 of the method for manufacturing a metallized guide plate; FIG. 3 (a) to FIG. 3 (b) are schematic diagrams of step 3 of the method for manufacturing a metallized guide plate; 4( a ) to 4 ( b ) are schematic diagrams of step 4 of the method for manufacturing a metallized guide plate; Figure 5 is a schematic diagram of step five of the method for manufacturing a metallized guide plate; Figure 6is a schematic diagram of step six of the method for manufacturing a metallized guide plate; Figure 7 It is a schematic plan view of a metalized guide plate according to an embodiment of the present invention.

[0016] The reference numerals are as follows: 100. Metalized guide plate; 10. substrate; 11. pinhole; 12. photoresist layer; 20. Graphic circuit; 2. Conductive layer; 21. Seed layer; 22. Electroplating layer. DETAILED DESCRIPTION

[0017] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a person skilled in the art can propose a variety of interchangeable structural modes and implementation modes. Therefore, the following specific implementation modes and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the whole of the present invention or as a limitation or restriction to the technical solution of the present invention.

[0018] An embodiment of the present invention provides a method for manufacturing a metallized guide plate 100 for a probe card, the method comprising the following steps: (1) providing a substrate 10 made of an insulating material, and performing a planarization process on two opposite surfaces of the substrate 10; (2) drilling the substrate 10 to form a needle implantation hole 11 that penetrates the substrate 10 and is used to implant the probe; (3) performing photolithography on two opposite sides of the substrate 10 to form a photoresist layer 12; (4) depositing a first conductive material on opposite side surfaces of the substrate 10 respectively, so as to form a seed layer 21 on the inner wall surface of at least a portion of the pin-implanting hole 11 and on opposite side surfaces of the substrate 10 corresponding to at least a portion of the pin-implanting hole 11; (5) electroplating a second conductive material on the surface of the seed layer 21 to form an electroplated layer 22 on the surface of the seed layer 21; (6) The substrate 10 is cleaned and the photoresist layer 12 is removed to obtain a metallized guide plate 100 with a graphic circuit 20.

[0019] The steps of the manufacturing method in the above embodiment of the present invention and the structural composition of the metallized guide plate 100 manufactured according to the manufacturing method are described in detail below with reference to the accompanying drawings.

[0020] As shown in FIG1 (a), a substrate 10 made of a ceramic material is provided, and the initial thickness D0 of the substrate 10 is 500 microns. In other embodiments, the substrate 10 may also be made of other insulating materials, such as sapphire, silicon carbide, silicon nitride, etc., and the initial thickness of the substrate 10 may also be selected in the range of 500 microns to 800 microns, without specific limitation.

[0021] As shown in FIG. 1 (b), the two opposite surfaces of the substrate 10 are planarized, and the process thickness D1 of the substrate 10 after the planarization process is 200 microns. Specifically, the two opposite surfaces of the substrate 10 are subjected to chemical mechanical polishing (CMP) treatment, and the substrate 10 is ground and polished to 200 microns. In other embodiments, other planarization processes may also be used, such as glass flow, spin-on glass (SOG), sputtering deposition, selective deposition, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), thermal reflow, etc., and the process thickness D1 of the substrate 10 after the planarization process can be controlled within the range of 200 microns to 450 microns, without specific limitation.

[0022] according to Figure 2 As shown, the substrate 10 is drilled to form a needle implantation hole 11 that penetrates the substrate 10 and is used to implant the probe. In this embodiment, the substrate 10 can be drilled using a laser rotary cutting drilling process, and the diameter of the needle implantation hole 11 formed is 20 microns. In other embodiments, the diameter of the needle implantation hole 11 can be controlled within a range of 20 microns to 100 microns, without specific limitation.

[0023] As shown in FIG3(a), a photoresist is coated on one side of the substrate 10 and photolithography is performed to form a photoresist layer 12. The thickness of the formed photoresist layer 12 is 15 micrometers, the exposure dose is 500 millijoules per square centimeter, and the development time is 50 seconds.

[0024] As shown in Fig. 3(b), a photoresist is coated on the other side of the substrate 10 and photolithography is performed to form a photoresist layer 12. The thickness of the formed photoresist layer 12 is 15 micrometers, the exposure dose is 500 millijoules per square centimeter, and the development time is 50 seconds.

[0025] As shown in FIG. 4 (a), a physical vapor deposition process (PVD) is used to sequentially deposit titanium / copper / gold materials on one side surface of the substrate 10 to form a seed layer 21 having a composite layer. The thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers. In other embodiments, other deposition processes may be used to deposit on one side surface of the substrate 10, such as chemical vapor deposition process (CVD), electrochemical deposition process (ECD), atomic layer deposition process (ALD), etc., and the deposited material is not limited to the composite layer material formed by sequentially depositing titanium / copper / gold, but may also be other first conductive materials, such as one or more composites of titanium, copper, gold, nickel, and chromium, and the deposited first conductive material is not limited to depositing only one layer, but may also be two or more layers alternately composited, such as a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, a nickel / copper / gold composite layer, etc., and the thickness of the seed layer 21 may be controlled within a range of 100 nanometers to 250 nanometers, without specific limitation.

[0026] As shown in FIG. 4 (b), a chemical vapor deposition process (CVD) is used to sequentially deposit titanium / copper / gold materials on the other side surface opposite to the substrate 10 to form a seed layer 21 having a composite layer. The thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers. In other embodiments, other deposition processes may be used to deposit on the other side surface opposite to the substrate 10, such as physical vapor deposition process (PVD), electrochemical deposition process (ECD), atomic layer deposition process (ALD), etc., and the deposited material is not limited to the composite layer material formed by sequentially depositing titanium / copper / gold, but may also be other first conductive materials, such as one or more composites of titanium, copper, gold, nickel, and chromium, and the deposited first conductive material is not limited to one layer, but may also be two or more layers alternately composited, such as a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, a nickel / copper / gold composite layer, etc., and the thickness of the seed layer 21 may be controlled within the range of 100 nanometers to 250 nanometers, without specific limitation.

[0027] according to Figure 5 As shown, the substrate 10 is electroplated to plate a layer of metal rhodium on the surface of the seed layer 21 of the substrate 10 as the electroplating layer 22, wherein the thickness of the electroplating layer 22 is 2 microns. In other embodiments, other second conductive materials, such as gold, silver and other metal materials with good conductivity, may also be plated on the surface of the seed layer 21, and the thickness of the electroplating layer 22 may be controlled to be 2 microns to 5 microns, without specific limitation.

[0028] according to Figure 6 As shown, the substrate 10 is ultrasonically cleaned with acetone, alcohol and deionized water in sequence, with each cleaning time being no less than 15 minutes, to remove the photoresist layer 12, thereby obtaining a metallized guide plate 100 with a graphic circuit 20.

[0029] By adopting the manufacturing method of the present invention, a conductive layer 2 is formed on the pin-implanting hole 11 of the substrate 10 and on the surfaces on both sides thereof by deposition and electroplating in sequence, and the conductive layer 2 includes a seed layer 21 and an electroplating layer 22. Thus, a metallized guide plate 100 with a preset graphic circuit 20 can be obtained. The process steps are stable and controllable, with high yield and low risk.

[0030] according to Figure 6 and Figure 7 As shown, after cleaning, you can get Figure 6 The cross-sectional structure of the metallized guide plate 100 is shown in FIG. After the probes are implanted in the part of the pin-implanting holes 11 through which the graphic circuit 20 passes, the probes are connected together through the graphic circuit 20, and the part of the pin-implanting holes 11 through which the graphic circuit 20 does not pass are isolated from each other, and after the probes are implanted in the part of the pin-implanting holes 11, each probe can be used as an independent test probe.

[0031] The metallized guide plate 100 manufactured by the steps of the above manufacturing method includes a substrate 10 and a graphic circuit 20. The substrate 10 is made of an insulating material, and a plurality of implantation holes 11 penetrating the substrate 10 and used for implanting probes are constructed on the substrate 10. The graphic circuit 20 includes a conductive layer 2, and the conductive layer includes a seed layer 21 and an electroplating layer 22, wherein the seed layer 21 is made of a first conductive material, and the seed layer 21 is formed on at least part of the inner wall of the implantation hole 11 and on the two opposite sides of the substrate 10 corresponding to at least part of the implantation hole 11, and the electroplating layer 22 is made of a second conductive material, and the electroplating layer 22 is formed on the surface of the seed layer 21. In other embodiments, the graphic circuit 20 can also be specifically designed, such as only selecting a part of the implantation holes 11 to lay the conductive layer 2 to form the graphic circuit 20, such as sequentially depositing and electroplating to form the seed layer 21 and the electroplating layer 22, and connecting these part of the implantation holes together through the graphic circuit 20, without specific limitation.

[0032] The metallized guide plate 100 manufactured by the manufacturing method of the present invention has a seed layer 21 deposited in a part of the pin holes and a plating layer 22 electroplated on the surface of the seed layer 21, so that the pin holes 11 in this part are connected together through the graphic circuit 20, and has high current resistance performance, which can improve the stability of the probe card for high-current, high-power wafer testing, and the pin holes 11 that the graphic circuit 20 does not pass through are isolated and independent from each other. After the probes are implanted, the pin holes 11 in this part can be used as separate test probes, so that the probe card has a wider range of application scenarios.

[0033] The technical scope of the present invention is not limited to the contents in the above description. Those skilled in the art can make various deformations and modifications to the above embodiments without departing from the technical idea of ​​the present invention, and these deformations and modifications should all fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a metallized guide plate for a probe card, characterized in that: The following steps are involved: (1) providing a substrate made of an insulating material and performing a planarization process on two opposite surfaces of the substrate; (2) drilling a hole in the substrate to form a needle hole that penetrates the substrate and is used to implant the probe; (3) performing photolithography on two opposite surfaces of the substrate to form a photoresist layer; (4) depositing a first conductive material on opposite side surfaces of the substrate respectively to form a seed layer on the inner wall surface of at least a portion of the pin implanting hole and on opposite side surfaces of the substrate corresponding to at least a portion of the pin implanting hole; (5) electroplating a second conductive material on the surface of the seed layer to form an electroplated layer on the surface of the seed layer; (6) Cleaning the substrate and removing the photoresist layer to obtain a metallized guide plate with a graphic circuit.

2. The method according to claim 1, characterized in that: In the step (1), the insulating material includes one of sapphire, ceramic, silicon carbide and silicon nitride.

3. The method according to claim 1, characterized in that: In the step (1), the planarization process includes one of chemical mechanical polishing, glass reflow, spin coating, sputtering deposition, selective deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and thermal reflow; after the planarization treatment is performed on the surfaces of the two opposite sides of the substrate, the thickness of the substrate is 200 μm to 450 μm.

4. The method according to claim 1, characterized in that: In the step (2), the diameter of the needle implantation hole is 20 microns to 100 microns.

5. The method according to claim 1, characterized in that: In the step (3), when photolithography is performed on the two opposite surfaces of the substrate, the thickness of the photoresist layer formed is 15 microns, the exposure dose is 500 millijoules per square centimeter, and the development time is 50 seconds.

6. The method according to claim 1, characterized in that: In the step (4), at least one layer of the first conductive material is deposited on the two opposite surfaces of the substrate, or multiple layers of the first conductive material are deposited successively, wherein the first conductive material comprises one or a composite of titanium, copper, gold, nickel, and chromium; the seed layer comprises one of a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, and a nickel / copper / gold composite layer, and the thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers.

7. The method according to claim 1, characterized in that: In the step (5), the second conductive material includes one of rhodium, gold and silver, and the thickness of the electroplated layer is 2 microns to 5 microns.

8. The method according to claim 1, characterized in that: In the step (6), the substrate is ultrasonically cleaned using acetone, alcohol and deionized water in sequence, with each cleaning time being no less than 15 minutes.

9. A metallized guide plate for a probe card, characterized in that: include: A substrate, made of insulating material, having a plurality of needle implantation holes penetrating through the substrate and used for implanting probes; The graphic circuit comprises a conductive layer, wherein the conductive layer is formed on at least a portion of the inner wall surface of the pin-implanting hole and on two opposite side surfaces of the substrate corresponding to at least a portion of the pin-implanting hole.

10. The method according to claim 9, characterized in that: The conductive layer includes a seed layer and an electroplating layer, wherein the seed layer is made of a first conductive material and is formed on at least part of the inner wall surface of the needle implanting hole and on two opposite sides of the substrate corresponding to at least part of the needle implanting hole, and the electroplating layer is made of a second conductive material and is formed on the surface of the seed layer.

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