A chip test circuit structure
By designing the chip test circuit structure, including memory and multiple circuits, and setting appropriate test modes, the problems of incomplete chip test path coverage and low operating frequency in the prior art are solved, and chip testing with high coverage and high frequency is achieved.
Patent Information
- Application Number
- CN202411886138.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2044-12-20
AI Technical Summary
The existing chip test paths are incomplete, resulting in low coverage of the test paths, and some paths cannot be measured at the frequency that the memory actually needs to run, and the introduction of too many logic devices reduces the chip operation frequency.
A chip test circuit structure is designed, including memory, function input circuit, MBIST input circuit, input selection circuit, function output circuit and MBIST output circuit. By setting the memory input interface test mode and the memory output port test mode, selecting appropriate input and output circuits, testing of all memory interface functional paths is realized, reducing the number of test vectors generated, and conducting full-speed testing at the frequency actually required by the memory.
Improves chip test path coverage and chip operation frequency, achieves full-speed testing, reduces circuit cost, and reduces the settings of logic devices on the output path.
Smart Images
Figure CN119335372B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing circuit structure. Background Art
[0002] During chip testing, the memory itself is usually tested through the MBIST (Memory Built-In Self-Test) circuit integrated inside the chip for testing semiconductor memory. Traditional chip testing tests the circuits around the memory by inserting a bypass circuit around the memory, and tests the memory interface by scanning the path. However, the MBIST circuit can only test the internal faults of the memory and cannot test the functional path of the memory interface. The introduction of the bypass circuit cannot truly reflect the path in the functional mode, and the introduction of logic devices such as multiplexers in the bypass circuit will increase the number of logic levels, further causing the timing to deteriorate. In addition, the scan path excludes the memory, and the clock frequency is very low, which cannot reach the frequency that the memory actually needs to run, and the frequency of the memory often determines the highest operating frequency of the chip. In summary, the existing chip test path coverage is incomplete, resulting in low chip test path coverage; some paths cannot be tested at the frequency that the memory actually needs to run, and the introduction of too many logic devices reduces the chip operating frequency. Summary of the invention
[0003] The present invention aims to provide a chip test circuit structure, which improves the chip test path coverage and chip operating frequency.
[0004] The present invention provides a chip test circuit structure, comprising a memory, a function input circuit, an MBIST input circuit, an input selection circuit, a function output circuit, and an MBIST output circuit. The MBIST input circuit and the MBIST output circuit are circuits integrated inside a chip for testing a semiconductor memory, and the function input circuit and the function output circuit are both combinational logic circuits.
[0005] The memory includes an input interface and an output interface;
[0006] The input selection circuit includes a first selection path and a second selection path, and the selection circuit is connected to the input interface of the memory;
[0007] Described function input circuit is connected to each other with described first selection path, described MBIST input circuit is connected to each other with described second selection path, and described function output circuit and MBIST output circuit are connected to each other with the output interface of memory respectively;
[0008] The chip test circuit structure includes a memory input interface test mode and a memory output port test mode;
[0009] When the chip test circuit structure is set to the memory input interface test mode, the first selection path of the input selection circuit is connected, and the function input circuit is selected as the current input circuit, and the MBIST output circuit is selected as the current output circuit;
[0010] When the chip test circuit structure is set to the memory output port test mode, the second selection path of the input selection circuit is connected, the MBIST input circuit is selected as the current input circuit, and the function output circuit is selected as the current output circuit.
[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a chip test circuit structure provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:
[0012] The chip test circuit structure of the present invention is provided with a memory input interface test mode and a memory output port test mode, and in the memory input interface test mode, a function input circuit is selected as a current input circuit, and an MBIST output circuit is selected as a current output circuit; in the memory output port test mode, an MBIST input circuit is selected as a current input circuit, and a function output circuit is selected as a current output circuit, so that the test of all memory interface function paths can be covered, the number of test vectors generated is reduced, and all tests pass through the memory, so that full-speed test is realized, and the chip frequency is improved. In addition, the chip test circuit structure of the present invention reduces the setting of logic devices such as selectors on the output path, and reduces the circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 A schematic diagram of a chip test circuit structure provided by an embodiment of the present invention;
[0015] Figure 2 A schematic diagram of the chip testing circuit structure provided in another embodiment of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0017] The embodiment of the present invention provides a chip test circuit structure, such as Figure 1 As shown, it includes a memory, a function input circuit, an MBIST input circuit, an input selection circuit, a function output circuit, and an MBIST output circuit. The MBIST input circuit and the MBIST output circuit are circuits integrated inside the chip for testing semiconductor memory, and the function input circuit and the function output circuit are both combinational logic circuits.
[0018] The memory includes an input interface and an output interface. The functional input circuit includes at least one input interface functional path. The functional output circuit includes at least one output interface functional path. In the embodiment of the present invention, the memory may be a random access memory (RAM) or a read-only memory (ROM). The input interface of the RAM includes a data input interface and an address input interface, and the input interface of the ROM includes only an address input interface.
[0019] The input selection circuit includes a first selection path and a second selection path, and the selection circuit is connected to the input interface of the memory. The selection circuit can be implemented based on a multiplexer (Multiplexer, MUX for short), and specifically, a two-input MUX can be set at each input interface, and each two-input MUX is provided with the first selection path and the second selection path.
[0020] The functional input circuit is connected to the first selection path, and the MBIST input circuit is connected to the second selection path. It should be noted that if the selection circuit can be implemented based on multiple two-input MUXs, the functional input circuit is connected to the first selection path of each two-input MUX, and the MBIST input circuit is connected to the first selection path of each two-input MUX.
[0021] Described function output circuit, MBIST output circuit are connected with the output interface of memory respectively, it should be noted that, in the prior art, it is necessary to access a multiplexer at the output interface, select different output paths under different modes, and different output paths include the path through the memory and the path without the memory. In the present application, it is not necessary to access a multiplexer at the input interface, reduce the number of stages of logic devices, further improve the frequency of chip operation, all test paths involved in the present application are through the memory, and the data of different output circuits are captured according to different modes later.
[0022] The chip test circuit structure includes a memory input interface test mode and a memory output port test mode.
[0023] When the chip test circuit structure is set to the memory input interface test mode, the first selection path of the input selection circuit is turned on, the functional input circuit is selected as the current input circuit, and the MBIST output circuit is selected as the current output circuit. That is, when the chip test circuit structure is set to the memory input interface test mode, the input of the memory is controlled by the input selection circuit, and the data in the memory is obtained by the MBIST output circuit, so as to realize the test of the input interface function path in the functional input circuit, and the test path all passes through the memory, so that the test path is operated at the required operating frequency of the memory, and the full-speed test is realized, thereby improving the chip operating frequency.
[0024] When the chip test circuit structure is set to the memory output port test mode, the second selection path of the input selection circuit is turned on, the MBIST input circuit is selected as the current input circuit, and the function output circuit is selected as the current output circuit. That is, when the chip test circuit structure is set to the memory output port test mode, the input of the memory is controlled by the MBIST input circuit, and the data in the memory is obtained by the function output circuit, so as to realize the test of the output interface function path in the function output circuit, and the test path all passes through the memory, so that the test path is operated at the required operating frequency of the memory, and the full-speed test is realized, thereby improving the chip operating frequency.
[0025] It should be noted that it is very difficult to test the memory input port and the memory output port at the same time through the same test vector, which will generate a lot of unnecessary overhead. The present invention isolates the chip test circuit structure into memory input port test and memory output port test by setting the memory input interface test mode and the memory output port test mode, thereby ensuring the efficient operation of the ATPG tool.
[0026] As an embodiment, a target input interface function path list can also be set for the chip test circuit structure, the target input interface function path list includes the target input interface function path in the functional input circuit connected to the memory input interface, and the target input interface function path is specifically arranged in order from large to small by the delay of static timing analysis, and the M input interface function paths are preset in the front. When the chip test circuit structure is set to the memory input interface test mode, the automatic test vector generation tool (ATPG) selects at least one target input interface function path from the target input interface function path list, and automatically generates a test vector based on the selected target input interface function path. The generated test vector is input into the memory through the selected target input interface function path, and a transition is created on the memory input interface to activate the fault. The target output data is captured through the MBIST output circuit, and the target output data is compared with the preset value. If they are consistent, the test passes, otherwise, the test fails, and the MBIST output circuit is connected to the output interface of the memory.
[0027] As an embodiment, a target output interface function path list can also be set for the chip test circuit structure. The target output interface function path list includes the target output interface function path in the functional output circuit connected to the memory output interface, and the target output interface function path is specifically arranged in order from large to small by the delay of static timing analysis, and the output interface function paths preset in front are N. An automatic test vector generation tool selects at least one target output interface function path from the target output interface function path list, and automatically generates a test vector based on the selected target output interface function path. The generated test vector is input into the memory through the MBIST input circuit connected to the memory input interface. A conversion is created at the output interface through the selected target output interface function path for activating a fault. Capture target output data, compare the target output data with a preset value, if consistent, the test passes, otherwise, the test fails.
[0028] As an example, Figure 2 As shown, the memory also includes a memory enable interface, and the chip test circuit structure also includes a first enable control circuit, the input end of the first enable control circuit is connected to the input selection circuit and the scan enable signal, and the output end of the first enable control circuit is connected to the memory enable interface.
[0029] During the loading phase (Scan Shift) of the test vector of the scan test, the scan enable signal is at the level of the loading mode, and the memory enable interface is set through the first enable control circuit to always be at an invalid level where the memory does not work, so that the memory does not work during the loading phase of the test vector of the scan test, thereby ensuring the stability of the data stored in the memory.
[0030] In the response data capture phase (Scan Capture) of the scan test, the scan enable signal is at the level of the capture mode, and the functional input circuit or the MBIST input circuit selected by the input selection circuit controls the first enable control circuit to set the memory enable interface to an effective level for normal operation of the memory during the memory operation period. When the memory enable interface is at an effective level for normal operation, read and write operations can be performed on the memory.
[0031] It should be noted that the first enabling control circuit can be implemented by a simple combination of logic devices to reduce circuit cost, which is described below through two specific implementations.
[0032] Implementation Method 1:
[0033] The level of the loading mode is a high level, the level of the capture mode is a low level, the first enable control circuit includes a first NOT gate and a first AND gate, the input selection circuit is connected to the first input pin of the first NOT gate, the scan enable signal is connected to the input pin of the first NOT gate, the output pin of the first NOT gate is connected to the second input pin of the first AND gate, and the single output pin of the first AND gate is connected to the memory enable interface.
[0034] When the scan enable signal is at a high level, it is flipped to a low level through the first NOT gate and serves as an input of the first AND gate, so that when the scan enable signal is at a high level, the output of the first AND gate must be a low level, thereby setting the memory enable interface to always be at a low level.
[0035] When the scan enable signal is at a low level, it is flipped to a high level through the first NOT gate and serves as an input of the first AND gate. At this time, the output of the first AND gate is completely controlled by another input, that is, the functional input circuit or the MBIST input circuit selected by the input selection circuit is controlled, and can be controlled according to specific operation requirements.
[0036] Implementation Method 2:
[0037] The level of the loading mode is a high level, the level of the capture mode is a low level, the first enable control circuit includes a second NOT gate and a first OR gate, the input selection circuit is connected to the first input pin of the first OR gate, the scan enable signal is connected to the second input pin of the first OR gate, the output pin of the first OR gate is connected to the input pin of the second NOT gate, and the output pin of the second NOT gate is connected to the memory enable interface.
[0038] When the scan enable signal is at a high level, the output of the first OR gate must be at a high level, and after being flipped through the second NOT gate, it must be at a low level, thereby setting the memory enable interface to always be at a low level.
[0039] When the scan enable signal is at a low level, the output of the first OR gate is completely controlled by another input, that is, the functional input circuit or the MBIST input circuit selected by the input selection circuit is controlled according to specific operation requirements.
[0040] As an example, Figure 2 As shown, the memory also includes a read-write enable interface, and the chip test circuit structure also includes a second enable control circuit, the input end of the second enable control circuit is connected to the input selection circuit and the scan enable signal, and the output end of the second enable control circuit is connected to the read-write enable interface.
[0041] It should be noted that, during the test vector loading phase of the scan test, the memory enable interface is always at an invalid level where the memory does not work, and thus no read or write operations are performed on the memory.
[0042] In the response data capture stage of the scan test, the scan enable signal is the level of the capture mode, and in the stage where the memory enable interface is a high level, the second enable control circuit is controlled by the function input circuit or the MBIST input circuit to set the write enable interface to be effective when performing a write operation, and to set the read-write enable interface to be effective when performing a read operation.
[0043] The read-write enable interface includes a pin shared by the read enable and the write enable; or includes two independent read enable pins or write enable pins. It should be noted that: Figure 2 The example shown is a read-write enable interface where the read enable and write enable share one pin.
[0044] It should be noted that the second enabling control circuit can be implemented by a simple combination of logic devices to reduce circuit cost, which is described below through two specific implementations.
[0045] Implementation Method 3:
[0046] The level of the loading mode is a high level, the level of the capture mode is a low level, the second enable control circuit includes a third NOT gate and a second AND gate, the input selection circuit is connected to the first input pin of the third NOT gate, the scan enable signal is connected to the input pin of the third NOT gate, the output pin of the third NOT gate is connected to the second input pin of the second AND gate, and the single output pin of the second AND gate is connected to the read and write enable interface.
[0047] When the scan enable signal is at a high level, it is flipped to a low level through the third NOT gate and serves as an input of the second AND gate, so that when the scan enable signal is at a high level, the output of the second AND gate must be a low level and no flipping will occur. At this time, the memory enable interface is always at a low level, so no read or write operations will be performed on the memory, further ensuring the stability of the data in the memory.
[0048] When the scan enable signal is at a low level, it is flipped to a high level through the third NOT gate and used as an input of the second AND gate. At this time, the output of the second AND gate is completely controlled by another input, that is, controlled by the functional input circuit or the MBIST input circuit selected by the input selection circuit, and can be controlled according to specific operation requirements.
[0049] Implementation Method 4:
[0050] The level of the loading mode is a high level, the level of the capture mode is a low level, the second enable control circuit includes a fourth NOT gate and a second OR gate, the input selection circuit is connected to the first input pin of the second OR gate, the scan enable signal is connected to the second input pin of the second OR gate, the output pin of the second OR gate is connected to the input pin of the fourth NOT gate, and the output pin of the fourth NOT gate is connected to the read and write enable interface.
[0051] When the scan enable signal is at a high level, the output of the second OR gate must be at a high level, and after being flipped through the fourth NOT gate, it must be at a low level, and no flipping will occur. At this time, the memory enable interface is always at a low level, so no read or write operations will be performed on the memory, further ensuring the stability of the data in the memory.
[0052] When the scan enable signal is at a low level, the output of the second OR gate is completely controlled by another input, that is, the functional input circuit or the MBIST input circuit selected by the input selection circuit is controlled according to specific operation requirements.
[0053] As an example, Figure 2 As shown, the memory further includes a clock interface for inputting a clock signal into the memory. The clock signal can be directly input into the clock interface based on an existing clock control method, which will not be described in detail here.
[0054] The chip test circuit structure of the embodiment of the present invention sets a memory input interface test mode and a memory output port test mode, and in the memory input interface test mode, selects the function input circuit as the current input circuit, and selects the MBIST output circuit as the current output circuit; in the memory output port test mode, selects the MBIST input circuit as the current input circuit, and selects the function output circuit as the current output circuit, which can cover the test of all memory interface function paths, reduces the number of test vectors generated, and all tests pass through the memory, realizes full-speed testing, and improves the chip frequency. In addition, the chip test circuit structure of the present invention reduces the setting of logic devices such as selectors on the output path, and reduces the circuit cost.
[0055] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.
Claims
1. A chip test circuit structure, characterized in that: It comprises a memory, a function input circuit, an MBIST input circuit, an input selection circuit, a function output circuit, and an MBIST output circuit, wherein the MBIST input circuit and the MBIST output circuit are circuits integrated inside the chip for testing a semiconductor memory, and the function input circuit and the function output circuit are both combinational logic circuits; The memory includes an input interface and an output interface; The input selection circuit includes a first selection path and a second selection path, and the input selection circuit is connected to the input interface of the memory; Described function input circuit is connected to each other with described first selection path, described MBIST input circuit is connected to each other with described second selection path, and described function output circuit and MBIST output circuit are connected to each other with the output interface of memory respectively; The chip test circuit structure includes a memory input interface test mode and a memory output port test mode; When the chip test circuit structure is set to the memory input interface test mode, the first selection path of the input selection circuit is connected, and the function input circuit is selected as the current input circuit, and the MBIST output circuit is selected as the current output circuit; When the chip test circuit structure is set to the memory output port test mode, the second selection path of the input selection circuit is connected, the MBIST input circuit is selected as the current input circuit, and the function output circuit is selected as the current output circuit.
2. The circuit structure according to claim 1, characterized in that: The memory further includes a memory enable interface, the chip test circuit structure further includes a first enable control circuit, an input end of the first enable control circuit is connected to an input selection circuit and a scan enable signal, and an output end of the first enable control circuit is connected to the memory enable interface; In the loading phase of the test vector of the scan test, the scan enable signal is at the level of the loading mode, and the memory enable interface is always set to an invalid level that the memory does not work through the first enable control circuit; In the response data capture phase of the scan test, the scan enable signal is at the level of the capture mode, and the functional input circuit or the MBIST input circuit selected by the input selection circuit controls the first enable control circuit to set the memory enable interface to an effective level for normal operation of the memory during the memory operation period.
3. The circuit structure according to claim 2, characterized in that: The level of the loading mode is a high level, the level of the capture mode is a low level, the first enable control circuit includes a first NOT gate and a first AND gate, the input selection circuit is connected to the first input pin of the first NOT gate, the scan enable signal is connected to the input pin of the first NOT gate, the output pin of the first NOT gate is connected to the second input pin of the first AND gate, and the single output pin of the first AND gate is connected to the memory enable interface.
4. The circuit structure according to claim 2, characterized in that: The level of the loading mode is a high level, the level of the capture mode is a low level, the first enable control circuit includes a second NOT gate and a first OR gate, the input selection circuit is connected to the first input pin of the first OR gate, the scan enable signal is connected to the second input pin of the first OR gate, the output pin of the first OR gate is connected to the input pin of the second NOT gate, and the output pin of the second NOT gate is connected to the memory enable interface.
5. The circuit structure according to claim 2, characterized in that: The memory further includes a read-write enable interface, the chip test circuit structure further includes a second enable control circuit, an input end of the second enable control circuit is connected to an input selection circuit and a scan enable signal, and an output end of the second enable control circuit is connected to the read-write enable interface; In the response data capture stage of the scan test, the scan enable signal is the level of the capture mode, and in the stage where the memory enable interface is a high level, the second enable control circuit is controlled by the function input circuit or the MBIST input circuit to set the write enable interface to be effective when performing a write operation, and to set the read-write enable interface to be effective when performing a read operation.
6. The circuit structure according to claim 5, characterized in that: The read-write enable interface includes a pin shared by the read enable and the write enable; or includes two independent read enable pins or write enable pins.
7. The circuit structure according to claim 5, characterized in that: The level of the loading mode is a high level, the level of the capture mode is a low level, the second enable control circuit includes a third NOT gate and a second AND gate, the input selection circuit is connected to the first input pin of the third NOT gate, the scan enable signal is connected to the input pin of the third NOT gate, the output pin of the third NOT gate is connected to the second input pin of the second AND gate, and the single output pin of the second AND gate is connected to the read and write enable interface.
8. The circuit structure according to claim 5, characterized in that: The level of the loading mode is a high level, the level of the capture mode is a low level, the second enable control circuit includes a fourth NOT gate and a second OR gate, the input selection circuit is connected to the first input pin of the second OR gate, the scan enable signal is connected to the second input pin of the second OR gate, the output pin of the second OR gate is connected to the input pin of the fourth NOT gate, and the output pin of the fourth NOT gate is connected to the read and write enable interface.
9. The circuit structure according to claim 1, characterized in that: The memory further comprises a clock interface for inputting a clock signal into the memory.
Citation Information
Patent Citations
Stacked chip and test method of stacked chip
CN114295868A
Semiconductor device
CN1929033A