Low-power-consumption reference voltage buffer applied to high-speed and high-precision ADC

Abstract

The invention discloses a low-power-consumption reference voltage buffer applied to a high-speed and high-precision ADC (Analog to Digital Converter). According to the low-power-consumption reference voltage buffer, a PMOS (P-channel Metal Oxide Semiconductor) tube connected in a diode mode is used for realizing resistance, and AB-class output is realized by combining the high bandwidth characteristic of an open-loop structure, so that the power consumption of the output voltage buffer can be effectively reduced while the transient response speed is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of reference voltage buffers, and in particular to a low-power reference voltage buffer applied to a high-speed and high-precision ADC. Background Art

[0002] In recent decades, the rapid development of VLSI has continuously spawned new application scenarios. In mobile terminal applications represented by WiFi, the successive approximation register analog-to-digital converter (SARADC) with low power consumption and small area is very popular. Under the 802.11ac / ax standard, a signal-to-noise ratio of 60-70dB is a necessary condition to meet the line link noise budget (requiring the analog-to-digital converter (ADC) to have a resolution of more than 10-bit); at the same time, as the operating frequency of WiFi signals is getting faster and faster, the requirements for signals are getting higher and higher. These conditions have continuously increased the speed and accuracy of ADCs; at the same time, the pursuit of power consumption by mobile terminals limits the choice of ADC architecture. The serial working characteristics of SAR ADC make its speed naturally limited. However, its good process compatibility makes its working speed increase as the complementary metal oxide semiconductor (CMOS) process is scaled down. The current 12-bit SAR ADC can already achieve a conversion rate of more than 100-MSPS.

[0003] High-speed conversion greatly increases the requirements for reference voltage buffers, and even becomes the main bottleneck factor limiting overall performance. For high-precision ADCs, non-ideal factors such as limited gain bandwidth of op amps, comparator offset, and capacitor mismatch will deteriorate ADC performance, and the accuracy of the reference voltage that determines its quantization standard will also directly affect the conversion accuracy of the ADC. Due to limited driving capabilities, the reference voltage circuit will inevitably introduce dynamic errors, and such errors are difficult to eliminate through correction technology. Therefore, for ADCs with higher operating frequencies and conversion accuracy, it is essential to have a high-precision and fast-response reference voltage.

[0004] The main function of the reference voltage buffer is to output the reference voltage input from the previous stage to drive the capacitive digital-to-analog converter (DAC) switch array load of the ADC. At the same time, it needs to have fast response capability and be able to establish the reference voltage to a range less than a least significant bit (LSB) during the fast switching of the load. The reference voltage buffer is generally used in the following two ways:

[0005] (1) Figure 1 As shown in the figure, it is a closed-loop structure based on voltage series negative feedback. A buffer with slow settling time but stable output voltage is obtained by connecting a large capacitor at the output end. This circuit structure is relatively simple to design and can easily achieve lower output resistance, but a large external capacitor is required at the load end to ensure low output impedance within a wide frequency band. Since the external capacitor will reach the μF level, the chip integration will be significantly reduced. In addition, since a large capacitor is connected to the output end, the output voltage settling response speed will be very slow. At the same time, due to the constraints of stability, the main pole must be very low, so it is only suitable for low-speed occasions.

[0006] (2) Figure 2 As shown in the figure, it is an open-loop structure based on source follower replication. This structure can maintain low output impedance in a wide frequency band due to its open-loop characteristics. It does not need to rely on large capacitors to suppress high-frequency components, so it has the ability to respond quickly. Since the source of Mn1 is no longer an output point, the source of Mn1 does not need to be connected to additional capacitors to achieve low output impedance in a wide frequency band. The gate-source parasitic capacitance (Cgs2) of the output tube is separated from the main pole of the loop where the op amp is located and the load. At the same time, the negative feedback loop where the op amp is located no longer participates in the formation of output impedance. The regulation function of the op amp is to generate a suitable output tube gate voltage to generate the required reference voltage value, making the op amp design simple. The reference voltage buffer of this structure has a large slew rate, high bandwidth, and the output voltage can be established quickly. Achieving a large slew rate and high bandwidth at the same time means a large current. Therefore, under the requirement of low power consumption of the system, this structure has a high design difficulty and challenge.

[0007] A good reference voltage buffer should have the ability to quickly drive low-resistance loads, achieve isolation between the front and back stage circuits, accurate voltage output, and low power consumption.

[0008] like Figure 3 As shown, it is an open-loop structure based on source follower replication ( Figure 2 ) is based on the symmetrical negative feedback loop and the duplicate open-loop structure (A2, Mp1 and Mp2) to form a class AB output structure at the output stage. Figure 2In comparison, the current reuse of the AB class output structure can maintain low output impedance in a wider frequency band. However, due to the increase in circuit structure, the current overhead increases, which will lead to greater power consumption.

[0009] Based on the above, the existing reference voltage buffer circuit has the following main disadvantages:

[0010] (1) Power consumption: Source follower replica circuit structure ( Figure 1 ), forming an open-loop structure to obtain a high transient response speed, but at the expense of a larger output current and power consumption; the AB class output structure based on source follower replication ( Figure 3 ) can maintain low output impedance over a wider frequency band, but at the expense of increased circuit power consumption.

[0011] (2) Output impedance: With resistance as load ( Figure 2 ) Compared with the AB class output structure, the output impedance is larger; Figure 3 Although the output impedance of the circuit shown is reduced, it is at the expense of increased circuit complexity and power consumption.

[0012] (3) Noise: When the reference voltage buffer is operating normally, the continuous switching of the load will introduce additional coupling and crosstalk into the loop, affecting the stability of the loop and thus the stability of the output voltage. There is a lack of protection measures to protect the feedback loop from output high-frequency noise interference.

[0013] Therefore, it is necessary to provide a low power consumption reference voltage buffer for high speed and high precision ADC. Summary of the invention

[0014] The purpose of the present invention is to provide a low-power reference voltage buffer for high-speed and high-precision ADC. The circuit uses a PMOS tube connected in a diode manner to realize resistance, and combines the high bandwidth characteristics of an open-loop structure to achieve class AB output. While ensuring the transient response speed, the power consumption of the output voltage buffer can be effectively reduced.

[0015] The technical solution of the present invention is: a low-power reference voltage buffer applied to a high-speed and high-precision ADC, comprising a feedback loop, a current mirror and an output branch; wherein,

[0016] The feedback loop includes an amplifier, a first NMOS transistor Mn1 and a first PMOS transistor Mp1, the output end of the amplifier is electrically connected to the gate of the first NMOS transistor Mn1, the reverse input end of the amplifier is electrically connected to the source of the first NMOS transistor Mn1 and the source of the first PMOS transistor Mp1, and the gate and drain of the first PMOS transistor Mp1 are grounded;

[0017] The output branch includes a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2 and a third PMOS transistor Mp3, the gate of the second NMOS transistor Mn2 is electrically connected to the gate of the third NMOS transistor Mn3, the source of the second NMOS transistor Mn2 is electrically connected to the source of the second PMOS transistor Mp2, the gate and drain of the second PMOS transistor Mp2 are grounded and electrically connected to the gate of the third PMOS transistor Mp3, the drain of the third NMOS transistor Mn3 is electrically connected to the first voltage source, the source of the third NMOS transistor Mn3 is electrically connected to the source of the third PMOS transistor Mp3, and the drain of the third PMOS transistor Mp3 is grounded;

[0018] The current mirror includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5, the source of the fourth PMOS tube Mp4 and the source of the fifth PMOS tube Mp5 are electrically connected to a second voltage source, the drain of the first NMOS tube Mn1 is electrically connected to the gate and drain of the fourth PMOS tube Mp4 and the gate of the fifth PMOS tube Mp5, and the drain of the second NMOS tube Mn2 is electrically connected to its gate and the drain of the fifth PMOS tube Mp5.

[0019] In the above technical solution, a bandgap reference voltage of 0.7V is input to the positive input terminal of the amplifier.

[0020] In the above technical solution, the first NMOS transistor Mn1 and the second NMOS transistor Mn2 meet the following conditions:

[0021] Mn2=K1 Mn1

[0022] The first PMOS transistor Mp1 and the second PMOS transistor Mp2 satisfy:

[0023] Mp2=K1 Mp1

[0024] The fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 satisfy:

[0025] W / L (Mp5) =K1 W / L (Mp4)

[0026] Among them, K1 is the proportionality coefficient.

[0027] In the above technical solution, the proportionality coefficient K1 is associated with the transconductance of the second NMOS transistor Mn2.

[0028] In the above technical solution, the input voltage of the first voltage source is smaller than the input voltage of the second voltage source.

[0029] In the above technical solution, the first voltage source inputs a voltage of 0.9V.

[0030] In the above technical solution, the second voltage source inputs a voltage of 1.8V.

[0031] In the above technical solution, a resistor R1 is connected in series between the drain of the second NMOS transistor Mn2 and the drain of the fifth PMOS transistor Mp5.

[0032] In the above technical solution, a resistor R2 is connected in series between the gate of the second NMOS transistor Mn2 and the gate of the third NMOS transistor Mn3.

[0033] In the above technical solution, a resistor R2 is connected in series between the gate of the second PMOS transistor Mp2 and the gate of the third PMOS transistor Mp3.

[0034] The advantages of the present invention are:

[0035] The low-power reference voltage buffer of the present invention uses a simple low-resistance implementation method and combines the high bandwidth of the open loop and the current multiplexing of the AB class output to effectively reduce the power consumption of the output voltage buffer and improve the transient response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0037] Figure 1 It is a schematic diagram of a closed-loop structure based on voltage series negative feedback in the background technology.

[0038] Figure 2 It is a schematic diagram of an open-loop structure based on source follower replication in the background technology.

[0039] Figure 3 It is a schematic diagram of a class AB output structure based on source follower replication in the background technology.

[0040] Figure 4 Schematic diagram of the structure of a buffer circuit according to an embodiment of the present invention.

[0041] Figure 5 The schematic diagram of the circuit structure for realizing low resistance based on the gate-drain shorting MOS tube according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] Example:

[0043] like Figure 4 As shown, the present invention provides a low-power reference voltage buffer applied to a high-speed and high-precision ADC, including a feedback loop, a current mirror and an output branch; wherein,

[0044] The feedback loop includes an amplifier, a first NMOS transistor Mn1 and a first PMOS transistor Mp1, the output end of the amplifier is electrically connected to the gate of the first NMOS transistor Mn1, the reverse input end of the amplifier is electrically connected to the source of the first NMOS transistor Mn1 and the source of the first PMOS transistor Mp1, and the gate and drain of the first PMOS transistor Mp1 are grounded;

[0045] The output branch includes a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2 and a third PMOS transistor Mp3, the gate of the second NMOS transistor Mn2 is electrically connected to the gate of the third NMOS transistor Mn3, the source of the second NMOS transistor Mn2 is electrically connected to the source of the second PMOS transistor Mp2, the gate and drain of the second PMOS transistor Mp2 are grounded and electrically connected to the gate of the third PMOS transistor Mp3, the drain of the third NMOS transistor Mn3 is electrically connected to the first voltage source, the source of the third NMOS transistor Mn3 is electrically connected to the source of the third PMOS transistor Mp3, and the drain of the third PMOS transistor Mp3 is grounded;

[0046] The current mirror includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5, the source of the fourth PMOS tube Mp4 and the source of the fifth PMOS tube Mp5 are electrically connected to a second voltage source, the drain of the first NMOS tube Mn1 is electrically connected to the gate and drain of the fourth PMOS tube Mp4 and the gate of the fifth PMOS tube Mp5, and the drain of the second NMOS tube Mn2 is electrically connected to its gate and the drain of the fifth PMOS tube Mp5.

[0047] The reference voltage outputted by the bandgap (BG) which is not dependent on PVT changes but has no driving capability is used as the input signal of the reverse input terminal of the amplifier A1, and a slow feedback loop is formed through the first NMOS tube Mn1 of the source follower connection method. The amplifier A1 has a high gain to achieve that the source voltage of the first NMOS tube Mn1 follows the voltage of BG. When the feedback loop (dashed box I) is stable, the DC operating point of the circuit can be determined to output a reference voltage with a certain value that has the ability to drive the load and can be quickly restored.

[0048] The replica structure is realized by the current mirror of the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5, wherein the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 satisfy W / L (Mp5) =K1 W / L (Mp4)

[0049] (K1 is the proportionality coefficient), the proportionality coefficient K1 is associated with the transconductance of the second NMOS tube Mn2, that is, the determination of the proportionality coefficient K1 should be specifically determined by the transconductance of the second NMOS tube Mn2, and the transconductance should be large enough to achieve a small output resistance at point C. At the same time, the first NMOS tube Mn1 and the second NMOS tube Mn2 satisfy Mn2=K1 Mn1, and the first PMOS tube Mp1 and the second PMOS tube Mp2 satisfy Mp2=K1 Mp1, so as to achieve the same voltage at node B as that at node A. The resistor R1 is connected in series between the drain of the second NMOS tube Mn2 and the drain of the fifth PMOS tube Mp5, and its function is to make the drain-source voltage V of the second NMOS tube Mn2 and the third NMOS tube Mn3 DS Similarly, the influence of channel length modulation effect on current replication is reduced to obtain better replication accuracy.

[0050] The first voltage source of the output branch is powered by a voltage of 0.9V because the output stage requires a larger current to obtain a higher bandwidth, thereby achieving a faster transient response speed. By supplying power with a lower output voltage alone, voltage waste can be avoided, and the same response speed can be achieved with lower power consumption. The output stage current size is set by controlling the ratio of the second NMOS tube Mn2 to the third NMOS tube Mn3, and the second PMOS tube Mp2 to the third PMOS tube Mp3, and the output of the reference voltage is achieved through the AB class output structure formed by the third NMOS tube Mn3 and the third PMOS tube Mp3. A resistor R2 is connected in series between the gate of the second NMOS tube Mn2 and the gate of the third NMOS tube Mn3, and between the gate of the second PMOS tube Mp2 and the gate of the third PMOS tube Mp3. The resistor R2 is a low-pass resistor, which is used as a resistor isolation between the output stage and the replica branch to reduce the interference of the high-frequency noise at the output end on the replica circuit and the slow feedback loop.

[0051] It should be understood that the continuous switching of the load will cause the output node voltage to change, and the resistance at point A needs to be small enough to achieve the effect of rapid stabilization of point A, so that the output voltage will stabilize quickly.

[0052] like Figure 2 As shown, to make the output resistance of amplifier A1 small enough, a large current I1 is often required; at the same time, the current I2 will not be very small to ensure reliable replication multiples with the output stage. Figure 5 As shown in Figure 2 The circuit structure shown in the figure is initially optimized. The resistance at point A is equal to the reciprocal series resistance R2 of the transconductance of the second NMOS tube Mn2. In order to make the reciprocal of the transconductance of the second NMOS tube Mn2 reach the same output impedance as the amplifier A1, the current of the replica branch can be increased by increasing the amplification factor (proportional coefficient K1) to achieve the same output impedance.

[0053] Under the condition of achieving the same output impedance at point A, Figure 2 The current I1+I2 in the circuit shown is greater than Figure 5 The current I1′+I2′+I3′ in the circuit shown achieves low resistance by shorting the gate and drain, which significantly reduces the current consumption and improves the power efficiency.

[0054] Figure 4 The buffer circuit of the present invention is shown in Figure 5 Further improvements based on the circuit shown,

[0055] contrast Figure 4 and Figure 5 It can be seen that the buffer circuit of the present invention uses a diode-connected PMOS tube instead of a resistor as a load.

[0056] Since the gate of the diode-connected PMOS tube is grounded, the output impedance at point B is equal to 0. The PMOS tube and the NMOS tube that serve as loads form a class AB output at the output stage, making the output impedance the parallel connection of the two MOS tube transconductances, reducing the impedance of the output node. Under the same output stage current, the class AB output structure has a faster response speed. At the same time, compared with the class AB output structure based on source follower replication ( Figure 3 ), although both achieve low output impedance in a wider frequency band, the circuit structure becomes much simpler and has better performance from the perspective of power consumption.

[0057] Based on the above, the low power consumption reference voltage buffer of the present invention has the following advantages:

[0058] 1. Power consumption: By shorting the gate and drain of the MOS tube, the source follower gate has low resistance, compared with the traditional structure ( Figure 2 ) reduces the current expenditure and improves the power efficiency. At the same time, by setting the current mirror replication ratio, the appropriate current size is allocated, the output stage adopts low-voltage power supply, and the current reuse of the AB class output structure, so that the overall power consumption of the circuit is smaller while obtaining a fast transient response speed.

[0059] 2. Output impedance: Compared with the output stage with resistor as load, the class AB output structure composed of diode-connected PMOS tube can effectively reduce the output resistance, so that under the same current, a larger bandwidth can be achieved through current multiplexing to ensure the speed of the buffer.

[0060] 3. Noise: By replicating the current and isolating the load from the replica branch using the low-pass resistor R2, the coupling noise and crosstalk introduced by load switching can be well isolated. The feedback loop can work more stably and output a stable reference voltage.

[0061] Of course, the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A low power consumption reference voltage buffer for high speed and high precision ADC, characterized in that: It includes a feedback loop, a current mirror and an output branch; among which, The feedback loop includes an amplifier, a first NMOS transistor Mn1 and a first PMOS transistor Mp1, the output end of the amplifier is electrically connected to the gate of the first NMOS transistor Mn1, the reverse input end of the amplifier is electrically connected to the source of the first NMOS transistor Mn1 and the source of the first PMOS transistor Mp1, and the gate and drain of the first PMOS transistor Mp1 are grounded; The output branch includes a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2 and a third PMOS transistor Mp3, the gate of the second NMOS transistor Mn2 is electrically connected to the gate of the third NMOS transistor Mn3, the source of the second NMOS transistor Mn2 is electrically connected to the source of the second PMOS transistor Mp2, the gate and drain of the second PMOS transistor Mp2 are grounded and electrically connected to the gate of the third PMOS transistor Mp3, the drain of the third NMOS transistor Mn3 is electrically connected to the first voltage source, the source of the third NMOS transistor Mn3 is electrically connected to the source of the third PMOS transistor Mp3, and the drain of the third PMOS transistor Mp3 is grounded; The current mirror includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5, the source of the fourth PMOS tube Mp4 and the source of the fifth PMOS tube Mp5 are electrically connected to a second voltage source, the drain of the first NMOS tube Mn1 is electrically connected to the gate and drain of the fourth PMOS tube Mp4 and the gate of the fifth PMOS tube Mp5, and the drain of the second NMOS tube Mn2 is electrically connected to its gate and the drain of the fifth PMOS tube Mp5.

2. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: A bandgap reference voltage of 0.7V is input to the positive input terminal of the amplifier.

3. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: The first NMOS transistor Mn1 and the second NMOS transistor Mn2 satisfy; Mn2=K1Mn1 The first PMOS transistor Mp1 and the second PMOS transistor Mp2 satisfy: Mp2=K1Mp1 The fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 satisfy: W / L (Mp5) =K1W / L (Mp4) Among them, K1 is the proportionality coefficient.

4. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 3, characterized in that: The proportionality coefficient K1 is associated with the transconductance of the second NMOS transistor Mn2.

5. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: An input voltage of the first voltage source is lower than an input voltage of the second voltage source.

6. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 5, characterized in that: The first voltage source inputs a voltage of 0.9V.

7. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 5, characterized in that: The second voltage source inputs a voltage of 1.8V.

8. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: A resistor R1 is connected in series between the drain of the second NMOS transistor Mn2 and the drain of the fifth PMOS transistor Mp5.

9. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: A resistor R2 is connected in series between the gate of the second NMOS transistor Mn2 and the gate of the third NMOS transistor Mn3.

10. The low power consumption reference voltage buffer for high speed and high precision ADC according to claim 1, characterized in that: A resistor R2 is connected in series between the gate of the second PMOS transistor Mp2 and the gate of the third PMOS transistor Mp3.

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