Random clock generation device and clock signal output method

Abstract

The embodiment of the invention provides a random clock generation device and a clock signal output method. The random clock generating device comprises a random sequence generator, a selection switching unit and a clock pool, wherein the clock pool and the random sequence generator are respectively connected to the selection switching unit; wherein the random sequence generator is used for generating a random sequence; the selecting and switching unit is used for selecting and switching a main clock of the random clock generating device and detecting whether a set low-frequency sequence appears in the random sequence or not; when the low-frequency sequence is detected, identifying a clock number from the random sequence and selecting a corresponding clock to replace the current clock to become a main clock of the random clock generation device; the master clock is used for outputting a clock signal controlled by a random sequence. According to the method provided by the invention, the use effect of the random clock generation device in the process of defending side channel attack clock switching is improved.

Description

Technical Field

[0001] The present application relates to the technical field of cryptographically secure clock signal processing, and in particular to a random clock generating device and a clock signal output method. Background Art

[0002] In the field of information security, side channel attacks analyze the energy, radiation and other information leaked during cryptographic operations and use statistical analysis to obtain keys, becoming an important factor threatening the security of cryptographic chips and applications. To this end, enhancing defense against side channel attacks, especially increasing the difficulty of external statistical analysis through technologies such as clock randomization, and ensuring that key data and external information are inconsistent in time and space, has become a key measure to ensure chip cryptographic security. Clock randomization effectively disrupts the attacker's analysis path based on clock-related side channel information by introducing unpredictability, and is one of the effective means to defend against such attacks.

[0003] Currently, random clock generators use clock randomization technology to defend against side channel attacks, that is, switching between different clock sources by setting time periods during cryptographic operations. The regularity of this switching will lead to a significant reduction in randomness, making the system more vulnerable to analysis and prediction by potential attackers. Summary of the invention

[0004] The present application provides a random clock generating device and a clock signal output method, which are used to solve the problem that when the existing random clock generating device switches the clock to defend against side channel attacks, the randomness of the clock switching is not good, resulting in poor use effect of the random clock generating device.

[0005] On the one hand, the present application provides a random clock generating device, which includes a random sequence generator, a selection switching unit and a clock pool, wherein the clock pool and the random sequence generator are respectively connected to the selection switching unit; wherein,

[0006] A random sequence generator, used to generate a random sequence;

[0007] A selection and switching unit is used to select and switch the main clock of the random clock generating device, and detect whether the random sequence has a set low-frequency sequence;

[0008] When a low frequency sequence is detected, a clock number is identified from the random sequence and a corresponding clock is selected to replace the current clock and become the master clock of the random clock generating device;

[0009] The master clock is used to output a clock signal controlled by a random sequence.

[0010] In a possible implementation, the clock number is determined according to a target bit, and the target bit is determined according to a position of the low-frequency sequence in the random sequence.

[0011] In a possible implementation, the random clock generating device includes a reference clock and a frequency dividing circuit, the frequency dividing circuit is connected between the reference clock and the clock pool, and the clock in the clock pool is obtained by dividing the reference clock by the frequency dividing circuit.

[0012] In a possible implementation, the selection switching unit includes a first configurator and a selection switching circuit;

[0013] A first configurator, configured to configure and detect a low frequency sequence in the random sequence in response to a configuration operation, and when the low frequency sequence is detected, identify a clock number from the random sequence according to the low frequency sequence;

[0014] The selection switching circuit is used to select a corresponding clock to replace the current clock according to the clock number identified from the random sequence, and become the main clock of the random clock generating device.

[0015] In a possible implementation, the occurrence frequency of the low-frequency sequence in the random sequence is determined according to the run length of the low-frequency sequence.

[0016] In a possible implementation, the random clock generating device further includes a gating unit, which is connected to the random sequence generator and the selection switching unit respectively;

[0017] The gating unit is used to perform a gating operation on the main clock connected to the selection switching unit when a high-frequency sequence in the random sequence is detected. The gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

[0018] In a possible implementation, the gating unit includes an efficiency control circuit, a clock gating subunit and a second configurator, the random sequence generator is connected to the efficiency control circuit and the clock gating subunit, the clock gating subunit is further connected to the selection switching unit, and the second configurator is connected to the efficiency control circuit;

[0019] A second configurator, used to configure the high frequency sequence;

[0020] an efficiency control circuit, used for detecting a high frequency sequence set by a second configurator in the random sequence, and outputting a gating signal when the high frequency sequence in the random sequence is detected;

[0021] The clock gating subunit is used to perform a gating operation on the main clock connected to the selection switching unit according to the gating signal.

[0022] In a possible implementation, the occurrence frequency of the high-frequency sequence in the random sequence is determined according to the run length of the high-frequency sequence.

[0023] On the other hand, the present application provides a cryptographic chip including a random clock generating device.

[0024] On the other hand, the present application provides a clock signal output method, which is applied to a random clock generating device, wherein the random clock generating device includes a selection switching unit, and the method includes:

[0025] Detecting whether a set low-frequency sequence appears in a random sequence, wherein the random sequence is generated by a random sequence generator in a random clock generating device;

[0026] When a low-frequency sequence is detected, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock, becoming the master clock of the random clock generating device. The master clock is used to output a clock signal controlled by the random sequence.

[0027] In a possible implementation manner, the random clock generating device further includes a gating unit, and the method further includes:

[0028] When a high frequency sequence set in the random sequence is detected, a gating operation is performed on the main clock connected to the selection switching unit, and the gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

[0029] On the other hand, the present application provides a control device for a random clock generating device, which is applied to the random clock generating device, and the random clock generating device includes a selection switching unit, including:

[0030] An identification module, used to detect whether a set low-frequency sequence appears in a random sequence, wherein the random sequence is generated by a random sequence generator in a random clock generating device;

[0031] The replacement module is used to identify the clock number from the random sequence and select the corresponding clock to replace the current clock when a low-frequency sequence is detected, and become the master clock of the random clock generating device. The master clock is used to output a clock signal controlled by the random sequence.

[0032] On the other hand, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0033] Memory stores computer-executable instructions;

[0034] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0035] On the other hand, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0036] On the other hand, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementations of the first aspect.

[0037] The random clock generating device and clock signal output method provided by the present application include a random sequence generator, a selection switching unit and a clock pool through the random clock generating device, and the clock pool and the random sequence generator are respectively connected to the selection switching unit; the random sequence generator is used to generate a random sequence; the selection switching unit is used to select and switch the master clock of the random clock generating device, and detect whether the random sequence appears a set low-frequency sequence; when the low-frequency sequence is detected, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock, becoming the master clock of the random clock generating device; the master clock is used to output a clock signal controlled by the random sequence. A random source or a pseudo-random source is used as an input, and the run length of the random number is used as a control factor, and the random sequence is mapped to the random clock output in real time, so that the random clock generating device, when in use, can improve the randomness of the clock switching by the non-fixed frequency of the low-frequency sequence in the random sequence, compared with the method of preventing side channel attacks by switching the clock through a fixed time period, thereby making the use effect of the random clock generating device better and effectively resisting the attack means based on time side channel analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] Figure 1 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 1 ;

[0040] Figure 2 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 2 ;

[0041] Figure 3 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 3 ;

[0042] Figure 4 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 4 ;

[0043] Figure 5 A schematic diagram of the structure of another random clock generating device provided in an embodiment of the present application;

[0044] Figure 6 A flowchart of a clock signal output method provided in an embodiment of the present application;

[0045] Figure 7 A flowchart of another clock signal output method provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure of a clock signal output device provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0048] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] First, the terms involved in this application are explained:

[0051] The clock signal can refer to the timing signal that controls the cryptographic operation process. The operations inside the cryptographic chip are driven by a fixed clock signal, which can determine the start and end time of each operation.

[0052] A random walk sequence can refer to a mathematical model that describes a random process in which the direction and / or distance of each step is randomly determined. In information security and cryptography, a random walk sequence can be used to generate unpredictable signals to increase the security of the system. For example, it can be used to generate random clock signals, making it difficult for attackers to analyze and infer the internal state of the system through side channel attacks.

[0053] A random sequence generator (RSG) can be a circuit or algorithm for generating a random bit sequence. Common implementation methods include linear feedback shift register (LFSR) and true random number generator (TRNG). LFSR generates pseudo-random sequences through feedback polynomials, which is suitable for applications that require long periods and predictability; while TRNG uses physical noise or other unpredictable natural phenomena to generate true random sequences, which is suitable for scenarios with extremely high randomness requirements, such as encryption and security applications.

[0054] A low-frequency sequence refers to a longer sequence of "0" or "1" in a random sequence. Its length is longer, and in terms of probability, the probability of its appearance in a random sequence is relatively low.

[0055] A high-frequency sequence refers to a shorter sequence of "0" or "1" in a random sequence. Due to its shorter length, its probability of appearing in a random sequence is relatively high.

[0056] A bit is the smallest unit in the binary digital system, representing one of two possible states, usually represented by 0 and 1. In clock randomization technology, bits can be used to represent different states of clock signals. For example, 0 can represent one phase of the clock, and 1 can represent another phase. By randomizing these bits, more complex and unpredictable clock signals can be generated.

[0057] In the related technology, although the multi-channel clock switching technology provides flexibility in clock management to a certain extent, its inherent mechanism inevitably weakens the randomness of the system. That is, when the system switches between different clock sources, this switching is only selected from the clock pool at a certain time, and the selection is also limited, resulting in low randomness.

[0058] The random clock generating device and clock signal output method provided by the present application include a random sequence generator, a selection switching unit and a clock pool through a random clock generating device, wherein the random sequence generator and the selection switching unit are respectively connected to the clock pool; when the device is working, the random sequence generator is used to generate a random sequence, and the selection switching unit detects whether a set low-frequency sequence appears in the random sequence. When a low-frequency sequence is detected in the random sequence, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock, which becomes the main clock of the random clock generating device to output the clock signal. In this process, since the set low-frequency sequence appears in the random sequence randomly, compared with the technical means of switching the clock to prevent side channel attacks by a fixed time period, the main clock switching is random. When preventing side channel attacks, the switching cycle of the clock switching also becomes more unpredictable, so that the use effect of the random clock generating device is better, and it can effectively resist the attack means based on time side channel analysis.

[0059] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0060] Figure 1 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the random clock generating device includes a random sequence generator, a selection switching unit and a clock pool, and the clock pool and the random sequence generator are respectively connected to the selection switching unit, wherein:

[0061] A random sequence generator, used to generate a random sequence;

[0062] A selection and switching unit is used to select and switch the main clock of the random clock generating device, and detect whether the random sequence has a set low-frequency sequence;

[0063] When a low frequency sequence is detected, a clock number is identified from the random sequence and a corresponding clock is selected to replace the current clock and become the master clock of the random clock generating device;

[0064] The master clock is used to output a clock signal controlled by a random sequence.

[0065] Among them, a random sequence can be used as a random input. The run of a random sequence is a subsequence of continuous "0" or "1" in the sequence, and the leading and succeeding elements of the subsequence are different from its own elements. The randomness test of a random sequence requires that its run conforms to a specific distribution. This stable probability distribution in randomness can provide a stable component in randomness. Through a specific run, it is possible to achieve a specific efficiency selection while maintaining a high degree of randomness in the clock output. This makes the generated clock signal not only difficult to predict, but also has excellent anti-analysis performance. At the same time, its working efficiency is effectively guaranteed, avoiding system performance fluctuations that may be caused by randomness.

[0066] In some embodiments, within a sequence in a random sequence, the number of runs of "0" and "1" of the same length is substantially equal, and the number of runs should be nearly halved for each increase in the run length by 1 bit, thereby approximating a continuous "1" sequence with a run length of 1, i.e., the number of "010" sequences appearing in the random number is close to 1 / 4, a continuous "1" sequence with a run length of 2, i.e., the number of "0110" sequences appearing in the random number is close to 1 / 8, .... By controlling the selection of the run, it can be ensured that a specific number of data appears randomly over a long period of time. A corresponding random clock change is generated according to this random point.

[0067] The low-frequency sequence may be a sequence that appears in a random sequence. In the embodiment of the present application, the low-frequency sequence may be arbitrarily set as needed. For example, the low-frequency sequence may be a "0" sequence such as a sequence of "1{10 0s}1" with a run length of 10, or a "1" sequence such as a sequence of "0{11 1s}0" with a run length of 10. The low-frequency run length is not limited here because low frequency and high frequency are relative.

[0068] Detecting a low frequency sequence in a random sequence may refer to a situation when a low frequency sequence appears in the random sequence. When a low frequency sequence appears, a pre-switched clock number may be identified from the random sequence. In an embodiment of the present application, the clock number may be determined according to the target bit.

[0069] The target bit may refer to a bit selected from a random sequence. According to the target bit, a corresponding clock number may be determined. Thus, according to a preset mapping relationship, a corresponding clock may be determined from a clock pool.

[0070] In an embodiment of the present application, the target bit is determined according to the position of the low-frequency sequence in the random sequence. For example, after the low-frequency sequence is detected from the random sequence, the subsequent or previous N bits can be used as target bits, or the subsequent or previous N bits can be selected according to a preset rule as needed, where N is a positive integer.

[0071] In some embodiments, the position of the target bit in the random sequence can be determined based on the number of clocks in the clock pool. For example, when the number of clocks in the clock pool is 16, the target bit can include four bits, that is, when the random sequence generator generates this low-frequency sequence, the subsequent 4 bits in the random sequence are used as the ID representing the clock identifier.

[0072] The mapping relationship may refer to a correspondence between a clock identifier set in advance and different clocks in a clock pool, wherein different target bits correspond to different clock identifiers, and different clock identifiers correspond to different clocks.

[0073] For example, in an embodiment of the present application, when the low-frequency sequence is "1{10 0s}1", and the random sequence generator generates this random sequence, the subsequent 4 bits are used as the ID, and one of the 16 alternative clocks is selected as the main clock (for example, if the ID is 8, then according to the mapping relationship, clock 8 is selected as the main clock. If "1{10 0s}1" is detected in the sequence output by clock 8, the clock switching is triggered again), and the switching of the main clock is completed through the clock switching circuit.

[0074] In the embodiment of the present application, the clock in the clock pool is obtained by dividing the reference clock.

[0075] The frequency division process may refer to reducing the frequency of the reference clock signal through the frequency division circuit to generate a series of lower frequency clock signals. For example, after the reference clock signal passes through the frequency division circuit, it will generate clock signals with 2 divisions, 4 divisions and 8 divisions. When the reference clock signal includes clk0, clk1, clk2 and clk3, each reference clock signal will generate 4 clock signals with different frequencies (original reference clock, 2 divisions, 4 divisions and 8 divisions), forming a total of 16 alternative clock pools. These divided clock signals provide the system with a variety of frequency options to meet different clock requirements.

[0076] Therefore, the random clock generating device provided in the embodiment of the present application ensures that when the clock is switched, the entire process becomes more unpredictable through the randomness of the low-frequency sequence appearing in the random sequence, so that the clock signal exhibits a high degree of unpredictability and randomness. Therefore, compared with the method of switching the clock through a fixed time period, due to its better randomness and less predictability, it can effectively resist the attack method based on time side channel analysis, ensure the security of the random clock generating device, and make the use effect of the random clock generating device better.

[0077] At the same time, the random clock generating device provided in the embodiment of the present application can adjust the random clock signal output by the random clock generating device through clock switching. Among them, clock switching refers to switching between clock signals of different frequencies or sources. Since such switching usually involves a long period of time, frequent switching will increase circuit complexity and power consumption. Therefore, using a low-frequency stroke (i.e., not switching the clock for a long time) can ensure the stability of clock switching.

[0078] In addition, in the embodiment of the present application, the random number in the random sequence itself has the statistical characteristics of the run distribution. Therefore, when the run length of the random number is used as a control factor, the run length of the random number can be adjusted so that the random clock generator can control the switching frequency of the random clock as needed (for example, if the confidentiality requirement is high, the length of the run length can be adjusted to make the clock switching more random and frequent. If the device performance is poor, the length of the run length can also be adjusted to reduce the frequency of clock switching). The frequency distribution of the random clock is controlled, and the random clock is improved. The random sequence is too random, which causes the random clock generator to be unable to be regulated when in use. Therefore, the control effect of the random clock generator is improved, so that the performance of the random clock can be predicted and flexibly regulated in a forward-looking manner, thereby ensuring randomness while minimizing the potential impact of randomness on system stability and reliability. And avoid the negative impact of the random clock generator when using random numbers.

[0079] In addition, the present application can also be simple and efficient in design. It abandons complex hardware architecture and cumbersome software algorithms, and instead relies on a simple and effective principle: as long as the validity of the random source is ensured (that is, it can continuously and stably generate high-quality random numbers or pseudo-random numbers), it can directly drive the system to generate the required random clock output. This design not only reduces the cost of implementation, but also greatly simplifies the maintenance and upgrade process, making the present application have extremely high practical value and promotion potential in various application scenarios that require random clock support. Figure 2 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 2 ,like Figure 2 As shown, in the embodiment of the present application, the selection switching unit in the random clock generation device includes a first configurator and a selection switching circuit; wherein,

[0080] A first configurator, configured to configure and detect a low frequency sequence in the random sequence in response to a configuration operation, and when the low frequency sequence is detected, identify a clock number from the random sequence according to the low frequency sequence;

[0081] The selection switching circuit is used to select a corresponding clock to replace the current clock according to the clock number identified from the random sequence, and become the main clock of the random clock generating device.

[0082] Among them, the first configurator may refer to a low-frequency run selection configuration unit, that is, a unit that can be used for the user to configure the low-frequency sequence. In the embodiment of the present application, the first configurator can configure the low-frequency sequence in a software or hardware manner. For example, a pattern matcher can be pre-set through hardware logic (such as using FPGA), and the matcher can be used to detect whether the input random sequence conforms to the "1{10 0}1" pattern. When the "1{10 0}1" sequence is detected, the hardware logic will automatically trigger the subsequent steps, such as reading the 4 bits that follow as the clock number, and based on this, the selection switching circuit selects one of the 16 alternative clocks as the new master clock for switching. For example, it can also be implemented by writing program code. The software can continuously monitor the data stream from the random sequence generator and apply an algorithm to find the "1{10 0}1" pattern. When this sequence is detected, the software can execute corresponding instructions, such as parsing the subsequent 4 bits and sending a command to the selection switching circuit to select a new master clock.

[0083] The selection switching circuit may be a main clock selection and switching circuit, which may include: a multiplexer (MUX), a register and decoder combination, a state machine controlled multiplexer, a programmable logic device (PLD / FPGA) and other circuits.

[0084] The random clock generating device provided in the embodiment of the present application, in view of the inherent statistical characteristics of the run distribution of the low-frequency sequence as a random number itself, can adjust the frequency of the low-frequency sequence appearing in the random sequence by configuring the low-frequency sequence with different run lengths through the first configurator. For example, when the run length of the low-frequency sequence is longer, the frequency of the low-frequency sequence appearing in the random sequence is lower. Conversely, when the run length of the low-frequency sequence is shorter, the frequency of the low-frequency sequence appearing in the random sequence is higher. Therefore, by adjusting the frequency of clock switching, clock switching under factors such as different processing speeds, power consumption management, real-time requirements and security considerations can be achieved.

[0085] In the related art, when the random clock generator is in use, the clock signal output by its main clock itself is flipped and transmitted according to a fixed period. In this way, when facing a side channel attack, since the clock signal that is flipped and transmitted according to a fixed period has a strong regularity, the power consumption characteristics and electromagnetic radiation patterns of its signal are highly predictable, resulting in attackers being able to infer the operating status or sensitive information inside the random clock generator by analyzing these characteristics, which reduces the defense effect when facing side channel attacks and increases the risk of the random clock generator. Therefore, in the embodiment of the present application, in order to make the clock signal transmitted by the random clock generator more difficult to predict, thereby further improving the defense effect of the random clock generator against side channel attacks, the random clock generator of the embodiment of the present application can perform a gated operation on the clock signal, so that the output clock signal becomes difficult to be used for attack due to the lack of regularity. That is:

[0086] Figure 3 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 3 ,like Figure 3 As shown, the random clock generating device may further include a gating unit, which is connected to the random sequence generator and the selection switching unit respectively;

[0087] The gating unit is used to perform a gating operation on the main clock connected to the selection switching unit when a high-frequency sequence set in the random sequence is detected. The gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

[0088] Among them, clock transition can refer to the process that the clock signal changes from low level to high level (rising edge) or from high level to low level (falling edge) within one cycle. Among them, when the clock is in use, it usually flips along a fixed cycle, so the output signal is usually susceptible to side channel attacks, thereby affecting the use of the random clock generation device. The embodiment of the present application can control the clock to be turned on or off by gating the main clock, thereby effectively reducing the power consumption characteristics of the random clock generation device during encryption operations and the predictability of the electromagnetic radiation pattern.

[0089] The random clock generating device provided in the embodiment of the present application adjusts the gating cycle by performing a gating operation, thereby adjusting the random clock signal output by the random clock generating device. Wherein, the gating cycle refers to turning off the clock signal within a specific time period, that is, no clock flip occurs within the cycle, and a clock flip can occur in a non-gated cycle. The gating cycle can be determined according to the gating operation, and the gating can frequently control the clock behavior of a single cycle to improve the randomness and flexibility of the system. In order to further effectively reduce the power consumption characteristics of the random clock generating device during the encryption operation and the predictability of the electromagnetic radiation pattern, a high-frequency sequence is used in the embodiment of the present application for gating operation. When the clock signal is output, the gating cycle can be adjusted according to the high-frequency sequence appearing in the random sequence. For example, when the run of the high-frequency sequence is less, the gating operation can be more frequent.

[0090] Figure 4 A schematic diagram of a random clock generator provided in an embodiment of the present application Figure 4 ,like Figure 4 As shown, the gating unit in the random clock generating device includes an efficiency control circuit and a clock gating subunit, the random sequence generator is connected to the efficiency control circuit and the clock gating subunit, and the clock gating subunit is also connected to the selection switching unit;

[0091] An efficiency control circuit is used for detecting a high frequency sequence in the random sequence and outputting a gating signal when the high frequency sequence in the random sequence is detected;

[0092] The clock gating subunit is used to perform a gating operation on the main clock connected to the selection switching unit according to the gating signal.

[0093] The efficiency control circuit may refer to a unit for checking the high-frequency run length, thereby outputting gating signals for different schemes of the main clock to achieve different clock efficiencies. The efficiency control circuit may be modified by hardware or software to generate a random clock suitable for product performance. It may be regulated to select a "101" or "010" sequence of length 1, a "1001" or "0110" sequence of length 2, ..., a "1{N 0s}1" or "0{N 1s}0" sequence of length N, or both a "0" and a "1" series may be selected.

[0094] The gating signal can refer to a signal used to turn on or off the gating operation of the main clock. The gating operation can temporarily turn on or off the transmission of the main clock signal through the gating signal, thereby achieving the purpose of adjusting the output clock frequency. For example, when a specific high-frequency sequence "10001" is detected, the gating unit will perform a gating operation on the main clock, that is, blocking the transmission of the main clock signal for a certain period of time, so that the output random clock signal has intermittent pauses. Therefore, by controlling the time length and frequency of the gating, the frequency of the output clock signal can be finely adjusted.

[0095] The clock gating subunit may refer to a unit for receiving a gating signal and performing a gating operation. In an embodiment of the present application, the clock gating subunit may be a clock gating circuit, which may include an AND gate circuit, a D-type flip-flop (DFF), a transmission gate, a tristate buffer, a multiplexer (MUX), etc. Wherein, when the clock gating circuit is a tristate buffer, the working process of the clock gating circuit may be: when the gating signal is a high-level signal, the tristate buffer outputs the main clock signal; when the gating signal is a low-level signal, the tristate buffer enters a high-impedance state, and the output is in a high-impedance state, thereby blocking the main clock signal.

[0096] Wherein, in the embodiment of the present application, the gate control unit further includes a second configurator, and the second configurator is connected to the efficiency control circuit;

[0097] The second configurator is used to configure the high-frequency sequence so that the efficiency control circuit detects the high-frequency sequence in the random sequence.

[0098] Among them, the second configurator may refer to a unit for configuring a high-frequency sequence to detect a random sequence. For example, the second configurator may configure a high-frequency sequence as a "10001" sequence. In an embodiment of the present application, the second configurator and the first configurator may be configuration units with the same structure and function but different purposes. Thus, when the efficiency control circuit detects the "10001" sequence, it may output a gating signal to the gating unit, wherein the efficiency control circuit may be a sequence detector, thereby detecting the high-frequency sequence.

[0099] In summary, through the combination of clock switching and gating cycles, the use effect of the random clock generation device in defending against side channel attacks is significantly improved.

[0100] Figure 5 A schematic diagram of the structure of another random clock generating device provided in an embodiment of the present application is shown in FIG. Figure 5As shown, the random clock generating device includes: a frequency division circuit, a clock pool, a master clock selection and switching circuit, a random sequence generator, an efficiency control circuit and a clock gating circuit. The use process of the random clock generating device may include:

[0101] Using four clock sources, namely reference clock clk0, reference clock clk1, reference clock clk2 and reference clock clk3, a frequency division circuit is used to generate a 2-frequency clock, a 4-frequency clock and an 8-frequency clock of the original reference clock and its four clocks, thereby forming a clock pool of 16 alternative clocks.

[0102] The software or hardware configures the low-frequency run selection sequence "1{10 0s}1". When the random sequence generator generates this random sequence, the subsequent 4 bits in the random sequence are used as the ID, one of the 16 alternative clocks is selected as the main clock and the switching of the main clock is completed through the clock switching circuit.

[0103] Software or hardware configures high-frequency strokes as input for efficiency control, such as selecting a 0-stroke "10001" sequence with a length of 3 as a control point. Each time the "10001" sequence is detected, the main clock is gated, and an adjustable random clock is finally output; you can also select a 0-stroke "100001" sequence with a length of 4 as a control point. Each time the "100001" sequence is detected, the main clock is gated, and an adjustable random clock is finally output; the length of the low-frequency stroke is not limited here, because low frequency and high frequency are relative. At the same time, the efficiency control circuit also retains the full efficiency state without gating, and the random clock is completely equivalent to the main clock. The main clock selection and switching circuit also supports the direct selection of a specific clock. These functions can support the output of stable alternative clocks and provide a variety of clock scheme options.

[0104] This random clock can combine low-frequency strokes and high-frequency strokes to achieve various predictable random clock outputs. When both low-frequency strokes and high-frequency strokes are adjusted to the highest frequency level, the random clock has the highest randomness, but its efficiency will be halved. The factors affecting the efficiency of the random clock can be clearly calculated. Among them:

[0105] 1. The selection of the master clock of the low-frequency run will not affect the efficiency of the random clock in the long run, because it is just switching, and the random expectation of the master clock remains unchanged. The clock frequency is (clk0+clk1+clk2+clk3)*(1+1 / 2+1 / 4+1 / 16)*(1 / 4)=(clk0+clk1+clk2+clk3)*(29 / 64). After clarifying clk0 / 1 / 2 / 3, you can understand the current master clock status.

[0106] 2. The efficiency adjustment of high-frequency runs. Gating will affect the efficiency of the random clock. When the "010" sequence with a number close to 1 / 4 is selected as the gating point, the total random clock efficiency will drop by 1 / 4. Selecting other sequences can also get the corresponding efficiency drop evaluation.

[0107] Therefore, by determining the efficiency of the current random clock operation, that is, the master clock expected * gating efficiency, and adjusting the efficiency of the high-frequency run to speed up or slow down, randomness is maintained.

[0108] The embodiment of the present application also provides a cryptographic chip, which may include the random clock generating device in the embodiment of the present application.

[0109] The random clock generating device provided in the embodiment of the present application can generate a clock signal that is highly random at the microscopic level and exhibits statistical regularity characteristics at the macroscopic level. Using this clock as the core working clock of the cryptographic chip can effectively disrupt the distribution pattern of sensitive information such as power consumption and radiation in the time domain, significantly improve the defense capability against potential attackers, and increase the difficulty of cracking. At the same time, it also has evaluation and optimization functions, and can accurately measure the specific impact of the random clock on the system's computing performance, while ensuring the stable operation of the system, and optimizing the working performance through intelligent regulation to achieve dual guarantees of safety and efficiency. Compared with traditional random solutions, the random clock generating device provided in the embodiment of the present application shows significant advantages in the control of random output, and can effectively avoid the system instability caused by randomness out of control, and provides a more reliable and efficient solution for cryptographic chips and other application scenarios that require high-precision random clocks.

[0110] Figure 6 A flowchart of a clock signal output method provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the method is applied to a random clock generating device, the random clock generating device includes a selection switching unit, and the method includes:

[0111] S601, detecting whether a random sequence has a set low-frequency sequence, wherein the random sequence is generated by a random sequence generator in a random clock generating device;

[0112] S602: When a low-frequency sequence is detected, a clock number is identified from the random sequence and a corresponding clock is selected to replace the current clock to become the master clock of the random clock generator, and the master clock is used to output a clock signal controlled by the random sequence. When a low-frequency sequence is detected in the random sequence, a switching unit is selected to determine a clock corresponding to the clock number from a clock pool, and the clock corresponding to the bit is switched as the master clock of the random clock generator, and outputting the corresponding random clock signal may also include:

[0113] Selecting a first configurator in the switching unit to configure a low frequency sequence, and determining a target bit when a low frequency sequence in a random sequence is detected;

[0114] The selection switching circuit in the selection switching unit determines the clock corresponding to the target bit from the clock pool, and switches the clock corresponding to the bit as the main clock of the random clock generating device to output the corresponding random clock signal.

[0115] Figure 7 A flowchart of another clock signal output method provided in an embodiment of the present application is shown as follows: Figure 7 As shown, the method is applied to a random clock generating device, the random clock generating device includes a gating unit, and the method includes:

[0116] S701. When a high frequency sequence set in a random sequence is detected, a gating operation is performed on a master clock connected to a selection switching unit, wherein the gating operation is used to prevent a random clock signal output by the master clock from performing clock flipping.

[0117] The random clock generating device includes a gating unit, which includes a clock gating subunit, a second configurator and an efficiency control circuit. In the embodiment of the present application, when the gating unit detects a high-frequency sequence in the random sequence, the gating unit performs a gating operation on the master clock so that the random clock signal corresponding to the master clock output may include:

[0118] The second configurator configures the high frequency sequence and detects the high frequency sequence in the random sequence;

[0119] When the efficiency control circuit detects a high frequency sequence in the random sequence, it sends a gating signal to the clock gating subunit;

[0120] When receiving the gating signal, the clock gating subunit performs a gating operation on the main clock to prevent the random clock signal output by the main clock from performing clock flipping.

[0121] A clock signal output method and another clock signal output method provided in this embodiment can be used in the above-mentioned random clock generating device. Their implementation principles and technical effects are similar, and are not described in detail in this embodiment.

[0122] Figure 8 A schematic diagram of the structure of a clock signal output device provided in an embodiment of the present application, such as Figure 8 As shown, the clock signal output device 80 provided in this embodiment includes:

[0123] The identification module 801 is used to detect the low-frequency sequence in the random sequence and identify the pre-switched clock number from the random sequence, where the random sequence is generated by a random sequence generator in the random clock generating device;

[0124] The replacement module 802 is used to identify the clock number from the random sequence when a low-frequency sequence is detected, and select the corresponding clock to replace the current clock to become the master clock of the random clock generating device. The master clock is used to output a clock signal controlled by the random sequence.

[0125] In a possible implementation, the replacement module 802 may also be specifically configured to:

[0126] In response to the configuration operation, a low frequency sequence in the random sequence is configured and detected, and when the low frequency sequence is detected, a target bit is determined from the random sequence according to the low frequency sequence;

[0127] According to the target bit, a clock having a mapping relationship with the target bit is selected from a clock pool, and the clock having a mapping relationship with the target bit is switched to a master clock of a random clock generating device.

[0128] In a possible implementation, the replacement module 802 may also be specifically configured to:

[0129] When a high-frequency sequence in a random sequence is detected, a gating operation is performed on a main clock connected to the selection switching unit, and the gating operation is used to prevent a random clock signal output by the main clock from undergoing clock flipping.

[0130] In a possible implementation, the replacement module 802 may also be specifically configured to:

[0131] Detecting a high frequency sequence in the random sequence, and outputting a gating signal when the high frequency sequence in the random sequence is detected;

[0132] According to the gating signal, a gating operation is performed on the main clock connected to the selection switching unit.

[0133] In a possible implementation, the replacement module 802 may also be specifically configured to:

[0134] The high frequency sequence is configured so that the efficiency control circuit detects the high frequency sequence in the random sequence.

[0135] The clock signal output device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be described in detail here.

[0136] Fig. 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig. 9 As shown, the electronic device 90 provided in this embodiment includes: at least one processor 901 and a memory 902. Optionally, the electronic device 90 further includes a communication component 903. The processor 901, the memory 902 and the communication component 903 are connected via a bus.

[0137] In a specific implementation process, at least one processor 901 executes the computer execution instructions stored in the memory 902, so that at least one processor 901 executes the above method.

[0138] The specific implementation process of the processor 901 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0139] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly implemented as a hardware processor, or can be implemented by a combination of hardware and software modules in the processor.

[0140] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0141] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0142] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0143] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0144] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0145] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0146] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0147] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0149] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0150] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0151] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A random clock generating device, characterized in that: The random clock generating device comprises a random sequence generator, a selection switching unit and a clock pool, wherein the clock pool and the random sequence generator are respectively connected to the selection switching unit; wherein, The random sequence generator is used to generate a random sequence; The selection and switching unit is used to select and switch the main clock of the random clock generating device, and detect whether the random sequence has a set low-frequency sequence; When the low frequency sequence is detected, a clock number is identified from the random sequence and a corresponding clock is selected to replace the current clock to become the master clock of the random clock generating device; The master clock is used to output a clock signal controlled by the random sequence.

2. The random clock generation device according to claim 1, characterized in that: The clock number is determined according to a target bit, and the target bit is determined according to a position of the low-frequency sequence in the random sequence.

3. The random clock generating device according to claim 1, characterized in that: The random clock generating device includes a reference clock and a frequency dividing circuit. The frequency dividing circuit is connected between the reference clock and the clock pool. The clock in the clock pool is obtained by dividing the reference clock by the frequency dividing circuit.

4. The random clock generating device according to claim 1, characterized in that: The selection switching unit includes a first configurator and a selection switching circuit; The first configurator is used to configure and detect a low frequency sequence in the random sequence in response to a configuration operation, and when the low frequency sequence is detected, identify a clock number from the random sequence according to the low frequency sequence; The selection switching circuit is used to select a corresponding clock to replace the current clock according to the clock number identified from the random sequence, and the clock becomes the main clock of the random clock generating device.

5. The random clock generating device according to any one of claims 1 to 4, characterized in that: The occurrence frequency of the low frequency sequence in the random sequence is determined according to the run length of the low frequency sequence.

6. The random clock generation device according to claim 1, characterized in that: The random clock generating device also includes a gating unit, which is connected to the random sequence generator and the selection switching unit respectively; the gating unit is used to perform a gating operation on the main clock connected to the selection switching unit when a high-frequency sequence in the random sequence is detected, and the gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

7. The random clock generation device according to claim 6, characterized in that: The gating unit includes an efficiency control circuit, a clock gating subunit and a second configurator, the random sequence generator is connected to the efficiency control circuit and the clock gating subunit, the clock gating subunit is also connected to the selection switching unit, and the second configurator is connected to the efficiency control circuit; The second configurator is used to configure the high frequency sequence; The efficiency control circuit is used to detect the high-frequency sequence set by the second configurator in the random sequence, and output a gating signal when the high-frequency sequence in the random sequence is detected; The clock gating subunit is used to perform a gating operation on the main clock connected to the selection switching unit according to the gating signal.

8. The random clock generating device according to any one of claims 6-7, characterized in that: The frequency of occurrence of the high frequency sequence in the random sequence is determined according to the run length of the high frequency sequence.

9. A clock signal output method, characterized in that: Applied to a random clock generating device, the random clock generating device includes a selection switching unit, and the method includes: Detecting whether a set low-frequency sequence appears in a random sequence, wherein the random sequence is generated by a random sequence generator in the random clock generating device; When the low frequency sequence is detected, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock to become the master clock of the random clock generating device, and the master clock is used to output a clock signal controlled by the random sequence.

10. The method according to claim 9, characterized in that The random clock generating device further includes a gating unit, and the method further includes: When the high frequency sequence set in the random sequence is detected, a gating operation is performed on the main clock connected to the selection switching unit, and the gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

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