FPGA (Field Programmable Gate Array) upgrading method and device, equipment and medium

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) upgrading method and device, equipment and a medium. The method comprises the following steps: acquiring a current package to-be-upgraded file sent by an upper computer, and setting the state of an FPGA flag bit according to an analysis result of the current package to-be-upgraded file; determining a corresponding FLASH operation instruction according to the analysis result of the current package to-be-upgraded file; and operating the FLASH according to the FLASH operation instruction, and setting the state of the FPGA flag bit according to the execution progress of the FLASH, so that the upper computer continues to send the next to-be-upgraded file according to the state of the FPGA flag bit. By setting the FPGA flag bit, the upper computer can directly obtain the current state of the FPGA and determine the opportunity for sending the data to the FPGA according to the current state of the FPGA, so that the invalid waiting time after the upper computer sends the data to the FPGA is avoided, the problem of low data transmission between the FPGA and the upper computer when the FPGA is upgraded is solved, and the FPGA upgrading efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of FPGA communication, and in particular to an FPGA upgrading method, device, equipment and medium. Background Art

[0002] With the development of electronic semiconductor technology, FPGA is applied to more and more fields. FPGA is a semi-custom circuit with strong flexibility. When the design changes, new upgrade configuration data can be generated and loaded into FPGA to achieve functional upgrade. The upgrade configuration data of FPGA often needs to be saved in external FLASH and read and loaded at startup.

[0003] The FPGA can be upgraded by writing the new upgrade configuration data into FLASH. Most of the commonly used FPGA upgrade methods use the protocol method. The MCU side acts as the host and sends the upgrade data. The FPGA acts as the slave and receives the data for parsing, and then sends a response command to the MCU side, and writes the parsed data into FLASH. After receiving the response command, the MCU side needs to wait for a while before sending the next data. During the upgrade process, the process of sending responses and waiting between the MCU and FPGA wastes too much time, resulting in each upgrade taking a long time. Especially when the FPGA chip resources are large, the upgrade time increases exponentially, greatly reducing the upgrade efficiency of the FPGA. Summary of the invention

[0004] The present invention provides an FPGA upgrade method, device, equipment and medium to solve the problem of low data transmission efficiency between the FPGA and a host computer MCU when upgrading the FPGA.

[0005] According to one aspect of the present invention, there is provided a method for upgrading an FPGA, comprising:

[0006] Obtain the current package to be upgraded file sent by the host computer, and set the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file;

[0007] Determine the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package;

[0008] The FLASH is operated according to the FLASH operation instruction, and the state of the FPGA flag is set according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the state of the FPGA flag.

[0009] According to another aspect of the present invention, there is provided an FPGA upgrading device, comprising:

[0010] A first flag status setting module is used to obtain the current package to be upgraded file sent by the host computer, and set the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file;

[0011] An operation instruction determination module, used to determine the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package;

[0012] The second flag status setting module is used to operate the FLASH according to the FLASH operation instruction and set the status of the FPGA flag according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the status of the FPGA flag.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the FPGA upgrading method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the FPGA upgrade method described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention sets the FPGA flag so that the host computer MCU can directly obtain the current state of the FPGA, and determines the timing of sending data to the FPGA according to the current state of the FPGA, thereby avoiding invalid waiting time after the host computer sends data to the FPGA, solving the problem of low data transmission between the host computer MCU and the host computer when upgrading the FPGA, and achieving the beneficial effect of improving the efficiency of FPGA upgrade.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flowchart of an FPGA upgrade method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a flowchart of an FPGA upgrade method provided according to Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of the overall framework of an FPGA upgrade system provided according to Embodiment 3 of the present invention;

[0024] Figure 4 is a structural schematic diagram of an FPGA upgrading device provided according to a fourth embodiment of the present invention;

[0025] Figure 5 It is a structural schematic diagram of an electronic device for implementing the FPGA upgrading method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "candidate", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1 A flowchart of an FPGA upgrade method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of upgrading the software program of the FPGA. The method can be executed by an FPGA upgrade device. The FPGA upgrade device can be implemented in the form of hardware and / or software. The FPGA upgrade device can be configured in the FPGA. Figure 1 As shown, the method includes:

[0030] S110, obtaining the current package to be upgraded file sent by the host computer, and setting the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file.

[0031] Among them, the host computer refers to a setting that controls the FPGA and has data transmission capability with the FPGA. For example, the host computer can be an MCU (Microcontroller Unit), that is, a single-chip microcomputer. The current package to be upgraded file refers to a data packet in the file to be upgraded currently sent by the host computer. Since the complete file to be upgraded is generally large, when the host computer sends the file to be upgraded, it usually divides the file to be upgraded into several data packets for transmission. When the FPGA processes a data packet, it cannot process other data packets. Therefore, the host computer needs to wait for the FPGA to process a data packet before continuing to send the next data packet. Therefore, in the present invention, an FPGA flag bit is set in the FPGA, and the current data processing progress of the FPGA is determined by the state of the FPGA flag bit. For example, when the FPGA flag bit is in a low state, it indicates that the FPGA is in an idle state, and the data sent by the host computer can be received at this time; when the FPGA flag bit is in a high state, it indicates that the FPGA is in a busy state, and the data sent by the host computer cannot be received at this time.

[0032] Specifically, the current package to be upgraded file sent by the host computer is obtained, the current package to be upgraded file is parsed, the operation instruction sent by the host computer is determined according to the parsing result, and the state of the FPGA flag bit is set according to the operation instruction, so that the operation currently being performed by the FPGA can be clearly understood according to the state of the FPGA flag bit.

[0033] In a feasible embodiment, the state of the FPGA flag bit is set according to the parsing result of the file to be upgraded in the current package, including:

[0034] If the parsing result is an erase FLASH instruction or a write FLASH instruction, the FPGA flag bit is pulled high;

[0035] If the parsing result is a FLASH read instruction, the FPGA flag bit is kept in a low state;

[0036] When the FPGA flag is in a low state, the host computer continues to send the next package of files to be upgraded; when the FPGA flag is in a high state, the host computer stops sending the next package of files to be upgraded.

[0037] Since erasing and writing FLASH requires FPGA to send data to FLASH, and reading FLASH requires FPGA to send data to the host computer, the reading FLASH operation does not affect the data transmission between the host computer and FPGA, while erasing and writing FLASH affects the data transmission between the host computer and FPGA. Therefore, the current package to be upgraded is parsed to obtain the data header and data. According to the data header, it is determined that the instruction sent by the host computer is an erase FLASH instruction or a write FLASH instruction, which means that FPGA needs to write data to FLASH. FPGA, as the host, pulls up the FPGA flag to indicate that FPGA is busy and does not receive data from the host computer to FPGA at this time; if it is determined that the instruction sent by the host computer is a read FLASH instruction according to the data header, it means that FPGA does not need to write data to FLASH. FPGA only needs to take out the data of the corresponding sector from FLASH according to the read address sent by the host computer and send the data to the host computer. At this time, the FPGA flag is kept in a low state, indicating that FPGA is in an idle state and can receive data sent by the host computer to FPGA.

[0038] By setting the status of the FPGA flag bit through the analysis results, the FPGA can indicate its own status information at the first time, further ensuring the timeliness of the host computer sending the next packet of data and avoiding the invalid waiting time in the middle. In particular, when the FPGA receives the read data instruction, the FPGA flag bit is still kept in a low state, so that the file data to be upgraded sent by the host computer can still be received during the data reading process. During the FPGA reading data process, the host computer determines that the FPGA is in an idle state according to the FPGA flag bit, and directly sends the next package of files to be upgraded to the FPGA, without the need for the FPGA's response message and without waiting for a period of time before sending data, which greatly shortens the time span for the host computer to send data and improves the upgrade efficiency.

[0039] S120: Determine the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package.

[0040] According to the current package to be upgraded file sent by the host computer, the current package to be upgraded is parsed to obtain the data header and data, the instruction sent by the host computer is determined according to the data header, and the operation instruction sent by the FPGA to the FLASH is generated according to the instruction and data. For example, the FLASH erase operation instruction, the FLASH write operation instruction or the FLASH read operation instruction.

[0041] S130, operating the FLASH according to the FLASH operation instruction, and setting the state of the FPGA flag bit according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the state of the FPGA flag bit.

[0042] According to different operation instructions, the FLASH is operated accordingly. Specifically, the FPGA operates the FLASH according to the FLASH hardware manual.

[0043] The FPGA also includes a FLASH read status module, which is used to determine the current operation execution progress of the FLASH and set the state of the FPGA flag bit according to the operation execution progress. Exemplarily, the FPGA determines the current operation execution progress of the FLASH. If the FLASH is not currently erased or the current data is not fully written, it means that the current interaction between the FPGA and the FLASH is not completed, and the FPGA flag bit is kept in a high state; if the FLASH is currently erased or the current data is fully written, it means that the current interaction between the FPGA and the FLASH is completed, and the FPGA flag bit is pulled down, indicating that the FPGA can perform an operation.

[0044] The status of the FPGA flag is set according to the execution progress of FLASH, which improves the accuracy of the FPGA flag and the timeliness of the status representation.

[0045] In a feasible embodiment, the state of the FPGA flag bit is set according to the execution progress of the FLASH, including:

[0046] Send periodic FLASH status read instructions to FLASH, and determine the execution progress of FLASH according to the status of FLASH;

[0047] If FLASH is in idle state, pull down the FPGA flag bit;

[0048] If FLASH is in busy state, the FPGA flag bit is kept high.

[0049] FPGA periodically sends status read requests to FLASH to obtain the current status of FLASH. If FLASH is in the idle state, it means that FLASH has completed processing the current instruction. If FLASH is in the busy state, it means that FLASH has not completed processing the current instruction.

[0050] If FLASH is in idle state, FPGA can continue to receive data sent by the host computer, and the FPGA flag bit will be pulled low; if FLASH is in busy state, FPGA still needs to maintain data interaction with FLASH, and the FPGA flag bit needs to be kept high to inform the host computer that the current FPGA cannot receive new upgrade files.

[0051] The timeliness of FPGA's determination of FLASH status is improved through periodic FLASH status reading instructions, and the timeliness of host computer's determination of FPGA status is further improved.

[0052] In a feasible embodiment, the state of FLASH is determined according to the FLASH flag bit.

[0053] When FLASH is in the erase operation or write operation, its own FLASH flag is pulled high; when it is not in the erase operation or write operation, its own FLASH flag is pulled low. By setting the FLASH flag, FPGA only needs to automatically read the FLASH flag to determine the FLASH status, without waiting for FLASH to respond to the status read request, thereby improving the efficiency of FLASH status acquisition.

[0054] In a feasible embodiment, the host computer periodically reads the status of the FPGA flag bit.

[0055] The timeliness of the host computer's determination of the FPGA status is improved through periodic FPGA flag reading instructions, and the setting of the FPGA flag makes it possible for the host computer to determine the FPGA status only by automatically reading the FPGA flag, without waiting for the FPGA to respond to the host computer's status reading request, thereby improving the efficiency of FPGA status acquisition and further improving the upgrade efficiency.

[0056] The technical solution of the embodiment of the present invention sets the FPGA flag so that the host computer MCU can directly obtain the current state of the FPGA, and determines the timing of sending data to the FPGA according to the current state of the FPGA, thereby avoiding invalid waiting time after the host computer sends data to the FPGA, solving the problem of low data transmission between the host computer MCU and the host computer when upgrading the FPGA, and achieving the beneficial effect of improving the efficiency of FPGA upgrade.

[0057] Embodiment 2

[0058] Figure 2 This is a flowchart of an FPGA method provided in the second embodiment of the present invention. This embodiment further describes the steps in the above embodiment in detail. Figure 2 As shown, the method includes:

[0059] S210, obtaining the current package to be upgraded file sent by the host computer, and setting the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file.

[0060] S220: Determine the data length and starting address of the file to be upgraded in the current package according to the parsing result of the file to be upgraded in the current package.

[0061] The data length indicates the size of the upgrade data included in the current package to be upgraded. The FPGA needs to write the upgrade data of this data length into the FLASH. The start address refers to the start address of the data written into the FLASH.

[0062] Specifically, the current package of files to be upgraded is parsed to obtain the data header and data, the starting address is determined according to the data header information, the data is counted, and the data length is obtained. Since the upper computer randomly divides the files to be upgraded into packets, the data length of the current package of files to be upgraded sent each time is different.

[0063] S230, the current package of files to be upgraded is divided into packets according to the data length, and the FLASH write operation instruction is determined according to the packet division result and the starting address.

[0064] The subpackaging result at least includes the subpackaging quantity, so as to determine the writing progress of the files to be upgraded in the current package according to the subpackaging quantity.

[0065] Since the data length of the current package of files to be upgraded sent by the host computer each time is different, in order to facilitate FPGA to determine the progress of writing data to FLASH, on the basis of determining the data length of the current package of files to be upgraded, the current package of files to be upgraded is sub-packetized according to fixed bytes. According to the data length and the fixed bytes of each package of data, the number of sub-packets and the data in each package that are written to FLASH can be determined. According to the count of the number of sub-packets, the progress of writing the current package of files to be upgraded to FLASH can be determined. According to the data of each package in the sub-packetization result, the FLASH write operation instruction is determined.

[0066] Specifically, when the host computer sends data, the FPGA acts as a slave and caches the data sent by the host computer. Since the length of the sent data is not fixed, the FPGA counts the data length and determines the FLASH write operation instruction based on the starting address when the host computer sends it, starting from the starting address according to a fixed byte packet, and writes the data into the FLASH. When the last packet of data is less than 256, 8'hFF will be added and written into the FLASH.

[0067] The fixed bytes of each packet are determined according to the size of data written to the FLASH at one time. For example, if the writing is performed in a page writing mode, the fixed bytes are determined according to the page writing capability and are set to 256 bytes.

[0068] S240, operate the FLASH according to the FLASH operation instruction, determine that the FLASH write operation of the last packet of data is completed according to the number of sub-packets, and then pull up the FPGA flag bit.

[0069] Among them, the progress of writing the current package of files to be upgraded can be determined according to the number of sub-packets. Therefore, in the process of FPGA writing to FLASH, the number of writes is counted. When the number of writes is equal to the number of sub-packets, it means that the last sub-packet data of the current package of files to be upgraded is currently being written to FLASH. If the state of FLASH is monitored to change, it means that the FLASH write operation is completed. At this time, it means that the FPGA has completed writing the current package of files to be upgraded to FLASH, and the FPGA flag is pulled high. The efficiency of FPGA in determining the progress of its own execution tasks is improved, and then the accuracy of the host computer in determining the timing of sending data according to the FPGA flag is improved, and the upgrade efficiency is improved.

[0070] In a feasible embodiment, the method further includes: determining the total data length of the file to be upgraded according to the parsing result of the file to be upgraded in the current package;

[0071] Determine whether the upgrade file of the host computer has been sent completely according to the comparison result of the total data length and the data length of the currently received upgrade file;

[0072] If the sending is completed, the status of the FPGA flag bit is set according to the execution progress of FLASH, and the self-restart operation is performed to upgrade.

[0073] Among them, the total data length represents the total length of the file to be upgraded. Since the host computer sends the complete file to be upgraded in packets, one packet at a time, when the host computer sends data, FPGA, as a slave, cannot determine whether the host computer has completed the sending. According to the determination of the total data length, FPGA determines the progress of receiving the file to be upgraded, and then can upgrade itself when the file to be upgraded is received. There is no need to wait for the host computer to send a message for upgrading, thereby improving the upgrading efficiency.

[0074] Specifically, the first package of files to be upgraded sent by the host computer includes the total data length information of the files to be upgraded. For example, the total data length information is stored in the data header of the first package of files to be upgraded. The first package of files to be upgraded is parsed to obtain the data header and the first package of data. The data length of the current package data and the total data length of the complete file to be upgraded are determined according to the data header.

[0075] Each time the FPGA receives a packet of files to be upgraded, the data length of the received files to be upgraded is accumulated. If the accumulated result reaches the total data length, it indicates that the current packet of files to be upgraded is the last packet of the complete files to be upgraded. Then, when the current packet of files to be upgraded is written into the FLASH, a self-restart operation can be performed for upgrading. If the accumulated result does not reach the total data length, it indicates that the complete files to be upgraded have not been sent. After the current packet of files to be upgraded is processed according to the execution progress of the FLASH, the status of the FPGA flag is modified. After the upper computer detects the status modification of the FPGA flag, it continues to send the next packet of files to be upgraded.

[0076] Through the self-monitoring of the total data length by FPGA, the FPGA can determine the upgrade timing by itself without waiting for the host computer to send an upgrade command, thereby improving the upgrade efficiency.

[0077] The embodiment of the present invention determines the data length of the file to be upgraded in the current package through FPGA, and sub-packets the sent data, and determines the timing of setting the FPGA flag bit in combination with the sub-packetization result and the FLASH execution progress. On the basis of ensuring the accuracy of the FPGA flag bit representation, the efficiency of FPGA flag bit modification is improved, thereby shortening the invalid waiting time of the upper computer sending data and improving the upgrade efficiency.

[0078] Embodiment 3

[0079] Figure 3 The overall framework diagram of an FPGA upgrade system provided by the third embodiment of the present invention is shown in FIG. Figure 3 As shown, the system includes:

[0080] MCU, that is, the upper computer, as the host, determines the time to send the file to be upgraded according to the FPGA flag. If the FPGA flag is detected to be high, it means that the FPGA is currently performing data operations and continues to wait until the next time the FPGA flag is detected to be low, then the file to be upgraded is sent. FPGA receives data as a slave. After receiving the data, FPGA parses it and determines different operation instructions based on the parsing results to perform corresponding operations on FLASH.

[0081] The FPGA includes a data transceiver state control module, which is used to control the reception of data sent by the MCU and the control of sending data to the MCU, and to parse the data sent by the MCU, and determine the execution module corresponding to the subsequent operation according to the parsing result. Specifically, after receiving the data sent by the MCU, the data transceiver state control module parses the data, and if it is determined that the data corresponds to an erase FLASH instruction, the received data is sent to the FLASH erase module; if it is determined that the data corresponds to a write FLASH instruction, the received data is sent to the FLASH write module, and if it is determined that the data corresponds to a read FLASH instruction, the received data is sent to the FLASH read module.

[0082] If the parsing result is an erase FLASH instruction or a write FLASH instruction, the FPGA flag is pulled high; if the parsing result is a read FLASH instruction, the FPGA flag is kept in a low state.

[0083] After receiving the erase data, the FLASH erase module determines the erase address in the corresponding FLASH according to the erase data, and erases the FLASH according to the erase address; after the erase is completed, the FLASH flag is pulled low, and the FLASH write module starts to work and divides the data into packets according to the received write data. Since the data length is not fixed, it is necessary to count the data length, and write the data into FLASH from the starting address according to the starting address when the MCU sends it, in packets of 256 bytes. When the last packet of data is less than 256, 8'hFF will be added and written into FLASH. For any length of byte data sent by the MCU, the FPGA can correctly divide the data into packets after receiving it and write it into the corresponding address of the FLASH.

[0084] After receiving the read address, the FLASH read module retrieves the data of the corresponding sector from the FLASH according to the read address sent by the MCU, and sends the data to the MCU. The FLASH read status module is a module that executes periodic FLASH status read instructions to the FLASH to determine the progress of FLASH task execution. The function of the FLASH control module is to connect to the external FLASH and implement various FLASH operations.

[0085] When the FPGA receives the erase or write FLASH instruction sent by the MCU, the FPGA will pull the flag high until the falling edge of the busy signal of the FLASH arrives, and then pull the FPGA flag low, so that the MCU and the FPGA can accurately and efficiently determine whether the current data area to be written has been completely erased. Specifically, for the judgment of the completion of the erase, the FPGA can judge by judging whether the FLASH flag is pulled low. Since there will be a delay between the MCU to the FPGA and then the FPGA to the FLASH, the MCU cannot directly judge the FLASH flag. Therefore, the flag is set by the FPGA as a busy flag for the MCU to judge, so as to improve the accuracy and efficiency of the MCU to determine the timing of sending data. When the MCU writes data to the FPGA, the FPGA acts as a slave, and when the FPGA writes data to the FLASH, the FPGA acts as a host. The FPGA performs a master-slave conversion in the middle, and the downlink data needs to be written into the FLASH, and the uplink data is correctly sent to the MCU. Through the FPGA flag, the FPGA can correctly and efficiently inform the MCU of the current status during the master-slave conversion process.

[0086] In the embodiment of the present invention, the FPGA code upgrade time will completely depend on the hardware process of FLASH, the FLASH erase time and the FLASH page write time. In most cases, the vast majority of FLASH upgrades about 2MB of code once, and the upgrade time will be able to be completed in about 50 seconds, which is about 15 times faster than the previous upgrade of 10 minutes. In the process of reading back the firmware, the present invention can be used to read back in about 30 seconds, which is about 20 times faster, greatly saving the developer's time cost.

[0087] The present invention realizes the upgrade and readback of FPGA code in the shortest time supported by FLASH hardware, and can make FPGA restart automatically after power failure, thereby greatly improving the efficiency of updating functions and reading back firmware versions during the FPGA development process.

[0088] Embodiment 4

[0089] Figure 4 This is a schematic diagram of the structure of an FPGA upgrade device provided by Embodiment 4 of the present invention. Figure 4 As shown, the device comprises:

[0090] The first flag bit state setting module 410 is used to obtain the current package to be upgraded file sent by the host computer, and set the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file;

[0091] An operation instruction determination module 420 is used to determine a corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package;

[0092] The second flag state setting module 430 is used to operate the FLASH according to the FLASH operation instruction and set the state of the FPGA flag according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the state of the FPGA flag.

[0093] Optionally, the operation instruction determination module includes:

[0094] Determine the data length and starting address of the file to be upgraded in the current package according to the parsing result of the file to be upgraded in the current package;

[0095] The current package of files to be upgraded is divided into packets according to the data length, and the FLASH write operation instruction is determined according to the packet division result and the starting address; wherein the packet division result at least includes the number of packets, so as to determine the writing progress of the current package of files to be upgraded according to the number of packets;

[0096] Correspondingly, the second flag state setting module includes a second FPGA flag setting unit, which is used to:

[0097] The FLASH write operation of the last packet of data is determined to be completed according to the number of sub-packets, and the FPGA flag is pulled high.

[0098] Optionally, the first flag state setting module includes a first FPGA flag setting unit, which is used to:

[0099] If the parsing result is an erase FLASH instruction or a write FLASH instruction, the FPGA flag bit is pulled high;

[0100] If the parsing result is a FLASH read instruction, the FPGA flag bit is kept in a low state;

[0101] When the FPGA flag is in a low state, the host computer continues to send the next package of files to be upgraded; when the FPGA flag is in a high state, the host computer stops sending the next package of files to be upgraded.

[0102] Optionally, the second flag state setting module includes a second FPGA flag setting unit, which is used to:

[0103] Send periodic FLASH status read instructions to FLASH, and determine the execution progress of FLASH according to the status of FLASH;

[0104] If FLASH is in idle state, pull down the FPGA flag bit;

[0105] If FLASH is in busy state, the FPGA flag bit is kept high.

[0106] Optionally, the state of FLASH is determined according to a FLASH flag bit.

[0107] Optionally, the device further includes a restart upgrade module, which is used to:

[0108] Determine the total data length of the file to be upgraded according to the parsing result of the file to be upgraded in the current package;

[0109] Determine whether the upgrade file of the host computer has been sent completely according to the comparison result of the total data length and the data length of the currently received upgrade file;

[0110] If the sending is completed, the status of the FPGA flag bit is set according to the execution progress of FLASH, and the self-restart operation is performed to upgrade.

[0111] Optionally, the host computer periodically reads the status of the FPGA flag bit.

[0112] The FPGA upgrade device provided in the embodiment of the present invention can execute the FPGA upgrade method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0113] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations and do not violate public order and good morals.

[0114] Embodiment 5

[0115] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0116] Figure 5 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0117] like Figure 5As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0118] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0119] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 performs the various methods and processes described above, such as the method FPGA upgrade.

[0120] In some embodiments, the method FPGA upgrade can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method FPGA upgrade described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the method FPGA upgrade in any other appropriate manner (for example, by means of firmware).

[0121] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific reference products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0122] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0123] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0124] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0125] The systems and techniques described herein may be implemented in a computing system that includes a backend component (e.g., as a data server), or a computing system that includes a switch component (e.g., an application server), or a computing system that includes a frontend component (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, switch components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0126] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0127] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0128] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for upgrading an FPGA, characterized in that: The method includes: Obtain the current package to be upgraded file sent by the host computer, and set the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file; Determine the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package; The FLASH is operated according to the FLASH operation instruction, and the state of the FPGA flag is set according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the state of the FPGA flag.

2. The method according to claim 1, characterized in that: Determining the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package includes: Determine the data length and starting address of the file to be upgraded in the current package according to the parsing result of the file to be upgraded in the current package; The files to be upgraded in the current package are sub-packaged according to the data length, and a FLASH write operation instruction is determined according to the sub-package result and the start address; wherein the sub-package result at least includes the number of sub-packages, so as to determine the writing progress of the files to be upgraded in the current package according to the number of sub-packages; Accordingly, the state of the FPGA flag bit is set according to the execution progress of FLASH, including: The FLASH write operation of the last packet of data is determined to be completed according to the number of sub-packets, and then the FPGA flag is pulled high.

3. The method according to claim 1, characterized in that: The state of the FPGA flag bit is set according to the parsing result of the file to be upgraded in the current package, including: If the analysis result is an erase FLASH instruction or a write FLASH instruction, the FPGA flag is pulled high; If the parsing result is a FLASH read instruction, the FPGA flag is kept in a low state; Wherein, when the FPGA flag is in a low state, the host computer continues to send the next package of files to be upgraded; when the FPGA flag is in a high state, the host computer stops sending the next package of files to be upgraded.

4. The method according to claim 3, characterized in that The state of the FPGA flag bit is set according to the execution progress of FLASH, including: Sending a periodic FLASH status reading instruction to the FLASH, and determining the execution progress of the FLASH according to the status of the FLASH; If the FLASH is in an idle state, the FPGA flag bit is pulled low; If the FLASH is in a busy state, the FPGA flag is kept in a high state.

5. The method according to claim 4, characterized in that The state of the FLASH is determined according to the FLASH flag bit.

6. The method according to claim 1, characterized in that The method further comprises: Determine the total data length of the file to be upgraded according to the parsing result of the file to be upgraded in the current package; Determine whether the file to be upgraded of the host computer has been sent completely according to the comparison result of the total data length and the data length of the currently received file to be upgraded; If the sending is completed, the state of the FPGA flag bit is set according to the execution progress of FLASH, and a self-restart operation is performed to upgrade.

7. The method according to claim 1, characterized in that The host computer periodically reads the status of the FPGA flag bit.

8. An FPGA upgrade device, characterized in that: The device includes: A first flag bit status setting module is used to obtain the current package to be upgraded file sent by the host computer, and set the state of the FPGA flag bit according to the parsing result of the current package to be upgraded file; An operation instruction determination module, used to determine the corresponding FLASH operation instruction according to the parsing result of the file to be upgraded in the current package; The second flag status setting module is used to operate the FLASH according to the FLASH operation instruction and set the status of the FPGA flag according to the execution progress of the FLASH, so that the host computer continues to send the next package of files to be upgraded according to the status of the FPGA flag.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the FPGA upgrading method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the FPGA upgrade method according to any one of claims 1 to 7 when executed.

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