Processor random verification program generation method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a processor random verification program generation method and device, equipment and a storage medium, and the method comprises the steps: generating a target processing instruction for a target instruction which may generate an unpredictable execution result during loop execution in a loop instruction sequence; inserting the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used for processing an operand in a source register of the target instruction before the target instruction is executed in each cycle execution process, so that the target instruction generates a predictable execution result in the cycle process. Thus, the execution result of the target instruction in the loop instruction sequence can be predicted, it is not needed to avoid the instruction with the execution result unpredictable in the instruction sequence, the instruction types in the loop instruction sequence are enriched, the verification efficiency of the microprocessor is improved, and the verification efficiency of the microprocessor is improved. And the quality of the random verification program and the convergence speed of the function verification coverage rate are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method for generating a random verification program for a processor, a device for generating a random verification program for a processor, an electronic device, and a storage medium. Background Art

[0002] With the development of very large-scale integrated circuit technology, the structure of microprocessors has become more and more complex, and more and more functions have been integrated on a single microprocessor chip. The instruction set of microprocessors has been continuously expanded, and the number and types of instructions have increased significantly, resulting in the functional verification of microprocessors becoming very complex and the verification cycle is very long, which will inevitably affect the development time of the processor.

[0003] During the microprocessor function verification process, it is necessary to compare the results of the RTL (Register Transfer Level) execution of the instructions in the test program with the "prediction" results of the verification platform for the instructions in the test program to prove the correctness of the RTL function. However, during the function verification process, the results of the RTL execution of the test program may be random values, and the verification personnel cannot know the execution results of the instructions in advance. In this way, it is impossible to verify the correctness of the instruction function through simulation comparison results. Therefore, in order to enable the verification personnel to know the execution results of the instructions in advance, instructions whose execution results cannot be predicted are often avoided in the loop instruction sequence. The instruction types in the loop instruction sequence are limited, and the convergence speed of the functional verification coverage is slow. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a method for generating a random verification program for a processor that overcomes the above problems or at least partially solves the above problems, so as to improve the convergence speed of functional verification coverage.

[0005] Correspondingly, an embodiment of the present invention also provides a processor random verification program generation device, an electronic device and a storage medium to ensure the implementation and application of the above method.

[0006] In order to solve the above problem, an embodiment of the present invention discloses a method for generating a random verification program for a processor, wherein the random verification program includes a cyclic instruction sequence, including:

[0007] generating a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped;

[0008] The target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during this loop process.

[0009] The embodiment of the present invention further discloses a device for generating a random verification program for a processor, wherein the random verification program includes a sequence of instructions to be executed cyclically, including:

[0010] A first generating module, configured to generate a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped;

[0011] The first insertion module is used to insert the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during the current loop process.

[0012] The embodiment of the present invention further discloses an electronic device including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors. The one or more programs include instructions for performing the following operations:

[0013] generating a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped;

[0014] The target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during this loop process.

[0015] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute one or more processor random verification program generation methods described in the embodiments of the present invention.

[0016] The embodiments of the present invention include the following advantages:

[0017] In an embodiment of the present invention, a target processing instruction is generated for a target instruction in a loop instruction sequence that may produce an unpredictable execution result when being executed in a loop; the target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operands in the source register of the target instruction before the target instruction is executed during each loop execution, so that the target instruction produces a predictable execution result during the loop. In this way, the operands in the source register of the target instruction can be processed by the target processing instruction, so that the execution result of the target instruction in the loop instruction sequence is predictable, and there is no need to avoid the appearance of instructions with unpredictable execution results in the instruction sequence, so that the target instruction can appear in the loop instruction sequence as an internal instruction, enriching the instruction types in the loop instruction sequence, and improving the quality of the random verification program to a certain extent, which is conducive to improving the verification efficiency of the microprocessor and improving the convergence speed of the functional verification coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flowchart of a method for generating a random verification program for a processor according to an embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of a dead loop phenomenon caused by a "J" type jump instruction of the present invention;

[0020] Figure 3 It is a specific schematic diagram of an embodiment of a method for generating a random verification program for a processor according to the present invention;

[0021] Figure 4 It is a flow chart of detecting and modifying the values ​​of operands in a divisor register and a dividend register based on a target processing instruction of the present invention;

[0022] Figure 5 It is a structural block diagram of an embodiment of a processor random verification program generation device of the present invention;

[0023] Figure 6 The present invention is a structural block diagram of an electronic device for generating a random verification program for a processor according to an exemplary embodiment. DETAILED DESCRIPTION

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Reference Figure 1 , shows a flowchart of the steps of an embodiment of a method for generating a random verification program for a processor of the present invention, wherein the random verification program includes a cyclic instruction sequence, and the above method can be applied to a processor.

[0026] The random instruction verification program is an instruction sequence generated based on some constraint information in a certain way. The instruction types contained in the random instruction verification program and the number of instructions corresponding to each type of instruction can be randomly set. In practical applications, the instructions in the random instruction verification program can be divided into random instructions and directed instructions according to the constraint information or the instruction generation method. Among them, the instruction type and instruction sequence of the random instructions are usually unconstrained. By presetting the weight value of each instruction in advance, in the process of generating the random instruction verification program, the instruction type of the random instruction generated at a certain moment is randomly selected according to the weight value corresponding to each instruction type.

[0027] The specific steps may include:

[0028] Step 101 : Generate a target processing instruction for a target instruction that may produce an unpredictable execution result when being executed cyclically.

[0029] In an embodiment of the present invention, a random instruction verification method for a microprocessor includes generating instructions and obtaining relevant running data when the instructions are simulated and executed on a verification platform. A loop instruction sequence refers to an instruction sequence that is executed in a loop in a random verification program, and the loop instruction sequence can be a loop body. The loop instruction sequence in the random instruction verification program is used to simulate the loop execution behavior of the microprocessor on the same program in an actual application. When the random instruction verification program includes a loop instruction sequence and it is determined that the loop instruction sequence contains a target instruction that may produce an unpredictable execution result when it is executed in a loop, a target processing instruction is generated. The target instruction is "unpredictable" in its execution result, such as the execution result of the target instruction can be a random value, wherein the target instruction can include a jump instruction, a division instruction, and a remainder instruction, etc.

[0030] Step 102: insert the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution, so that the target instruction produces a predictable execution result during the loop.

[0031] In an embodiment of the present invention, after generating a target processing instruction, the target processing instruction is inserted into a specified position in a loop instruction sequence to process the value of the operand in the source register indicated by the target instruction. The processor includes a plurality of general registers, for example, the processor may include 32 general registers. The meaning of the source register of the target instruction is that before generating the target instruction, a source register is randomly selected as the starting address for storing the specified data of the target instruction. Each target instruction may specify one or more source registers, which may be specifically determined according to the type of the target instruction. Exemplarily, in the case where the target instruction is a jump instruction, the source register may be one, and the target address (TargetAddr) of the jump instruction may be obtained by adding an immediate number to the operand stored in the source register; in the case where the target instruction is a division instruction, the source register may be two, wherein the operand stored in one source register is used as a divisor, and the register may be referred to as a divisor register, and the operand stored in another source register is used as a dividend, and the register may be referred to as a dividend register. The target processing instruction is used to judge the operand in the source register of the target instruction based on the target processing instruction before the target instruction is executed during the loop execution of the loop instruction sequence, and process the operand if the operand in the source register meets the preset conditions, so that the target instruction produces a predictable execution result during this loop process.

[0032] Optionally, after step 102, the embodiment of the present invention may further include the following steps:

[0033] Step 103: Based on the loop logic of the loop instruction sequence, loop execute the loop instruction sequence including the target processing instruction.

[0034] In the embodiment of the present invention, based on the loop logic of the loop instruction sequence, the loop instruction sequence including the target processing instruction is executed cyclically. After the loop instruction sequence is generated, each internal instruction (such as the target instruction and the target processing instruction) of the loop instruction sequence is executed one by one until the loop end condition is met, the execution of the loop instruction sequence is terminated, the loop instruction sequence is jumped out, and the ordinary random instructions are continuously generated and executed.

[0035] In summary, in the embodiment of the present invention, a target processing instruction is generated for a target instruction in a loop instruction sequence that may produce an unpredictable execution result when being executed in a loop; the target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operands in the source register of the target instruction before the target instruction is executed during each loop execution, so that the target instruction produces a predictable execution result during the loop. In this way, the operands in the source register of the target instruction can be processed by the target processing instruction, so that the execution result of the target instruction in the loop instruction sequence is predictable, and there is no need to avoid the appearance of instructions with unpredictable execution results in the instruction sequence, so that the target instruction can appear in the loop instruction sequence as an internal instruction, enriching the instruction types in the loop instruction sequence, and improving the quality of the random verification program to a certain extent, which is conducive to improving the verification efficiency of the microprocessor and improving the convergence speed of the functional verification coverage.

[0036] Optionally, the target instruction includes a "J" type jump instruction, and the target address (TargetAddr) of the "J" type jump instruction is obtained by adding the source register value to the immediate value. Therefore, when such an instruction appears in a loop instruction sequence, the TargetAddr will appear at some illegal addresses (the jump target address is uncontrollable) as the value inside the register changes, which may cause an infinite loop. Figure 2 The example of the "J" type jump instruction causing an infinite loop is shown below. Figure 2 The instruction sequence from "inst1" to "inst5" in the program is a loop body, and the target address of the "J" type jump instruction is related to the value of the operand in the $n register, that is, the target address is determined by the value of the operand in the $n register and the immediate value (imm). However, if the "inst4" instruction happens to select the $n register as the target storage address of the calculation result, that is, the result of the calculation is stored in the $n register, when the "inst4" instruction is executed, the value in the $n register will be modified. In the actual execution process, the ideal program execution direction is “inst1”->“…”->“inst2”->“J”->“inst3”->“inst4”->“…”->“inst5”->“inst1”->“…”->“inst2”->“J”->“inst3”->“inst4”->“…”, but because the “inst4” instruction will modify the value of the operand in the $n register, this will cause the target address of the “J” type jump instruction to change. If the target address happens to fall at the position of “inst2”, the program will fall into “inst2”->“J”->“inst2”->“J”->“inst2”->“…”, which is an infinite loop.

[0037] It can be understood that the “J” type jump instructions are instructions that can implement a jump function, and may include a “J” instruction, a “JR” instruction, a “JAL” instruction, and the like.

[0038] In the case where the target instruction includes a J-type instruction, correspondingly, the target processing instruction may be used to modify the operand in the source register indicated by the J-type jump instruction to a fixed value.

[0039] Accordingly, the step of generating the target processing instruction in step 101 may include:

[0040] In an embodiment of the present invention, when it is determined that a J-type jump instruction is included in a loop instruction sequence, a register is randomly selected as the source register indicated by the J-type jump instruction, and the generation of the J-type jump instruction is suspended, a target processing instruction is generated, and the value of the operand in the source register is modified to a fixed value using the target processing instruction. The target processing instruction may be a write register instruction, such as an "LI" instruction, and the target processing instruction is used to modify the value of the operand in the source register indicated by the J-type jump instruction to a fixed value to ensure that the TargetAddr remains unchanged (i.e., it can be predicted) during the loop execution of the instruction. The source register indicated by the J-type jump instruction may be a source operand register (sReg). Exemplarily, the fixed value may be a first target value, and the value of the first target value may be a used instruction counter (Program Counter, PC) address (usedPc), that is, the TargetAddr of the J-type jump instruction falls near usedPc, avoiding the risk of failure in finding a legal address. By loading a fixed value (first target value) into the source register, it is ensured that the loaded J-type jump instruction can find an address space that allows the instruction to be stored within the valid target address range.

[0041] Accordingly, step 102 may include the following steps:

[0042] Step 201: Insert the target processing instruction before the J-type jump instruction.

[0043] In the embodiment of the present invention, before the target processing instruction is inserted into the execution position of the J-type jump instruction, after the target processing instruction modifies the value of the operand in the source register to a fixed value, the J-type jump instruction is continuously generated, and the target processing instruction is bound to the J-type jump instruction, that is, each time the loop instruction sequence is repeatedly executed, the J-type jump instruction is executed after the target processing instruction is executed. For example, Figure 3As shown, a fixed value (usedPc) is loaded into the $n register (source register) at the "inst2" instruction position. In this way, during the loop execution, each time a "J" type jump instruction is executed, the value in the $n register (source register) remains unchanged, which is usedPc. That is, the target address of the "J" type jump instruction can be controlled to remain unchanged, and the random instruction verification program is controllable. In this case, even if the "inst4" instruction modifies the value in the $n register, when another loop is started, "inst2" will change the value in this register to usedPc.

[0044] In an embodiment of the present invention, by generating a target processing instruction, the value of the operand in the source register indicated by the J-type jump instruction is modified to a fixed value, and the target processing instruction is bound to the J-type jump instruction. This allows the value in the source register indicated by the J-type jump instruction to remain unchanged each time a loop instruction sequence is executed, that is, the target address of the J-type jump instruction remains unchanged, thereby avoiding the situation in which the value of the operand in the source register is modified, resulting in uncontrollable behavior of the J-type jump instruction, and improving the executableness of the J-type jump instruction in the loop instruction sequence.

[0045] Optionally, step 103 may include the following steps:

[0046] Step 301 : Based on the loop logic of the loop instruction sequence, loop execute the loop instruction sequence including the target processing instruction and the J-type jump instruction.

[0047] Step 302: Whenever the target processing instruction bound to the J-type jump instruction is executed, the operand in the source register of the J-type jump instruction is modified to a fixed value.

[0048] In the embodiment of the present invention, when a loop instruction sequence is executed in a loop, when the target processing instruction is executed, the value of the operand in the source register is modified to a fixed value.

[0049] Step 303: Whenever the J-type jump instruction is executed, a target jump address is determined based on the fixed value and the immediate value stored in the J-type jump instruction, and the program jumps to the target jump address.

[0050] In an embodiment of the present invention, after executing the target processing instruction, the J-type jump instruction is executed sequentially, and the target jump address required for the J-type jump instruction to jump is determined based on the fixed value in the source register and the immediate value stored in the J-type jump instruction. For example, assuming that the assembly format of the J-type jump instruction is: "J$1 0x20", that is, the J-type jump instruction selects register No. 1 as the source register, and the value 0x20 is used as the immediate value imm, then its target jump address is obtained based on "the value inside the $1 register plus the immediate value 0x20", that is, the target jump address determined based on the fixed value inside the $1 register and the immediate value. Since the target processing instruction modifies the value of the operand in the source register to a fixed value each time the loop instruction sequence is executed, the target jump address of the J-type jump instruction will not change during the loop instruction sequence execution, thereby avoiding an infinite loop and ensuring the normal execution of the J-type jump instruction.

[0051] Optionally, the target instruction includes a division instruction. The division instruction may be a "D" type division instruction, and the "unpredictable" situation of the calculation result of the division instruction may include: division by zero and overflow. Exemplarily, assuming that the assembly format of a certain division instruction is "D$2$3$4", that is, two registers $2 and $3 are selected as source registers (dividend register and divisor register), and the $4 register is used as the target storage register, that is, the operation completed by the division instruction is: "take the value of the operand stored in the $2 register and divide it by the value of the operand stored in the $3 register, and store the calculated result in the $4 register"; when the value of the operand stored in the $3 register is zero, a "division by zero" operation occurs; when the value of the operand stored in the $2 register is the smallest negative number that can be represented by the computer and the value of the operand stored in the $3 register is -1, an "overflow" operation occurs. It can be understood that, taking a 32-bit computer as an example, the range of numerical values ​​that can be represented is -2147483648 (0x80000000) to 2147483647 (0x7ffffff), (-2147483648) is the smallest number that can be represented by the computer, and its division by -1 (0xffffffff) is 2147483648, which exceeds the maximum number 2147483647 that can be represented by the computer. This situation is called "overflow".

[0052] It can be understood that the “D” type division instructions are instructions that can implement the division function, and may include a “DIV” instruction, a “DIV.S” instruction, a “DIV.PS” instruction, and the like.

[0053] In the case where the target instruction includes a division instruction, the target processing instruction is used to detect whether the operand in the source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow occurs.

[0054] Accordingly, the step of generating the target processing instruction in step 101 may include:

[0055] In the embodiment of the present invention, when it is determined that the loop instruction sequence includes a division instruction, a register is randomly selected as the dividend register and the divisor register indicated by the division instruction, the operand in the divisor register is used as the divisor used by the division instruction, the operand of the dividend register is used as the dividend used by the division instruction, and the generation of the division instruction is suspended, and a target processing instruction is generated. At this time, the target processing instruction is used to detect whether the operand in the source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow is caused. The target processing instruction can be an operand detection instruction, and the target processing instruction can be an instruction sequence, so that after the target processing instruction is executed, the values ​​of the operands in the dividend register and the divisor register must be legal, that is, there is no situation that causes division by zero or overflow. Since the dividend register and the divisor register are randomly selected, if the same register is randomly selected in the process of selecting the dividend register and the divisor register, then the dividend register and the divisor register can be the same. It can be understood that, in the process of randomly selecting registers as the dividend register and the divisor register indicated by the division instruction, the values ​​of the operands in the selected dividend register and the divisor register are legal.

[0056] Accordingly, step 102 may further include the following steps:

[0057] Step 401: Insert the target processing instruction before the division instruction.

[0058] In an embodiment of the present invention, a target processing instruction is inserted before a division instruction so that before each execution of the division instruction, the values ​​of the operands in the dividend register and the divisor register are detected by the target processing instruction to ensure that the values ​​of the operands in the dividend register and the divisor register are legal.

[0059] In an embodiment of the present invention, by generating a target processing instruction and inserting the target processing instruction before a division instruction, it can be ensured that the values ​​of the operands in the dividend register and the divisor register are legal, and then when the division instruction is executed, the divisor and dividend used by the division instruction are both legal, ensuring that the execution result of the division instruction is controllable.

[0060] Accordingly, before step 103, the embodiment of the present invention may further include the following steps:

[0061] Step 501: Based on the target processing instruction, detect whether the value of the operand in the divisor register and the value of the operand in the dividend register meet preset conditions, and the preset conditions include: the value of the operand in the divisor register is not zero, or the value of the operand in the divisor register is the second target value and the value of the operand in the dividend register is not the third target value.

[0062] In an embodiment of the present invention, based on the target processing instruction, the value of the operand in the divisor register and the value of the operand in the dividend register are detected. Specifically, it is detected whether the value of the operand in the divisor register is zero, and it is detected that the value of the operand in the divisor register is the second target value and the value of the operand in the dividend register is not the third target value. Among them, the second target value can be -1, and the third target value can be the smallest negative number that can be represented by the computer, such as -2147483648 (0x80000000). When the value of the operand in the divisor register is not zero, or the value of the operand in the divisor register is the second target value and the value of the operand in the dividend register is not the third target value, that is, the divisor is not 0, or the divisor is -1 and the dividend is not the smallest negative number that can be represented by the computer, it is determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions.

[0063] Step 502: When it is detected that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset condition, generate the division instruction and store the division instruction to the target address.

[0064] In the embodiment of the present invention, when it is detected that the value of the operand in the divisor register is not zero, or the value of the operand in the divisor register is the second target value and the value of the operand in the dividend register is not the third target value, the division instruction continues to be generated and the division instruction is stored in the target address. In the subsequent loop process, the processor fetches the division instruction from the target address to complete the execution operation.

[0065] Accordingly, step 103 may include the following steps:

[0066] Step 503: When the loop condition of the loop instruction sequence is satisfied, repeatedly execute the loop instruction sequence including the target processing instruction and the division instruction.

[0067] In the embodiment of the present invention, when the constraint condition of the start of the loop instruction sequence is met, the loop instruction sequence is repeatedly executed until the constraint condition of the end of the loop instruction sequence is met. In the process of repeatedly executing the loop instruction sequence, before each execution of the division instruction, the target processing instruction detects whether the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions, so that the value of the operand in the divisor register and the value of the operand in the dividend register detected by the target processing instruction are legal, and then the divisor and dividend used when executing the division instruction are also legal.

[0068] In an embodiment of the present invention, a target processing instruction is used to detect whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition, so that the target processing instruction detects that the value of the operand in the divisor register and the value of the operand in the dividend register are legal, thereby avoiding division by zero or overflow, which affects the verification correctness of the random verification program.

[0069] Optionally, step 503 may include the following steps:

[0070] Step 5031: Each time the target processing instruction is executed, based on the target processing instruction, detecting whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition.

[0071] In the embodiment of the present invention, when the loop instruction sequence is executed in a loop, the values ​​in the divisor register and the dividend register may be modified by other instructions. For example, when other instructions just select the divisor register and / or the dividend register indicated by the division instruction to store the calculation result, the value inside the divisor register and / or the dividend register will be overwritten. In order to ensure that the values ​​in the divisor register and the dividend register are "legal" each time the division instruction is executed, therefore, each time the target processing instruction is executed, the value of the operand in the divisor register and the value of the operand in the dividend register are detected based on the target processing instruction to ensure that the divisor and the dividend are legal each time the division instruction is executed in a loop. It can be understood that the detection method in this step is similar to the detection method in step 501, and will not be repeated here.

[0072] Step 5032: When the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition, execute the division instruction at the target address.

[0073] In the embodiment of the present invention, when the value of the operand in the divisor register and the value of the operand in the dividend register meet preset conditions, it is characterized that the values ​​in the divisor register and the dividend register are "legal", and therefore, the division instruction at the target address is executed.

[0074] In an embodiment of the present invention, when a loop sequence is repeatedly executed, the value of the operand in the divisor register and the value of the operand in the dividend register are first detected through the target processing instruction, and when the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions, the division instruction is executed. In this way, it can be ensured that the values ​​of the operands in the divisor register and the dividend register always remain in a legal state during the process of repeatedly executing the loop instruction sequence.

[0075] Furthermore, since processors of different architectures handle division by zero and overflow of "D" type division instructions differently, in order to ensure that the above-mentioned illegal operations do not occur when executing "D" type division instructions, the incompatibility of processors of different architectures in functional verification can be avoided, thereby improving the versatility of the generator.

[0076] Optionally, “based on the target processing instruction, detecting whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition” may be implemented by the following steps:

[0077] Step 601: Detect whether the operand in the divisor register of the division instruction is zero.

[0078] In an embodiment of the present invention, the target processing instruction may include a first sub-instruction, a first write instruction, and a third sub-instruction, wherein the first sub-instruction may be a conditional transfer instruction (such as a "BEQZ" instruction), and the first sub-instruction may be used to detect whether the value of the operand in the divisor register is zero, that is, to detect whether the divisor of the division instruction is 0. When the value of the operand in the divisor register is zero, it indicates that division by zero will occur. In order to modify the value of the operand in the divisor register, a second sub-instruction may be generated, and a jump behavior may occur to jump to the second sub-instruction.

[0079] Step 602: When the operand in the divisor register is zero, a value that is neither zero nor -1 is loaded into the divisor register.

[0080] In the embodiment of the present invention, when the operand in the divisor register is zero, the value of the operand in the divisor register can be modified based on the second sub-instruction. Specifically, a first random value can be loaded into the divisor register, and the first random value can be a value that is non-zero and non-1. The second sub-instruction can be an "ORI" instruction, and the second sub-instruction is used to write a first random value into the divisor register so that the value in the divisor register is non-zero, thereby avoiding the "division by zero" phenomenon.

[0081] After the value of the operand in the divisor register is modified to the first random value, it can be determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset condition.

[0082] In an embodiment of the present invention, after modifying the value of the operand in the divisor register to be a first random value, the occurrence of division by zero is avoided. Therefore, it can be determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions. At this time, a jump instruction can be generated to jump to the target address and execute the division instruction, wherein the jump instruction can be a "B" instruction.

[0083] In an embodiment of the present invention, the value of the operand in the divisor register is detected and modified through the first sub-instruction and the second sub-instruction, and the value of the operand in the divisor register can be selectively modified, that is, the value of the operand is only modified when the operand is 0, thereby ensuring the randomness of the operand value to the greatest extent.

[0084] Step 603: When the operand in the divisor register is not zero, check whether the operand in the divisor register is -1.

[0085] If the value of the operand in the divisor register is not zero, it indicates that the "division by zero" phenomenon will not occur at present. Therefore, the first write instruction in the target processing instruction is executed sequentially, wherein the first write instruction can be a "NOR" instruction, and the first write instruction is used to write the second target value into the first preset register, and the second target value can be -1. Exemplarily, the 0xffffffff (-1) value can be loaded into the $t register through the "NOR" instruction. After executing the first write instruction, the third sub-instruction in the target processing instruction is executed sequentially, and the third sub-instruction can be a conditional transfer instruction (such as a "BEQ instruction"). The third sub-instruction is used to detect whether the value of the operand in the divisor register is the same as the second target value in the first preset register, that is, to detect whether the value of the operand in the divisor register is -1. If the value of the operand in the divisor register is not -1, it can be determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions, and then the division instruction of the target address is executed sequentially.

[0086] In an embodiment of the present invention, by detecting whether the value of the operand in the divisor register is -1, it can be determined whether an "overflow" phenomenon will occur. When the value of the operand in the divisor register is different from the second target value, that is, it is not -1, the possibility of the "overflow" phenomenon is eliminated, thereby ensuring the normal execution of the loop instruction sequence, thereby improving the convergence speed of the functional verification coverage.

[0087] Step 604: When the operand in the divisor register is -1, check whether the operand in the dividend register of the division instruction is the smallest representable negative number.

[0088] In an embodiment of the present invention, if the value of the operand in the divisor register is the same as the second target value, that is, the operand in the divisor register is -1, it indicates that an "overflow" phenomenon may occur, and it is necessary to further determine whether the value of the operand in the dividend register is the smallest representable negative number. Exemplarily, a second write instruction and a fourth sub-instruction can be generated, and a jump to the second write instruction can be made. The second write instruction can be an "LI" instruction for writing a third target value into the second preset register. The third target value can be the smallest negative number representable by the computer. In other words, the smallest negative number representable by the computer, such as 0x80000000, can be loaded into the second preset register through the "LI" instruction. The first preset register can be the same as or different from the second preset register.

[0089] After writing the third target value into the second preset register based on the second write instruction, the fourth sub-instruction is executed sequentially. The fourth sub-instruction can be a conditional transfer instruction (such as a "BEQ instruction"). The fourth sub-instruction is used to detect whether the value of the operand in the dividend register is the same as the third target value, that is, to detect whether the value of the operand in the dividend register is the smallest negative number that can be represented by the computer. If so, the fifth sub-instruction is generated and a jump action is executed to jump to the fifth sub-instruction. If not, it can be determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions. At this time, a jump instruction can be generated to jump to the target address and execute the division instruction, wherein the jump instruction can be a "B" instruction.

[0090] Step 605: When the operand in the dividend register is a minimum negative number, modify the operand in the dividend register to a non-minimum negative number.

[0091] In the embodiment of the present invention, when the operand in the dividend register is the smallest negative number, based on the fifth sub-instruction, the value of the operand in the dividend register is modified to a second random value, wherein the fifth sub-instruction may be an "ORI" instruction, and the second random value may be a non-minimum negative number, that is, a random value greater than the third target value. It is understandable that the value range of the second random value may be greater than the smallest negative number that can be represented by the computer, and less than or equal to the largest positive number that can be represented by the computer.

[0092] After the value of the operand in the dividend register is modified to a non-minimum negative number, it is determined whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition.

[0093] In an embodiment of the present invention, when the value of the operand in the dividend register is modified to a non-minimum negative number, the value in the divisor register is not -1 and the value of the operand in the dividend register is not the smallest negative number representable by the computer, then it is determined that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset conditions, and a jump instruction can be generated to jump to the target address and execute the division instruction, wherein the jump instruction can be a "B" instruction.

[0094] In an embodiment of the present invention, the fourth sub-instruction is used to detect whether the value of the operand in the dividend register is the same as the third target value, and the value of the operand in the dividend register is modified based on the fifth sub-instruction. This ensures that when the value of the operand in the divisor register is the second target value, that is, when the divisor is -1, the value of the operand in the dividend register, that is, the dividend is the smallest negative number that can be represented by a computer, thereby avoiding the "overflow" phenomenon and ensuring the normal execution of the loop instruction sequence, thereby improving the convergence speed of the functional verification coverage.

[0095] For example, Figure 4 A flow chart of detecting and modifying the values ​​of operands in a divisor register and a dividend register based on a target processing instruction is shown, such as Figure 4 As shown, assuming that the division instruction is "DIV$q$m$n", the $n register is the divisor register and the $m register is the dividend register. First, based on the "BEQZ$n imm" instruction, check whether the value of the operand in the $n register is 0. If so, jump to "ORI$n$n imm", write the first random value (a non-zero and non-1 value) to the $n register, execute the "B" instruction, jump to the division instruction and execute the division instruction; if not, execute "NOR$t$0$0" in sequence, load 0xffffffff (-1) value into the $t register, execute "BEQ1$n$t imm", if the values ​​in the $n and $t registers are not equal, execute the division instruction in sequence; if the values ​​in the $n and $t registers are equal, jump to "LI$t 0x80000000", load 0x80000000 into the $t register, execute "BEQ2$m$t imm", if the values ​​in the $m and $t registers are equal, jump to "ORI$m$m imm", write the second random value (not the smallest negative number) to the $n register, execute the "B" instruction, jump to the division instruction and execute the division instruction; if the values ​​in the $m and $t registers are not equal, execute the "B" instruction, jump to the division instruction and execute the division instruction.

[0096] In one possible implementation, before generating a division instruction, since the values ​​of the operands in the divisor register and the dividend register are both legal, the executed instruction sequence can be divided into the following two cases: 1. When the value of the operand in the divisor register is -1 and the value of the operand in the dividend register is not the smallest representable negative number, the executed instruction sequence is: "BEQZ" instruction, detects whether the divisor (the value of the operand in the $n register) is zero. This condition is not met, so no jump occurs; "NOR" instruction, writes -1 value (0xffffffff) to the $t register; "BEQ1" instruction, detects whether the value of the operand in the $n register is -1, and a jump occurs; "LI" instruction, writes the smallest representable negative number (0x80000000) to the $t register; "BEQ2" instruction, detects whether the dividend (the value of the operand in the $m register) is the smallest representable negative number. The condition is not met and no jump occurs; "B" instruction, jumps back to the division instruction position and generates a division instruction. 2. When the value of the operand in the divisor register is not -1, the instruction sequence executed is: "BEQZ" instruction, detects whether the divisor (the value of the operand in the $n register) is zero. This condition is not met, so no jump occurs; "NOR" instruction, writes -1 value (0xffffffff) to the $t register; "BEQ1" instruction, detects whether the divisor (the value of the operand in the $n register) is -1. The condition is not met and no jump occurs; a division instruction is generated.

[0097] In another possible implementation, when a loop instruction sequence is executed in a loop and the values ​​of the operands in the divisor register and the dividend register are modified by other instructions during the loop execution, if the value of the operand in the divisor register ($n register) is modified to 0, then when the "BEQZ" instruction is executed, a jump occurs, an "ORI" instruction is generated at the target address location, and a non-zero and non-1 value is written to the $n register based on the "ORI" instruction, and then the "B" instruction is used to jump back to the "DIV" position to continue executing the division instruction; if the value of the operand in the divisor register ($n register) is modified to -1, and the value of the operand in the dividend register ($m register) is modified to the smallest non-representable negative value. When the "BEQ1" instruction is executed, a jump occurs, and the "LI" instruction is generated at the target address. Based on the "LI" instruction, the smallest representable negative number is written to the $t register, and then "BEQ2" is generated. It is determined that the dividend (the value of the operand in the $m register) is not equal to the smallest representable negative number, and the "B" instruction is generated to jump back to the "DIV" instruction position to execute the division instruction; if the value of the operand in the divisor register ($n register) is modified to -1, and the value of the operand in the dividend register ($m register) is modified to the smallest representable negative number. When "BEQ2" is executed, the jump condition is met, and the jump is generated and the "ORI" instruction is generated to modify the dividend (the value of the operand in the $m register) to a non-representable smallest negative number, and then the "B" instruction is generated to jump back to the "DIV" instruction position to continue executing the division instruction.

[0098] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0099] Reference Figure 5 , shows a structural block diagram of an embodiment of a processor random verification program generation device of the present invention, wherein the random verification program includes a cyclic instruction sequence, and specifically may include the following modules:

[0100] A first generating module 701, for generating a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped;

[0101] The first insertion module 702 is used to insert the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during the loop process.

[0102] Optionally, the device may further include:

[0103] The first execution module 703 is used for cyclically executing the loop instruction sequence including the target processing instruction based on the loop logic of the loop instruction sequence.

[0104] In the embodiment of the present application, a target processing instruction is generated for a target instruction in a loop instruction sequence that may produce an unpredictable execution result when being executed in a loop; the target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operands in the source register of the target instruction before the target instruction is executed during each loop execution, so that the target instruction produces a predictable execution result during the loop. In this way, the operands in the source register of the target instruction can be processed by the target processing instruction, so that the execution result of the target instruction in the loop instruction sequence is predictable, and there is no need to avoid the appearance of instructions with unpredictable execution results in the instruction sequence, so that the target instruction can appear in the loop instruction sequence as an internal instruction, enriching the instruction types in the loop instruction sequence, and improving the quality of the random verification program to a certain extent, which is conducive to improving the verification efficiency of the microprocessor and improving the convergence speed of the functional verification coverage.

[0105] Optionally, the target instruction includes a J-type jump instruction; the target processing instruction is used to modify the operand in the source register of the J-type jump instruction to a fixed value;

[0106] The first insertion module comprises:

[0107] The first insertion submodule is used to insert the target processing instruction before the J-type jump instruction.

[0108] Optionally, the first execution module 703 includes:

[0109] A first execution submodule, configured to cyclically execute a loop instruction sequence including the target processing instruction and the J-type jump instruction based on the loop logic of the loop instruction sequence;

[0110] A first modification module is used for modifying the operand in the source register indicated by the J-type jump instruction to a fixed value each time the target processing instruction bound to the J-type jump instruction is executed;

[0111] The first jump module is used to determine a target jump address based on the fixed value and an immediate value stored in the J-type jump instruction each time the J-type jump instruction is executed, and jump to the target jump address.

[0112] Optionally, the target instruction comprises a division instruction; the target processing instruction is used to detect whether an operand in a source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow is caused;

[0113] The first insertion module comprises:

[0114] The second insertion submodule is used to insert the target processing instruction before the division instruction.

[0115] Optionally, the device comprises:

[0116] A first detection module is used to detect whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition based on the target processing instruction, wherein the preset condition includes: the value of the operand in the divisor register is not zero, or the value of the operand in the divisor register is a second target value and the value of the operand in the dividend register is not a third target value;

[0117] A second generating module is used to generate the division instruction and store the division instruction to a target address when it is detected that the value of the operand in the divisor register and the value of the operand in the dividend register meet the preset condition;

[0118] The first execution module includes:

[0119] The second execution submodule is used for repeatedly executing the loop instruction sequence including the target processing instruction and the division instruction when the loop condition of the loop instruction sequence is satisfied.

[0120] Optionally, the second execution submodule includes:

[0121] A second detection module is used for detecting whether the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition based on the target processing instruction each time the target processing instruction is executed;

[0122] The third execution submodule is used to execute the division instruction at the target address when the value of the operand in the divisor register and the value of the operand in the dividend register meet a preset condition.

[0123] Optionally, the device further comprises:

[0124] A first detection submodule, used for detecting whether the operand in the divisor register of the division instruction is zero;

[0125] A first loading module, for loading a non-zero and non-1 value into the divisor register when the operand in the divisor register is zero;

[0126] A second detection submodule, used for detecting whether the operand in the divisor register is -1 when the operand in the divisor register is not zero;

[0127] A third detection submodule, used for detecting whether the operand in the dividend register of the division instruction is the smallest representable negative number when the operand in the divisor register is -1;

[0128] The first modifying submodule is used to modify the operand in the dividend register to a non-minimum negative number when the operand in the dividend register is a minimum negative number.

[0129] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0130] Reference Figure 6 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the processor random verification program generation method of the aforementioned embodiment.

[0131] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by a processor 820 of an electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0132] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of a terminal, enables the terminal to perform a method for generating a processor random verification program, the method comprising:

[0133] generating a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped;

[0134] The target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during this loop process.

[0135] Optionally, the target instruction includes a J-type jump instruction; the target processing instruction is used to modify the operand in the source register of the J-type jump instruction to a fixed value;

[0136] The inserting the target processing instruction into a specified position in the loop instruction sequence comprises:

[0137] The target processing instruction is inserted before the J-type jump instruction.

[0138] Optionally, the address of the instruction counter used during the loop execution is loaded into the source register of the J-type jump instruction as the fixed value.

[0139] Optionally, the target instruction comprises a division instruction; the target processing instruction is used to detect whether an operand in a source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow occurs.

[0140] Optionally, detecting whether the operand in the source register of the division instruction causes division by zero or overflow and modifying the operand of the division instruction comprises:

[0141] Detecting whether the operand in the divisor register of the division instruction is zero;

[0142] If the operand in the divisor register is zero, a non-zero and non-1 value is loaded into the divisor register;

[0143] If the operand in the divisor register is not zero, check whether the operand in the divisor register is -1;

[0144] In the case where the operand in the divisor register is -1, it is detected whether the operand in the dividend register of the division instruction is the smallest representable negative number;

[0145] In the case where the operand in the dividend register is the least negative number, the operand in the dividend register is modified to be the non-least negative number.

[0146] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0147] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0148] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0149] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0151] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0152] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0153] The above is a detailed introduction to a processor random verification program generation method and device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for generating a random verification program for a processor, wherein the random verification program comprises a cyclic instruction sequence, wherein the method include: generating a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped; The target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during this loop process.

2. The method according to claim 1, characterized in that The target instruction includes a J-type jump instruction; the target processing instruction is used to modify the operand in the source register of the J-type jump instruction to a fixed value; The inserting the target processing instruction into a specified position in the loop instruction sequence comprises: The target processing instruction is inserted before the J-type jump instruction.

3. The method according to claim 2, characterized in that The address of the instruction counter used in the loop execution process is loaded into the source register of the J-type jump instruction as the fixed value.

4. The method according to claim 1, characterized in that The target instruction comprises a division instruction; the target processing instruction is used to detect whether an operand in a source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow occurs.

5. The method according to claim 4, characterized in that The detecting whether the operand in the source register of the division instruction causes division by zero or overflow and modifying the operand of the division instruction comprises: Detecting whether the operand in the divisor register of the division instruction is zero; If the operand in the divisor register is zero, a non-zero and non-1 value is loaded into the divisor register; If the operand in the divisor register is not zero, check whether the operand in the divisor register is -1; In the case where the operand in the divisor register is -1, it is detected whether the operand in the dividend register of the division instruction is the smallest representable negative number; In the case where the operand in the dividend register is the least negative number, the operand in the dividend register is modified to be the non-least negative number.

6. A processor random verification program generation device, characterized in that: The random verification program includes a sequence of instructions that are executed cyclically, including: A first generating module, configured to generate a target processing instruction for a target instruction in the loop instruction sequence that may produce an unpredictable execution result when being looped; The first insertion module is used to insert the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during the loop process 。 7. The device according to claim 6, characterized in that The target instruction includes a J-type jump instruction; the target processing instruction is used to modify the operand in the source register of the J-type jump instruction to a fixed value; The first insertion module comprises: The first insertion submodule is used to insert the target processing instruction before the J-type jump instruction.

8. The device according to claim 6, characterized in that The target instruction includes a division instruction; the target processing instruction is used to detect whether the operand in the source register of the division instruction causes division by zero or overflow, and to modify the operand of the division instruction when division by zero or overflow is caused; the apparatus further includes: A first detection submodule, used for detecting whether the operand in the divisor register of the division instruction is zero; A first loading module, for loading a non-zero and non-1 value into the divisor register when the operand in the divisor register is zero; A second detection submodule, used for detecting whether the operand in the divisor register is -1 when the operand in the divisor register is not zero; A third detection submodule, used for detecting whether the operand in the dividend register of the division instruction is the smallest representable negative number when the operand in the divisor register is -1; The first modifying submodule is used to modify the operand in the dividend register to a non-minimum negative number when the operand in the dividend register is a minimum negative number.

9. An electronic device, characterized in that: The system comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the following operations: generating a target processing instruction for a target instruction that may produce an unpredictable execution result when being cyclically executed; The target processing instruction is inserted into a specified position in the loop instruction sequence; the target processing instruction is used to process the operand in the source register of the target instruction before the target instruction is executed during each loop execution process, so that the target instruction produces a predictable execution result during this loop process.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the processor random verification program generation method as described in one or more of method claims 1-5.

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