Computing chip and execution method of computing task

Abstract

The invention discloses a computing chip and an execution method of a computing task. The computing chip comprises transmission modules, computing core particles and storage core particles, a data cache sub-module is arranged in each transmission module, a plurality of transmission modules are arranged on a substrate of the computing chip, and for each transmission module, the transmission module is connected with at least one computing core particle and / or at least one storage core particle; the transmission module is used for reading the task data from the storage core grain and storing the task data in the data cache sub-module according to the access task management data, and reading the task data from the local data cache sub-module and sending the task data to the target calculation core grain; the storage core particle is used for storing task data and sending the task data to the target transmission module; and the calculation core particle is used for executing the calculation task according to the received task data. According to the scheme, the data access efficiency in the computing chip is greatly improved, and the execution efficiency of the computing task is further improved.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a computing chip and a method for executing a computing task. Background Art

[0002] In the field of machine learning and deep learning, the rapid increase in model size and training data volume has placed increasingly higher demands on computing power. Therefore, chip integration technology has emerged and has gradually developed into one of the important means to improve system performance.

[0003] Chip integration technology integrates multiple small, independent chips through advanced packaging and interconnection technologies to form a system-level chip with higher performance, lower power consumption and greater flexibility, thereby achieving higher chip performance at lower production costs.

[0004] However, in the existing chip integration technology, when the number of integrated chips reaches a certain scale, some computing chips cannot be directly connected to the storage chips. In this case, the computing chips need to obtain data from adjacent computing chips or obtain data from the storage chips through the substrate circuit. The circuit structure of the substrate will cause a long communication distance between the computing chip that needs to obtain data and the target storage chip, thereby introducing additional delays and causing a loss in computing performance.

[0005] Therefore, how to reduce the internal delay of computing chips and improve the computing performance of chips is an urgent problem to be solved. Summary of the invention

[0006] This specification provides a computing chip and a method for executing computing tasks to partially solve the above-mentioned problems existing in the prior art.

[0007] This manual adopts the following technical solutions: This specification provides a computing chip, the computing chip 100 comprising: a transmission module 200, a computing core particle 101 and a storage core particle 102, the transmission module 200 is provided with a data cache submodule 207, a substrate 103 of the computing chip 100 is provided with a plurality of transmission modules 200, and for each transmission module 200, the transmission module 200 is connected to at least one computing core particle 101 and / or at least one storage core particle 102; The transmission module 200 is used to obtain memory access task management data, read task data required for the computing core 101 to perform computing tasks from the storage core 102 according to the memory access task management data, and store the task data in the local data cache submodule 207, and read the task data from the local data cache submodule 207 according to the data read request sent by the target computing core and send it to the target computing core; The storage core 102 is used to store task data and send the task data to the target transmission module according to a data read request sent by the target transmission module; The computing core 101 is used to send a data read request to the transmission module 200 , and after receiving the task data returned by the transmission module 200 , execute the computing task according to the received task data.

[0008] Optionally, for each transmission module 200, the transmission module 200 includes: a parsing and distribution submodule 203; The parsing and distributing submodule 203 is used to receive a data packet and parse the data packet to determine the data type corresponding to the data; According to the data type, the data is sent to other submodules in the transmission module 200.

[0009] Optionally, the other submodules include: a channel selection submodule 204, a task management submodule 205 and a cache management submodule 206; The parsing and distributing submodule 203 is used to send the forwarding data to the channel selecting submodule 204 if the data type is forwarding data; If the data type is memory access task management data, the memory access task management data is sent to the task management submodule 205 for storage; If the data type is task data, the task data is sent to the data cache submodule 207 for storage; If the data type is instruction data corresponding to the data read request, the instruction data is sent to the cache management submodule 206 .

[0010] Optionally, the channel selection submodule 204 is used to determine a target output channel corresponding to the forwarded data, and send the forwarded data through the target output channel; The task management submodule 205 is used to execute the data memory access task corresponding to the memory access task management data when it is detected that the remaining storage space in the data cache submodule 207 is greater than a preset threshold; The cache management submodule 206 is used to map the addresses corresponding to the data stored in the cache submodule, and read the task data from the data cache submodule 207 according to the instruction data and the mapped address.

[0011] Optionally, the task management submodule 205 includes: a task parsing unit 205_1, a task management list unit 205_3 and a task management control unit 205_2; The task parsing unit 205_1 is used to parse the data packet of the access task management data; The task management list unit 205_3 is used to store the data list of the parsed access task management data; The task management control unit 205_2 is used to read the task data required for the computing core 101 to perform the computing task from the storage core 102 according to the data list and store it in the data cache submodule 207 when it is monitored that the remaining storage space in the data cache submodule 207 is greater than a preset threshold.

[0012] Optionally, for each transmission module 200, the transmission module 200 further includes: an input port 201, an input buffer submodule 202, an output queue submodule 208 and an output port 209; The input port 201 is used to receive data sent by at least one of the computing core 101, the storage core 102 and the other transmission modules 200; The input buffer submodule 202 is used to temporarily store received data; The output port 209 is used to send the input forwarding data; The output queue submodule 208 is provided with a plurality of output channels for transmitting the forwarded data to the output port 209 corresponding to the target output channel through the target output channel.

[0013] This specification provides a method for executing a computing task, the method is applied to a computing chip 100, the computing chip 100 includes: a plurality of transmission modules 200, a computing core particle 101 and a storage core particle 102, the method includes: Get access task management data; According to the memory access task management data, task data required for each computing core particle 101 to perform computing tasks is read from at least one storage core particle 102 through each transmission module 200, and stored in the local data cache submodule 207 of each transmission module 200; After receiving the execution request of the computing task, according to the execution request, a data reading request is sent to at least one target transmission module connected thereto through each computing core particle 101, so that the target transmission module reads the task data from the local data cache submodule 207 according to the data reading request and sends it to each computing core particle 101; The computing core particles 101 are used to execute computing tasks according to the received task data.

[0014] Optionally, before reading the task data required for each computing core grain 101 to perform the computing task from at least one storage core grain 102 through each transmission module 200 according to the memory access task management data, the method further includes: In response to the startup instruction of the runtime, the memory access task management data is sent to each transmission module 200 through a preset intelligent agent according to the topological structure of each core grain and the transmission module 200 included in the computing chip 100.

[0015] Optionally, before acquiring the memory access task management data, the method further includes: Receiving a data packet of data, and parsing the data packet to determine the data type of the data; According to the memory access task management data, task data required for each computing core particle 101 to perform computing tasks is read from at least one storage core particle 102 through each transmission module 200, and stored in the local data cache submodule 207 of each transmission module 200, specifically including: If the data type is memory access task management data, the memory access task management data is stored, and when it is detected that the remaining storage space in the data cache submodule 207 is greater than a preset threshold, a data read request is sent to each storage core grain 102 through each transmission module 200, so that each storage core grain 102 sends the task data to each transmission module 200 according to the data read request; If the data type is task data, the task data is stored in the local data cache submodule 207 of each transmission module 200; If the data type is forwarding data, the channel selection submodule 204 determines the target output channel corresponding to the forwarding data, and sends the forwarding data through the target output channel.

[0016] Optionally, each computing core particle 101 sends a data read request to at least one target transmission module connected thereto, so that the target transmission module reads the task data from the local data cache submodule 207 according to the data read request and sends it to each computing core particle 101, comprising: If the data type is instruction data corresponding to a data read request, task data is read from the data cache submodule 207 and sent to each computing core particle 101 according to the instruction data and the address corresponding to the pre-mapped data stored in the cache submodule.

[0017] This specification provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the execution method of the above-mentioned computing task is implemented.

[0018] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned method for executing the computing task when executing the program.

[0019] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects: The computing chip 100 provided in this specification includes: a transmission module 200, a computing core 101 and a storage core 102, wherein the transmission module 200 is provided with a data cache submodule 207, and a plurality of transmission modules 200 are provided on the substrate 103 of the computing chip 100, and for each transmission module 200, the transmission module 200 is connected to at least one computing core 101 and at least one storage core 102; the transmission module 200 is used to read task data from the storage core 102 and store it in the data cache submodule 207 according to the memory access task management data, and to read task data from the local data cache submodule 207 and send it to the target computing core; the storage core 102 is used to store task data and send task data to the target transmission module; the computing core 101 is used to perform computing tasks according to the received task data.

[0020] It can be seen from the above method that the computing chip of this scheme not only integrates a number of computing core particles and storage core particles, but also is provided with a transmission module connected to the above two. Before the computing core particle performs a computing task, the transmission module will pre-read the task data required for the computing core particle to perform the computing task from the storage core particle according to the memory access task management data, and store it in the local data cache sub-module. In this way, when the computing chip actually performs a computing task, it can directly read the task data from the transmission module connected to it, without the need to obtain the task data through the substrate line or with the help of other computing chips, thereby improving the data memory access efficiency inside the computing chip, and further improving the chip performance and the execution efficiency of computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings: Figure 1 A schematic diagram of an existing chip integration structure provided in this specification; Figure 2 A schematic diagram of the structure of a computing chip provided in this specification; Figure 3 A schematic diagram of the structure of a transmission module provided in this specification; Figure 4 A flowchart of a method for executing a computing task provided in this specification. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0023] As computing power requirements increase, the scale of chip integration is further increasing, and more and more computing chips and storage chips are packaged into one chip. For ease of understanding, this specification provides a schematic diagram of an existing chip integration structure, such as Figure 1 shown.

[0024] in, Figure 1 (a) is a top view of the chip structure. Figure 1 (b) is a side view of the chip structure, S represents a storage core particle, C represents a computing core particle, and the 9 computing core particles and 6 storage core particles shown in the figure are packaged into a computing chip, and each core particle is connected to the substrate of the computing chip. Figure 1 As can be seen in the figure, the computing chip C5 is not directly connected to any memory chip, so it needs to obtain data from the memory chip through other computing chips (such as C4 or C6) or the communication lines on the substrate. As the number of integrated chips reaches a certain scale, more computing chips will not be able to be directly connected to the memory chips, which seriously affects the chip performance.

[0025] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0026] Figure 2 1 is a schematic diagram of the structure of a computing chip 100 provided in this specification, wherein: Figure 2 (a) is a top view of the structure of the computing chip 100. Figure 2 (b) is a side view of the structure of the computing chip 100, which includes: a transmission module 200, a computing core 101 and a storage core 102, wherein a plurality of transmission modules 200 are arranged on the substrate 103 of the computing chip 100, and for each transmission module 200, the transmission module 200 is connected to at least one computing core 101 and at least one storage core 102.

[0027] In practical applications, the basic topological structure of each transmission module 200 can be Figure 2 The mesh structure shown in (a) in the figure may, of course, also be other topological structures such as 3D-torus, and this specification does not make any specific limitation on this.

[0028] Among them, the transmission module 200 is used to obtain memory access task management data, read the task data required for the computing core 101 to perform the computing task from the storage core 102 according to the memory access task management data, and store the task data in the local data cache sub-module 207, and, according to the data read request sent by the target computing core, read the task data from the local data cache sub-module 207 and send it to the target computing core.

[0029] The storage core 102 is used to store task data and send the task data to the target transmission module according to a data read request sent by the target transmission module. In addition, in actual applications, the storage core 102 may also store intermediate result data generated during the calculation process.

[0030] It should be pointed out that, for any transmission module 200, when the transmission module 200 sends a data read request to any storage core 102, the transmission module 200 can serve as a target transmission module; similarly, for any computing core 101, when the computing core 101 sends a data read request to any transmission module 200, the computing core 101 can serve as a target computing core.

[0031] The computing core 101 is used to send a data read request to the transmission module 200 , and after receiving the task data returned by the transmission module 200 , execute the computing task according to the received task data.

[0032] In the process of training the model, the deep learning framework compiler and runtime will generate memory access task management data according to the detailed specifications of the deep learning model and the storage resources owned by the computing chip 100, and dynamically update the memory access task management data according to the task running status, wherein the data form of the memory access task management data can be a data list, which is used to characterize the data information of the data required when the computing core particle 101 performs the computing task, and the data list records the serial number, operation type, address, data size and other information corresponding to the task data. Each computing core particle 101 can obtain the memory access task management data in advance and send it to the corresponding transmission module 200 on the substrate 103 in the form of a data packet (adding the data packet type and destination address). The data format of the memory access task management data is shown in Table 1: Table 1

[0033] When the current task is completed, the mark bit is marked as executed. When a valid return result is received, the mark bit is marked as completed. When an error or timeout occurs in the return result, the mark bit is marked as completed and an exception is reported.

[0034] In actual applications, the task data required for each computing core 101 to perform computing tasks may include model parameter data, such as weights, biases, hyperparameters, and variables, and of course, may also include other data involved in the model training process, which is not specifically limited in this specification.

[0035] The computing chip can respond to the startup instruction of the runtime, and through a preset intelligent agent, send the memory access task management data to each transmission module 200 according to the topological structure of each core particle and the transmission module 200 included in the computing chip 100.

[0036] At the runtime level of the external CPU, an intelligent agent can be set up. When the runtime manages the memory and schedules the computing tasks, the intelligent agent can use an adaptive algorithm to update the memory access task management data to the corresponding transmission module based on the topological structure of the core grain and the transmission module on the substrate.

[0037] Furthermore, this specification also provides a schematic diagram of the structure of a transmission module 200, such as Figure 3 shown.

[0038] Figure 3 It is a structural schematic diagram of a transmission module 200 provided in this specification.

[0039] Among them, the transmission module 200 is provided with multiple sub-modules, including: input port 201, input cache sub-module 202, parsing and distribution sub-module 203, task management sub-module 205, channel selection sub-module 204, cache management sub-module 206, data cache sub-module 207, output queue sub-module 208 and output port 209.

[0040] In practical applications, the computing core 101, the storage core 102 and other transmission modules 200 usually send data to the transmission module 200 in the form of data packets, and the data types of these data may include: memory access task management data, forwarding data, task data to be cached, and instruction data corresponding to data read requests. For each transmission module 200, the transmission module 200 can receive data sent by different cores or other transmission modules 200 through different input ports 201, and temporarily store the data in the input cache submodule 202. The format of the above data packets is shown in Table 2: Table 2

[0041] Op_cmd is an operation command used to distinguish the operation type of the current data packet (including core grain write command, core grain read command, configuration task management list command, write data cache command, read data cache command, configuration task list completion command, read data cache return command, write data cache return command, configuration task list return command, read command between transmission modules 200, write command between transmission modules 200, etc.); ID1 is the core grain ID or transmission module ID on the command receiving side, ID2 is the core grain ID or transmission module ID on the command sending side; Size or State is the data size or state; Data is the task data or memory access task management data; Parity bit is the check bit.

[0042] The format of the core write command is: core write command + core id + data size + data + checksum; The command format for configuring the task management list is: configure the task management list command + send and receive ID + task management list + verification; The format of the write data cache command is: write data cache command + transceiver ID + data address + data size + data + checksum; The format of the read data cache command is: read data cache command + transceiver ID + data address + data size + checksum; The format of the read data cache return command is: read data cache return command + transceiver ID + status flag + data + check; The format of the write data cache return command is: read data cache return command + send and receive ID + status flag + check; The command format of configuring the task management list is: configuring the task management list return command + sending and receiving ID + status flag + verification; The format of the read command between the transmission modules 200 is: read data command between data modules + transceiver ID + data address + data size + checksum; The format of the write command between the transmission modules 200 is: write data command between data modules + transceiver ID + data address + data size + data + checksum; The format of the core grain read command is: core grain read command + transceiver ID + data size + checksum.

[0043] When the parsing and distribution submodule 203 is in an idle state, data can be read from the data cache submodule 207 and the data packet of the data can be parsed to determine the data type corresponding to the data, and then the data can be sent to other submodules in the transmission module 200 according to the data type.

[0044] Specifically, if the data type is forwarding data, the parsing and distribution submodule 203 can send the forwarding data to the channel selection module, determine the target output channel corresponding to the forwarding data through the channel selection submodule 204, and send the forwarding data to other transmission modules 200 or core particles through the target output channel pair.

[0045] The output queue submodule 208 is provided with several output channels. When the channel selection submodule 204 determines the target output channel corresponding to the forwarded data, the output queue submodule 208 can transmit the forwarded data to the output port 209 corresponding to the target output channel through the target output channel.

[0046] If the type of the data is memory access task management data, the parsing and distributing submodule 203 may send the memory access task management data to the task management submodule 205 for storage.

[0047] When the task management submodule 205 detects that the remaining storage space in the data cache submodule 207 is greater than the preset threshold, it executes the data access task corresponding to the access task management data, that is, according to the data list of the access task management data, it sequentially reads the task data required for the computing core 101 to execute the computing task from the storage core 102 and stores it in the data cache submodule 207. The above preset threshold can be set according to the actual situation, and this specification does not make a specific limitation on this.

[0048] Furthermore, the task management submodule 205 may include: a task parsing unit 205_1 , a task management list unit 205_3 , and a task management control unit 205_2 .

[0049] The task parsing unit 205_1 is used to parse the relevant fields of the data packet of the memory access task management data, and store the parsed data list of the memory access task management data into the task management list unit 205_3.

[0050] When the task management control unit 205_2 detects that the remaining storage space in the data cache submodule 207 is greater than a preset threshold, it can read the task data required for the computing core 101 to perform the computing task from the storage core 102 according to the data list of the task management data and store it in the data cache submodule 207.

[0051] If the data type is task data to be cached, the parsing and distributing submodule 203 may send the task data to the data caching submodule 207 for storage. After the data caching submodule 207 stores the task data, the cache management submodule 206 may map the address corresponding to the data stored in the cache submodule.

[0052] If the data type is instruction data corresponding to the data read request, the parsing and distributing submodule 203 may send the instruction data to the cache management submodule 206 , and the cache management submodule 206 may read the task data from the data cache submodule 207 according to the instruction data and the mapped address.

[0053] The above instruction data may carry the address and data length corresponding to the data to be read by the instruction type data read request.

[0054] Based on the computing chip 100 of the above structure, during the process of performing a model training task, the framework compiler and runtime generate memory access task management data, and send it to the transmission module 200 through the interface between the computing core particle 101 and the transmission module 200.

[0055] After receiving the data packet, the transmission module 200 parses it through the parsing and distribution submodule 203 and writes the memory access task management data into the task management submodule 205 .

[0056] When there are tasks in the task management list, the task management submodule 205 can determine whether to execute the memory access task in the task management list according to the free degree of the storage space of the current data cache submodule 207, wherein, if the storage space + write size in the current data cache module is less than the preset threshold, the task management submodule 205 can sequentially execute the data reading task according to the information provided by the data list of the memory access task management data, and generate a data reading request, and the data packet corresponding to the data reading request can be forwarded to the corresponding output port 209 for output through the channel selection module; and if the storage space + write size in the current data cache submodule 207 is greater than the threshold, then wait for the storage space to be released and meet the conditions before continuing to execute the data reading task. In addition, if there is an exception such as a request timeout or error, the corresponding cache usage is subtracted in the cache module.

[0057] The adjacent transmission module 200 can forward the data read request to the target storage core 102 and convert it into a data read command at the interface. The storage core 102 can then execute the data read command to determine the requested task data and return the task data packet to the transmission module 200.

[0058] After the transmission module 200 receives the data packet of the task data, it can parse it through the parsing and distribution submodule 203, and write the parsed task data into the data cache submodule 207 through the data cache management submodule 206. The data cache management submodule also completes the management of the address mapping relationship.

[0059] When the computing chip 100 performs a computing task, the computing core 101 can obtain data from the transmission module 200 according to the model training arrangement, and send a data read request to the transmission module 200. After the transmission module 200 receives the data packet of the data read request, it can parse it through the parsing and distribution sub-module 203 to determine the instruction data corresponding to the data read request, and then send the instruction data to the data cache management sub-module 206.

[0060] The data cache management submodule 206 can read the corresponding task data from the data cache submodule 207 according to the command data, and package it, and then forward it to the corresponding output port 209 through the channel selection module to output it to the computing chip 101; if the required data is not in the data cache, the data cache management submodule 206 can send a data acquisition command to the storage chip 102 according to the command content, and at the same time notify the computing chip 101 that the current data is not hit.

[0061] Furthermore, this specification also provides a computing task execution method applied to the above computing chip 100, such as Figure 4 shown.

[0062] Figure 4 A flowchart of a method for executing a computing task provided in this specification includes the following steps: S401: Acquire memory access task management data; S402: According to the memory access task management data, task data required for each computing core particle 101 to perform a computing task is read from at least one storage core particle 102 through each transmission module 200, and stored in a local data cache submodule 207 of each transmission module 200; S403: after receiving the execution request of the computing task, according to the execution request, sending a data read request to at least one target transmission module connected thereto through each computing core particle 101, so that the target transmission module reads the task data from the local data cache submodule 207 according to the data read request and sends it to each computing core particle 101; S403: Execute the computing task according to the received task data through each computing core particle 101.

[0063] The computing chip can respond to the startup instruction of the runtime, and through a preset intelligent agent, send the memory access task management data to each transmission module 200 according to the topological structure of each core particle and the transmission module 200 included in the computing chip 100.

[0064] If the data type is memory access task management data, the computing chip 100 may store the memory access task management data, and when it is detected that the remaining storage space in the data cache submodule 207 is greater than a preset threshold, the computing chip 100 may send a data read request to each storage core particle 102 through each transmission module 200, so that each storage core particle 102 sends the task data to each transmission module 200 according to the data read request; If the data type is task data, the computing chip 100 stores the task data in the local data cache submodule 207 of each transmission module 200 .

[0065] If the data type is instruction data corresponding to the data read request, the computing chip 100 can read the task data from the data cache submodule 207 and send it to each computing core 101 according to the instruction data and the address corresponding to the data stored in the pre-mapped cache submodule.

[0066] After the computing core particles 101 read the task data, the computing chip 100 can execute the computing tasks involved in the model training process according to the task data through each computing core particle 101 .

[0067] It should be pointed out that the above computing tasks and task data may also be computing tasks and task data in other business scenarios such as model reasoning and testing, and this specification does not make specific limitations on this.

[0068] It can be seen from the above method that this solution takes advantage of the long memory access path in the integration of the computing storage core 102, which leads to a large data delay problem. By setting a data forwarding module and a data cache mechanism on the substrate 103, the data waiting time during the model training process can be effectively shortened; A data communication method between the computing / storage core 102 and the substrate 103 is proposed, which is helpful to build a complete core system data transmission system; The data pre-fetching mechanism adopted in this paper can support the simultaneous training of a single or multiple models, which can improve the overall performance of the core particle system, especially the demand for computing power for the current large model training, reduce data waiting time, and improve model training efficiency.

[0069] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 1 A method for executing a computing task is provided.

[0070] For the improvement of a technology, it can be clearly distinguished whether it is a hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or a software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0071] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, and the memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

[0072] The systems, devices, modules or submodules described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0073] For the convenience of description, the above device is described by dividing it into various submodules according to its functions. Of course, when implementing this specification, the functions of each submodule can be implemented in the same or multiple software and / or hardware.

[0074] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0076] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0077] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0078] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0079] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0080] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0081] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0082] It should be understood by those skilled in the art that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0084] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A computing chip, characterized in that: The computing chip (100) comprises: a computing core particle (101), a storage core particle (102) and a transmission module (200); the transmission module (200) is provided with a data cache submodule (207); a plurality of transmission modules (200) are provided on a substrate (103) of the computing chip (100); and for each transmission module (200), the transmission module (200) is connected to at least one computing core particle (101) and / or at least one storage core particle (102); The transmission module (200) is used to obtain memory access task management data, read task data required for the computing core (101) to perform a computing task from the storage core (102) according to the memory access task management data, and store the task data in a local data cache submodule (207), and read the task data from the local data cache submodule (207) according to a data read request sent by a target computing core and send the task data to the target computing core; The storage core (102) is used to store task data and, according to a data read request sent by the target transmission module, send the task data to the target transmission module; The computing core particle (101) is used to send a data read request to the transmission module (200), and after receiving the task data returned by the transmission module (200), execute the computing task according to the received task data.

2. The computing chip (100) according to claim 1, characterized in that: For each transmission module (200), the transmission module (200) includes: a parsing and distribution submodule (203); The parsing and distributing submodule (203) is used to receive a data packet and parse the data packet to determine the data type corresponding to the data; According to the data type, the data is sent to other submodules in the transmission module (200).

3. The computing chip (100) according to claim 2, characterized in that: The other submodules include: a channel selection submodule (204), a task management submodule (205) and a cache management submodule (206); The parsing and distributing submodule (203) is used to send the forwarding data to the channel selecting submodule (204) if the data type is forwarding data; If the data type is memory access task management data, sending the memory access task management data to the task management submodule (205) for storage; If the data type is task data, sending the task data to the data cache submodule (207) for storage; If the data type is instruction data corresponding to the data read request, the instruction data is sent to the cache management submodule (206).

4. The computing chip (100) according to claim 3, characterized in that: The channel selection submodule (204) is used to determine the target output channel corresponding to the forwarded data, and send the forwarded data through the target output channel; The task management submodule (205) is used to execute the data memory access task corresponding to the memory access task management data when it is detected that the remaining storage space in the data cache submodule (207) is greater than a preset threshold; The cache management submodule (206) is used to map the addresses corresponding to the data stored in the cache submodule, and to read the task data from the data cache submodule (207) according to the instruction data and the mapped address.

5. The computing chip (100) according to claim 4, characterized in that: The task management submodule (205) comprises: a task parsing unit (205_1), a task management list unit (205_3) and a task management control unit (205_2); The task parsing unit (205_1) is used to parse the data packet of the access task management data; The task management list unit (205_3) is used to store a data list of parsed access task management data; The task management control unit (205_2) is used to, when it is detected that the remaining storage space in the data cache submodule (207) is greater than a preset threshold, read the task data required for the computing core particle (101) to perform the computing task from the storage core particle (102) according to the data list and store it in the data cache submodule (207).

6. The computing chip (100) according to claim 1, characterized in that: For each transmission module (200), the transmission module (200) further includes: an input port (201), an input buffer submodule (202), an output queue submodule (208) and an output port (209); The input port (201) is used to receive data sent by at least one of the computing core particle (101), the storage core particle (102) and other transmission modules (200); The input buffer submodule (202) is used to temporarily store received data; The output port (209) is used to send the input forwarding data; The output queue submodule (208) is provided with a plurality of output channels, which are used to transmit the forwarded data to the output port (209) corresponding to the target output channel through the target output channel.

7. A method for executing a computing task, characterized in that: The method is applied to a computing chip (100), the computing chip (100) comprising: a plurality of transmission modules (200), a computing core particle (101) and a storage core particle (102), and the method comprises: Get access task management data; According to the memory access task management data, task data required for each computing core particle (101) to perform a computing task is read from at least one storage core particle (102) through each transmission module (200), and stored in a local data cache submodule (207) of each transmission module (200); After receiving an execution request of a computing task, according to the execution request, sending a data read request to at least one target transmission module connected thereto through each computing core particle (101), so that the target transmission module reads the task data from the local data cache submodule (207) according to the data read request and sends the task data to each computing core particle (101); The computing tasks are executed according to the received task data through the computing core particles (101).

8. The method according to claim 7, characterized in that Before reading task data required for each computing core particle (101) to perform a computing task from at least one storage core particle (102) through each transmission module (200) according to the memory access task management data, the method further comprises: In response to a startup instruction of the runtime, the memory access task management data is sent to each transmission module (200) through a preset intelligent agent according to the topological structure of each core particle and the transmission module (200) contained in the computing chip (100).

9. The method according to claim 7, characterized in that Before acquiring the memory access task management data, the method further includes: Receiving a data packet of data, and parsing the data packet to determine the data type of the data; According to the memory access task management data, task data required for each computing core particle (101) to perform a computing task is read from at least one storage core particle (102) through each transmission module (200), and stored in a local data cache submodule (207) of each transmission module (200), specifically including: If the data type is memory access task management data, the memory access task management data is stored, and when it is detected that the remaining storage space in the data cache submodule (207) is greater than a preset threshold, a data read request is sent to each storage core particle (102) through each transmission module (200), so that each storage core particle (102) sends the task data to each transmission module (200) according to the data read request; If the data type is task data, the task data is stored in a local data cache submodule (207) of each transmission module (200); If the data type is forwarding data, a channel selection submodule (204) determines a target output channel corresponding to the forwarding data, and sends the forwarding data through the target output channel.

10. The method according to claim 9, characterized in that Sending a data read request to at least one target transmission module connected thereto through each computing core particle (101), so that the target transmission module reads task data from a local data cache submodule (207) according to the data read request and sends the task data to each computing core particle (101), specifically comprising: If the data type is instruction data corresponding to a data read request, task data is read from the data cache submodule (207) and sent to each computing core particle (101) according to the instruction data and the address corresponding to the pre-mapped data stored in the cache submodule.

11. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of claims 8 to 10 is implemented.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method described in any one of claims 7 to 10 is implemented.

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