Processing and query method and query system for host memory

Abstract

The invention relates to the technical field of data storage, and discloses a host memory processing and query method and a query system.The host memory processing method is applied to flash memory equipment, the flash memory equipment is in communication connection with a host, and the host memory processing method comprises the steps that when the cache space of the flash memory equipment is larger than a preset memory, a first range array in the cache space is obtained; moving the first range array in the cache space to a host memory to generate a second range array in the host memory; after the migration is completed, obtaining a logic address field corresponding to the first range array; modifying the first global range table, changing a pointer corresponding to the logic address field from a first range array to a second range array, and moving the first range array in the cache space to a host memory so as to generate the second range array in the host memory, therefore, the memory space of the flash memory device is saved, and the data processing efficiency of the system is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of data storage, and in particular to a method for processing and querying a host memory and a query system thereof. Background Art

[0002] In modern solid-state drives (SSDs), the logical address to physical address mapping table (L2P table) is an important part of the flash translation layer (FTL). This L2P table not only directly affects the read and write performance, but also occupies most of the SSD's memory resources. In addition, the size of the mapping table increases with the increase in flash memory capacity, but the physical space available for memory particles in the SSD is approaching its limit. With the exponential increase in global data volume and the emergence of large-capacity QLC SSDs, the contradiction of internal memory shortage in SSDs has become increasingly prominent.

[0003] At present, there are two existing technical solutions: the first is to use the Open-Channel SSD solution to use the host computing power and host memory to complete the work of FTL. The open-channel solid-state drive (Open-Channel Solid State Drive) is a special solid-state drive that does not implement the flash translation layer (FTL) in the drive's firmware, but transfers the management task of physical solid-state storage to the computer's operating system. The architecture of the Open-Channel SSD is more complex than that of the traditional SSD, and the host side is required to manage and coordinate the operations of each channel, including data writing, erasing, and garbage collection, etc., which requires higher host-side resources, which increases the software development and maintenance costs of the host side. The second is to place the array in the host memory and statically occupy the host memory, which lacks flexibility like the Open-Channel SSD. The second is to apply for a fixed size of memory for HMB through the NVMe driver when the system starts, and it will continue to occupy it until the system is shut down. A small amount of occupation has little impact on the system, but a large-capacity SSD needs to occupy several GB of memory, which is unacceptable for hosts with memory shortages. Therefore, the existing technical solutions all have the disadvantage of not being able to take into account both data processing efficiency and saving memory space. Summary of the invention

[0004] An embodiment of the present application provides a host memory processing and query method and a query system thereof. By moving a first range array in a cache space to the host memory to generate a second range array in the host memory, the present application can save memory space of a flash memory device and improve the data processing efficiency of the system.

[0005] The embodiments of the present application provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a host memory processing method, which is applied to a flash memory device, the flash memory device is communicatively connected to a host, wherein the host includes a host memory, the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used to store a pointer corresponding to a logical address segment, and the first range array is used to store a mapping pair generated by a random write, the method comprising:

[0007] When the cache space of the flash memory device is larger than the preset memory, obtaining a first range array in the cache space;

[0008] Moving the first range array in the cache space to the host memory to generate a second range array in the host memory;

[0009] After the migration is completed, the logical address segment corresponding to the first range array is obtained;

[0010] The first global range table is modified to change the pointer corresponding to the logical address segment from the first range array to the second range array.

[0011] In some embodiments, the flash memory device includes a flash memory controller, and moving the first range array in the cache space to the host memory includes:

[0012] Obtaining a transfer request, wherein the transfer request is used to request the host to transfer the first range array to the host memory;

[0013] Sending the transfer request to a transfer queue via the flash memory controller;

[0014] The first range array in the cache space is moved to the host memory through the transfer queue.

[0015] In some embodiments, the method further comprises:

[0016] In the process of moving the first range array to the host memory, determining whether a write operation needs to be performed on the first range array at present;

[0017] If a write operation needs to be performed on the first range array at present, the transmission flag corresponding to the current move is determined as a failure state;

[0018] The transfer flag is transmitted to the host through the transfer queue, so that when the migration is completed, the host detects that the transfer flag is in a failed state, determines the migration as an invalid migration, and re-initiates the migration operation on the flash memory device.

[0019] In a second aspect, an embodiment of the present application provides a host memory query system, the system comprising a flash memory device and a host;

[0020] The flash memory device is communicatively connected to the host, the flash memory device includes a cache space, and the flash memory device is used to obtain a first range array in the cache space when the cache space is larger than a preset memory; move the first range array to the host memory to generate a second range array in the host memory;

[0021] The host is communicatively connected to the flash memory device. Before sending a read request to the flash memory device, the host queries the physical address corresponding to the logical address in the read request through the second range array; generates a read command according to the physical address, and sends the read command to the flash memory device so that the flash memory device returns the corresponding data according to the physical address.

[0022] In some embodiments, the flash memory device includes a flash memory controller, which is used to obtain a transfer request, wherein the transfer request is used to request a host to transfer a first range array to a host memory; send the transfer request to a transfer queue, and move the first range array in the cache space to the host memory through the transfer queue.

[0023] In some embodiments, the host includes a kernel module and a host memory, the host memory stores a second global range table, the host includes a kernel module, and the kernel module is used to obtain a read request; when the host queries a physical address corresponding to the logical address through the second range array, the host sends a read command to the flash memory device, wherein the read command includes the physical address, or when the host does not query the physical address corresponding to the logical address through the second range array, the host sends a read request to the flash memory device;

[0024] The flash memory device is further used to send a notification message to the kernel module after moving the first range array to the host memory, so that the kernel module updates the second global range table according to the notification message, wherein the notification message includes the logical address segment corresponding to the first range array;

[0025] The kernel module is also used to receive a notification message, and update the second global range table according to the notification message, so as to change the pointer corresponding to the logical address segment in the second global range table from the first range array to point to the second range array.

[0026] In some embodiments, the host further comprises a mapping module and a main control processor;

[0027] The mapping module is used to establish an internal address conversion mapping relationship between the internal address of the flash memory device and the bus address of the host; according to the internal address conversion mapping relationship, the offset address of the logical address is converted into the bus address;

[0028] The main control processor is used to access the second range array according to the bus address to obtain the physical address corresponding to the logical address.

[0029] In a third aspect, an embodiment of the present application provides a host memory query method, which is applied to a host memory query system, wherein the host memory query system includes a flash memory device and a host, wherein the flash memory device is communicatively connected to the host, wherein the host includes a host memory, the host memory is used to store a second global range table and a second range array, and the second global range table is used to store a pointer corresponding to a logical address segment, and the method includes:

[0030] Get the logical address;

[0031] Query the second global range table to determine whether the pointer corresponding to the logical address points to the host;

[0032] If the pointer corresponding to the logical address points to the host, the physical address corresponding to the logical address is obtained through the second range array.

[0033] In some embodiments, obtaining the logical address includes:

[0034] Get read request;

[0035] According to the read request, obtain the starting address in the read request;

[0036] Get the starting address of the namespace and the logical page size of the flash device;

[0037] The logical address is calculated based on the starting address in the read request, the starting address of the namespace, and the logical page size of the flash device.

[0038] In some embodiments, obtaining the physical address corresponding to the logical address through the second range array includes:

[0039] Determine whether an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host;

[0040] If an internal address conversion mapping relationship has been established between the internal address of the flash memory device and the bus address of the host, the offset address of the logical address is converted into a bus address according to the internal address conversion mapping relationship;

[0041] According to the bus address, the second range array is accessed to obtain the physical address corresponding to the logical address.

[0042] In some embodiments, the method further comprises:

[0043] Determine whether the physical address corresponding to the logical address is found in the second range array;

[0044] If the physical address corresponding to the logical address is not found in the second range array, a read request is sent to the flash memory device, so that the flash memory device queries the physical address corresponding to the logical address according to the read request.

[0045] In some embodiments, the method further comprises:

[0046] If the physical address corresponding to the logical address is found in the second range array, it is determined whether the physical address is a continuous physical address;

[0047] If the physical address is a continuous physical address, generating a first read command according to the physical address, and sending the first read command to the flash memory device;

[0048] If the physical address is not a continuous physical address, the read request is disassembled into multiple second read commands, and the second read commands are sent to the flash memory device, wherein each second read command corresponds to the same number of logical addresses and physical addresses corresponding to the logical addresses.

[0049] In some embodiments, the method further comprises:

[0050] When the physical address corresponding to the logical address is found in the second range array, the hit count is recorded once;

[0051] Determine whether the number of hits is greater than a threshold within a preset fixed time;

[0052] If the number of hits is greater than the threshold, the physical memory page corresponding to the physical address is obtained; the physical memory page corresponding to the physical address is moved to the cache space of the flash memory device to generate a first range array in the flash memory device, and the second global range table is updated to point the pointer corresponding to the logical address to the flash memory device.

[0053] In some embodiments, the first version number corresponding to the second range array is stored in the cache space of the flash memory device, and after updating the second global range table, the method further includes:

[0054] The flash memory device updates the first version number corresponding to the second range array, and writes the first version number to the host memory at a preset time interval to generate a second version number in the host memory;

[0055] When the host sends a first read command or a second read command to the flash memory device, the host writes the second version number into the first read command or the second read command, so that the flash memory device obtains the second version number through the first read command or the second read command;

[0056] The flash memory device determines whether the second version number is consistent with the first version number stored in the current cache space;

[0057] If the second version number is inconsistent with the first version number stored in the current cache space, the second range array is queried again.

[0058] In a fourth aspect, an embodiment of the present application provides a non-volatile computer-readable storage medium, in which a computer program or instruction is stored. When the computer program or instruction is executed, the host memory processing method of the first aspect or the host memory query method of the third aspect is implemented.

[0059] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the embodiments of the present application provide a host memory processing method, which is applied to a flash memory device, and the flash memory device is communicatively connected to a host, wherein the host includes a host memory, and the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used to store a pointer corresponding to a logical address segment, and the first range array is used to store a mapping pair generated by a random write, and the method includes: when the cache space of the flash memory device is larger than a preset memory, obtaining a first range array in the cache space; moving the first range array in the cache space to the host memory to generate a second range array in the host memory; after the moving is completed, obtaining the logical address segment corresponding to the first range array; modifying the first global range table, and changing the pointer corresponding to the logical address segment from the first range array to point to the second range array. The present application can save the memory space of the flash memory device and improve the data processing efficiency of the system by moving the first range array in the cache space to the host memory to generate the second range array in the host memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0061] Figure 1 It is a flowchart of a method for processing host memory provided by an embodiment of the present application;

[0062] Figure 2 yes Figure 1 A detailed flow chart of step S102 in FIG.

[0063] Figure 3 This is a flowchart of determining whether a write operation needs to be performed on a first range array, provided by an embodiment of the present application;

[0064] Figure 4 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0065] Figure 5 It is a structural diagram of a host memory query system provided by an embodiment of the present application;

[0066] Figure 6 It is a structural diagram of a flash memory device and a flash memory controller provided in an embodiment of the present application;

[0067] Figure 7 This is a schematic diagram of the connection relationship between a kernel module and a user module provided in an embodiment of the present application;

[0068] Figure 8 It is a schematic diagram of the connection relationship between a mapping module and a main control processor provided in an embodiment of the present application;

[0069] Fig. 9 It is a flowchart of a host memory query method provided by an embodiment of the present application;

[0070] Fig.10 yes Fig. 9 A detailed flow chart of step S901 in FIG.

[0071] Fig.11 It is a flowchart of determining whether an internal address conversion mapping relationship is established between an internal address of a flash memory device and a bus address of a host provided by an embodiment of the present application;

[0072] Fig.12 It is a flowchart of determining whether a physical address corresponding to a logical address is found in a second range array provided by an embodiment of the present application;

[0073] Fig.13 It is a flowchart of determining whether the number of hits is greater than a number threshold within a preset fixed time provided by an embodiment of the present application;

[0074] Fig.14 It is a flowchart of a flash memory device provided by an embodiment of the present application for determining whether a second version number is consistent with a first version number stored in a current cache space.

[0075] Description of Figure Numbers:

[0076] Label name Label name 100 Flash memory devices 101 processor 102 Memory 10 Host memory query system 101 Cache space 102 Flash Memory Controller 110 Host 111 Host memory 112 Kernel modules 113 User Modules 114 Mapping Module 115 Main control processor DETAILED DESCRIPTION

[0077] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right" and similar expressions used in this specification are for illustrative purposes only.

[0078] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0079] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings:

[0080] In an embodiment of the present application, the present application provides a data structure of a range hash bucket stored in a flash memory device, wherein the range bucket hash table is composed of a global range table, a range bucket, and a range array, wherein the global range table is used to record the mapping table address corresponding to each logical address range (logical address segment), and the pointer corresponding to the storage logical address segment. It should be noted that the range in the global range table is of indefinite length, and its range changes dynamically according to the splitting and merging of the range bucket and the range array, wherein the starting address of each logical address segment is stored in the global range table, and the starting address of the next range is also the end address of the previous range. The range bucket is a hash table structure, and the range bucket has a fixed size, which is used to store the mapping pair of the logical address (Logi cal Page Address, LPA) in the range to the physical address (Phys i cs Page Address, PPA), wherein the mapping pair is composed of two fields, LPA and PPA. Compared with the array structure, the range bucket is more suitable for storing sparse mapping pairs. When the density of the range bucket reaches the upper limit of a range bucket storage mapping pair, that is, when the capacity of the range bucket reaches the capacity threshold, the range bucket will be split. According to the actual situation, it can be split into two range buckets, or multiple range arrays, or a combination of range arrays and range buckets. The range array is an array with a fixed length, which is organized according to the structure of the traditional array solution to store PPAs within a range. Specifically, the range array is used to store mapping pairs generated by random reads and writes. The base address of each range array is recorded in the global range table, and when the number of valid mappings in the range array decreases, it will be converted back to a range bucket. Compared with the range bucket, the insertion and query performance of the range array is higher, and it is more suitable for storage in the host memory. In some embodiments, since the range bucket query may encounter hash conflicts, linear detection will cause multiple memory accesses. The range array only needs one memory access to obtain the PPA, so the range array is more suitable for being placed in the host memory than the range bucket. Placing the range array in the host memory can reduce the number of PCI e requests. Therefore, when a large number of range arrays are generated in random scenarios, resulting in insufficient cache space of the flash memory device, the present application reduces the storage pressure of the flash memory device and saves the memory of the flash memory device by moving the range array from the flash memory device to the host memory.

[0081] See also Figure 1 , Figure 1 It is a flowchart of a method for processing host memory provided by an embodiment of the present application;

[0082] In an embodiment of the present application, a method for processing host memory is applied to a flash memory device, which is communicatively connected to a host, and the flash memory device includes a solid-state drive (SSD), wherein the host includes a host memory, and the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used for logical address segments and pointers corresponding to each logical address segment, and the first range array is used to store mapping pairs generated by random writes, wherein random writes refer to that in a file or data storage, data is not written in a specific order, but a storage location is randomly selected for write operations, and this writing method is opposite to sequential writing, and sequential writing refers to that data is continuously written to a storage medium in a certain order, while random write operations usually involve a large randomness in the selection of storage locations, which is independent of the location of the previous write or the order of data.

[0083] like Figure 1 As shown, the process of the host memory processing method includes:

[0084] Step S101: when the cache space of the flash memory device is larger than the preset memory, obtaining a first range array in the cache space;

[0085] Specifically, when the cache space actually used by the flash memory device is larger than the preset memory, a first range array in the cache space is obtained, wherein the preset memory can be set according to actual needs. The preset memory refers to a memory size. For example, the flash memory device includes 8GB of memory space, and the first range array is limited to use only 1GB of cache space, then 1GB is the size of the preset memory. When the cache space used by the first range array is larger than 1GB, a move operation is initiated. That is to say, when the cache space actually used by the flash memory device is larger than the preset memory, a move operation needs to be initiated to release the memory of the flash memory device and reduce the memory occupancy on the disk.

[0086] Step S102: moving the first range array in the cache space to the host memory to generate a second range array in the host memory;

[0087] In the embodiment of the present application, the host memory includes HMB (Host Memory Buffer), which is used to allow the host to provide the memory resources that are not currently needed to the flash memory device through the NVMe protocol. The HMB process refers to moving the first range array in the cache space to the host memory. The principle of HMB technology is to reserve a cache area in the host's memory for SSD use. This area only occupies a small part of the memory space (within 128MB), and the memory reserves sufficient space to coordinate the data exchange between the CPU and the hard disk. It can be understood that the size of HMB is usually set to within 128MB in the NVMe driver, but by using different types of drivers, the size of HMB can be adjusted according to actual needs, wherein the size of HMB is limited by the size of the host's physical memory.

[0088] For details, please refer to Figure 2 , Figure 2 yes Figure 1 A detailed flow chart of step S102 in FIG.

[0089] like Figure 2 As shown, step S102: moving the first range array in the cache space to the host memory to generate a second range array in the host memory, including:

[0090] Step S121: obtaining a transmission request;

[0091] Specifically, a transfer request is obtained, wherein the transfer request is used to request the host to transfer the first range array to the host memory.

[0092] Step S122: sending the transfer request to the transfer queue via the flash memory controller;

[0093] Specifically, the flash memory device includes a flash memory controller, and the host is equipped with DMA hardware. The flash memory controller interacts with the DMA hardware through a queue, and DMA is executed independently from the main control. Among them, DMA (Direct Memory Access) is a technology that allows direct memory access. It implements direct data transmission between memory and memory or between memory and I / O devices through hardware, that is, it allows certain types of hardware devices to directly access the system memory without the intervention of the central processing unit (CPU). The DMA hardware includes a DMA controller, which is responsible for coordinating and controlling the data transmission between the hardware device and the system memory. Data transmission between the flash memory device and the host through DMA technology can reduce CPU consumption when transmitting large amounts of data, thereby improving CPU utilization efficiency and data transmission efficiency. Through the flash memory controller, the transmission request is sent to the transmission queue.

[0094] In the embodiment of the present application, the flash memory device only needs to send one or more transfer requests of the first range array to the queue, and then continue with other tasks, and then update the first global range table when the DMA is completed.

[0095] In an embodiment of the present application, the method of accessing HMB includes a DMA module suitable for large-scale data transmission, and a zero-copy iATU module. The present invention combines the two methods to access HMB, and completes the batch transmission of multiple range arrays through DMA. It can write from the SSD to the host to reduce memory pressure, and load the range array back from the host, that is, the first range array in the flash memory device can be converted to the second range array in the host for structural adjustment to dynamically adjust the host memory resources and the memory resources of the flash memory device. Specifically, iATU is suitable for single query range array for access within 8 bytes (the range array can complete the query with one memory access); and DMA is used to complete batch memory copying, which is suitable for copying pages of 4KB and above to the host, or from the host to the SSD.

[0096] Step S123: moving the first range array in the cache space to the host memory through the transmission queue;

[0097] Specifically, the first range array includes multiple mapping pairs. Through the transmission queue, all mapping pairs of the first range array in the cache space are moved to the host memory to generate a second range array in the host memory. It can be understood that the second range array includes all mapping pairs in the first range array.

[0098] Step S103: after the migration is completed, obtaining the logical address segment corresponding to the first range array;

[0099] Specifically, each range array corresponds to a logical address segment, and after the migration is completed, the logical address segment corresponding to the first range array is obtained.

[0100] Step S104: modify the first global range table, and change the pointer corresponding to the logical address segment from the first range array to the second range array;

[0101] Specifically, the first global range table records the pointers corresponding to the logical address segments of the first range array. Before the first range array is moved, the pointers of the logical address segments corresponding to the first range array in the first global range table point to the cache space in the flash memory device. After the first range array is moved, the first global range table needs to be modified to change the pointers corresponding to the logical address segments from the first range array to point to the second range array in the host memory. In addition, the host memory includes the second global range table. When modifying the first global range table, the second global range table also needs to be modified synchronously. For example, in the second global range table, the logical address segments corresponding to the second range array are added, and the pointers of the logical address segments corresponding to the second range array are pointed to the host memory.

[0102] In an embodiment of the present application, the pointer in the first global scope table / the second global scope table is updated by an atomic operation, wherein the atomic type is a data type provided by the compiler that can be safely accessed without using a mutex lock, and secure access is achieved in a multi-core system. Specifically, the atomic operation includes calling an atomic type operation in the compiler. The atomic operation is used here to ensure the atomicity of the pointer update in the RCU mechanism to prevent other cores from obtaining incomplete addresses.

[0103] Please refer to Figure 3 , Figure 3 This is a flowchart of determining whether a write operation needs to be performed on a first range array, provided by an embodiment of the present application;

[0104] like Figure 3 As shown, the process of determining whether a write operation needs to be performed on the first range array currently includes:

[0105] Step S301: moving the first range array;

[0106] Specifically, the first range array in the cache space of the flash memory device is moved to the host memory through the transmission queue.

[0107] Step S302: during the process of moving the first range array to the host memory, determining whether a write operation needs to be performed on the first range array;

[0108] Specifically, in the process of moving the first range array to the host memory, there may be a situation where a write operation needs to be performed on the first range array. Therefore, it is necessary to determine whether a write operation needs to be performed on the first range array. If a write operation needs to be performed on the first range array, proceed to step S304; if a write operation does not need to be performed on the first range array, proceed to step S303.

[0109] Step S303: determining the transmission flag corresponding to the current move as a success state;

[0110] Specifically, if no write operation is required on the first range array, that is, no write operation is performed on the first range array during the migration process, the transmission flag corresponding to this migration is determined to be a successful state. After the migration is completed, a second range array is generated in the host memory, and the cache space of the first range array in the flash memory device is automatically released.

[0111] Step S304: determining the transmission flag corresponding to the current migration as a failure state;

[0112] Specifically, if a write operation needs to be performed on the first range array, that is, a write operation is performed on the first range array during the migration process, the transmission flag corresponding to the migration is determined to be in a failed state.

[0113] Step S305: transmitting the transfer flag to the host through the transfer queue, so that when the transfer is completed, the host detects that the transfer flag is in a failed state, determines the transfer as invalid, and re-initiates the transfer operation on the flash memory device;

[0114] Specifically, the flash memory device transmits the transfer flag to the host through the transfer queue, so that when the transfer is completed, the host detects that the transfer flag is in a failed state through the main control processor, and determines the transfer as an invalid transfer. The host will clear the transfer flag corresponding to the transfer and re-initiate the transfer operation (DMA retransmission) to the flash memory device. It should be noted that when a write operation is performed on the first range array, the transfer process cannot be terminated immediately. The data written by the write operation will be stored in the address segment corresponding to the first range array. When the transfer is completed, the transfer is determined to be an invalid transfer, and the transfer operation is re-initiated to the flash memory device. It can be understood that the write operation will cause the data in the first range array to change (the data is changed, resulting in possible errors in the data moved to the host), but the transfer operation will not be terminated immediately due to the write operation, so the flash memory device will send a failure status flag to the host after the transfer is completed to inform the host that the transfer is invalid and let the host re-initiate the transfer operation.

[0115] In an embodiment of the present application, a host memory processing method is provided, which is applied to a flash memory device, wherein the flash memory device is communicatively connected to the host, wherein the host includes a host memory, and the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used to store pointers corresponding to logical address segments, and the first range array is used to store mapping pairs generated by random writes, and the method includes: when the cache space of the flash memory device is larger than the preset memory, obtaining the first range array in the cache space; moving the first range array in the cache space to the host memory to generate a second range array in the host memory; after the move is completed, obtaining the logical address segment corresponding to the first range array; modifying the first global range table, changing the pointer corresponding to the logical address segment from the first range array to point to the second range array. The present application can save the memory space of the flash memory device and improve the data processing efficiency of the system by moving the first range array in the cache space to the host memory to generate the second range array in the host memory.

[0116] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0117] like Figure 4 As shown, the flash memory device 100 includes one or more processors 101 and a memory 102. Figure 4 A processor 101 is taken as an example.

[0118] The processor 101 and the memory 102 may be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.

[0119] The processor 101 is used to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to perform the process of the host memory processing method in any of the above method embodiments, which is applied to the flash memory device, and the flash memory device is communicatively connected to the host, wherein the host includes the host memory, and the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used to store pointers corresponding to logical address segments, and the first range array is used to store mapping pairs generated by random writes, and the method includes: when the cache space of the flash memory device is larger than the preset memory, obtaining the first range array in the cache space; moving the first range array in the cache space to the host memory to generate a second range array in the host memory; after the move is completed, obtaining the logical address segment corresponding to the first range array; modifying the first global range table, and changing the pointer corresponding to the logical address segment from the first range array to point to the second range array.

[0120] The present application can save memory space of the flash memory device by moving a first range array in the cache space of the flash memory device to the host memory to generate a second range array in the host memory.

[0121] The processor 101 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general array logic (GAL) or any combination thereof.

[0122] The memory 102 is a non-transient computer-readable storage medium, which can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the host memory processing method in the embodiment of the present application. The processor 101 can implement the host memory processing method in any of the above method embodiments, or the host memory query method by running the non-transient software programs, instructions and modules stored in the memory 102. Specifically, the memory 102 may include a volatile memory (VM), such as a random access memory (RAM); the memory 102 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory (flash memory), a hard disk (HDD) or a solid-state drive (SSD) or other non-transient solid-state storage device; the memory 102 may also include a combination of the above-mentioned types of memory.

[0123] The memory 102 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 102 may optionally include a memory remotely arranged relative to the processor 101, and these remote memories may be connected to the processor 101 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0124] One or more modules are stored in the memory 102, and when executed by one or more processors 111, the host memory processing method in any of the above method embodiments is executed.

[0125] In the embodiment of the present application, the flash memory device 100 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 100 may also include other components for realizing device functions, which will not be described in detail here.

[0126] Please refer to Figure 5 , Figure 5 It is a structural diagram of a host memory query system provided by an embodiment of the present application;

[0127] like Figure 5 As shown, the host memory query system 10 includes: Figure 4 A flash memory device 100 and a host 110;

[0128] The flash memory device 100 is communicatively connected to the host 110, and the flash memory device 100 includes a cache space 103. The flash memory device 100 is used to obtain a first range array in the cache space when the cache space is larger than the preset memory; move the first range array to the host memory to generate a second range array in the host memory; specifically, when the cache space of the flash memory device is larger than the preset memory, obtain the first range array in the cache space, wherein the preset memory can be set according to actual needs, for example, the preset memory is set to 1GB, and obtain a transfer request, wherein the transfer request is used to request the host to transfer the first range array to the host memory, and the transfer request is sent to a transfer queue through the flash memory controller, the first range array includes multiple mapping pairs, and all mapping pairs of the first range array in the cache space are moved to the host memory through the transfer queue to generate a second range array in the host memory. It can be understood that the second range array includes all mapping pairs in the first range array. After the move is completed, the logical address segment corresponding to the first range array is obtained, and the first global range table is modified to change the pointer corresponding to the logical address segment from the first range array to the second range array.

[0129] The host 110 is communicatively connected to the flash memory device 100. The host includes a host memory 111. The host memory 111 stores a second global range table and a second range array. The host 110 is used to query the physical address corresponding to the logical address in the read request through the second range array before sending a read request to the flash memory device; generate a read command according to the physical address, and send the read command to the flash memory device, so that the flash memory device returns the corresponding data according to the physical address; specifically, the conventional query process is that the host directly sends a read request to the flash memory device, so that the flash memory device performs a query according to the read request, and the solution of the present application is to query the physical address corresponding to the logical address in the read request through the second range array in the host before sending a read request to the flash memory device; generate a read command according to the physical address, and send the read command to the flash memory device, so that the flash memory device returns the corresponding data according to the physical address. In an embodiment of the present application, before sending a read request to the flash memory device, the physical address corresponding to the logical address is first queried in the second range array of the host. The present application can query the physical address corresponding to the logical address in advance by utilizing the computing power of the host, and this method can improve the query efficiency of the physical address.

[0130] Please refer to Figure 6 , Figure 6 It is a structural diagram of a flash memory device and a flash memory controller provided in an embodiment of the present application;

[0131] like Figure 6As shown, the flash memory device 100 includes a flash memory controller 104, and the flash memory controller 104 is used to obtain a transfer request, wherein the transfer request is used to request the host to transfer the first range array to the host memory; the transfer request is sent to the transfer queue, and the first range array in the cache space is moved to the host memory through the transfer queue; specifically, the flash memory device includes a flash memory controller, and the host is equipped with DMA hardware. The flash memory controller interacts with the DMA hardware through the transfer queue, and the DMA is independently executed between the main control, wherein DMA (Direct Memory Access) is a technology that allows direct memory access, which implements direct data transmission between memory and memory or between memory and I / O devices through hardware, that is, allows certain types of hardware devices to directly access the system memory without intervention through the central processing unit (CPU), and the DMA hardware includes a DMA controller, which is responsible for coordinating and controlling the data transmission between the hardware device and the system memory. Data transmission between the flash memory device and the host through DMA technology can reduce CPU consumption when large amounts of data are transmitted, thereby improving CPU utilization efficiency and data transmission efficiency. A transfer request is sent to a transfer queue through a flash memory controller; the first range array includes multiple mapping pairs, and all mapping pairs of the first range array in the cache space are moved to the host memory through the transfer queue to generate a second range array in the host memory. It can be understood that the second range array includes all mapping pairs in the first range array.

[0132] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the connection relationship between a kernel module and a user module provided in an embodiment of the present application;

[0133] like Figure 7 As shown, the host 110 includes a kernel module 112 and a user module 113, the kernel module 112 includes a driver, and the user module 113 includes an application program;

[0134] The user module 113 is communicatively connected to the kernel module 112, and the user module 113 is used to send a read request to the kernel module 112. Specifically, the application in the user module 113 sends a read request to the driver in the kernel module 112, so that the driver queries the physical address corresponding to the logical address according to the logical address in the read request, wherein the read request includes the logical address.

[0135] The kernel module 112 is used to receive a read request sent by the user module 113; when the host queries the physical address through the second range array, a read command is sent to the flash memory device, or when the host does not query the physical address through the second range array, a read request is sent to the flash memory device; specifically, the kernel module includes an NVMe driver, and the read request includes an NVMe read request. After the host queries the physical address corresponding to the logical address through the second range array, it is necessary to determine whether the physical address is a continuous physical address. If the physical address is a continuous physical address, a first read command is generated according to the physical address, and the first read command is sent to the flash memory device, which In the embodiment, generating a first read command according to the physical address refers to recording the starting address of the queried physical address into a specified field in the first read command to generate the first read command; if the physical address is not a continuous physical address, the read request is disassembled into multiple second read commands, and the second read commands are sent to the flash memory device, wherein each second read command corresponds to the same number of logical addresses and the physical addresses corresponding to the logical addresses. For example, if the physical address is not a continuous physical address, assuming that the read request includes 12 logical addresses, the read request can be split in a manner of generating a second read command for every 4 logical addresses and the physical addresses corresponding to the logical addresses.

[0136] The flash memory device 100 is also used to send a notification message to the kernel module 112 after moving the first range array to the host memory, so that the kernel module updates the second global range table according to the notification message, wherein the notification message includes the logical address segment corresponding to the first range array; specifically, the notification message includes an asynchronous event notification (Asynchronous Event Notification, AEN) message. In an embodiment of the present application, the process of exchanging the first range array of the flash memory device to the host memory is called DMA transfer. After the DMA transfer of a range array is completed, the flash memory device will use a custom asynchronous event notification (Asynchronous Event Notification, AEN) message to inform the host of the base address and the length of the logical address segment of the second range array, as well as the direction of the DMA transfer, wherein the direction of the DMA transfer includes transmission from the cache space of the flash memory device to the host memory or from the host memory to the cache space of the flash memory device.

[0137] The kernel module 112 is further used to receive a notification message sent by the flash memory device, and update the second global range table according to the notification message, so as to change the pointer corresponding to the logical address segment in the second global range table from the first range array to the second range array; specifically, in order to synchronize the second global range table in the host memory with the first global range table in the flash memory device, after each DMA transmission is completed, the second global range table in the host memory and the first global range table in the flash memory device are synchronously updated to ensure the accuracy of the data. For example, when the direction of the DMA transmission is from the cache space of the flash memory device to the host memory, the first range array is updated from the flash memory device to the first range array. The cache space of the flash memory device is exchanged to the host memory to generate a second range array in the host memory, then the logical address segment of the first range array is obtained, and the pointer corresponding to the logical address segment in the first global range table and the second global range table is pointed from the first range array to the second range array; when the direction of DMA transmission is from the memory space of the host to the cache space of the flash memory device, the second range array is exchanged from the host memory to the cache space of the flash memory device to generate the first range array in the cache space, then the logical address segment of the second range array is obtained, and the pointer corresponding to the logical address segment in the first global range table and the second global range table is pointed from the second range array to the first range array.

[0138] Please refer to Figure 8 , Figure 8 It is a schematic diagram of the connection relationship between a mapping module and a main control processor provided in an embodiment of the present application;

[0139] like Figure 8 As shown, the host also includes a mapping module 114 and a main control processor 115;

[0140] The mapping module 114 is used to map the internal address of the flash memory device to the bus address of the host to create an internal address conversion mapping relationship; according to the internal address conversion mapping relationship, the offset address of the logical address is converted into a bus address; specifically, the mapping module includes an internal address translation unit (iATU), and the internal address conversion mapping relationship refers to the iATU mapping relationship. The establishment of the mapping relationship of the iATU (internal address translation unit) is to convert the PCI (or PCIe) address inside the flash memory device into the bus address inside the host. In the embodiment of the present application, the mapping module can map the internal address of the flash memory device to the internal bus of the host, so that the main control processor in the host can directly access the internal address of the flash memory device through the internal address conversion mapping relationship. Therefore, if there is no internal address conversion mapping relationship between the internal address of the flash memory device and the bus address of the host, the internal address conversion mapping relationship is created through the iATU module; according to the internal address conversion mapping relationship, the offset address of the logical address is converted into a bus address recognizable by the host to improve the query efficiency of the host.

[0141] The main control processor 115 is used to access the second range array according to the bus address to obtain the physical address corresponding to the logical address; specifically, the bus address is an important component in the computer system. The bus address allows the CPU or a unit with DMA capability to communicate with a memory element or a flash memory device to access the memory location or the address of the flash memory device. For example, according to the bus address corresponding to the second range array, the second range array is accessed to obtain the physical address corresponding to the logical address.

[0142] Please refer to Fig. 9 , Fig. 9 It is a flowchart of a host memory query method provided by an embodiment of the present application;

[0143] In the embodiment of the present application, the following logical address and physical address both refer to a logical page address (LPA) and a physical page address (PPA) in units of pages.

[0144] like Fig. 9 As shown, the process of the host memory query method includes:

[0145] Step S901: Obtaining a logical address;

[0146] For details, please refer to Fig.10 , Fig.10 yes Fig. 9 A detailed flow chart of step S901 in FIG.

[0147] like Fig.10 As shown, step S901: obtaining a logical address, including:

[0148] Step S911: Obtain a read request;

[0149] Specifically, the host is composed of a hardware part and a software part, wherein the hardware part includes a main control processor, and the software part includes an application, wherein the application is used to generate a read request and send the read request to the kernel module of the host, and the kernel module of the host obtains the read request sent by the application, wherein the read request includes an NVMe request, and NVMe (Non-Volume Memory Express) provides an interface standard for flash memory devices and hosts, so that flash memory devices can communicate with the host system in a more efficient manner.

[0150] Step S912: according to the read request, obtaining the starting address in the read request;

[0151] Specifically, the read request includes an NVMe read request, wherein the NVMe read request includes an offset address, and the starting address in the read request is obtained to facilitate subsequent calculation of the logical address.

[0152] Step S913: Obtain the starting address of the namespace and the logical page size of the flash memory device;

[0153] Specifically, obtain the starting address of the namespace and the logical page size of the flash memory device, where the namespace is a basic concept of logical space in the NVMe protocol. The namespace logically divides the user space of the NVMe SSD. Each namespace has its own NAND particles and can independently perform operations such as formatting and encryption. The namespace is an area that maintains a unique name, which is defined by using the namespace keyword. The starting address of the namespace is determined by the operating system and hardware, which indicates the lowest address where the program starts addressing. The logical page size of the flash memory device refers to a fixed-size area in the logical address space, which is used to manage pages in the memory. According to the logical page size, the logical address space can be divided into multiple logical pages. Its size determines how many logical pages the logical address space is divided into. Each logical page includes a starting address and an end address.

[0154] Step S914: Calculate the logical address according to the starting address in the read request, the starting address of the namespace and the logical page size of the flash memory device;

[0155] Specifically, the read request includes the starting address of the data to be read, and the data to be read is specified by the application in the host. The application obtains the starting address of the data to be read, and the starting address is used to indicate which address to start reading the data from, and stores the starting address in the read request. The host calculates the logical address based on the starting address in the read request, the starting address of the namespace, and the logical page size of the flash memory device, wherein the logical address refers to the logical page address (LPA) in pages, and the calculation formula for calculating the logical page address is: Logical page address = starting address in the read request / (logical page size of the flash memory device / host sector size) + starting address of the namespace.

[0156] Step S902: query the second global range table to determine whether the pointer corresponding to the logical address points to the host;

[0157] Specifically, query the second global range table to determine whether the pointer corresponding to the logical address points to the host; if the pointer corresponding to the logical address points to the host, go to step S904; if the pointer corresponding to the logical address does not point to the host, go to step S903.

[0158] Step S903: Obtain the physical address corresponding to the logical address in the local memory;

[0159] Specifically, if the pointer corresponding to the logical address points to the host, it means that the logical address points to the local memory, and then the physical address corresponding to the logical address is obtained in the local memory.

[0160] Step S904: Obtain the physical address corresponding to the logical address through the second range array;

[0161] For details, please refer to Fig.11 , Fig.11 It is a flowchart of determining whether an internal address conversion mapping relationship is established between an internal address of a flash memory device and a bus address of a host provided by an embodiment of the present application;

[0162] like Fig.11 As shown, the process of determining whether an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host includes:

[0163] Step S941: Obtain a second global range table;

[0164] Specifically, the flash memory device obtains a second global range table, wherein the second global range table stores an internal address conversion mapping relationship between an internal address of the flash memory device and a bus address of the host.

[0165] Step S942: determining whether an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host;

[0166] Specifically, the flash memory device queries the second global range table to determine whether an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host. The internal address conversion mapping relationship is used to enable the flash memory device to access the host. If an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host, the process proceeds to step S944; if no internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host, the process proceeds to step S943.

[0167] Step S943: Establishing an internal address translation mapping relationship;

[0168] Specifically, if no internal address translation mapping relationship is established between the internal address of the flash memory device and the bus address of the host, an internal address translation mapping relationship between the internal address of the flash memory device and the bus address of the host is established through an internal address translation unit (I nput / Output Address Translation Unit, iATU).

[0169] Step S944: converting the offset address of the logical address into a bus address according to the internal address conversion mapping relationship;

[0170] Specifically, if an internal address conversion mapping relationship has been established between the internal address of the flash memory device and the bus address of the host, the offset address of the logical address is converted into the bus address according to the internal address conversion mapping relationship.

[0171] Step S945: access the second range array according to the bus address to obtain the physical address corresponding to the logical address;

[0172] Specifically, the master processor is used to access the second range array according to the bus address to obtain the physical address corresponding to the logical address; the bus address is an important component in the computer system. The bus address allows the CPU or a unit with DMA capability to communicate with a memory element or a flash memory device to access the memory location or the address of the flash memory device. For example, through the master processor, according to the bus address corresponding to the second range array, the second range array is accessed to obtain the physical address corresponding to the logical address.

[0173] Please refer to Fig.12 , Fig.12 It is a flowchart of determining whether a physical address corresponding to a logical address is found in a second range array provided by an embodiment of the present application;

[0174] like Fig.12 As shown, the process of determining whether the physical address corresponding to the logical address is found in the second range array includes:

[0175] Step S1201: access the second range array;

[0176] Specifically, the second range array is accessed through the mapped bus address, wherein the second range array stores the physical address corresponding to the logical address.

[0177] Step S1202: Determine whether the physical address corresponding to the logical address is found in the second range array;

[0178] Specifically, the kernel module of the host queries the second range array through the second global range table, and determines whether the physical address corresponding to the logical address is found in the second range array. If the physical address corresponding to the logical address is found in the second range array, step S1204 is entered; if the physical address corresponding to the logical address is not found in the second range array, step S1203 is entered.

[0179] Step S1203: sending a read request to the flash memory device, so that the flash memory device queries the physical address corresponding to the logical address according to the read request;

[0180] Specifically, if the physical address corresponding to the logical address is not queried in the second range array, it means that the mapping pair corresponding to the logical address in the read request does not exist in the host memory. Therefore, it is necessary to continue to query the physical address corresponding to the logical address in the flash memory device. The read request is directly sent to the flash memory device, so that the flash memory device queries the physical address corresponding to the logical address according to the read request.

[0181] Step S1204: determining whether the physical address is a continuous physical address;

[0182] Specifically, the continuity of the physical address refers to the continuous arrangement of the data in the memory on the physical storage medium. If the physical address corresponding to the logical address is queried in the second range array, it is further determined whether the physical address is a continuous physical address. If the physical address is a continuous physical address, step S1205 is entered; if the physical address is a discontinuous physical address, step S1206 is entered.

[0183] Step S1205: Generate a first read command according to the physical address, and send the first read command to the flash memory device;

[0184] Specifically, if the physical address is a continuous physical address, a first read command is generated according to the physical address, and the first read command is sent to the flash memory device, wherein generating the first read command according to the physical address means recording the starting address of the queried physical address into a designated field in the first read command to generate the first read command.

[0185] Step S1206: Decompose the read request into multiple second read commands, and send the second read commands to the flash memory device;

[0186] Specifically, if the physical address is not a continuous physical address, the read request is disassembled into multiple second read commands, and the second read commands are sent to the flash memory device, wherein each second read command corresponds to the same number of logical addresses and the physical addresses corresponding to the logical addresses. For example, if the physical address is not a continuous physical address, assuming that the read request includes 12 logical addresses, the read request can be split in a manner such that a second read command is generated for every 4 logical addresses and the physical addresses corresponding to the logical addresses.

[0187] Please refer to Fig.13 , Fig.13 It is a flowchart of determining whether the number of hits is greater than a number threshold within a preset fixed time provided by an embodiment of the present application;

[0188] Step S1301: when the physical address corresponding to the logical address is found in the second range array, the number of hits is recorded;

[0189] Specifically, the hit modulus number of the physical address is recorded by a counter, and the hit number is increased by 1 each time the physical address corresponding to the logical address is successfully queried in the second range array.

[0190] Step S1302: determining whether the number of hits is greater than a threshold within a preset fixed time;

[0191] Specifically, determine whether the number of hits is greater than the number threshold within the preset fixed time, where the number threshold and the preset fixed time can be set according to actual needs, for example, the number threshold is set to 2 times, and the preset fixed time is set to 30 seconds; if the number of hits is greater than the number threshold within the preset fixed time, enter step S1303; if the number of hits is less than or equal to the number threshold within the preset fixed time, enter step S1305.

[0192] Step S1303: Obtain the physical memory page corresponding to the physical address;

[0193] Specifically, if the number of hits is greater than a threshold within a preset fixed time, it means that the physical memory page corresponding to the physical address is frequently accessed in a short period of time, and then the physical memory page corresponding to the physical address is obtained.

[0194] Step S1304: moving the physical memory page corresponding to the physical address to the cache space of the flash memory device to generate a first range array in the flash memory device, and updating the second global range table to point the pointer corresponding to the logical address to the flash memory device;

[0195] Specifically, after obtaining the physical memory page corresponding to the physical address, the physical memory page corresponding to the physical address is moved to the cache space of the flash memory device to generate a first range array in the flash memory device, and the second global range table is updated to point the pointer corresponding to the logical address to the flash memory device. In an embodiment of the present application, by moving the physical memory page corresponding to the physical address to the cache space of the flash memory device, and moving the first range array in the flash memory device to the host memory, bidirectional interaction between the flash memory device and the host can be achieved.

[0196] In an embodiment of the present application, for a page moved (copied) from a flash memory device to a host, the host needs to insert a table entry corresponding to the page into a second global range table. For a page moved (copied) from the host to a flash memory device, the host needs to delete the table entry corresponding to the page from the second global range table, wherein the table entry includes the physical address of the page. For example, the flash memory device informs the host that a range array is copied into the host memory whose physical address is A, the base address of the array is B, and the length is C. At this time, the first global range table and the second global range table need to be updated synchronously. In the second global range table, an entry with a value of A should be inserted in the range of [B, B+C], and the entry corresponding to the range array should be deleted in the first global range table.

[0197] Step S1305: Do not move the physical memory page corresponding to the physical address;

[0198] Specifically, each physical address corresponds to a hit count, which refers to the number of times the physical address is accessed. Each time the physical address is accessed, the hit count will increase once. If the hit count is less than or equal to the threshold value within a preset fixed time, it means that the physical memory page corresponding to the physical address is not a page that is frequently accessed in the short term, and there is no need to move the physical memory page corresponding to the physical address.

[0199] Please refer to Fig.14 , Fig.14 It is a flowchart of a flash memory device according to an embodiment of the present application for determining whether a second version number is consistent with a first version number stored in a current cache space;

[0200] like Fig.14 As shown, the process of the flash memory device determining whether the second version number is consistent with the first version number stored in the current cache space includes:

[0201] Step S1401: the flash memory device updates the first version number corresponding to the second range array, and writes the first version number to the host memory at a preset time interval to generate a second version number in the host memory;

[0202] Specifically, the cache space of the flash memory device stores a first version number corresponding to the second range array, and the first version number is updated as the second range array changes. It can be understood that when the second range array is not generated, the first version number is an initial value, for example, the initial value can be set to 0. After the second range array is generated in the host memory, the first version number will increase by 1. Thereafter, each time the data in the second range array is modified, the first version number will automatically increase by 1. For example, when the mapping pairs in the first range array are moved to the second range array, or after the mapping pairs in the second range array are moved to the first range array, the first version number corresponding to the second range array will be updated by the flash memory device. The updating method includes adding 1 to the previous first version number. For example, if the previous first version number is 200, the first version number after the update is 201. In addition to updating the first version number in its own cache space, the flash memory device also writes the current latest first version number to the host memory at preset intervals to generate a second version number in the host memory, wherein the second version number is the same as the first version number written by the flash memory device. That is to say, in addition to maintaining its own first version number according to changes in the second range array, the flash memory device also maintains the second version number in the host memory at fixed intervals.

[0203] Step S1402: when the host sends a first read command or a second read command to the flash memory device, the host writes the second version number into the first read command or the second read command, so that the flash memory device obtains the second version number through the first read command or the second read command;

[0204] Specifically, when the host sends a first read command or a second read command to the flash memory device, the host writes the latest second version number in the current host memory into the first read command or the second read command, so that after the flash memory device receives the first read command or the second read command, it can obtain the second version number from the first read command or the second read command. For example, assuming that the latest second version number in the current host memory is 301, the host sends a first read command to the flash memory device and writes the second version number 301 into the first read command, so that the flash memory device obtains the second version number 301 through the first read command.

[0205] Step S1403: the flash memory device determines whether the second version number is consistent with the first version number stored in the current cache space;

[0206] Specifically, determine whether the second version number corresponding to the first read command or the second read command is consistent with the first version number stored in the current cache space; for example, when the host sends a first read command to the flash memory device, the flash memory device determines whether the second version number corresponding to the first read command is consistent with the first version number stored in the current cache space; when the host sends a second read command to the flash memory device, the flash memory device determines whether the second version number corresponding to the second read command is consistent with the first version number stored in the current cache space; if the second version number corresponding to the first read command or the second read command is consistent with the first version number stored in the current cache space, proceed to step S1404; if the second version number corresponding to the first read command or the second read command is inconsistent with the first version number stored in the current cache space, proceed to step S1405.

[0207] Step S1404: acquiring data corresponding to the physical address according to the first read command or the second read command;

[0208] Specifically, if the second version number corresponding to the first read command or the second read command is consistent with the first version number stored in the current cache space, it means that the data update between the host and the flash memory device is synchronized. According to the first read command or the second read command, the data corresponding to the physical address is obtained, and the obtained data is returned to the host to complete the data query operation.

[0209] Step S1405: re-query the second range array;

[0210] Specifically, if the second version number corresponding to the first read command or the second read command is inconsistent with the first version number stored in the current cache space, it means that due to the certain delay in the periodic update of the second version number in the host memory by the flash memory device, the data in the flash memory device and the host may be out of sync. When the data in the flash memory device and the host are out of sync, the flash memory device re-queries the second range array of the host.

[0211] In an embodiment of the present application, in order to maintain data consistency and prevent the host from querying old mappings, the flash memory device internally maintains the version number of the second range array in the HMB. It is understandable that the version number will be updated whenever the flash memory device performs range modification and mapping updates on the host, and the version number is periodically synchronized with the host. The host will fill the version number when the query is successful in the specified field in the first read command or the second read command. If the flash memory device finds that the version number is inconsistent when processing the read command, it will re-query the host's second range array. By detecting whether the version number corresponding to the first read command or the second read command is consistent with the version number recorded in the flash memory device, it can ensure that the data in the flash memory device and the host remain synchronized, avoiding querying the wrong physical address during the query of the physical address.

[0212] In an embodiment of the present application, a host memory query method is provided, which is applied to a host memory query system. The host memory query system includes a flash memory device and a host. The flash memory device is communicatively connected to the host, wherein the host includes a host memory, and the host memory is used to store a second global range table and a second range array. The second global range table is used to store pointers corresponding to logical address segments. The method includes: obtaining a logical address; querying the second global range table to determine whether the pointer corresponding to the logical address points to the host; if the pointer corresponding to the logical address points to the host, obtaining the physical address corresponding to the logical address through the second range array. The present application can query the physical address corresponding to the logical address in advance by utilizing the computing power of the host. This method can improve the query efficiency of the physical address.

[0213] In an embodiment of the present application, the execution subject of the host memory query method is the host memory query system, and the execution subject of the host memory processing method is the flash memory device. Specifically, the flash memory device controller controls the flash memory device to execute each method step in the above-mentioned host memory processing method. The flash memory device includes a solid-state hard disk or other storage device using flash memory as storage medium, and the flash memory device also includes a flash memory controller, wherein the flash memory device controller includes a controller of a solid-state hard disk or other storage device using flash memory as storage medium.

[0214] The embodiment of the present application also provides a computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the host memory processing method in the above embodiment, or the host memory query method. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0215] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the host memory processing method in the above embodiment, or the host memory query method. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0216] The embodiment of the present application also provides a computer program product, which includes one or more program codes, and the program codes are stored in a non-volatile computer-readable storage medium. The processor of the flash memory device reads the program code from the non-volatile computer-readable storage medium, and the processor executes the program code to complete the method for processing the host memory provided in the above embodiment, or the method steps of the method for querying the host memory.

[0217] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0218] Through the description of the above implementation methods, ordinary technicians in this field can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Ordinary technicians in this field can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0219] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for processing host memory, characterized in that: Applied to a flash memory device, the flash memory device is communicatively connected to a host, wherein the host includes a host memory, the flash memory device includes a cache space, the cache space is used to store a first global range table and a first range array, the first global range table is used to store a pointer corresponding to a logical address segment, and the first range array is used to store a mapping pair generated by random write, the method comprising: When the cache space of the flash memory device is larger than the preset memory, obtaining a first range array in the cache space; Moving the first range array in the cache space to the host memory to generate a second range array in the host memory; After the migration is completed, obtaining the logical address segment corresponding to the first range array; The first global range table is modified to change the pointer corresponding to the logical address segment from the first range array to the second range array.

2. The method according to claim 1, characterized in that: The flash memory device includes a flash memory controller, and the step of moving the first range array in the cache space to the host memory includes: Obtaining a transfer request, wherein the transfer request is used to request the host to transfer a first range array to the host memory; sending the transfer request to a transfer queue via the flash memory controller; The first range array in the cache space is moved to the host memory through the transmission queue.

3. The method according to claim 1, characterized in that The method further comprises: In the process of moving the first range array to the host memory, determining whether a write operation needs to be performed on the first range array at present; If a write operation needs to be performed on the first range array at present, the transmission flag corresponding to the current move is determined as a failure state; The transfer flag is transmitted to the host through the transfer queue, so that when the migration is completed, the host detects that the transfer flag is in a failed state, determines the migration as an invalid migration, and re-initiates a migration operation on the flash memory device.

4. A host memory query system, characterized in that: The system includes a flash memory device and a host; The flash memory device is communicatively connected to the host, the flash memory device includes a cache space, and the flash memory device is used to obtain a first range array in the cache space when the cache space is larger than a preset memory; move the first range array to the host memory to generate a second range array in the host memory; The host is communicatively connected to the flash memory device. The host is used to query the physical address corresponding to the logical address in the read request through the second range array before sending a read request to the flash memory device; generate a read command according to the physical address, and send the read command to the flash memory device so that the flash memory device returns corresponding data according to the physical address.

5. The system according to claim 4, characterized in that The flash memory device includes a flash memory controller, which is used to obtain a transfer request, wherein the transfer request is used to request the host to transfer the first range array to the host memory; send the transfer request to a transfer queue, and move the first range array in the cache space to the host memory through the transfer queue.

6. The system according to claim 4, characterized in that The host comprises a kernel module and a host memory, wherein the host memory stores a second global range table; The kernel module is used to obtain the read request; when the host queries the physical address corresponding to the logical address through the second range array, send a read command to the flash memory device, wherein the read command includes the physical address, or when the host does not query the physical address corresponding to the logical address through the second range array, send the read request to the flash memory device; The flash memory device is further configured to send a notification message to the kernel module after moving the first range array to the host memory, so that the kernel module updates the second global range table according to the notification message, wherein the notification message includes a logical address segment corresponding to the first range array; The kernel module is also used to receive the notification message, and update the second global range table according to the notification message, so as to change the pointer corresponding to the logical address segment in the second global range table from the first range array to the second range array.

7. The system according to claim 6, characterized in that The host also includes a mapping module and a main control processor; The mapping module is used to establish an internal address conversion mapping relationship between the internal address of the flash memory device and the bus address of the host; according to the internal address conversion mapping relationship, the offset address of the logical address in the second range array is converted into a bus address; The master control processor is used to access the second range array according to the bus address to obtain the physical address corresponding to the logical address.

8. A method for querying host memory, characterized in that: A query system applied to a host memory, the query system of the host memory comprising a flash memory device and a host, the flash memory device being communicatively connected to the host, wherein the host comprises a host memory, the host memory being used to store a second global range table and a second range array, the second global range table being used to store a pointer corresponding to a logical address segment, the method comprising: Get the logical address; Query the second global range table to determine whether the pointer corresponding to the logical address points to the host; If the pointer corresponding to the logical address points to the host, the physical address corresponding to the logical address is obtained through the second range array.

9. The method according to claim 8, characterized in that The obtaining of the logical address comprises: Get read request; According to the read request, obtaining a starting address in the read request; Obtaining the starting address of the namespace and the logical page size of the flash memory device; The logical address is calculated according to the starting address in the read request, the starting address of the namespace, and the logical page size of the flash memory device.

10. The method according to claim 9, characterized in that The acquiring the physical address corresponding to the logical address through the second range array includes: Determining whether an internal address conversion mapping relationship is established between the internal address of the flash memory device and the bus address of the host; If an internal address conversion mapping relationship has been established between the internal address of the flash memory device and the bus address of the host, converting the offset address of the logical address into a bus address according to the internal address conversion mapping relationship; The second range array is accessed according to the bus address to obtain a physical address corresponding to the logical address.

11. The method according to claim 9, characterized in that The method further comprises: Determine whether the physical address corresponding to the logical address is found in the second range array; If the physical address corresponding to the logical address is not found in the second range array, the read request is sent to the flash memory device, so that the flash memory device queries the physical address corresponding to the logical address according to the read request.

12. The method according to claim 11, characterized in that The method further comprises: If the physical address corresponding to the logical address is found in the second range array, determining whether the physical address is a continuous physical address; If the physical address is a continuous physical address, generating a first read command according to the physical address, and sending the first read command to the flash memory device; If the physical address is not a continuous physical address, the read request is disassembled into multiple second read commands, and the second read commands are sent to the flash memory device, wherein each second read command corresponds to the same number of logical addresses and physical addresses corresponding to the logical addresses.

13. The method according to claim 12, characterized in that The method further comprises: When the physical address corresponding to the logical address is found in the second range array, a hit count is recorded; Determine whether the hit count is greater than a count threshold within a preset fixed time; If the hit count is greater than the count threshold, obtaining a physical memory page corresponding to the physical address; The physical memory page corresponding to the physical address is moved to the cache space of the flash memory device to generate a first range array in the flash memory device, and the second global range table is updated to point the pointer corresponding to the logical address to the flash memory device.

14. The method according to claim 13, characterized in that The first version number corresponding to the second range array is stored in the cache space of the flash memory device. After updating the second global range table, the method further includes: The flash memory device updates the first version number corresponding to the second range array, and writes the first version number to the host memory at a preset time interval to generate a second version number in the host memory; When the host sends a first read command or a second read command to the flash memory device, the host writes the second version number into the first read command or the second read command, so that the flash memory device obtains the second version number through the first read command or the second read command; The flash memory device determines whether the second version number is consistent with the first version number stored in the current cache space; If the second version number is inconsistent with the first version number stored in the current cache space, the second range array is queried again.

15. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer storage medium stores a computer program or instruction. When the computer program or instruction is executed, the host memory processing method described in any one of claims 1 to 3, or the host memory query method described in any one of 8 to 14 is implemented.

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