Measurement system synchronization method, device and system based on feedback of one group of hardware signals

Abstract

The invention discloses a measurement system synchronization method, device and system based on feedback of a group of hardware signals, and belongs to the field of tests.The method comprises the steps that for a system architecture of an upper computer and a plurality of lower computers, feedback of configuration states and measurement states of the lower computers is achieved through hardware signals, and the synchronous trigger module is used for generating a synchronous trigger signal and / or starting a next round of measurement period, so that the synchronization of function board card levels among the lower computers and the system-level synchronization of the lower computers and the upper computer are realized. According to the invention, a group of hardware feedback signals is adopted to realize the feedback of the configuration state and the measurement state of the lower computer measurement unit with low delay and low protocol stack complexity, the board card level synchronization among the lower computers is realized, and the system level synchronization of the lower computers and the upper computer is realized.

Description

Technical Field

[0001] The present invention relates to the field of testing, and more specifically, to a measurement system synchronization method, device and system based on a set of hardware signal feedback. Background Art

[0002] Modern measurement systems, including automatic test equipment (such as chip testers) and radar systems, often use a system architecture of host computer-high-speed bus-slave computer, such as Figure 1 As shown. Specifically, the host computer (computer system) generates instructions according to the test program; the high-speed bus (such as PCIe, Ethernet, Aurora bus, etc.) transmits the instructions and measurement data, and the high-speed bus includes routing and control units such as the master control; the logic chip or CPU in the lower computer is responsible for parsing the measurement instructions, and the measurement unit (such as various hardware circuits, AD / DA, etc.) is responsible for execution. When there are multiple measurement units in the test system, in order to ensure the synchronization of each measurement unit, after each measurement unit completes signal parsing and successfully configures, it is necessary to generate a special synchronization trigger signal (trigger) on the bus (generally the master control) to enable the measurement unit. After receiving the synchronization trigger signal, each measurement unit starts execution according to the configuration data sent by the bus. When each measurement unit completes the measurement, the host computer starts the next round of configuration-measurement cycle.

[0003] There are currently two main ways for the test system to generate a synchronous trigger signal and start the next round of measurement cycle. The first method uses the time estimation method, that is, after the upper computer sends the measurement instructions to each lower computer, it waits for an estimated time interval, and then sends a synchronous enable command to the main control. After the main control parses this command, it sends a synchronous enable signal to each measurement unit. The upper computer waits for an estimated time interval before starting the next measurement cycle. The second method uses the lower computer to report an ack message through the high-speed bus, that is, each lower computer reports a message to the upper computer through the high-speed bus after completing the configuration and measurement. The upper computer decides to send a synchronous trigger generation command and start the next round of measurement cycle based on the received message.

[0004] It should be noted that at the moment when the master generates the synchronization enable signal, all slave computers must complete the parsing of the configuration commands sent by the upper computer, so as to ensure that all slave computers start the measurement process synchronously. When the upper computer configures the measurement mode of the lower computer through the high-speed bus, due to the different configuration contents of each measurement unit, there may even be a situation where the processor of the lower computer is occupied, resulting in different times for each measurement unit to complete the bus instruction parsing, and the difference may even be very large. In order to ensure the smooth progress of the measurement process, when using the time estimation method, this estimated waiting time needs to be set large enough to minimize the possibility that some lower computers have not completed the configuration, which leads to reduced measurement efficiency and poor robustness of the test system.

[0005] When the message reporting method is adopted, the problem of estimated time can be avoided, but all the lower computers need to report status information through the high-speed bus after configuration and measurement are completed. Since the messages reported by each lower computer are passed serially in the high-speed bus, the delay from the completion of the lower computer configuration or measurement to the completion of the upper computer message parsing will be large, especially when there are more lower computer measurement units, which slows down the measurement efficiency. From the perspective of the protocol layer, the ack message reporting on the high-speed bus is an integral part of the handshake communication between the upper computer and the lower computer. In order to improve the low latency of the system, from the time the upper computer unloads the command to the time the ack message of the lower computer is received, the upper computer resources are occupied to process the protocol stack and cannot process other transactions. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a measurement system synchronization method, device and system based on a set of hardware signal feedback. A set of hardware feedback signals is used to realize the feedback of the configuration status and measurement status of the lower computer measurement unit with low latency and low protocol stack complexity, realize the board-level synchronization between the lower computers, and realize the system-level synchronization between the lower computer and the upper computer.

[0007] The object of the present invention is achieved through the following solutions:

[0008] A measurement system synchronization method based on a set of hardware signal feedback comprises the following steps:

[0009] For the system architecture of a host computer and multiple slave computers, hardware signals are used to implement feedback on the configuration status and measurement status of the slave computers, which are used to generate synchronization trigger signals and / or start the next round of measurement cycle, thereby achieving functional board-level synchronization between the slave computers and system-level synchronization between the slave computers and the host computer.

[0010] Furthermore, the hardware signal is specifically a group of hardware signals.

[0011] Furthermore, the set of hardware signals is used as the input signal of the master control and the output signal of each slave computer to feedback the configuration and measurement status of the slave computer; and then through this set of hardware signals and the control commands on the high-speed bus, the state feedback of the slave computer instruction parsing and the measurement operation process is realized in a closed loop, thereby avoiding the generation of a synchronous trigger signal and / or the estimation of uncertain time when starting the next round of measurement cycle.

[0012] Furthermore, by adopting hardware signal feedback, there is no need to report messages serially via a high-speed bus during the process of generating a synchronous trigger signal.

[0013] Furthermore, the use of hardware signals to implement feedback of the configuration state and measurement state of the lower computer specifically includes the following sub-steps:

[0014] The feedback of the configuration state and measurement state of the lower computer is realized by a resistor pull-up or pull-down design. The resistor pull-up or pull-down design includes two feedback signals, s1 and s2, which are both connected to the input of the master control and the output of each lower computer. Both signals are pulled up or down by resistors.

[0015] Furthermore, when a resistor is used for pull-up, the output of the lower computer has two states: low level "0" and high impedance "z". The initial state is high impedance. At this time, the following workflow is included:

[0016] Step (a), before sending configuration data to each slave computer, the upper computer first sends a packet of "START" instructions;

[0017] Step (b), when each lower computer parses the start "START" instruction through the logic circuit, it pulls down the s1 and s2 signals;

[0018] Step (c), the host computer sends configuration information;

[0019] Step (d), the host computer sends an end "END" instruction;

[0020] Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z";

[0021] Step (f), when all the slave computers output "z", the master control will detect the rising edge of s1, and then the master control will send a synchronization trigger signal to the slave computers;

[0022] Step (g), each slave computer starts measuring;

[0023] Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z";

[0024] Step (i), when all host computers release s2, the master will detect the rising edge of s2, and then send a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

[0025] Furthermore, when the resistor pull-down design is adopted, the output state of each slave computer s1, s2 is high impedance state "z" and high level "1". At this time, the following workflow is included:

[0026] When the resistor pull-down design is adopted, the output state of each slave computer s1 and s2 is high impedance state "z" and high level "1". At this time, the following workflow is included:

[0027] Step (a), before sending configuration data to each slave computer, the upper computer first sends a packet of "START" instructions;

[0028] Step (b), when each lower computer parses the start "START" instruction through the logic circuit, it pulls up the s1 and s2 signals;

[0029] Step (c), the host computer sends configuration information;

[0030] Step (d), the host computer sends an end "END" instruction;

[0031] Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z";

[0032] Step (f), when all the slave computers output "z", the master control will detect the falling edge of s1, and then the master control will send a synchronization trigger signal to the slave computers;

[0033] Step (g), each slave computer starts measuring;

[0034] Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z";

[0035] Step (i), when all host computers release s2, the master will detect the falling edge of s2, and then the master sends a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

[0036] Furthermore, for the s1 and s2 signals, the outputs of the lower computers are in an “AND” relationship.

[0037] Furthermore, for the s1 and s2 signals, the outputs of the lower computers are in an "or" relationship.

[0038] A measurement system synchronization device based on a set of hardware signal feedback comprises a measurement unit based on a set of hardware signal feedback, and is used to execute any of the above methods.

[0039] A measurement system synchronization system based on a set of hardware signal feedback comprises the device as described above.

[0040] The beneficial effects of the present invention include:

[0041] In the present invention, through signal feedback, the measurement system can feedback the status of the lower computer command parsing and measurement process with low latency, forming a closed-loop control, realizing the synchronization of the functional board level and the system-level synchronization of the upper computer and the lower computer, avoiding the estimation of an uncertain time when generating a synchronization trigger signal and starting the next round of measurement cycle, and because of the use of hardware signal feedback, there is no need to report messages serially through a high-speed bus during the generation of the synchronization trigger signal, the feedback delay is low and does not occupy the upper computer resources, thereby improving the measurement efficiency and the robustness of the system. In addition, the embodiment of the present invention only includes a small amount of hardware feedback signals (two feedback signals s1 and s2 in the example), the circuit design is simple, and it is easy to implement and promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0043] Figure 1 It is the system architecture of upper computer-high-speed bus-lower computer;

[0044] Figure 2 A synchronous triggering scheme based on pull-up signal feedback in an embodiment of the present invention;

[0045] Figure 3 A synchronous triggering scheme based on pull-down signal feedback in an embodiment of the present invention;

[0046] Figure 4a It is the operation process of the measurement system based on hardware signal feedback in an embodiment of the present invention;

[0047] Figure 4b It is the operation process of the measurement system based on hardware signal feedback in an embodiment of the present invention;

[0048] Figure 5 It is a timing diagram of s1 and s2 signals based on the pull-up signal feedback design in an embodiment of the present invention;

[0049] Figure 6 s1 and s2 signal timing diagram based on pull-down signal feedback design in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0051] In view of the current situation in the background, especially the problems of high delay and occupation of host computer resources caused by the need to estimate the time or serially report status messages when generating a synchronous trigger signal in the two existing technical solutions, the present invention conceives to use a group of hardware signals to realize the status feedback of the lower computer, aiming to solve the following problems: 1) functional board-level synchronization of each lower computer in the test system and system-level synchronization of each lower computer with the upper computer; 2) reducing the delay of the lower computer status feedback when generating a synchronous trigger signal and starting the next round of measurement cycle, and reducing the occupation of the host computer resources in this process.

[0052] In a further conceptual scheme, the present invention proposes a method for realizing low-latency feedback of the status of the slave computers based on a set of hardware signals when there are multiple slave computers (functional boards) in the measurement system, which is used to generate a synchronization trigger signal and start the next round of measurement cycle, thereby realizing the synchronization of the functional board level between the slave computers and the system-level synchronization between the slave computers and the upper computer.

[0053] In the specific design, a set of hardware signals is included as the input signal of the master control and the output signal of each slave computer, which is used to feedback the configuration and measurement status of the slave computer. Through this set of hardware signals and the control commands on the high-speed bus, the state feedback of the slave computer instruction parsing and measurement operation process is realized in a closed loop, avoiding the estimation of uncertain time when generating a synchronous trigger signal or starting the next round of measurement cycle. In addition, due to the use of hardware signal feedback, there is no need to report messages serially through the high-speed bus during the generation of the synchronous trigger signal, which reduces the feedback delay and does not occupy the resources of the upper computer, thereby improving the measurement efficiency and system robustness.

[0054] In a more specific implementation, the present invention uses the resistor pull-up or pull-down design as an example to illustrate the working principle of this synchronous measurement method based on hardware signal feedback, but the implementation of the present invention is not limited to the design of this pull-up or pull-down signal. The resistor pull-up or pull-down design includes two feedback signals, s1 and s2, which are connected to the input of the master control and the output of each slave computer. Both signals are pulled up by resistors ( Figure 2 ) or pull down ( Figure 3). When using a resistor pull-up, the output of the lower computer has two states: "0" (low level) and "z" (high configuration), and the initial state is high impedance. The specific workflow of the feedback measurement system based on hardware signals is as follows (such as Figure 4a to Figure 4b shown): Figure 4a The host computer sends a packet of "START" command before sending configuration data to each slave computer; Figure 4b When each lower computer analyzes the "START" instruction through the logic circuit (T1 moment, such as Figure 5 As shown), pull down the s1 and s2 signals; (c) the upper computer sends configuration information; (d) the upper computer sends the "END" instruction; (e) each lower computer releases the s1 signal when parsing the "END" instruction, and the s1 output of the lower computer is "z". (f) When all the lower computers output "z", the master will detect the rising edge of s1 (T2 moment), and then the master sends a synchronous trigger signal (trigger) to the lower computer (T3 moment); (g) each lower computer starts measurement; (h) after the lower computer completes the measurement, it releases s2 and outputs "z". (i) when all the upper computers release s2, the master will detect the rising edge of s2 (T4 moment), and then the master sends a "DONE" message to the upper computer, indicating that this round of configuration-measurement process is over and the next round of configuration-measurement process can be carried out.

[0055] For the s1 and s2 signals, the outputs of each lower computer are in an "AND" relationship. Therefore, when any lower computer outputs a low level, the signal is low. When the outputs of all lower computers are in a high impedance state, the s1 and s2 signals are high due to the pull-up resistors. Therefore, in process (b), when any lower computer completes the parsing of the "START" instruction, s1 and s2 will be pulled low; in process (f), when all lower computers complete the parsing of the "END" instruction, s1 will be pulled high; in process (i), when all lower computers complete the measurement operation, s2 will be pulled high.

[0056] When the s1 and s2 signals are designed with a pull-down, the output states of the s1 and s2 of each lower computer are "z" and "1". When this design is adopted, the relationship between the s1 and s2 signals on each lower computer is "or". When one lower computer outputs "1", the signal line will be pulled high. When all lower computers release the s1 and s2 signals and output high impedance, they will return to a low level due to the pull-down resistor. This can also achieve the same feedback effect as the pull-up design: in process (b), when the lower computer parses the "START" command, s1 and s2 are pulled high (such as Figure 6 As shown); in process (f), the lower computer releases s1, and s1 returns to the default low level; in process (i), the lower computer releases s2, and s2 returns to the default low level.

[0057] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0058] Example 1

[0059] A measurement system synchronization method based on a set of hardware signal feedback comprises the following steps:

[0060] For the system architecture of a host computer and multiple slave computers, hardware signals are used to implement feedback on the configuration status and measurement status of the slave computers, which are used to generate synchronization trigger signals and / or start the next round of measurement cycle, thereby achieving functional board-level synchronization between the slave computers and system-level synchronization between the slave computers and the host computer.

[0061] Specifically, the hardware signal is a set of hardware signals. The set of hardware signals is used as the input signal of the master control and the output signal of each slave computer to feedback the configuration and measurement status of the slave computer; and then through this set of hardware signals and the control command on the high-speed bus, the state feedback of the slave computer instruction parsing and the measurement operation process is realized in a closed loop, thereby avoiding the generation of a synchronous trigger signal and / or the estimation of uncertain time when starting the next round of measurement cycle.

[0062] Specifically, by adopting hardware signal feedback, there is no need to report messages serially via a high-speed bus during the process of generating a synchronous trigger signal.

[0063] Example 2

[0064] On the basis of Example 1, the use of hardware signals to implement feedback of the configuration state and measurement state of the lower computer specifically includes the following sub-steps:

[0065] The feedback of the configuration state and measurement state of the lower computer is realized by a resistor pull-up or pull-down design. The resistor pull-up or pull-down design includes two feedback signals, s1 and s2, which are both connected to the input of the master control and the output of each lower computer. Both signals are pulled up or down by resistors.

[0066] When using resistor pull-up, the output of the lower computer has two states: low level "0" and high impedance "z". The initial state is high impedance. At this time, the following workflow is included:

[0067] Step (a), before sending configuration data to each slave computer, the upper computer first sends a packet of "START" instructions;

[0068] Step (b), when each lower computer parses the start "START" instruction through the logic circuit, it pulls down the s1 and s2 signals;

[0069] Step (c), the host computer sends configuration information;

[0070] Step (d), the host computer sends an end "END" instruction;

[0071] Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z";

[0072] Step (f), when all the slave computers output "z", the master control will detect the rising edge of s1, and then the master control will send a synchronization trigger signal to the slave computers;

[0073] Step (g), each slave computer starts measuring;

[0074] Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z";

[0075] Step (i), when all host computers release s2, the master will detect the rising edge of s2, and then send a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

[0076] For the s1 and s2 signals, the outputs of each lower computer are in an "AND" relationship.

[0077] Example 3

[0078] On the basis of Example 2, when a resistor pull-down design is adopted, the output states of the slave computers s1 and s2 are high impedance state "z" and high level "1". At this time, the following workflow is included:

[0079] Step (a), before sending configuration data to each slave computer, the upper computer first sends a packet of "START" instructions;

[0080] Step (b), when each lower computer parses the start "START" instruction through the logic circuit, it pulls up the s1 and s2 signals;

[0081] Step (c), the host computer sends configuration information;

[0082] Step (d), the host computer sends an end "END" instruction;

[0083] Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z";

[0084] Step (f), when all the slave computers output "z", the master control will detect the falling edge of s1, and then the master control will send a synchronization trigger signal to the slave computers;

[0085] Step (g), each slave computer starts measuring;

[0086] Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z";

[0087] Step (i), when all host computers release s2, the master will detect the falling edge of s2, and then the master sends a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

[0088] For the s1 and s2 signals, the outputs of each lower computer are in an "or" relationship.

[0089] In other implementations, the present invention may also provide a measurement system synchronization device based on a set of hardware signal feedback, including a measurement unit based on a set of hardware signal feedback, used to execute any one of the methods in Examples 1 to 3.

[0090] In other implementations, the present invention may also provide a measurement system synchronization system based on a set of hardware signal feedback, including the device described in the above embodiment.

[0091] The above description is only the technical principle and preferred embodiment used in the present invention. It will be understood by those skilled in the art that the present invention is not limited to the specific embodiments described herein. It is possible for those skilled in the art to make various obvious changes, adjustments and substitutions without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the principles and concepts of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

[0092] The units involved in the embodiments of the present invention are based on hardware implementation, and some functions can be implemented by software. The units described can also be set in a processor. Among them, the names of these units do not constitute a limitation on the units themselves under certain circumstances. The embodiments of the present invention can provide a corresponding computer program product or a computer program, and the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a corresponding hardware device. The corresponding hardware device reads and executes the computer instruction, so that the hardware device executes the method provided in the above-mentioned various optional implementations.

Claims

1. A measurement system synchronization method based on a set of hardware signal feedback, characterized in that: The following steps are involved: For the system architecture of a host computer and multiple slave computers, hardware signals are used to implement feedback on the configuration status and measurement status of the slave computers, which are used to generate synchronization trigger signals and / or start the next round of measurement cycle, thereby achieving functional board-level synchronization between the slave computers and system-level synchronization between the slave computers and the host computer.

2. The measurement system synchronization method based on a set of hardware signal feedback according to claim 1, characterized in that: The hardware signal is specifically a group of hardware signals.

3. The measurement system synchronization method based on a set of hardware signal feedback according to claim 2, characterized in that: The set of hardware signals is used as the input signal of the master control and the output signal of each slave computer to feedback the configuration and measurement status of the slave computer; and then through this set of hardware signals and the control commands on the high-speed bus, the state feedback of the slave computer instruction parsing and the measurement operation process is realized in a closed loop, thereby avoiding the generation of a synchronous trigger signal and / or the estimation of uncertain time when starting the next round of measurement cycle.

4. The measurement system synchronization method based on a set of hardware signal feedback according to claim 1, characterized in that: By adopting hardware signal feedback, there is no need to report messages serially via a high-speed bus during the process of generating a synchronous trigger signal.

5. The measurement system synchronization method based on a set of hardware signal feedback according to claim 1, characterized in that: The use of hardware signals to implement feedback of the configuration state and measurement state of the lower computer specifically includes the following sub-steps: The feedback of the configuration state and measurement state of the lower computer is realized by a resistor pull-up or pull-down design. The resistor pull-up or pull-down design includes two feedback signals, s1 and s2, which are both connected to the input of the master control and the output of each lower computer. Both signals are pulled up or down by resistors.

6. The measurement system synchronization method based on a set of hardware signal feedback according to claim 5, characterized in that: When using resistor pull-up, the output of the lower computer has two states: low level "0" and high impedance "z". The initial state is high impedance. At this time, the following workflow is included: Step (a), before sending configuration data to each slave computer, the host computer first sends a packet of "START" instructions; Step (b), when each lower computer parses the "START" instruction through the logic circuit, it pulls down the s1 and s2 signals; Step (c), the host computer sends configuration information; Step (d), the host computer sends an "END" instruction; Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z"; Step (f), when all the slave computers output "z", the master control will detect the rising edge of s1, and then the master control will send a synchronization trigger signal to the slave computers; Step (g), each slave computer starts measuring; Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z"; Step (i), when all host computers release s2, the master will detect the rising edge of s2, and then send a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

7. The measurement system synchronization method based on a set of hardware signal feedback according to claim 5, characterized in that: When the resistor pull-down design is adopted, the output state of each slave computer s1 and s2 is high impedance state "z" and high level "1". At this time, the following workflow is included: Step (a), before sending configuration data to each slave computer, the host computer first sends a packet of "START" instructions; Step (b), when each lower computer parses the "START" instruction through the logic circuit, it pulls up the s1 and s2 signals; Step (c), the host computer sends configuration information; Step (d), the host computer sends an "END" instruction; Step (e), each lower computer releases the s1 signal when parsing the end "END" instruction, and the s1 output of the lower computer is "z"; Step (f), when all the slave computers output "z", the master control will detect the falling edge of s1, and then the master control will send a synchronization trigger signal to the slave computers; Step (g), each slave computer starts measuring; Step (h), after the lower computer completes the measurement, it releases s2 and outputs "z"; Step (i), when all host computers release s2, the master will detect the falling edge of s2, and then send a "DONE" message to the host computer, indicating that the current round of configuration and measurement process is completed and the next round of configuration and measurement process is carried out.

8. The measurement system synchronization method based on a set of hardware signal feedback according to claim 6, characterized in that: For the s1 and s2 signals, the outputs of each lower computer are in an "AND" relationship.

9. The measurement system synchronization method based on a set of hardware signal feedback according to claim 7, characterized in that: For the s1 and s2 signals, the outputs of each lower computer are in an "or" relationship.

10. A measurement system synchronization device based on a set of hardware signal feedback, characterized in that: The invention comprises a measurement unit based on a set of hardware signal feedback, and is used to execute the method according to any one of claims 1 to 9.

11. A measurement system synchronization system based on a set of hardware signal feedback, characterized in that: Comprising the device according to claim 10.

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