A communication method and system for a field programmable logic device

Abstract

This application provides a communication method, system, computer-readable storage medium, and electronic device for field-programmable logic devices (FPGAs). The method includes: a FPGA host receiving control commands sent by a host computer; a first processor on the FPGA host controlling a first intellectual property core to send the control commands to a second processor on the FPGA slave via an inter-chip bus; the second processor on the FPGA slave processing the control commands and obtaining the processing result, and sending the processing result back to the FPGA host via a link layer protocol based on the second intellectual property core; and the FPGA host storing the processing result in memory or uploading it to the host computer. This application can improve the data transmission efficiency between the FPGA host and the FPGA slave, and simplify the control process of the FPGA.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular to a communication method, system, computer-readable storage medium, and electronic device using a field-programmable logic device. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) have evolved from peripheral devices in electronic design to the core of digital systems in recent years. Simultaneously, various application scenarios have raised demands for higher logic resources, larger data interaction requirements, higher transmission rates, and lower latency. The logic resources of a single FPGA chip are gradually becoming insufficient to meet these requirements. To satisfy real-time, high-speed, and highly complex digital signal processing, two or even multiple FPGAs may be needed for collaborative processing.

[0003] Interconnection and communication between multiple field-programmable logic device (FPGA) development boards primarily employs Low-Voltage Differential Signaling (LVDS). LVDS is typically used for parallel data transmission at data rates of 155MHz, 622MHz, or 1.25GHz. This approach suffers from excessively low transmission speeds. Traditional parallel transmission methods attempt to increase transmission rates by increasing clock frequency and data bit width, but this leads to problems such as difficult system layout and routing, clock and data signal offsets, difficulties in interconnecting multiple endpoints, and poor scalability. Summary of the Invention

[0004] The purpose of this application is to provide a communication method, system, computer-readable storage medium, and electronic device for field-programmable logic devices, which processes control instructions through a first intellectual property core and improves inter-board communication efficiency through a link layer of a second intellectual property core.

[0005] To address the aforementioned technical problems, this application provides a communication method for field-programmable logic devices, the specific technical solution of which is as follows:

[0006] The field-programmable logic device (FPGA) host receives control commands sent by the host computer.

[0007] The first processor on the host of the field-programmable logic device (FPGA) controls the first intellectual property core to send the control commands to the second processor on the slave of the FPGA via the inter-chip bus.

[0008] The second processor on the slave of the field-programmable logic device processes the control instructions and obtains the processing result, and sends the processing result to the master of the field-programmable logic device through a link layer protocol based on the second intellectual property core;

[0009] The field-programmable logic device host stores the processing result in memory or uploads it to the host computer.

[0010] Before the field-programmable logic device (FPGA) host receives control commands from the host computer, it also includes:

[0011] A hardware platform project is established, in which the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module; the data control module is used for data communication through the high-speed transceiver.

[0012] The method further includes:

[0013] An embedded software project is established. In the embedded software project, electrical consistency checks are performed on the high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, and interface controller. Pin configuration is performed, bit stream files are generated, and hardware platform files are exported.

[0014] The method further includes:

[0015] The first high-speed transceiver on the host of the field-programmable logic device (FPGA) and the second high-speed transceiver on the slave of the FPGA are connected by optical fiber.

[0016] The processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave are connected via a general-purpose input / output interface.

[0017] The system further includes, after connecting the processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave via a general-purpose input / output interface:

[0018] The host computer is connected to the Ethernet controller of the field-programmable logic device (FPGA) host. After the FPGA host is powered on, the first intellectual property core is initialized.

[0019] After generating the bitstream file and exporting the hardware platform file, the process also includes:

[0020] Write the host program corresponding to the first intellectual property core into the host of the field-programmable logic device;

[0021] Write the slave program corresponding to the first intellectual property core into the slave device of the field programmable logic device.

[0022] Wherein, if the control instruction is a reset instruction, the second processor on the field-programmable logic device slave processes the control instruction and obtains the processing result including:

[0023] The second processor on the field-programmable logic device slave controls the first intellectual property core to reset according to the reset instruction;

[0024] The first intellectual property core controls the phase-locked loop of the second high-speed transceiver to reset, and cancels the reset of the first intellectual property core;

[0025] The processor on the second board of the field-programmable logic device (FPGA) slave sends a reset completion signal to the processor on the first board of the FPGA master.

[0026] This application also provides a communication system for field-programmable logic devices, including:

[0027] The receiving module is used to receive control commands sent by the host computer.

[0028] The instruction sending module is used to control the first intellectual property core to send the control instructions to the second processor on the field-programmable logic device slave via the inter-chip bus;

[0029] The result receiving module is used to receive the processing result sent by the field-programmable logic device slave device through a link layer protocol based on the second intellectual property core after the second processor on the field-programmable logic device slave device processes the control instruction and obtains the processing result;

[0030] The communication result processing module is used by the field-programmable logic device host to store the processing result in memory or upload it to the host computer.

[0031] The communication system further includes:

[0032] The hardware configuration module is used to establish a hardware platform project. In the hardware platform project, the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module. The data control module is used for data communication through the high-speed transceiver.

[0033] The communication system further includes:

[0034] The software configuration module is used to establish an embedded software project. In the embedded software project, electrical consistency checks are performed on the high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, and interface controller. Pin configuration is also performed, bit stream files are generated, and hardware platform files are exported.

[0035] The communication system further includes:

[0036] The host computer configuration module is used to connect the first high-speed transceiver on the host of the field-programmable logic device and the second high-speed transceiver on the slave of the field-programmable logic device via optical fiber.

[0037] The processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave are connected via a general-purpose input / output interface.

[0038] The communication system further includes an initialization module for connecting the host computer to the Ethernet controller of the field-programmable logic device host, and initializing the first intellectual property core after the field-programmable logic device host is powered on.

[0039] The communication system also includes

[0040] The intellectual property core configuration module is used to generate a bitstream file and export a hardware platform file, then write the host program corresponding to the first intellectual property core to the host of the field-programmable logic device (FPGA); and write the slave program corresponding to the first intellectual property core to the slave of the FPGA.

[0041] If the control command is a reset command, it further includes:

[0042] The slave processing module, located on the slave device of the field-programmable logic device, is used to control the first intellectual property core to reset according to the reset instruction through the second processor; the first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core; and controls the processor on the second board to send a reset completion signal to the processor on the first board on the host of the field-programmable logic device.

[0043] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0044] This application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described above when it invokes the computer program in the memory.

[0045] This application provides a communication method for a field-programmable logic device (FPGA), comprising: a FPGA host receiving a control command sent by a host computer; a first processor on the FPGA host controlling a first intellectual property core to send the control command to a second processor on the FPGA slave via an inter-chip bus; the second processor on the FPGA slave processing the control command and obtaining a processing result, and sending the processing result to the FPGA host via a link layer protocol based on the second intellectual property core; and the FPGA host storing the processing result in memory or uploading it to the host computer.

[0046] This application, by setting up a first intellectual property core and a second intellectual property core, enables the field-programmable logic device (FPGA) master to quickly process control commands and rapidly distribute them to the FPGA slave via the second intellectual property core, which includes a link layer protocol, thereby improving the data transmission efficiency between the FPGA master and the FPGA slave. Simultaneously, through the connection between the FPGA master and the FPGA slave, the host computer only needs to control the FPGA master to synchronously operate the FPGA slave, simplifying the FPGA control process and improving control efficiency in one-to-many application scenarios.

[0047] This application also provides a communication system, a computer-readable storage medium, and an electronic device based on a field-programmable logic device, which have the aforementioned beneficial effects, and will not be elaborated here. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0049] Figure 1 A flowchart illustrating a communication method for a field-programmable logic device provided in an embodiment of this application;

[0050] Figure 2 This is a schematic diagram of the hardware structure provided in the embodiments of this application;

[0051] Figure 3 A schematic diagram of the reset operation process of a field-programmable logic device provided in an embodiment of this application;

[0052] Figure 4 This is a schematic diagram of a communication system structure for a field-programmable logic device provided in an embodiment of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] Please refer to Figure 1 , Figure 1 A flowchart illustrating a communication method for a field-programmable logic device provided in this application embodiment, the method comprising:

[0055] S101: The field-programmable logic device (FPGA) host receives control commands sent by the host computer.

[0056] S102: The first processor on the host of the field-programmable logic device (FPGA) controls the first intellectual property core to send the control command to the second processor on the slave of the FPGA via the inter-chip bus;

[0057] S103: The second processor on the slave of the field-programmable logic device processes the control command and obtains the processing result, and sends the processing result to the master of the field-programmable logic device through the link layer protocol based on the second intellectual property core;

[0058] S104: The field-programmable logic device host stores the processing result in memory or uploads it to the host computer.

[0059] The specific application of the host computer is not limited here, and it can be any device that can issue control commands to the user, such as terminal devices. Furthermore, the host computer only needs to establish a communication connection with the field-programmable logic device (FPGA) host.

[0060] There is no limitation on the type of control instructions issued by the host computer. These instructions can include control instructions sent to the master, slave, or both of the field-programmable logic devices (FPGAs), including but not limited to data read, write, delete, and modify instructions, as well as reset, initialization, or resetting instructions.

[0061] After receiving control commands, the FPGA master device uses its first processor to control the first intellectual property core to send the commands to the second processor on the FPGA slave device via the inter-chip bus. Typically, the FPGA master and slave devices can use the same or different processors. For example, the MicroBlaze embedded soft core can be used, which is a reduced instruction set processor soft core that can be embedded in the FPGA, offering advantages such as high speed, low resource consumption, and high configurability.

[0062] The inter-chip bus can be an AXI (Advanced eXtensible Interface) bus, an on-chip bus designed for high performance, high bandwidth, and low latency. Both the first and second intellectual property cores are intellectual property cores (IP cores), which are reusable modules in the form of logic units or chip designs. There are no restrictions on which first or second IP core is used, but the first IP core is used to implement bridging based on the inter-chip bus, connecting two devices via the AXI bus. Its bridging function also allows all AXI channels to operate independently by sending and receiving data and control information for each channel, conforming to the "valid-ready" handshake for each AXI channel. The second IP core is used to accelerate data transmission between FPGA master and FPGA slave devices. For example, Chip2chip can be used as the first IP core, and Aurora64b / 66b as the second IP core. It is a scalable, lightweight link layer protocol for high-speed serial communication, typically used in applications requiring low-cost, high-data-rate, scalable, and flexible serial data channels. Using the Aurora protocol as the transmission protocol solves the problem of high-speed signal communication between multiple reconfigurable in-memory computing chips. Furthermore, Aurora is an open, scalable, small, link-layer protocol that can be used for point-to-point serial data transmission, eliminating the resource inefficiencies of other serial protocols. It can be implemented in any silicon device / technology, including reconfigurable in-memory computing chips, and can use one or more high-speed serial channels. If Chip2chip and Aurora IP cores are used as the first and second intellectual property cores respectively, a high-speed transceiver GT (gimbit transceiver) can be used for data transmission and reception, achieving a communication line rate of up to 25Gb / s. Furthermore, an embedded MicroBlaze soft-core processor and related peripherals can be used, allowing users to flexibly configure the system according to their needs.

[0063] The field-programmable logic device (FPGA) master unit can store the processing results obtained from the FPGA slave unit in its own memory or upload them to the host computer. The specific processing method depends on the type of control instruction. If the host computer needs the processing result corresponding to the control instruction, then the result needs to be uploaded to the host computer.

[0064] This application, by setting up a first intellectual property core and a second intellectual property core, enables the field-programmable logic device (FPGA) master to quickly process control commands and rapidly distribute them to the FPGA slave via the second intellectual property core, which includes a link layer protocol, thereby improving the data transmission efficiency between the FPGA master and the FPGA slave. Simultaneously, through the connection between the FPGA master and the FPGA slave, the host computer only needs to control the FPGA master to synchronously operate the FPGA slave, simplifying the FPGA control process and improving control efficiency in one-to-many application scenarios.

[0065] The following describes the construction and configuration process between the field-programmable logic device (FPGA) master and the FPGA slave in this application:

[0066] A hardware platform project is established, in which the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, along with a high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, interface controller, and data control module. The data control module is used for data communication through the high-speed transceiver. Specifically, the hardware platform project can be established using Vivado software, adding Chip2chip as the first intellectual property core, Aurora as the second intellectual property core, and MicroBlaze as the on-chip processor, etc., and configuring them. RTL code is written, mainly for the data control module. After connecting the various intellectual property cores and modules, electrical consistency checks are performed, pin constraints are applied, synthesis is performed, implementation is completed, a bitstream file is generated, and a hardware platform .xsa file is exported. The bitstream file mainly contains the software generation results, which are executable binary files that can be downloaded to the FPGA, while the .xsa file mainly contains software-related information.

[0067] Next, an embedded software project is created. Within this project, electrical compliance checks are performed on the high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, and interface controller. Pin configuration is then performed, a bitstream file is generated, and the hardware platform file is exported. Specifically, the embedded software project can be created using Vitis software. The .xsa file obtained in the previous step is imported, and C language code is written using the Ethernet "lwip tcp" template. After compilation, an .elf file is generated, which can be directly written to the FPGA master or FPGA slave.

[0068] In addition, it is optional to burn the program to flash memory. The program mainly consists of a bitstream file and a compiled .elf file. After being burned to flash memory, it is not necessary to perform the file compilation process every time the system is booted.

[0069] It's important to note that, for ease of operation, the hardware configuration of the FPGA master and FPGA slave devices can be identical. However, if Chip2chip is used as the primary intellectual property core, the corresponding software program of Chip2chip distinguishes between the master and slave devices; that is, the software programs for the FPGA master and FPGA slave devices will differ. See also... Figure 2 , Figure 2 This is a schematic diagram of the hardware structure provided in the embodiments of this application. Figure 2 As can be seen, the field-programmable logic device (FPGA) master and slave devices are connected by optical fiber, and a general-purpose input / output interface is used to establish a connection between the first processor and the second processor. The host computer is connected to the FPGA master via network cable and serial port. After the FPGA master is powered on, it controls the initialization of the first intellectual property core. Simultaneously, or after the FPGA master is powered on, the FPGA slave is powered on, and the first intellectual property core on the FPGA slave is also powered on. After the link is established, inter-chip communication between the FPGA master and the FPGA slave can be achieved through control by the host computer.

[0070] The hardware requirements for the above process are: two Xilinx Vitex UltraScale+ series field-programmable logic device development boards, a computer as the host computer, fiber optic cable, network cable, etc. The required software tools are: Vivado IDE, Vitis IDE, and a network debugging assistant.

[0071] Field-programmable logic devices (FPGAs) consist of a processor section and a programmable logic section. The processor section includes an on-chip processor (e.g., a MicroBlaze processor), an AXI bus router, an Ethernet controller, a UART serial port controller, a Quad SPI interface controller as a serial peripheral interface, and a DDR4 controller; this part requires joint development by Vivado and Vitis. The programmable logic section includes a data controller module, a first intellectual property core, and a second intellectual property core; this part is developed solely using Vivado. The data controller module is written in Verilog HDL and implements data communication via a high-speed transceiver (GTY). It can facilitate communication between FPGA master and FPGA slave devices, and can also store or retrieve data from Double Data Rate (DDR) memory via an inter-chip bus. Registers are defined for key configuration information such as data bit width, address bit width, and reset control, allowing for flexible processor control.

[0072] If Chip2Chip is used as the first intellectual property core, the global configuration option must be selected as master or slave during configuration. For the selection of the port physical layer type, using SelectI0 would significantly increase the number of hardware pins and result in a low communication rate. Therefore, a second intellectual property core is chosen to implement the conversion between chip2chip data and high-speed serial transceiver data. In this embodiment, if Aurora64B66B is used as the second intellectual property core, a high-speed physical layer transceiver is used during the configuration of the second intellectual property core. The line rate and number of channels can be selected according to requirements; in this example, the line rate is 25Gbps and the number of channels is 1.

[0073] If the MicroBlaze processor is used as the on-chip processor, during embedded development, C language code needs to be written based on the driver library to implement basic functions for accessing processor peripherals, including Ethernet access, UART serial port printing, flash memory read / write, memory read / write, input / output control of general-purpose input / output interfaces, and configuration of relevant registers in the data controller module. Furthermore, additional code logic is added to achieve a more user-friendly operation.

[0074] For example, the communication status between the FPGA master and FPGA slave can be displayed in real time via the UART serial port. For instance, if the Qualcomm access channel link is not established, "link error" will be displayed on the host computer interface; if the inter-chip bus access error occurs, "AXI error" will be displayed on the host computer interface; and if the FPGA master and FPGA slave are communicating normally, "lane up, receive and send correctly at high speed" will be displayed.

[0075] The following describes how this application executes the reset operations of the field-programmable logic device (FPGA) master and FPGA slave via a host computer:

[0076] S201: The second processor on the field-programmable logic device slave controls the first intellectual property core to reset according to the reset instruction;

[0077] S202: The first intellectual property core controls the phase-locked loop of the second high-speed transceiver to reset, and cancels the reset of the first intellectual property core;

[0078] S203: The processor on the second board of the field-programmable logic device slave sends a reset completion signal to the processor on the first board of the field-programmable logic device master.

[0079] First, the first intellectual property core of the second on-chip processor of the field-programmable logic device (FPGA) slave is reset. The QPLL phase-locked loop of the high-speed transceiver is reset, and its locking is checked. The reset operation of the first intellectual property core of the second on-chip processor is then cancelled. The first intellectual property core of the first on-chip processor is then reset, and the link establishment is checked. Resetting the first intellectual property core of the FPGA master requires the master processor to send a reset command to the data controller module via the AXI bus. Resetting the first intellectual property core of the FPGA slave requires the master processor to send a reset command to the slave processor via a general-purpose input / output interface. Upon receiving the command, the slave's on-chip processor resets via the AXI bus to the data controller module.

[0080] During the upgrade process, the host computer remotely updates the programs of both the field-programmable logic device (FPGA) master and slave devices via Ethernet. The host computer first accesses the FPGA master via Ethernet, then uses QSPI (Quad Schedule Performance Index, a six-wire serial peripheral interface) and the first intellectual property core to burn a new .bin file into the FPGA master's flash memory. Finally, the FPGA is powered off and restarted, completing the upgrade. For detailed procedures, please refer to [link to documentation]. Figure 3 , Figure 3 This is a schematic diagram of the reset operation process of a field-programmable logic device provided in an embodiment of this application.

[0081] The communication system of the field-programmable logic device provided in the embodiments of this application will be described below. The communication system of the field-programmable logic device described below can be referred to in correspondence with the communication method of the field-programmable logic device described above.

[0082] Figure 4 This application provides a schematic diagram of a communication system structure for a field-programmable logic device (FPGA). The application also provides a communication system for an FPGA, comprising:

[0083] The receiving module is used to receive control commands sent by the host computer.

[0084] The instruction sending module is used to control the first intellectual property core to send the control instructions to the second processor on the field-programmable logic device slave via the inter-chip bus;

[0085] The result receiving module is used to receive the processing result sent by the field-programmable logic device slave device through a link layer protocol based on the second intellectual property core after the second processor on the field-programmable logic device slave device processes the control instruction and obtains the processing result;

[0086] The communication result processing module is used by the field-programmable logic device host to store the processing result in memory or upload it to the host computer.

[0087] Based on the above embodiments, as a preferred embodiment, it further includes:

[0088] The hardware configuration module is used to establish a hardware platform project. In the hardware platform project, the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module. The data control module is used for data communication through the high-speed transceiver.

[0089] Based on the above embodiments, as a preferred embodiment, the system further includes:

[0090] The software configuration module is used to establish an embedded software project. In the embedded software project, electrical consistency checks are performed on the high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, and interface controller. Pin configuration is also performed, bit stream files are generated, and hardware platform files are exported.

[0091] Based on the above embodiments, as a preferred embodiment, the system further includes:

[0092] The host computer configuration module is used to connect the first high-speed transceiver on the host of the field-programmable logic device and the second high-speed transceiver on the slave of the field-programmable logic device via optical fiber.

[0093] The processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave are connected via a general-purpose input / output interface.

[0094] Based on the above embodiments, as a preferred embodiment, it further includes:

[0095] An initialization module is used to connect the host computer to the Ethernet controller of the field-programmable logic device host, and to initialize the first intellectual property core after the field-programmable logic device host is powered on.

[0096] Based on the above embodiments, as a preferred embodiment, it further includes:

[0097] The intellectual property core configuration module is used to generate a bitstream file and export a hardware platform file, then write the host program corresponding to the first intellectual property core to the host of the field-programmable logic device (FPGA); and write the slave program corresponding to the first intellectual property core to the slave of the FPGA.

[0098] Based on the above embodiments, as a preferred embodiment, if the control command is a reset command, it further includes:

[0099] The slave processing module, located on the slave device of the field-programmable logic device, is used to control the first intellectual property core to reset according to the reset instruction through the second processor; the first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core; and controls the processor on the second board to send a reset completion signal to the processor on the first board on the host of the field-programmable logic device.

[0100] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, can perform the steps provided in the above embodiments. The storage medium may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0101] This application also provides an electronic device that may include a memory and a processor. The memory stores a computer program, and when the processor calls the computer program in the memory, it can implement the steps provided in the above embodiments. Of course, the electronic device may also include various network interfaces, power supplies, and other components.

[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. As the system provided in the embodiments corresponds to the method provided in the embodiments, the description is relatively simple; relevant parts can be found in the method section.

[0103] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0104] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A communication method for a field-programmable logic device, characterized in that, include: The field-programmable logic device (FPGA) host receives control commands sent by the host computer. The first processor on the host of the field-programmable logic device (FPGA) controls the first intellectual property core to send the control instructions to the second processor on the slave of the FPGA via the inter-chip bus. After the second processor on the field-programmable logic device slave processes the control command and obtains the processing result, the field-programmable logic device master receives the processing result sent by the field-programmable logic device slave through the link layer protocol based on the second intellectual property core; The field-programmable logic device host stores the processing result in memory or uploads it to the host computer; Before the field-programmable logic device (FPGA) host receives control commands from the host computer, it also includes: A hardware platform project is established, in which the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module; the data control module is used for data communication through the high-speed transceiver.

2. The communication method according to claim 1, characterized in that, Also includes: An embedded software project is established. In the embedded software project, electrical consistency checks are performed on the high-speed transceiver, on-board processor, bus router, Ethernet controller, serial port controller, and interface controller. Pin configuration is performed, bit stream files are generated, and hardware platform files are exported.

3. The communication method according to claim 2, characterized in that, Also includes: The first high-speed transceiver on the host of the field-programmable logic device (FPGA) and the second high-speed transceiver on the slave of the FPGA are connected by optical fiber. The processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave are connected via a general-purpose input / output interface.

4. The communication method according to claim 3, characterized in that, After connecting the processor on the first board of the field-programmable logic device (FPGA) host and the processor on the second board of the FPGA slave via a general-purpose input / output interface, the system further includes: The host computer is connected to the Ethernet controller of the field-programmable logic device (FPGA) host. After the FPGA host is powered on, the first intellectual property core is initialized.

5. The communication method according to claim 3, characterized in that, After generating the bitstream file and exporting the hardware platform file, the process also includes: Write the host program corresponding to the first intellectual property core into the host of the field-programmable logic device; Write the slave program corresponding to the first intellectual property core into the slave device of the field programmable logic device.

6. The communication method according to claim 3, characterized in that, If the control instruction is a reset instruction, the second processor on the field-programmable logic device slave processes the control instruction and obtains the processing result, including: The second processor on the field-programmable logic device slave controls the first intellectual property core to reset according to the reset instruction; The first intellectual property core controls the phase-locked loop of the second high-speed transceiver to reset, and cancels the reset of the first intellectual property core; The processor on the second board of the field-programmable logic device (FPGA) slave sends a reset completion signal to the processor on the first board of the FPGA master.

7. A communication system using a field-programmable logic device, characterized in that, include: The receiving module is used to receive control commands sent by the host computer. The instruction sending module is used to control the first intellectual property core to send the control instructions to the second processor on the field-programmable logic device slave via the inter-chip bus; The result receiving module is used to receive the processing result sent by the field-programmable logic device master device through a link layer protocol based on the second intellectual property core after the second processor on the field-programmable logic device slave device processes the control command and obtains the processing result. The communication result processing module is used by the field-programmable logic device host to store the processing result in memory or upload it to the host computer; This also includes: The hardware configuration module is used to establish a hardware platform project. In the hardware platform project, the first intellectual property core and the second intellectual property core are configured on both the field-programmable logic device (FPGA) host and the FPGA slave, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module. The data control module is used for data communication through the high-speed transceiver.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the communication method for the field-programmable logic device as described in any one of claims 1-6.

9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and the processor invokes the computer program in the memory to implement the communication method of the field-programmable logic device as described in any one of claims 1-6.

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