Coarse-grained reconfigurable architecture CTMA for context switching and operation method

Abstract

The invention provides a context switching-oriented coarse-grained reconfigurable architecture CTMA and an operation method thereof. The coarse-grained reconfigurable architecture CTMA comprises an independent routing network, a CTMA command receiver module and a global CTMA controller module, the global CTMA controller module is used for iteratively generating a cross-Tile memory access command for each operation, and sending the cross-Tile memory access command to the corresponding Tiles through a chain bus connected with each Tile in sequence; the CTMA command receiver module is used for registering the transmitted CTMA command, checking the routing legality between the received CTMA command and the existing CTMA command, processing the generated conflict and locally caching the CTMA command; and the independent routing network is used for directly executing cross-Tile memory access under the control of a locally buffered CTMA command. According to the invention, the experimental task can directly access the memory distribution before context switching after context switching, data migration is not needed, and the negative influence of dynamic resource allocation on the task throughput rate is avoided.

Description

Technical Field

[0001] The invention relates to a context switching-oriented coarse-grained reconfigurable architecture CTMA and an operation method thereof, and belongs to the technical field of dynamic resource allocation. Background Art

[0002] Fast-growing industries such as automotive, aerospace, and medical require embedded coprocessors with high performance and energy efficiency, but cannot afford the non-recurring engineering (NRE) cost of ASIC implementation. FPGAs are adaptable to emerging applications, but their overly fine-grained reconfigurability limits frequency and power. As a natural trade-off between ASICs and FPGAs, coarse-grained reconfigurable architectures (CGRAs) not only have performance and energy efficiency close to ASICs, but also have a reconfiguration granularity suitable for the computing field, so they have attracted widespread attention from industry and academia.

[0003] Early research focused on compiling and executing a single task on the entire CGRA. But real-world embedded environments are full of mixed workloads. For example, machine learning (ML)-based face detection in access control systems may consist of multiple data-dependent tasks that share the entire CGRA and are executed in a pipelined manner. Automotive electronic control units (ECSs) can also process independent tasks from entertainment video, sound, and data generated by sensors around the vehicle in parallel. Therefore, how to efficiently execute multiple tasks on the CGRA has been the focus of many studies. Since multiple tasks have different resource requirements at different stages of their life cycle, dynamic resource allocation (DRA) has become one of the technical trends to improve the resource utilization of CGRA. More specifically, tasks with higher priorities can dynamically absorb resources from other tasks during the construction process. Many input-sensitive tasks, such as pollution, power grid, and traffic monitoring systems, can dynamically request more resources during peak hours. The large amount of resources released by task destruction can be dynamically reused by other tasks.

[0004] However, after executing DRA in the embedded CGRA architecture, all data stored in the previously allocated CGRATiles are incompatible with the newly allocated CGRATiles, which requires context switching to resolve. Data migration is the latest method to implement context switching. Although the corresponding delay introduced to the task execution timeline can be alleviated by double buffering, the efficiency is still low. Because the task cannot continue to execute on the new resource allocation decision before the data migration is completed. If DRA is triggered frequently due to environmental changes, the overall throughput of multi-tasking will be seriously affected. Summary of the invention

[0005] The present invention aims to solve the technical problem in the prior art that dynamic resource allocation has a negative impact on task throughput, and further proposes a coarse-grained reconfigurable architecture CTMA for context switching and an operation method thereof.

[0006] The technical solution adopted by the present invention to solve the above problems is: the present invention proposes a coarse-grained reconfigurable architecture CTMA for context switching, including:

[0007] Independent routing network, CTMA command receiver module and global CTMA controller module;

[0008] The global CTMA controller module is used to receive all memory access operations that are incompatible with the data memory of the layout tiles, iteratively generate cross-tile memory access commands for each operation, and send them to the corresponding tiles through the chain bus that sequentially connects each tile;

[0009] The CTMA command receiver module is used to register the incoming CTMA commands, check the routing legitimacy between the received CTMA commands and the existing CTMA commands, handle the conflicts that occur, and cache the CTMA commands locally;

[0010] An independent routing network is used to directly execute cross-tile memory accesses under the control of locally buffered CTMA commands.

[0011] Optionally, the global CTMA controller module includes an input manager, a local buffer module, a finite state machine, a path finder, and a command generator;

[0012] The input manager is used to decode the received input data;

[0013] The local buffer module is used to store the decoded data;

[0014] The finite state machine is used to control the generation of different types of CTMA commands, where the different types of CTMA commands include a head CTMA command, a middle CTMA command, and a tail CTMA command;

[0015] The path finder is used to generate Tiles to which the different types of CTMA commands belong.

[0016] The command generator is used to generate CTMA commands for cross-tile memory access.

[0017] Optionally, the CTMA command receiver module includes a register, a command memory module, a routing conflict processor, and a command memory read module;

[0018] The register is used to store the CTMA command passed in each clock cycle;

[0019] The command memory module is used to buffer CTMA commands;

[0020] The routing conflict handler is used to write control command memory during context switching;

[0021] The command memory reading module is used to read the control command memory during the task execution after the context switch.

[0022] Optionally, an independent routing network includes a memory arbiter, routing registers in 8 directions, and functional units;

[0023] The memory arbiter is used to divert the data from the tiles routed in eight directions, namely east, south, west, north, northeast, northwest, southeast, and southwest, to the input port of the memory access unit and sample it at the rising edge of the next clock cycle;

[0024] The functional unit is used to provide output signals to the memory arbiter to perform STORE operations or LOAD operations on the memory access unit.

[0025] The operation method of the context switching oriented coarse-grained reconfigurable architecture CTMA includes:

[0026] Step 1: Based on the global CTMA controller, all memory access operations that are incompatible between the layout tiles and the data memory are received and stored in the local buffer module. The finite state machine switches between the four states under the control of the self-incrementing Cnt. When a new SrcTile is found through the path finder, the command generator is called to generate the corresponding CTMA command for it, and transmitted to the corresponding tile through the chain bus;

[0027] Step 2: register the generated CTMA command through the register module in the CTMA command receiver, handle the conflict through the command memory module and the routing conflict processor and write the CTMA command into the cache, and control the command memory reading through the command memory reading module during the task execution after the context switch;

[0028] Step 3: Cross-tile memory accesses are performed directly under the control of locally buffered CTMA commands through an independent routing network.

[0029] Optionally, in step 1, when a new SrcTile is found by the path finder, the command generator is called to generate a corresponding CTMA command for it, and the step of transmitting the command to the corresponding Tile through the link bus includes:

[0030] Step 1.1: Cache the decoded incompatible memory access operations through the local buffer module. In the pre-mapping stage, the horizontal (X) and vertical (Y) coordinates of the placement blocks of the incompatible memory access operations before and after resource allocation are recorded through SrcTileXY and TgtTileXY in the local buffer module. SrcTileCycle provides the planned clock cycle of the memory access operation on the layout tile after resource allocation, and XY2Tile queries the corresponding tile of the given (X, Y) coordinates.

[0031] Step 1.2: Calculate the XY coordinate difference DiffXY between SrcTileXY and TgtTileXY through the finite state machine, obtain the number of CTMA commands required to implement cross-tile memory access, and generate the head CTMA command, the middle CTMA command, and the tail CTMA command;

[0032] Step 1.3: The path optimizer finds and receives the generated head CTMA command, middle CTMA command and tail CTMA command, updates SrcTile and uses the iteratively updated SrcTileXY to query XY2Tile, obtains the shortest path between the Tile with the target data memory and the Tile that actually performs the memory access operation, and compares it with DiffXY to refresh SrcTileXY and SrcCycle, and optimizes SrcTile in the next iteration;

[0033] Step 1.4: Based on the command generator, the CTMA command for cross-tile memory access is output. The CTMA command for cross-tile memory access is 24 bits, including five fields: Opt, Cycle, TileID, XbarIn, and XbarOut. Opt is 4 bits in size and is used to control the memory access unit in the tile to perform LOAD, STORE, or BYPASS operations; Cycle is 4 bits in size and is used to obtain the execution clock cycle of Opt; TileID is 8 bits in size and is used to identify the tile that executes Opt; XbarIn and XbarOut are both 4 bits in size and are used to control the tile's memory arbiter to route the memory access results from the source direction to the target direction.

[0034] Optionally, in step 1.3, obtaining the shortest path between the Tile having the target data memory and the Tile that actually performs the memory access operation specifically includes:

[0035] For cross-tile memory access of LOAD operation, the head CTMA command reads the data memory of the current tile and routes the result to the next tile in the path. For cross-tile memory access of STORE operation, the head CTMA command reads the output of the functional unit and routes it to the next tile in the path.

[0036] The intermediate CTMA command does not involve any memory access operation, but only BYPASSes the memory access result to the next tile in the path;

[0037] For cross-tile memory access of LOAD operation, the tail CTMA command redirects the memory access result to the register in the CTMA command receiver. For cross-tile memory access of STORE operation, the tail CTMA command writes the routing value to the data memory in the tile.

[0038] Optionally, the step of processing the conflict in step 2 and writing the CTMA command into the cache includes:

[0039] Step 2.1: The routing conflict processor compares the TileID field of the stored CTMA command with its own ID. If TileID=ID, the stored CTMA command is written into the command memory. If TileID≠ID, the routing conflict processor reads the existing CTMA command of the current Tile at the same Cycle, and checks whether the Opt, XbarIn, and XbarOut fields in the CTMA command are the same as the corresponding fields of the stored CTMA command. If any of the corresponding blocks are the same, a conflict occurs, and the corresponding CTMA command is written into the conflict cache. If they are not the same, the corresponding CTMA command is written into the normal cache.

[0040] Step 2.2: After writing the CTMA command to the cache, the write address wrAddr is indicated by the field Cycle when writing to the normal cache, and is generated by the counter when writing to the conflict cache. The write order of the conflict cache and the normal cache is recorded in the jump register. Each bit of the jump register will be responsible for selecting the two counters that generate the corresponding cache read address. After the context switch, the CTMA command will be read out from the normal cache or the conflict cache in reverse order.

[0041] Optionally, in step 3, directly executing cross-tile memory access under the control of the locally buffered CTMA command specifically includes:

[0042] After receiving the control instructions of the XbarIn and XbarOut fields of the CTMA command, the memory arbiter receives data routed from tiles in eight directions: east, south, west, north, northeast, northwest, southeast, and southwest, and turns the input to the input port of the memory access unit, and samples it on the rising edge of the next clock cycle; the memory arbiter also uses the output signal of the functional unit as input or write signal. When used as input, it selects tiles routed to other directions. When used as write signal, it performs a STORE operation on the memory access unit or directly performs a LOAD operation on the memory access unit. The read signal is used as the input of the memory arbiter, and it selects tiles routed to other directions or sends it as an operand to the functional unit for calculation to complete cross-tile memory access.

[0043] The beneficial effects of the present invention are:

[0044] 1. The present invention can bring an average 1.68× throughput improvement to the Streamimg-Bench and Polybench task sets after using CTMA. At the same time, within 5 input data after triggering resource allocation, an average of more than 90.0% of the resource allocation decision target throughput can be achieved.

[0045] 2. According to the synthesis and layout and routing reports of Synopsys+Cadence, the CTMA designed by the present invention only occupies 9.02% of the area under TSMC 45nm process.

[0046] 3. The present invention enables a task to directly access the memory distribution before the context switch after the context switch without data migration, thereby avoiding the negative impact of dynamic resource allocation on task throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A structural block diagram of the coarse-grained reconfigurable architecture CTMA for context switching provided by the present invention;

[0048] Figure 2 A flow chart of an operation method of a coarse-grained reconfigurable architecture CTMA for context switching provided by the present invention;

[0049] Figure 3 This is a flow chart of the CTMA controller algorithm provided by the present invention. DETAILED DESCRIPTION Specific implementation method 1

[0051] In this implementation, CGRA is a coarse-grained reconfigurable architecture, and CTMA is a cross-tile memory accessor.

[0052] Combination Figure 1 To illustrate this embodiment, Figure 1As shown in (a), the structure of the coarse-grained reconfigurable architecture CTMA for context switching described in this embodiment includes: an independent routing network, a CTMA command receiver module and a global CTMA controller module;

[0053] The global CTMA controller module is used to receive all memory access operations that are incompatible with the data memory of the layout tiles, iteratively generate cross-tile memory access commands for each operation, and send them to the corresponding tiles through the chain bus that sequentially connects each tile;

[0054] like Figure 1 As shown in (d), the global CTMA controller module includes an input manager, a local buffer module, a finite state machine, a path finder, and a command generator;

[0055] The input manager is used to receive input data for decoding;

[0056] The local buffer module is used to store the decoded data;

[0057] The finite state machine is used to perform state conversion within a clock cycle and control the generation of different types of CTMA commands, which include head CTMA commands, middle CTMA commands and tail CTMA commands;

[0058] The path finder is used to read from the data memory of the current tile and route the read result to the next tile in the path according to the different types of CTMA commands generated;

[0059] The command generator is used to generate CTMA commands for cross-tile memory access.

[0060] The CTMA command receiver module is used to register the incoming CTMA commands, check the routing legitimacy between the received CTMA commands and the existing CTMA commands, handle the conflicts that occur, and cache the CTMA commands locally. After the context switch, the task continues to run on the new resource allocation decision;

[0061] like Figure 1 As shown in (c), the CTMA command receiver module includes a register, a command memory module, a routing conflict processor and a command memory reading module;

[0062] The register is used to store the CTMA command passed in each clock cycle;

[0063] The command memory module is used to buffer CTMA commands;

[0064] The routing conflict handler is used to write control command memory during context switching;

[0065] The command memory reading module is used to read the control command memory during the task execution after the context switch.

[0066] An independent routing network is used to directly execute cross-tile memory accesses under the control of locally buffered CTMA commands.

[0067] like Figure 1 As shown in (b), the independent routing network includes a memory arbiter, routing registers in 8 directions, and functional units;

[0068] The memory arbiter is used to divert the data from the tiles routed in eight directions, namely east, south, west, north, northeast, northwest, southeast, and southwest, to the input port of the memory access unit and sample it at the rising edge of the next clock cycle;

[0069] The functional unit is used to provide output signals to the memory arbiter to perform STORE operations or LOAD operations on the memory access unit. Specific implementation method 2

[0071] Combination Figure 1-3 This embodiment is described as follows. Figure 2 As shown, the steps of the method for operating the context switching oriented coarse-grained reconfigurable architecture CTMA described in this embodiment include:

[0072] S1: Global CTMA controller (receives all memory access operations that are incompatible with the data memory of the layout tile, iteratively generates cross-tile memory access commands (CTMA commands) for each operation, and sends them to the corresponding tiles through the chain bus that sequentially connects each tile;

[0073] S101: Figure 1 As shown in (d), the input manager interacts with the central processor to receive input data from the CTMA controller, and then stores it in local buffers, including SrcTileXY, SrcTireCycle, TgtTileXY, and XY2Tile. For each incompatible memory access operation, SrcTileXY and TgtTileXY respectively record the horizontal (X) and vertical (Y) coordinates of its placement block before and after resource allocation. SrcTileCycle provides the planned clock cycle of the memory access operation on the layout tile after resource allocation. XY2Tile is used to query the corresponding tile for a given (X, Y) coordinate. All inputs are generated in the pre-mapping stage and are well organized in the off-chip memory. During the context switch, the corresponding input is transferred to the CTMA controller via DMA and then decoded by the bus controller within the input manager.

[0074] S102: The CTMA command (24 bits) output by the CTMA controller contains 5 fields, including Opt, Cycle, TileID, XbarIn and XbarOut, to achieve cross-tile memory access. Opt (4 bits) is used to control the memory access unit in the tile to perform LOAD, STORE or BYPASS operations; Cycle (4 bits) indicates in which clock cycle Opt should be executed; TileID (8 bits) identifies the tile that executes Opt; XbarIn (4 bits) and XbarOut (4 bits) are used to control the memory arbiter of the tile to route the memory access results from the source direction to the target direction.

[0075] S103: According to the input of S101-S102, the CTMA controller Figure 3 The algorithm shown outputs CTMA commands, finds the shortest path between the tile with the target data memory and the tile that actually performs the memory access operation, and generates CTMA commands for each tile within the path.

[0076] S10301: Figure 3 The algorithm shown first uses Init() to calculate the XY coordinate difference DiffXY between SrcTileXY and TgtTileXY (line 1), and then uses Max() to obtain the number of CTMA commands NumCmds required to implement cross-tile memory access (line 2). In order to iteratively find the shortest path, SrcTile is first updated at the beginning of each While loop iteration by querying XY2Tile with the latest SrcTileXY (lines 3-5). At the end of the While loop iteration, MoveToNextTile() is called to refresh SrcTileXY and SrcCycle by comparing with DiffXY (line 15), which makes SrcTile in the next iteration closer to TgtTile. Finally, Update() updates DiffXY to prepare for the next iteration (line 16).

[0077] S10302: Each tile in the shortest path requires a CTMA command to continuously transmit memory access results. According to the Cnt value and the size of NumCmds, Figure 3 The algorithm shown may output three types of CTMA commands (lines 6-14): head CTMA command, middle head CTMA command, and tail head CTMA command;

[0078] Cnt == 0 represents the head CTMA command, which is always generated by GenCmd_Head(). For cross-Tile memory access of the LOAD operation, this command actually reads from the data memory of the current Tile and routes the result to the next Tile in the path. For cross-Tile memory access of the STORE operation, this command reads the output of the functional unit and routes it to the next Tile in the path.

[0079] 0 < Cnt < NumCmds represents the intermediate CTMA command generated by GenCmd_Body(), which does not involve any memory access operations and only BYPASSes the memory access result to the next Tile in the path.

[0080] Cnt == NumCmds represents the tail CTMA command, which is always generated by GenCmd_Tail(). For cross-Tile memory access of the LOAD operation, this command redirects the memory access result to the input register of the functional unit. For cross-Tile memory access of the STORE operation, this command actually writes the routed value to the data memory in the Tile.

[0081] S10303: When Figure 3 the algorithm shown is converted to a hardware design, the while loop is abstracted into a finite state machine. For LOAD or STORE memory access operations, the finite state machine switches between 4 states under the control of the incrementing Cnt, including INIT, HEAD, BODY, and TAIL. All state transitions and state outputs are combinational logic circuits, and the state switching is sequential logic circuit. Other functions including Init(), MoveToNextTile(), and GenCmd_Head / Body / Tail() are abstracted into two hardware modules, a path finder and a command generator, both composed of combinational and sequential logic circuits and controlled by the finite state machine using the State signal.

[0082] S2: During the transmission of CTMA commands on the chain bus, if it is determined to belong to the current Tile, it is buffered locally by the CTMA command receiver in the Tile. The receiver also checks the routing legality between the received CTMA command and the existing CTMA commands and handles conflicts if necessary;

[0083] S201: As Figure 1 (c) shows, a register at the top of the CTMA command receiver is used to latch the incoming CTMA command at the rising edge of each clock cycle so that each CTMA command generated by the CTMA controller can be transmitted along the chain bus to all Tiles;

[0084] S202: Processing the conflict through the command memory module and the routing conflict processor and writing the CTMA command into the cache, and performing control command memory reading through the command memory reading module during the task execution after the context switching;

[0085] S20201: In the routing conflict processor, the Tile compares the TileID field of the registered CTMA command with its own ID. The registered CTMA command is allowed to be written to the command memory only when TileID == ID. Since no conflict check is performed in the CTMA controller, the routing conflict processor reads the existing CTMA command Exist_Cmd of the current Tile at the same Cycle, and checks whether its Opt, XbarIn, and XbarOut fields are the same as the fields corresponding to the registered CTMA command. If any of these fields are the same, a conflict occurs, and the write enable signal wrEn of the conflict cache is valid, and the registered CTMA command is written to the conflict cache. Otherwise, write to the normal cache.

[0086] S20202: The write address wrAddr is indicated by the field Cycle when writing to the normal cache, and is generated by the counter when writing to the conflict cache. The write order of the two caches will be recorded in the jump register. After the context switch, the CTMA command will be read from the normal cache or the conflict cache in reverse order, which can avoid conflicts. To achieve this goal, each bit of the jump register will be responsible for gating the two counters that generate the corresponding cache read address.

[0087] S3: After the context switch, the task continues to run on the new resource allocation decision. The independent routing network in each tile consists of a memory arbiter, registers (R), and memory access units, which perform cross-tile memory accesses under the control of the locally buffered CTMA commands to avoid data migration.

[0088] S301: The input of the memory arbiter mainly includes data from tiles routed in eight directions: east, south, west, north, northeast, northwest, southeast, and southwest. The data can be diverted to the input ports of eight routing registers and sampled at the rising edge of the next clock cycle, so that the tiles in the corresponding direction can stably receive the data in the next clock cycle.

[0089] S302: The memory arbiter also uses the output signal (FU_output) of the functional unit as input, selects the tiles routed to other directions, or uses it as a write signal (write_Data) to perform a STORE operation on the memory access unit. Conversely, the tile can also perform a LOAD operation directly on the memory access unit, using the read signal (Read_Data) as the input of the memory arbiter, and selects the tiles routed to other directions or sends it as an operand (Operand) to the functional unit for further calculation. All behaviors of the memory arbiter and the memory access unit in each cycle are controlled by the XbarIn and XbarOut fields of the CTMA command, so that the task can directly access the memory distribution before the context switch after the context switch, without the need for data migration, thereby avoiding the negative impact of dynamic resource allocation on task throughput.

[0090] Example

[0091] Combination Figure 2 This embodiment is described as follows. Figure 2 As shown, the application steps of the operation method of the context switching oriented coarse-grained reconfigurable architecture CTMA described in this embodiment include:

[0092] Step 1: Assume that the LOAD operation of the variable X[i] in a computing task is mapped to Tile 1 at clock cycle 3, but the corresponding data X[i] is actually located in the data memory of Tile 10, which will generate cross-tile memory access requirements. During the context switch process, the CTMA controller uses 4 clock cycles to go through 4 states, including INIT, HEAD, BODY, and TAIL, and generates the head CTMA command for Tile 10, the middle CTMA command for Tile 6, and the tail CTMA command for Tile 1 in turn. These commands are transmitted through the Tiles connected sequentially by the chain bus and are buffered by the CTMA command receiver in the corresponding tile at clock cycles 5, 10, and 14, respectively.

[0093] Step 2: After the context switch is completed, when the CGRA executes tasks under the new resource allocation decision, the CTMA command in Tile 10 first activates the memory access unit to read X[i] from the data memory at clock cycle 1, and then controls the memory arbiter to redirect X[i] to the South register connected to Tile 6. Secondly, the CTMA command in Tile 6 controls the memory arbiter to redirect the registered value to the Southwest register connected to Tile 1 at clock cycle 2. Finally, the CTMA command in Tile 1 controls the memory arbiter to redirect the registered value to the input register of the functional unit at clock cycle 3. Therefore, X[i] accurately routes the value to the consumer operation in Tile 1 through CTMA at clock cycle 4, which achieves the same effect as migrating X[i] from the data memory of Tile 1 to Tile 10, but eliminates the delay to the CGRA task execution timeline.

[0094] In order to verify the technical effect of the present invention, this embodiment adopts the following experimental settings:

[0095] (1) CGRA architecture: The size of the CGRA processing unit array is 16×16, with a total of 256 tiles. The data memory size of each tile is 1KB, the configuration memory size is 512Bytes, and the topology of the interconnection between tiles is "orthogonal + diagonal"; the command memory in the CTMA controller is set to 1KB, which is enough to accommodate the input required for all tasks to generate CTMA commands (XY2Tile is 512Bytes, TileXY and TileCycle are 512Bytes in total); the cache in the CTMA command receiver is set to 64Bytes, which is divided into normal cache (48Bytes) and conflict cache (16Bytes).

[0096] (2) Data-intensive tasks: First, three embedded streaming tasks are selected from the open source CGRA task set Streamimg-Bench, including GCN, RayTrac, and LU. Each task has its own 16×16 CGRA, and all kernels within the task are executed in a pipeline manner. In addition, this embodiment selects three computing tasks in the matrix multiplication field from the open source CGRA task set Polybench, namely GEMM, SYRK, and SYMM. The three tasks are executed in parallel and share the 16×16 CGRA.

[0097] (3) Dynamic resource allocation decisions: For the Streamimg-Bench task set, resource allocation decisions are generated by the DRIPS controller; for the Polybench task set, resource allocation decisions are generated by the modified Linux EEVDF algorithm.

[0098] Under the above experimental settings, the use of CTMA can bring an average throughput improvement of 1.68× for Streamimg-Bench and Polybench task sets. At the same time, within 5 input data after triggering resource allocation, an average resource allocation decision target throughput of more than 90.0% can be achieved. According to the synthesis and layout and routing reports of Synopsys+Cadence, CTMA only occupies 9.02% of the area under TSMC 45nm process.

[0099] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A coarse-grained reconfigurable architecture CTMA for context switching, characterized by: The structure of the coarse-grained reconfigurable architecture CTMA for context switching includes: Independent routing network, CTMA command receiver module and global CTMA controller module; The global CTMA controller module is used to receive all memory access operations that are incompatible between the layout tiles and the data memory, iteratively generate cross-tile memory access commands for each operation, and send them to the corresponding tiles through the chain bus that sequentially connects each tile; The CTMA command receiver module is used to store the incoming CTMA command, check the routing legitimacy between the received CTMA command and the existing CTMA command, handle the conflicts that occur, and cache the CTMA command locally; The independent routing network is used to directly perform cross-tile memory accesses under the control of locally buffered CTMA commands.

2. The coarse-grained reconfigurable architecture CTMA for context switching according to claim 1, characterized in that: The global CTMA controller module includes an input manager, a local buffer module, a finite state machine, a path finder and a command generator; The input manager is used to decode the received input data; The local buffer module is used to store decoded data; The finite state machine is used to control the generation of different types of CTMA commands, where the different types of CTMA commands include a head CTMA command, a middle CTMA command, and a tail CTMA command; The path finder is used to generate Tiles to which the different types of CTMA commands belong; The command generator is used to generate a CTMA command for cross-tile memory access.

3. The coarse-grained reconfigurable architecture CTMA for context switching according to claim 1, characterized in that: The CTMA command receiver module includes a register, a command memory module, a routing conflict processor and a command memory reading module; The register is used to store the CTMA command passed in each clock cycle; The command memory module is used to buffer CTMA commands; The routing conflict processor is used to write control command memory during context switching; The command memory reading module is used to read the control command memory during the task execution after the context switching.

4. The coarse-grained reconfigurable architecture CTMA for context switching according to claim 1, characterized in that: The independent routing network includes a memory arbiter, routing registers in eight directions and functional units; The memory arbiter is used to divert data from Tiles routes in eight directions, namely, east, south, west, north, northeast, northwest, southeast, and southwest, to the input port of the memory access unit and perform sampling at the rising edge of the next clock cycle; The functional unit is used to provide an output signal to the memory arbiter to perform a STORE operation or a LOAD operation on the memory access unit.

5. A method for operating a coarse-grained reconfigurable architecture CTMA for context switching, applied to the coarse-grained reconfigurable architecture CTMA for context switching according to any one of claims 1 to 4, characterized in that: include: Step 1: Based on the global CTMA controller, all memory access operations that are incompatible between the layout tiles and the data memory are received and stored in the local buffer module. The finite state machine switches between four states under the control of the self-incrementing Cnt. When a new SrcTile is found through the path finder, the command generator is called to generate the corresponding CTMA command for it, and the command is transmitted to the corresponding tile through the chain bus. Step 2: register the generated CTMA command through the register module in the CTMA command receiver, handle the conflict through the command memory module and the routing conflict processor and write the CTMA command into the cache, and control the command memory reading through the command memory reading module during the task execution after the context switch; Step 3: Cross-tile memory accesses are performed directly under the control of locally buffered CTMA commands through an independent routing network.

6. The method for operating the context switching oriented coarse-grained reconfigurable architecture CTMA according to claim 5, characterized in that: In step 1, when a new SrcTile is found by the path finder, the command generator is called to generate a corresponding CTMA command for it, and the steps of transmitting it to the corresponding Tile through the chain bus include: Step 1.1: Cache the decoded incompatible memory access operations through the local buffer module. In the pre-mapping stage, the horizontal (X) and vertical (Y) coordinates of the placement blocks of the incompatible memory access operations before and after resource allocation are recorded through SrcTileXY and TgtTileXY in the local buffer module. SrcTileCycle provides the planned clock cycle of the memory access operation on the layout tile after resource allocation, and XY2Tile queries the corresponding tile of the given (X, Y) coordinates. Step 1.2: Calculate the XY coordinate difference DiffXY between SrcTileXY and TgtTileXY through the finite state machine, obtain the number of CTMA commands required to implement cross-tile memory access, and generate the head CTMA command, the middle CTMA command, and the tail CTMA command; Step 1.3: The path optimizer finds and receives the generated head CTMA command, middle CTMA command and tail CTMA command, updates SrcTile and uses the iteratively updated SrcTileXY to query XY2Tile, obtains the shortest path between the Tile with the target data memory and the Tile that actually performs the memory access operation, and compares it with DiffXY to refresh SrcTileXY and SrcCycle, and optimizes SrcTile in the next iteration; Step 1.4: Based on the command generator, the CTMA command for cross-tile memory access is output. The CTMA command for cross-tile memory access is 24 bits, including five fields: Opt, Cycle, TileID, XbarIn and XbarOut. Opt is 4 bits in size and is used to control the memory access unit in the Tile to perform LOAD, STORE or BYPASS operations; Cycle is 4 bits in size and is used to obtain the execution clock cycle of Opt; TileID is 8 bits in size and is used to identify the Tile that executes Opt; XbarIn and XbarOut are both 4 bits in size and are used to control the memory arbiter of the Tile to route the memory access results from the source direction to the target direction.

7. The method for operating the context switching oriented coarse-grained reconfigurable architecture CTMA according to claim 6, characterized in that: The shortest path between the Tile with the target data memory and the Tile that actually performs the memory access operation in step 1.3 specifically includes: For cross-tile memory access of LOAD operation, the head CTMA command reads the data memory of the current tile and routes the result to the next tile in the path. For cross-tile memory access of STORE operation, the head CTMA command reads the output of the functional unit and routes it to the next tile in the path. The intermediate CTMA command does not involve any memory access operation, but only BYPASSes the memory access result to the next tile in the path; For cross-tile memory access of LOAD operation, the tail CTMA command redirects the memory access result to the register in the CTMA command receiver. For cross-tile memory access of STORE operation, the tail CTMA command writes the routing value to the data memory in the tile.

8. The method for operating the context switching oriented coarse-grained reconfigurable architecture CTMA according to claim 5, characterized in that: The steps of handling the conflict and writing the CTMA command into the cache in step 2 include: Step 2.1: The routing conflict processor compares the TileID field of the stored CTMA command with its own ID. If TileID=ID, the stored CTMA command is written into the command memory. If TileID≠ID, the routing conflict processor reads the existing CTMA command of the current Tile at the same Cycle, and checks whether the Opt, XbarIn, and XbarOut fields in the CTMA command are the same as the corresponding fields of the stored CTMA command. If any of the corresponding blocks are the same, a conflict occurs, and the corresponding CTMA command is written into the conflict cache. If they are not the same, the corresponding CTMA command is written into the normal cache. Step 2.2: After writing the CTMA command to the cache, the write address wrAddr is indicated by the field Cycle when writing to the normal cache, and is generated by the counter when writing to the conflict cache. The write order of the conflict cache and the normal cache is recorded in the jump register. Each bit of the jump register will be responsible for selecting the two counters that generate the corresponding cache read address. After the context switch, the CTMA command will be read from the normal cache or the conflict cache in reverse order.

9. The method for operating the context switching oriented coarse-grained reconfigurable architecture CTMA according to claim 5, characterized in that: In step 3, directly executing cross-tile memory access under the control of the locally buffered CTMA command specifically includes: After receiving the control instructions of the XbarIn and XbarOut fields of the CTMA command, the memory arbiter receives data routed from tiles in eight directions of east, south, west, north, northeast, northwest, southeast, and southwest, and turns the input to the input port of the memory access unit, and samples it at the rising edge of the next clock cycle; and the memory arbiter also uses the output signal of the functional unit as input or write signal. When used as input, it selects to route to tiles in other directions. When used as a write signal, it performs a STORE operation on the memory access unit or directly performs a LOAD operation on the memory access unit. The read signal is used as the input of the memory arbiter, and selects to route to tiles in other directions or sends it as an operand to the functional unit for calculation to complete cross-tile memory access.

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