System and method for clock calibration adjustment for three-dimensional integrated circuit (3DIC)

Abstract

The invention relates to a system and method for clock calibration adjustment for a three-dimensional integrated circuit (3DIC). Some embodiments disclosed herein relate to an apparatus. An apparatus may include a first conductive element configured to receive a first signal at a first functional block. The device may include a second conductive element configured to communicate the first signal to a second functional block of the device. The apparatus may include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase shift. The apparatus may include a first circuit configured to determine the phase shift between the first signal and the second signal. The apparatus may include a second circuit configured to generate a third signal based on the phase shift, the first signal, the second signal.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 514,995, filed on July 21, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to systems and methods for inter-block (eg, inter-chip) clock networks. For example, the clock network can synchronize various operations of a semiconductor device. Background Art

[0004] Verification of timing constraints (sometimes referred to as timing closure) in digital designs can be challenging in modern digital devices. For example, a device may include various interconnected clock networks and large monolithic or multi-chip devices, such as stacked die devices (sometimes referred to as three-dimensional integrated circuits or "3DICs"). Failure to achieve timing closure may result in latching or propagating unstable data, which may register or propagate incorrect bit values ​​(causing logic errors in combinational circuits) or incorrect memory values. Conversely, design changes to achieve timing closure may include inserting intermediate latches or other additional pipeline stages, reducing the maximum frequency (f max ) or clock tree optimizations that may shift critical path combinational circuits, any of which would degrade device performance. Summary of the invention

[0005] Tracking and recovering the clock between clock subdomains can increase the timing margin of the system. Achieving timing closure in 3DIC can impose additional variables, such as chip-to-chip variables (e.g., process, voltage, or temperature (PVT), different cell libraries with various setup or hold times, different aging characteristics, etc.). By calibrating and adjusting the clock signals at the chip-to-chip boundaries (or other domain boundaries of various functional blocks), timing closure within each chip can be performed separately, and the multi-phase generator can generate adjusted clock signals between chips (e.g., to evaluate and mitigate offsets). In some embodiments, the multi-phase generator may include periodic updates (e.g., to compensate for variability in voltage and frequency scaling) or temperature of the device over time. The multi-phase generator may provide offset updates based on sampled or received data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, wherein the same reference characters identify all corresponding elements. In the drawings, the same reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0007] Figure 1is a block diagram depicting a system for clock calibration and adjustment in a three-dimensional integrated circuit (3DIC) device, according to some embodiments.

[0008] Figure 2 is another schematic block diagram of a system for clock calibration and adjustment according to some embodiments.

[0009] Figure 3 is a schematic block diagram of a clock calibration and adjustment circuit depicting a first die connected to various second dies, according to some embodiments.

[0010] Figure 4 Depicted is a representation of data signal transitions between a first and a second die in accordance with some embodiments.

[0011] Figure 5 Depicted is another representation of data signal transitions between a first and a second die in accordance with some embodiments.

[0012] Figure 6 is a flow chart illustrating the operation of a method of circuit operation according to some embodiments.

[0013] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. The disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Some embodiments disclosed herein relate to a device. The device may include a first conductive element configured to receive a first signal at a first functional block of the device. The device may include a second conductive element configured to transmit the first signal to a second functional block of the device. The device may include a third conductive element configured to receive a second signal from the second functional block of the device, the second signal varying from the first signal according to a phase shift. The device may include a first circuit configured to determine the phase shift between the first signal and the second signal. The device may include a second circuit configured to generate a third signal based on the phase shift, the first signal, the second signal, and the third signal having the same frequency.

[0016] In some embodiments, the first signal is a first clock signal input to the first functional block. The third signal may be a second clock signal input to the second functional block. The second signal may be a clock signal output from the second functional block.

[0017] In some embodiments, the first functional block is disposed on a first semiconductor die of the device.The second functional block may be disposed on a second semiconductor die of the device.

[0018] In some embodiments, the first semiconductor die is a first node and the second semiconductor die is a second node different from the first node.

[0019] In some embodiments, a first core voltage of the first semiconductor die is different from a second core voltage of the second semiconductor die.

[0020] In some embodiments, the first semiconductor die is configured to couple with a plurality of semiconductor die including the second semiconductor die. The first circuit may be configured to determine a plurality of phase shifts for each of the semiconductor die. The second circuit may be configured to adjust the phase of each of the semiconductor die.

[0021] In some embodiments, the first circuit is configured to compare the first signal with the second signal to generate a representation of the phase shift to a plurality of predefined phases and transmit the representation to the second circuit. A third circuit is configured to select a predefined register value corresponding to the second circuit, the predefined register value corresponding to the phase shift.

[0022] In some embodiments, the first circuit and the second circuit are components of an analog domain of the first functional block, and the third circuit is a component of a digital domain of the first functional block.

[0023] In some embodiments, the second circuit includes a multiphase generator. The multiphase generator may receive the first signal from a phase-locked loop (PLL). The multiphase generator may phase shift the first signal to generate the third signal. The multiphase generator may transmit the third signal to the first functional block, wherein the first signal from the PLL is transmitted to the second functional block.

[0024] In some embodiments, the first conductive element includes a metal interconnect disposed over an active surface of the first semiconductor die. The second conductive element may include a first metal interconnect of a hybrid bond between the first semiconductor die and the second semiconductor die. The third conductive element may include a second metal interconnect of the hybrid bond.

[0025] Some embodiments disclosed herein relate to a system. The system may include a first semiconductor die and a second semiconductor die. The first semiconductor die may include a first conductive element configured to receive a first signal. The first semiconductor die may include a second conductive element configured to transmit the first signal to the second semiconductor die. The first semiconductor die may include a third conductive element configured to receive a second signal from the second semiconductor die. The second signal may vary from the first signal according to a phase shift. The first semiconductor die may include a first circuit configured to determine the phase shift between the first signal and the second signal. The first semiconductor die may include a second circuit configured to generate a third signal based on the phase shift, the first signal, the second signal, and the third signal has the same frequency.

[0026] In some embodiments, the first signal is a first clock signal input to the first semiconductor die. The third signal may be a second clock signal input to the second semiconductor die. The second signal may be a clock signal output from the second semiconductor die.

[0027] In some embodiments, the first semiconductor die is configured to couple with a plurality of semiconductor die including the second semiconductor die. The first circuit may be configured to determine the phase shift of each of the semiconductor dies. The second circuit may be configured to adjust the phase output of each of the semiconductor dies.

[0028] In some embodiments, the first circuit is configured to compare the first signal with the second signal to generate a representation of the phase shift to a predefined phase and transmit the representation to a third circuit. The third circuit is configured to select a predefined register value, the predefined register value corresponding to the phase shift.

[0029] In some embodiments, the first semiconductor die includes an analog domain and a digital domain. The analog domain may include the first circuit and the second circuit. The digital domain may include the second circuit.

[0030] In some embodiments, the second circuit includes a multiphase generator. The multiphase generator may receive the first signal from a phase locked loop (PLL). The multiphase generator may phase shift the first signal to generate the third signal. The multiphase generator may transmit the third signal to the first semiconductor die. The first signal from the PLL may be transmitted to the second semiconductor die.

[0031] Some embodiments disclosed herein relate to a method. The method may include receiving a first signal at a first conductive element of a first semiconductor die. The method may include transmitting the first signal to a second semiconductor die through a second conductive element of the first semiconductor die. The method may include receiving a second signal at a third conductive element of the first semiconductor die. The method may include determining a first phase shift between the first signal and the second signal. The method may include generating a third signal according to a second phase shift from the first signal in response to the first phase shift. The method may include providing the third signal to a combinational logic of the first semiconductor die.

[0032] In some embodiments, determining the first phase shift includes comparing the first signal to the second signal to generate a representation of the first phase shift to a set of predefined phases and selecting a predefined register value, the predefined register value corresponding to the second phase shift.

[0033] In some embodiments, the determining of the first phase shift and the generating of the third signal are performed in an analog domain of the first semiconductor die.The selecting of the predefined register value may be performed in a digital domain of the first semiconductor die including the combinatorial logic.

[0034] In some embodiments, generating the third signal includes receiving the first signal from a phase locked loop (PLL). Generating the third signal may further include phase shifting the first signal to generate the third signal. Generating the third signal may further include transmitting the third signal to the first semiconductor die, wherein the first signal from the PLL is transmitted to the second semiconductor die.

[0035] To clarify the present disclosure, before proceeding to further describe the systems and methods provided herein, an illustrative description of various terms is provided:

[0036] In some embodiments, a functional block may refer to or include a physical or logical portion of a device. For example, a functional block may include a semiconductor die or a portion thereof, a logical block of a schematic diagram, or another logical or physical subdivision of a circuit. A functional block may include or span one or more semiconductor dies coextensive with a semiconductor die, or a semiconductor die may include various functional blocks. In some embodiments, a semiconductor die may refer to or include a semiconductive material having an active surface. A semiconductor die may include one or more metallization layers disposed on or connected to the active surface of a semiconductor die. In some embodiments, an active surface may refer to or include a surface having n-wells and p-wells for diodes and transistors, films or dopants for resistors, polysilicon resistors, capacitors, or other components for circuits. The metallization layer may interconnect the elements of the active surface to form a circuit.

[0037] A circuit may refer to or include a combination of components configured to generate, transmit, or process a signal. A circuit may generate, transmit, or process a digital signal, an analog signal, or a combination thereof. For example, a circuit or combination of circuits may include a digital domain or an analog domain. In some embodiments, a digital domain may refer to or include a domain configured to digitally encode or process information according to discrete values. For example, a digital domain may include combinatorial logic, such as a NOR gate, a NAND gate, an AND gate, or other logic gates. A digital domain may include one or more clock-driven sequential elements (such as flip-flops) between combinatorial logic portions of a circuit. In some embodiments, combinatorial logic may refer to or include a circuit for generating an output mapped to one or more input values. In some embodiments, an analog domain may refer to or include a domain having a circuit configured to process a non-discrete signal portion (such as a continuously variable phase). An analog domain may include isolation elements for providing isolation from a digital domain, such as a separate or split ground plane, a power supply, and the like.

[0038] In some embodiments, hybrid bonding may refer to or include bonding between semiconductor dies (e.g., wafers), including bonding conductive and dielectric layers. For example, bonding between conductive elements may be between metal interconnects of metallization layers and configured to pass signals between various semiconductor dies. Molecular interactions between silicon or other semiconductive materials or dielectrics formed thereon may mechanically couple the wafers to each other. In some embodiments, metal interconnects may refer to or include metal connections between conductive elements. For example, metal interconnects may include interconnects between semiconductor dies or between metallization layers on semiconductor dies. In some embodiments, conductive elements may refer to or include conductive materials configured to pass electrical signals. For example, conductive elements may include metal interconnects.

[0039] In some embodiments, a node of a semiconductor die may refer to or include a set of physical dimensions of its features or design rules for a semiconductor device. For example, a node may include a 7nm node, a 3nm node, a planar node, a FinFET node, and the like. A node (sometimes referred to as a process node or a manufacturing node) may include the physical dimensions of a gate or channel structure or design rules associated with the placement of its features. The size of a node may indicate the literal size of a feature or another node attribute (e.g., a relative density or power efficiency that can be achieved relative to other nodes according to a set of design rules). A node may correspond to an operating temperature, a core voltage, or other operating characteristics. In some embodiments, a core voltage may refer to or include a nominal voltage at which a logic circuit of a semiconductor die operates. The core voltage may vary according to a node or its operating point, and an operating point corresponds to a performance or power attribute.

[0040] In some embodiments, a signal may refer to or include a variable indication of information or timing. For example, a signal may include a clock signal. In some embodiments, a clock signal may refer to or include a periodic signal configured to gate a sequential logic device (e.g., a flip-flop). In some embodiments, the frequency of a signal (e.g., a clock signal) may refer to or include the nominal periodicity of the signal. The periodicity may vary according to temperature, voltage, manufacturing differences, and other aspects of the semiconductor device. In some embodiments, a clock signal input may refer to or include a signal provided at the input of a circuit. A clock signal output may refer to or include a signal received at the output from a circuit. The phase of a clock signal output may lead or lag relative to a clock signal input. In some embodiments, a phase shift may refer to a time or phase difference between two signals of the same or related frequencies. For example, a phase shift may be provided as time (e.g., ns) or phase (e.g., degrees).

[0041] In some embodiments, a phase-locked loop (PLL) may refer to or include a circuit for generating a clock signal. For example, a PLL may generate a clock signal based on a clock input via a PLL system, and the PLL system includes a voltage-controlled oscillator (VCO) having a frequency proportional to the input voltage. In some embodiments, a multiphase generator may refer to or include a circuit configured to generate an output that is phase-shifted relative to an input signal. For example, a multiphase generator may include a register for receiving a predefined value. In some embodiments, a predefined register value may refer to or include a digital value corresponding to a phase shift. In some embodiments, a register value may be referred to as a representation of a phase shift. For example, a 5-bit register including 32 values ​​may correspond to a phase shift of 0°, 11.25°, 22.5°, etc.

[0042] Timing closure in 3DIC can be challenging because convergence must account for variations between multiple semiconductor dies. The present disclosure provides systems and methods for tracking and recovering clocks to improve timing margins. The systems and methods include a self-aligned calibration system. The systems and methods can be employed by various devices that send and receive data, such as multi-chip devices, single-chip devices, printed circuit board assemblies, etc. The systems and methods can provide for correct timing in construction. The solution can be reused without substantial circuit customization. The systems and methods can track the increased timing margins of various IP paths and can simplify and reduce resources used for custom IP design.

[0043] Figure 1A block diagram is provided depicting a system for clock calibration and adjustment in a three-dimensional integrated circuit (3DIC) device according to some embodiments. The system may include a plurality of functional blocks. A functional block may refer to, for example, a portion of a circuit disposed on one or more semiconductor dies, a circuit board, or other substrate. For example, a functional block may correspond to a semiconductor die of a multi-chip module (MCM). That is, a first functional block may include or be formed on an active surface of a first semiconductor die 102; a second functional block may include or be formed on an active surface of a second semiconductor die 104. An inter-chip interface 106 including various interconnects is between the first semiconductor die 102 and the second semiconductor die 104.

[0044] The first semiconductor die 102 or the second semiconductor die 104 may include manufacturing variations such that the performance of the logic element may vary between instances or over time, temperature, voltage, etc. The performance of the circuit element may vary such that performance corners may be defined. The typical (T) performance of two elements (e.g., switching speed / delay) may be referred to as a typical-typical (TT) instance. The performance of a fast first element and a fast second element (p-type transistor and n-type transistor) may be referred to as the FF corner, where the element exhibiting greater delay or switching speed may be referred to as the SS corner. Timing closure may be achieved by ensuring positive margins according to the various corners (FF, SF, FS, SS).

[0045] In an MCM where various semiconductor dies or other functional blocks may be manufactured from multiple nodes or from separate wafers, variability may be extended to each semiconductor die. For example, the variability of a two-die MCM may include 16 corners (FF-FF, FF-SF, FF-FS, FF-SS, SF-FF, etc.). A semiconductor die or other functional block may include different performance based on voltage (e.g., core voltage) or temperature level (e.g., local hot spots), even if the circuit is formed on a monolithic die. Thus, for a system including various functional devices, clock calibration phase adjustment may be employed.

[0046] The first semiconductor die 102 may receive or generate a clock signal. For example, the first semiconductor die 102 may include a phase locked loop (PLL) 120 for the clock signal. The clock signal may be communicated as an output to any number of dies or portions thereof (e.g., circuits of the first semiconductor die 102 and circuits of the second semiconductor die 104). For example, as depicted, the clock signal may be communicated to a multi-phase generator 126 of the first semiconductor die 102 and various circuits of the second semiconductor die 104. The clock input (of the second semiconductor die 104) is derived from the clock output of the first semiconductor die.

[0047] In the depicted embodiment, the clock signal is transmitted to the first synchronization device 108 and the second synchronization device 112, wherein the first synchronization device 108 or the second synchronization device 112 can gate various combinational logic circuit portions of the second semiconductor die 104. The depicted embodiment is not intended to be limiting; various embodiments may include a different number of synchronization stages, different synchronization devices, etc. For example, a signal may be latched according to a rising or falling edge, according to a propagation delay of a combinational logic disposed between two or more synchronization devices. That is, according to various embodiments, synchronization devices or combinational logic may be added, omitted, substituted, etc.

[0048] The second semiconductor die 104 may include a first combinatorial circuit 110 having a clock gated by its input, by the first synchronization device 108, and at its output by the second synchronization device 112. The various circuit elements of the second semiconductor die 104 may include circuit portions configured to perform functions of a device (e.g., a microprocessor pipeline stage) or determine die performance (e.g., a ring oscillator). The second combinatorial circuit 114 is configured to interface with the inter-chip interface 106 (e.g., may include digital logic, pull-up, or level shifting circuits). The clock signal may be propagated from the second semiconductor die 104 to the first semiconductor die 102 across the inter-chip interface 106. For example, the clock signal may be returned as a discrete signal or embedded in a data stream, and then the sampling circuit 122 of the first semiconductor die 102 may recover the clock signal to determine its characteristics (e.g., phase).

[0049] The return path for the clock signal may be through the third combinatorial circuit 116 of the first semiconductor die 102, which may include, for example, the digital logic, pull-up, or level shifting circuitry of the second combinatorial circuit 114 and the like. In some embodiments, some portions of the depicted system 100 may be omitted. For example, the second combinatorial circuit 114 or the third combinatorial circuit 116 may be omitted. Likewise, the system 100 may include additional or fewer links, such as one connection for a single-ended clock, two connections for a differential clock, or connections to multiple clocks (or Figure 3 The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112. The clock signal may be measured by sampling circuit 112.

[0050] The sampling circuit 122 of the first semiconductor die 102 may recover the phase shift, its representation, or other information associated with the clock signal. For example, the sampling circuit 122 may receive a clock signal originating from the second semiconductor die 104. The sampling circuit 122 may further receive another clock signal originating from the same clock source as the second semiconductor die 104 (e.g., PLL 120). The multi-phase generator (MFG) 126 is configured to phase shift the signal received from the PLL. For example, the MFG 126 may generate an initial signal having a zero or non-zero phase shift relative to the clock signal transmitted to the second semiconductor die 104, and then the sampling circuit 122 (e.g., a phase detector, such as a full-tap phase detector) may generate a representation of the phase shift. The representation may include, for example, a voltage level output (e.g., a positive or negative voltage corresponding to a lead or lag signal), a pulse width output, or a binary output (e.g., a register value mapped to a predefined numerical value of the phase shift amount). The representation may include an analog or digital indication.

[0051] Another circuit (e.g., controller 124 or other control circuitry) may select a register value corresponding to a representation of the phase shift. The register value may be a predefined value corresponding to the phase shift. For example, one or more discrete phase shift values ​​may correspond to a second phase shift that is equal to or different from the detected phase shift. For example, the second phase shift may be a fixed offset from the first phase shift, the second phase shift being configured to increase the margin, as described below. Figure 4 and Figure 5 124. The controller 124 may be disposed in the digital domain of the semiconductor die and configured to interface across the mixed signal domain to interface with the PLL 120 and the MFG 126, which belong to the analog domain. The various representations of the phase shift may differ from one another. For example, a first indication may include a voltage level, a pulse width, or other analog domain indication of the phase shift; a first indication may include a digitally resolved value at the controller 124; a third indication may include another representation employed by the MFG 126.

[0052] The controller 124 may determine the phase shift incidental to the manufacture of the device. For example, the controller 124 may trigger a register of a one-time fuse to transmit a representation of the phase shift to the MFG 126. The controller 124 may determine the phase shift at device power-up or startup. For example, the controller 124 may write a representation of the phase shift to a register when the device is powered on, associated, paired, etc. The controller 124 may update the representation of the phase shift during device operation (e.g., by rewriting a register value). For example, the controller 124 may update the representation in response to an event (e.g., a voltage or temperature change or based on a periodic update).

[0053] MFG 126 may generate another clock signal that is a phase shift of a clock signal received from PLL 120 or other clock source in response to receiving a phase shift representation of the signal from controller 124. For example, the phase shift may be configured to increase margin along a timing path (sometimes referred to as a critical path).

[0054] The sampling circuit 122, controller 124, or MFG 126 may be integrated or separate from the first semiconductor die 102 or a semiconductor device including the first semiconductor die 102. Other dies may include corresponding sampling circuits 122, controllers 124, or MFG 126, or corresponding logic circuits. The sampling circuit 122, controller 124, or MFG 126 may interface with further corresponding logic circuits. For example, the controller 124 may select a separate representation of the phase shift for each semiconductor die or other functional block or a phase shift based on multiple representations. The controller 124 may receive further information (e.g., voltage information, temperature information, etc.) from one or more dies of the system 100 during operation so that the controller 124 can determine adjustment commands for the multi-phase generator 126. That is, the semiconductor die may include or interface with temperature, voltage, current, propagation delay, or other sensors.

[0055] Thus, when establishing timing closure, the system 100 including multiple dies is not constrained by the full range of silicon variations, temperature variations, voltage variations, etc. simultaneously. For example, instead of establishing timing closure with a setup time variation of 5 nanoseconds (ns) corresponding to a population of dies, the variation can be reduced to 2ns corresponding to a particular die, where the controller 124 can make adjustments before or during operation of the system 100. Furthermore, this system can be implemented in existing systems without additional logic changes. That is, the phase or other clock properties of the third synchronizer 128 or the fourth synchronizer 132 that gates the third combinational circuit 130 can be an offset that is otherwise adjusted relative to the clock signal of the PLL 120. This operation can improve the performance of the system (e.g., increase f max , reducing energy or reducing pipeline stages).

[0056] Reference Figure 2 , another schematic block diagram of a system for clock calibration and adjustment is provided. The block diagram depicts a data path between a first semiconductor die 102 and a second semiconductor die 104. As with other aspects of the present disclosure, in some embodiments, a reference of a semiconductor die can be applied to functional clocks corresponding to the same monolithic die, circuit board, interposer, etc.

[0057] The clock input 202 is provided from the first semiconductor die 102 to the second semiconductor die 104. In particular, the clock input 202 is provided by the conductive element 204 of the first semiconductor die 102 to the conductive element 206 of the second semiconductor die 104. The conductive elements 204, 206 may include, for example, terminals of through silicon vias (TSVs) or other inter-layer vias (ILVs), bumps, pillars, etc. (e.g., copper pillars of hybrid bonding). Further conductive elements may include metallization layers disposed on the respective dies.

[0058] The additional conductive element may transmit a data signal (e.g., a forward data signal 208) from the first semiconductor die 102 to the second semiconductor die 104 via respective conductive elements 210, 212 of the first and second semiconductor dies 102, 104. The forward data signal 208 may include various values ​​or states transformed according to propagation through various circuit portions. The forward data signal 208 may be timed based on the clock input 202 or may include an embedded clock (e.g., which may be a digital link). Likewise, a return data signal 214 may extend between respective conductive elements 216, 218 of the first and second semiconductor dies 102, 104. The return data signal 214 may correspond to the clock input 202 (e.g., according to the embedded clock), or another clock may be passed from the second semiconductor die 104 to the first semiconductor die 102 along the return path.

[0059] The clock network may include various gates for the clock. For example, the gate may include a buffer configured to maintain clock integrity or a delay element configured to adjust clock skew based on, for example, the routing path of the clock. Additional or fewer gates may be provided depending on various circumstances. For example, the gate may be established, configured, or designed according to circuit layout, according to various design rules (DRCs). In particular, the clock input 220 may be received by one or more gates, such as a first gate 224 of a circuit that gates the first semiconductor die 102. For example, the first gate 224 may transmit a clock from a first synchronization device 228 for an input 222 of a forward data signal 208 configured to provide a forward data signal 208, which may be based on a first combinational circuit 230. The second gate 226 may transmit a clock signal to the second semiconductor die 104.

[0060] After receiving at the second semiconductor die 104, the third gate 232 may transmit the clock from the clock input 202 to another gate (e.g., the fourth gate 234, the fifth gate 236, or the sixth gate 238) of the second semiconductor die 104. The gates 234, 236, 238 may transmit the signal propagation from the corresponding synchronization device. For example, the second synchronization device 240 may gate the received signal (e.g., transformed by the second combinational circuit 242) in response to the forward data signal 208 to provide the forward data signal 208 to the third combinational circuit 244 for further transformation of the forward data signal 208. According to various transformations, the return data signal 214 may be generated in response to the forward data signal 208. In fact, although referred to as "forward data signal 208" and its transformation and "return data signal 214" and its transformation, the boundaries between the forward and return portions of the data path may vary according to convention and are not intended to be limiting. As depicted, the return path includes a third synchronizer 246 that gates a fourth combinatorial circuit 248 and a fourth synchronizer 250 that gates a fifth combinatorial circuit 252 that provides a return data signal 214 across the inter-chip interface 106 .

[0061] Each element of the first and second semiconductor dies 102, 104 may include skew, voltage levels, temperature, or other properties based on manufacturing variations. In addition, the inter-chip interface 106 may impose a further variable delay or absolute delay σ, such as a delay (σ) from the first semiconductor die 102 to the second semiconductor die 104. 1-2 ) or the delay (σ 2-1 ). Therefore, the clock signal input 202 transmitted from the second gate 226 may be skewed (μ) by a factor equal to the process variation (μ) of the first semiconductor die 102. 1 ) and the circuit skew (Δn 1 ) is described by the accumulated skew (Δ) of the output of the second semiconductor die 104. The total delay at the output close to the second semiconductor die 104 can be described by μ 1 +Δn 1 Description (eg, where the delay σ of the clock signal input 202 matches the delay σ of the forward data signal 208).

[0062] The input of the first semiconductor die 102 (e.g., the conductive element 216 configured to receive the signal of the return data signal 214) may receive a combination of the signal skewed by the delay σ of the inter-chip interface 106 and the skew of the second semiconductor die 104. That is, a portion of the skew may be represented as μ 2 +Δn 2 The skew may be relative to the signal μ provided to the second semiconductor die 104. 1 +Δn 1In addition, the chip-to-chip interface can cause delays σ 1-2 , σ 2-1 , but the variability of this delay may be somewhat consistent between signals (eg, the inter-chip interface 106 may be substantially balanced for the various connections).

[0063] The signal may cause further skew before being received at a component of the first semiconductor die 102, such as the sampling circuit 122, such as the sixth combinational circuit 254 gated by the clock of the clock input 220. Thereafter, the return signal may travel to a return signal path that may include the sampling circuit 122, additional logic, etc. The sixth combinational circuit 254 may be gated by the fifth synchronizer 256.

[0064] The gating of the fifth synchronizer 256 may be based on the variable gate 258. That is, the variable gate 258 may be a component of the MFG 126, and then the return signal may be gated based on the phase shift signal, phase shifted to increase the setup or hold margin. This phase shift may be in response to the skew accumulation, which includes the skew μ received by the first semiconductor die 102. 1 +Δn 1 +σ 21 and any additional manufacturing differences μ of the second semiconductor die 104 2 or by the circuit skew Δn of the second semiconductor die 104 2 That is, MFG 126 can be based on μ 1 +Δn 1 +σ 21 +μ 2 +Δn 2 The accumulated (e.g., additive or subtractive) skew of the received signal is used to adjust the gating of the received signal. Thus, a skew range may be received by the system 100. By determining the clock skew of the return signal, the system 100 may minimize the variation so that at design time, the design may not be configured to tolerate the full range of potential skews. Thus, the process variation skew may be adjusted to reduce the total skew, where the remaining skew (e.g., temperature, aging, etc.) may be included in the timing closure or may be further defined by periodic calibration and adjustment or by receiving further data (e.g., input of temperature, frequency, aging data, etc.) by the controller 124 as described above.

[0065] Reference Figure 3, another schematic block diagram 300 is provided, which includes a first semiconductor die 102 connected to various second semiconductor dies 104A, 104B, 104C, 104D (collectively referred to as second semiconductor dies 104). The PLL 120 or other clock source can provide the same or separate clock signals via corresponding conductive elements 302A, 302B, 302C, 302D. The various second semiconductor dies 104A, 104B, 104C, 104D can have various sequential and combinational logic, temperatures, voltage levels, etc. that can cause variable clock skew. The various second semiconductor dies 104A, 104B, 104C, 104D can pass a return signal to the first semiconductor die 102 via the corresponding conductive elements 304A, 304B, 304C, 304D. For example, the return signal can include a discrete clock or a clock recovered from a data signal. The sampling circuit 122 may determine a phase shift of the signal corresponding to each of the second semiconductor dies 104 , which may increase the timing margin at the first semiconductor die 102 .

[0066] The controller 124 may cause the MFG 126 to adjust the phase of one or more signals. That is, the MFG 126 may receive a signal from the PLL 120 and a signal from the second semiconductor die 104 to generate a signal based thereon. For example, the MFG 126 may generate a first clock signal 306A, a second clock signal 306B, a third clock signal 306C, and a fourth clock signal 306D to gate a data signal received from the corresponding second semiconductor die 104. The clock signal may be generated by a buffer, a delay, an element, or other MFG 126 portion. For example, the clock signal may be generated according to a register value mapped to a phase shift step, according to one or more steps corresponding to the phase shift.

[0067] Reference Figure 4 , depicts a representation 400 of a data path transition from the second semiconductor die 104 to the first semiconductor die 102. The data path propagates from a second data signal 404 propagating according to the FF corner of the second semiconductor die 104 to a first data signal 402 propagating according to the SS corner of the first semiconductor die 102. The digital signals 402, 404 are depicted along with corresponding clock signals, which are depicted as a first clock signal 406 for the first semiconductor die 102 and a second clock signal 408 for the second semiconductor die 104.

[0068] An example of a typical (TT) signal 410 is provided, which corresponds to the nominal clock transition time of the second clock 408. Depending on time, temperature, manufacturing process, supply voltage, number of stages in a pipeline of a data flow (e.g., clock cycles), or other variations across semiconductor dies or groups thereof. Some signals may propagate faster, causing the clock to transition faster (as depicted by FF signal 412) or transition according to a delay (as depicted by SS signal 414). That is, the signal may arrive earlier in time (as depicted) or the circuit may resolve a lower or higher voltage to a defined state, causing the signal to resolve faster. The window between the arrival of the FF signal 412 and the SS signal 414 relative to a stable data signal may be referred to as clock uncertainty 420 or setup and hold time.

[0069] The phase shift 416 of the first clock signal 406 may be defined according to the setup and hold times associated with the information associated with the first data signal 402. The phase shift 416 may extend a time that is less than the offset 418 between the first clock 406 and the second clock 408. That is, the phase shift 416 may be relative to a predefined offset 418 from the second clock 408. The phase shift 416 may be configured to maintain a spacing between the data sampling periods (e.g., setup and hold times or clock uncertainty 420) of the rising edge of the second clock 408. The spacing may be centered or otherwise increased in spacing from (or reduced in overlap with) the setup or hold times.

[0070] As depicted, the phase shift 416 of the first clock 406 can be aligned with the stable data signal by adjusting the setup margin 422 between the convergence of one setup and hold time 424 and the clock uncertainty of the rising edge of the first clock 406. In addition, the hold margin 426 defines the margin between the convergence of the uncertainty of the rising edge of the clock and the subsequent opening of another setup and hold time 428.

[0071] The position of the setup and hold times may vary depending on the relative performance of the first semiconductor die 102 and the second semiconductor die 104, such as depending on temperature, manufacturing process, or supply voltage. For example, as depicted, the SS corner of the first die 102 may correspond to a setup and hold time 424 that is extended beyond nominal, such that the clock uncertainty 420 may overlap therewith if the second clock 408 is not phase shifted. That is, the phase shift 416 of the second clock signal 408 may be greater than the setup margin 422.

[0072] Reference Figure 5, another representation 500 of a data path transition from another instance of the second semiconductor die 104 to another instance of the first semiconductor die 102 is depicted. The data path propagates from a second data signal 404 propagating according to the SS corner of the second semiconductor die 104 to a first data signal 402 propagating according to the FF corner of the first semiconductor die 102. The digital signals 402, 404 are depicted along with corresponding clock signals, which are depicted as a first clock signal 406 for the first semiconductor die 102 and a second clock signal 408 for the second semiconductor die 104.

[0073] The phase shift 502 of the first clock signal 408 relative to Figure 4 The phase shift 416 of is negative. The phase shift 502 is positive relative to the offset 418 between the first clock 406 and the second clock 408. Figure 4 The depicted phase shift 502 may be configured to increase timing margins by increasing the phase shift 416. That is, the phase shift 502 may increase the hold margin 510 or the setup margin 506. For example, the phase shift 502 may be configured to center the clock uncertainty 420 between the previous setup and hold period 508 and the subsequent setup and hold period 512. The phase shift 502 may improve margins, wherein the performance of a particular die or a group of dies may be improved.

[0074] Reference Figure 6 , which is a flow chart showing the operation of a method 600 of circuit operation according to some embodiments. In operation 602, a first signal is received. The signal may be received from a component of the first semiconductor die 102, such as the PLL 120 or other portion of a clock network, or a crystal oscillator, a microelectromechanical system (MEMS) oscillator, or other device external to the die. The signal may be, include, or be derived from a periodic clock signal. The signal may be received at one or more conductive elements, such as device interconnects, terminals, or the like.

[0075] In operation 604, the first signal is transmitted to the second semiconductor die 104. The signal may be transmitted by another conductive element. The signal may be transmitted via a microbump, an interposer, a via structure, a copper pillar, etc. For example, the signal may be transmitted between corresponding interconnects of a hybrid bond. The hybrid bond may include many connections so that other signals (e.g., data signals) provided with the signal (e.g., gated by a clock signal) may include similar propagation delays across the bond interface. The transmission may be along any number of conductive elements, such as symmetrical connectors of two semiconductor dies.

[0076] In operation 606, a second signal is received at the first semiconductor die 102. The second signal may be derived from the signals of operations 602 and 604. For example, the second signal may be the output of one or more circuits to which the signal of operation 602 or 604 is an input (e.g., an input clock of a synchronization device). The second signal may be or include the same frequency as the first signal. For example, the second signal may be a phase shifted instance of the first signal or may be a data stream including a clock at the same frequency as the first signal. The offset may vary according to manufacturing, temperature, voltage, or other properties of the first semiconductor die 102, the second semiconductor die 104, or another component (e.g., an interconnect, a dielectric, or other device portion).

[0077] In operation 608, a first phase shift is determined. For example, the sampling circuit 122 may determine the phase shift based on the signal of operation 602 and the second signal of operation 606. For example, in some embodiments, the phase shift may be a shift between the signal of operation 602 and the second signal of operation 606. In some embodiments, the phase shift of the second signal is a phase shift of a predefined offset from the signal of operation 602. For example, the predefined offset may be an offset fill level setting between two semiconductor dies, and the determined phase shift may be adjusted therefor.

[0078] In operation 610, a third signal is generated based on the phase shift. For example, the third signal may be an output clock configured to interface at the first semiconductor die 102 with a signal received from a data path including the second semiconductor die 104. The generated signal may be configured to increase setup or hold margin (e.g., to center clock transitions of stable data in time). The adjustment may include, for example, a register value mapped to the phase shift so that the controller can register the phase shift according to a predefined increment (e.g., 1°, 5°, etc.). That is, the predefined offset may be selected to increase setup margin or hold margin. In operation 612, the third signal is provided to the combinational logic of the first semiconductor die 102. For example, a synchronization device that may be configured to gate a data path extending from the second semiconductor die 104 is provided.

[0079] Reference to "or" may be interpreted as inclusive, such that any term described using "or" may indicate any of a single, more than one, and all of the described terms. Reference to at least one of a conjunction list of terms may be interpreted as an inclusive "or" to indicate any of a single, more than one, and all of the described terms. For example, reference to "at least one of 'A' and 'B'" may include only 'A', only 'B', and both 'A' and 'B'. Such references used in conjunction with "includes" or other open terms may include additional items.

[0080] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in conjunction with transmission spatial streams, sounding frames, responses, and subsets of devices to identify or distinguish them from each other. These terms are not intended to relate entities (such as first device and second device) only in time or according to a sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (such as reader elements, writer elements, or magnetic media) that can operate in a system or environment. It should be understood that the above-mentioned system may provide multiple of any or each of these components and these components may be provided on a stand-alone machine or, in some embodiments, multiple machines in a distributed system. In addition, the bit field position may be changed and multi-bit words may be used. In addition, the above-mentioned systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or tapes). The program may be implemented in any programming language (such as LISP, PERL, C, C++, C#) or any byte code language (such as JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture. In addition, the above-described systems and methods may be provided as hardware circuits (e.g., finite state machines) defined in a register transfer logic (RTL) language (e.g., VHDS, Verilog, SystemVerilog, or the like).

[0081] The term "coupled" and its variations include two components being directly or indirectly connected to each other. The term "electrically coupled" and its variations include two components being directly coupled to each other or indirectly connected through a conductive material (e.g., metal or copper traces). This connection may be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). This connection may be achieved by two components being directly coupled to each other, by two components being coupled to each other using a separate intermediary component and any additional intermediate components that are coupled to each other, or by two components being coupled to each other using an intermediary component that is integrally formed as a single entity with one of the two components. If "coupled" or its variations are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the colloquial language meaning of the additional terms (e.g., "directly coupled" means that two components are connected without any separate intermediary components) to result in a narrower definition than the general definition of "coupled" provided above. This coupling may be mechanical, electrical (e.g., magnetic), or fluid.

[0082] Although the above written description of the methods and systems enables one of ordinary skill in the art to make and use embodiments thereof, one of ordinary skill in the art should understand and appreciate the variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems of the present invention should not be limited by the above-described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A device comprising: a first conductive element configured to receive a first signal at a first functional block of the device; a second conductive element configured to transmit the first signal to a second functional block of the device; a third conductive element configured to receive a second signal from the second functional block of the device, the second signal varying from the first signal according to a phase shift; a first circuit configured to determine the phase shift between the first signal and the second signal; and A second circuit is configured to generate a third signal based on the phase shift, the first signal, and the second signal, wherein the third signal has a same frequency.

2. The device according to claim 1, wherein: The first signal is a first clock signal input to the first functional block; The third signal is a second clock signal input to the second functional block; and The second signal is a clock signal output from the second functional block. 3 . The device of claim 1 , wherein the first functional block is disposed on a first semiconductor die of the device and the second functional block is disposed on a second semiconductor die of the device. 4 . The device of claim 3 , wherein the first semiconductor die is a first node and the second semiconductor die is a second node different from the first node. 5 . The apparatus of claim 3 , wherein a first core voltage of the first semiconductor die is different from a second core voltage of the second semiconductor die.

6. The device according to claim 3, wherein: The first semiconductor die is configured to be coupled with a plurality of semiconductor dies including the second semiconductor die; The first circuit is configured to determine a plurality of phase shifts for each of the plurality of semiconductor dies; and The second circuit is configured to adjust a phase of each of the plurality of semiconductor dies.

7. The device according to claim 1, wherein: The first circuit is configured to compare the first signal with the second signal to generate a representation of the phase shifted to a plurality of predefined phases and to communicate the representation to the second circuit; and A third circuit is configured to select a predefined register value corresponding to the second circuit, the predefined register value corresponding to the phase shift.

8. The device according to claim 7, wherein: The first circuit and the second circuit are components of an analog domain of the first functional block, and the third circuit is a component of a digital domain of the first functional block.

9. The device of claim 1, wherein the second circuit comprises a multi-phase generator configured to: Receiving the first signal from a phase-locked loop (PLL); phase-shifting the first signal to generate the third signal; and The third signal is communicated to the first functional block, wherein the first signal from the PLL is communicated to the second functional block.

10. The device according to claim 3, wherein: The first conductive element comprises a metal interconnect disposed over an active surface of the first semiconductor die; The second conductive element comprises a first metal interconnect of a hybrid bond between the first semiconductor die and the second semiconductor die; and The third conductive element includes the hybrid-bonded second metal interconnect.

11. A system comprising: A first semiconductor die comprising: a first conductive element configured to receive a first signal; a second conductive element configured to transmit the first signal to a second semiconductor die; a third conductive element configured to receive a second signal from the second semiconductor die, the second signal varying from the first signal according to a phase shift; a first circuit configured to determine the phase shift between the first signal and the second signal; and a second circuit configured to generate a third signal based on the phase shift, the first signal, and the second signal, wherein the third signal has a same frequency; and the second semiconductor die.

12. The system of claim 11, wherein: The first signal is a first clock signal input to the first semiconductor die; The third signal is a second clock signal input to the second semiconductor die; and The second signal is a clock signal output from the second semiconductor die.

13. The system of claim 11, wherein: The first semiconductor die is configured to be coupled with a plurality of semiconductor dies including the second semiconductor die; The first circuit is configured to determine a phase shift for each of the plurality of semiconductor dies; and The second circuit is configured to adjust a phase output of each of the plurality of semiconductor dies.

14. The system of claim 11, wherein: The first circuit is configured to compare the first signal with the second signal to generate a representation of the phase shifted to a plurality of predefined phases and to communicate the representation to a third circuit; and The third circuit is configured to select a predefined register value, the predefined register value corresponding to the phase shift.

15. The system of claim 11, wherein the first semiconductor die comprises: an analog domain, comprising the first circuit and the second circuit; and A digital domain includes the second circuit.

16. The system of claim 11, wherein the second circuit comprises a multi-phase generator configured to: Receiving the first signal from a phase-locked loop (PLL); phase-shifting the first signal to generate the third signal; and The third signal is communicated to the first semiconductor die, wherein the first signal from the PLL is communicated to the second semiconductor die.

17. A method comprising: receiving a first signal at a first conductive element of a first semiconductor die; transmitting the first signal to a second semiconductor die by a second conductive element of the first semiconductor die; receiving a second signal at a third conductive element of the first semiconductor die; determining a first phase shift between the first signal and the second signal; generating a third signal according to a second phase shift from the first signal in response to the first phase shift; and The third signal is provided to combinatorial logic of the first semiconductor die.

18. The method of claim 17, wherein determining the first phase shift comprises: comparing the first signal to the second signal to produce a representation of the first phase shifted to a plurality of predefined phases; and A predefined register value is selected, the predefined register value corresponding to the second phase shift.

19. The method according to claim 18, wherein: The determining of the first phase shift and the generating of the third signal are performed in an analog domain of the first semiconductor die; and The selection of the predefined register value is performed in a digital domain of the first semiconductor die, the digital domain including the combinatorial logic.

20. The method of claim 17, wherein generating the third signal comprises: Receiving the first signal from a phase-locked loop (PLL); phase shifting the first signal to generate the third signal; and The third signal is communicated to the first semiconductor die, wherein the first signal from the PLL is communicated to the second semiconductor die.

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