Neural Network-Based Analog Circuit Design Method

Abstract

This application relates to a method, apparatus, device, and medium for designing analog circuits based on neural networks. The method includes: acquiring a training dataset for analog circuit design; designing the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators; identifying the number of neurons in the initial neural network, and determining the processing mode and spatial distribution of the neuron circuit modules on the training dataset based on the number of neurons; designing the analog circuit according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit with a multi-level complex neuron group; and training the multi-level complex neuron group neural network training circuit using the training dataset to obtain a simulation-verified neural network circuit model. The entire scheme can achieve efficient and accurate analog circuit design.

Description

Technical Field

[0001] This application relates to the field of analog circuit design technology, and in particular to an analog circuit design method, apparatus, computer device, storage medium and computer program product based on neural networks. Background Technology

[0002] In recent years, neural networks have been widely used due to their ability to handle complex training tasks, becoming one of the important approaches to realizing artificial intelligence. Neural network training algorithms require carefully designed network structures, which are often limited by resources, cost, and computational efficiency. Optimizing the neural network implementation structure by designing circuit systems composed of underlying devices to realize hardware neural networks has become an effective solution, improving overall computing speed and reducing system component costs.

[0003] Neuron-level chip design primarily encompasses various methods, including digital, analog, mixed-signal, and programmable chip implementations. Signal digitization facilitates the detection, reception, processing, and information extraction of complex signals. Existing hardware neuron implementations are based on setting signal transmission thresholds, defining signal input / output lookup tables, and utilizing computational units. Digital implementation is relatively simple, offers high signal-to-noise ratios, and is easy to cascade. However, digital neurons require powerful hardware support, and digital multipliers operate slowly. This not only consumes significant chip area for storage and computation but also relies on analog control bit and output conversion, greatly increasing overall power consumption.

[0004] It is evident that there is an urgent need for an efficient and simple analog circuit design solution. Summary of the Invention

[0005] Therefore, it is necessary to provide an efficient and simple neural network-based analog circuit design method, device, computer equipment, storage medium, and computer program product to address the aforementioned technical problems.

[0006] Firstly, this application provides a neural network-based analog circuit design method. The method includes:

[0007] Obtain the training dataset for analog circuit design;

[0008] Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design;

[0009] Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons;

[0010] Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group.

[0011] The neural network training circuit of the multi-level complex neuron group is trained using the training dataset to obtain a simulation-verified neural network circuit model.

[0012] In one embodiment, the acquisition of the training dataset for the analog circuit design includes:

[0013] Obtain the necessary data and input voltage domain for analog circuit design;

[0014] The training dataset is obtained by mapping the required data and the input voltage domain.

[0015] In one embodiment, the activation function type for designing the analog circuit design based on the training dataset and circuit model metrics includes:

[0016] Based on the training dataset and circuit model metrics, determine the types of components in the analog circuit and the operating modes of different components in the analog circuit.

[0017] The type of target analog input signal is determined based on the type of components and the operating mode of the analog circuit.

[0018] Based on the target analog input signal type, the activation function type corresponding to the analog circuit design is selected. In one embodiment, the analog circuit component types include NMOS and PMOS;

[0019] Determining the target analog input signal type based on the types of components and operating mode of the analog circuit includes:

[0020] Based on the types of components and operating mode of the analog circuit, determine the corresponding level signals for the input and output signals of the analog circuit;

[0021] The type of the target analog input signal is determined based on the corresponding level signal.

[0022] In one embodiment, the activation function includes Sigmoid and Tanh.

[0023] In one embodiment, before obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network, the method further includes:

[0024] The transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model verified by the simulation are obtained.

[0025] By using a negative feedback system to adjust the feedforward transmission, the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model verified by simulation are obtained.

[0026] Based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), the neural network circuit model verified by the simulation is tested to determine whether it is qualified.

[0027] If it is not qualified, then return to the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators.

[0028] In one embodiment, the detection of whether the simulated neural network circuit model is qualified, based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, the input signal relationship function IN(s), and the output signal relationship function OUT(s), includes:

[0029] Determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), satisfy the input signal relationship in the output signal domain; wherein, the input signal relationship in the output signal domain is:

[0030]

[0031] Secondly, this application also provides an analog circuit design apparatus based on a neural network. The apparatus includes:

[0032] The dataset acquisition module is used to acquire training datasets for analog circuit design.

[0033] The type selection module is used to design the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators.

[0034] The identification module is used to identify the number of neurons corresponding to the initial neural network, and to determine the processing mode and spatial distribution of the training dataset by the neuron circuit module based on the number of neurons.

[0035] The model building module is used to design analog circuits based on the activation function type and the determined processing mode and spatial distribution, and to build a neural network training circuit with a multi-level complex neuron group.

[0036] The model training module is used to train the neural network training circuit of the multi-level complex neuron group using the training dataset to obtain a neural network circuit model for simulation verification.

[0037] The design module is used to obtain the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network.

[0038] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0039] Obtain the training dataset for analog circuit design;

[0040] Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design;

[0041] Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons;

[0042] Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group.

[0043] The neural network training circuit of the multi-level complex neuron group is trained using the training dataset to obtain a simulation-verified neural network circuit model.

[0044] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0045] Obtain the training dataset for analog circuit design;

[0046] Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design;

[0047] Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons;

[0048] Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group.

[0049] The neural network training circuit of the multi-level complex neuron group is trained using the training dataset to obtain a simulation-verified neural network circuit model.

[0050] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0051] Obtain the training dataset for analog circuit design;

[0052] Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design;

[0053] Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons;

[0054] Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group.

[0055] The neural network training circuit of the multi-level complex neuron group is trained using the training dataset to obtain a simulation-verified neural network circuit model.

[0056] The aforementioned neural network-based analog circuit design method, apparatus, computer equipment, storage medium, and computer program products acquire a training dataset for analog circuit design; based on the training dataset and circuit model indicators, design the activation function type corresponding to the analog circuit design; identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons; design the analog circuit according to the activation function type and the determined processing mode and spatial distribution, constructing a neural network training circuit with a multi-level complex neuron group; train the multi-level complex neuron group neural network training circuit using the training dataset to obtain a simulation-verified neural network circuit model. Throughout the process, the training dataset and activation function type are specifically acquired based on the actual situation of the analog circuit. Based on the selected activation function type and the determined processing mode and spatial distribution, a multi-level complex neuron group neural network training circuit is specifically constructed and trained, enabling efficient and accurate analog circuit design. Attached Figure Description

[0057] Figure 1 This is an application environment diagram of a neural network-based analog circuit design method in one embodiment;

[0058] Figure 2 This is a schematic diagram of a basic MOSFET structure;

[0059] Figure 3 It is an NMOS transistor operating in the deep transistor region;

[0060] Figure 4 This is a block diagram of a negative feedback system.

[0061] Figure 5 This is a flowchart illustrating a neural network-based analog circuit design method in one embodiment.

[0062] Figure 6 This is a flowchart illustrating a neural network-based analog circuit design method in another embodiment;

[0063] Figure 7 Design a flowchart for partial classification patterns;

[0064] Figure 8(a) shows the partial classification mode design of PMOS+NMOS;

[0065] Figure 8(b) shows one of the classification modes of PMOS+NMOS;

[0066] Figure 8(c) shows the second classification mode design of PMOS+NMOS;

[0067] Figure 8(d) shows the third type of PMOS+NMOS partial classification design;

[0068] Figure 9(a) shows the partial classification mode design of NMOS+PMOS;

[0069] Figure 9(b) shows one of the classification modes of NMOS+PMOS design;

[0070] Figure 9(c) shows the second classification mode design of NMOS+PMOS;

[0071] Figure 9(d) shows the third type of NMOS+PMOS partial classification design;

[0072] Figure 10 This is a structural block diagram of an analog circuit design device based on a neural network in one embodiment;

[0073] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0075] The neural network-based analog circuit design method provided in this application can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or placed on a cloud or other network server. Terminal 102 sends an analog circuit design request to server 104. Server 104 responds to the design request by obtaining the training dataset for the analog circuit design; based on the training dataset and circuit model indicators, it designs the activation function type corresponding to the analog circuit design; identifies the number of neurons corresponding to the initial neural network, and determines the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons; performs analog circuit design according to the activation function type and the determined processing mode and spatial distribution, constructing a neural network training circuit with a multi-level complex neuron group; and trains the neural network training circuit with the multi-level complex neuron group using the training dataset to obtain a simulation-verified neural network circuit model. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0076] To explain in detail the technical principles and effects of the neural network-based analog circuit design method of this application, the basic principles and theoretical basis involved in this application will be introduced first.

[0077] I. Basic Principles of MOSFETs

[0078] Figure 2 The basic MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a metal-oxide-semiconductor field-effect transistor, abbreviated as MOS transistor. Among them, the MOS that conducts electricity using N-type (ion with a chemical bond of 5 valence) charge carriers is called NMOS, and the MOS that conducts electricity using P-type (ion with a chemical bond of 3 valence) charge carriers is called PMOS. A pair of complementary NMOS and PMOS transistors constitutes CMOS.

[0079] Taking NMOS as an example, after it is turned on, it satisfies the current formula:

[0080]

[0081] Among them, I D This represents the drain-to-source current of a MOSFET, measured in amperes (A); μ n This represents electron carrier mobility, measured in square meters per volt-second (m).2 / (V*s); C ox This represents the gate oxide capacitance per unit area, expressed in farads per square meter (F / m). 2 L represents the lateral dimension of the gate along the source-drain channel—the gate length, in meters (m); W represents the gate width perpendicular to the gate length, in meters (m). A MOSFET contains three terminals: gate (G), source (S), and drain (D). V GS This represents the gate-source voltage difference of a MOSFET, measured in volts (V). TH This represents the channel turn-on threshold voltage of a MOSFET, measured in volts (V). DS λ represents the drain-source voltage difference of a MOSFET, measured in volts (V). λ represents the channel length modulation factor, which is dimensionless.

[0082] When V GS ≤V TH At this time, the channel of the MOSFET cannot form a conductive path, and no current flows through the source and drain of the MOSFET. The current formula for the MOSFET simplifies to the following:

[0083] I D ≈0

[0084] When V GS >V TH And V DS <V GS -V TH At this time, the MOS device will operate in the "transistor region". If V DS <<2(V) GS -V TH In this state, the MOS device will operate in the "deep transistor region," and the channel length modulation effect can be ignored. The source-drain current can be obtained using the MOS transistor current formula at this time:

[0085]

[0086] At this time, the drain current is approximately V. DS The source-drain path is a linear function, and can be represented by a linear resistance. For example... Figure 3 As shown, an NMOS transistor operating in the deep transistor region is equivalent to a voltage-controlled drain-source resistor R. on_linear According to Ohm's law, R = V / I, R on The resistance value is given by the following formula:

[0087]

[0088] When V GS >V TH And V DS ≥V GS -VTH At this time, the MOS device will operate in the "saturation region". Based on the MOS transistor's current formula and its channel pinch-off characteristic, the source and drain currents at this point can be obtained as follows:

[0089]

[0090] At this time, the drain current is approximately V. DS The source-drain path can still be represented by a linear resistance, which is a linear function of the source-drain path. Figure 3 Similarly, an NMOS transistor operating in the saturation region is also equivalent to a drain-source resistance R controlled by the drain-source voltage. on_sat According to Ohm's law, R = V / I, R on_sat The resistance value is given by the following formula:

[0091]

[0092] II. Negative Feedback Regulation Principle

[0093] Figure 4 The diagram illustrates a typical negative feedback system. The transfer function of the feedforward transmission network is H(s), and the transfer function of the feedback transmission network is G(s). According to the signal feedback path, after the feedback network detects the output change ΔOUT(s), it passes through an inverting unit and is added to the input signal at the adder to obtain the error signal IN(s) - G(s) * OUT(s). Subsequently, the error is amplified by the feedforward path, and the output is corrected, causing the output signal to return to the expected value. Therefore, the relationship of the output signal can be derived:

[0094] OUT n+1 (s)=H(s)*[IN(s)-G(s)*OUT n (s)]

[0095] Once the feedback system stabilizes, there is an OUT. n+1 (s)=OUT n (s) = OUT(s), the above formula is:

[0096] OUT(s) = H(s) * [IN(s) - G(s) * OUT(s)], thus the relationship between the output signal and the input signal can be obtained:

[0097]

[0098] When the amplification factor of the feedforward transmission network approaches infinity, i.e., H(s)≈∞, the above equation can be simplified to:

[0099]

[0100] Analyzing the above formula, we can obtain three types of results:

[0101] If G(s)≈∞, then OUT(s)≈0;

[0102] If G(s)≈0, then OUT(s)≈∞. In practice, due to constraints, OUT(s) can only reach the conditional extreme value.

[0103] If G(s)≈N, and N is a finite number, then

[0104] Based on the principles of analog integrated circuits, the design pattern adopted is described from multiple perspectives, including data processing, neuron distribution, activation function selection, and error training.

[0105] In one embodiment, such as Figure 5 As shown, a neural network-based analog circuit design method is provided, which can be applied to... Figure 1 Taking server 104 as an example, the following steps are included:

[0106] S100: Obtain the training dataset for analog circuit design.

[0107] To construct a training dataset, we first acquire the necessary data and input voltage domain for analog circuit design. Then, we perform data mapping based on this data and voltage domain. This data mapping fully leverages the classification options available from the existing data, preparing for subsequent model training.

[0108] Here, data mapping is performed based on the required data input and input voltage domain, including nonlinear feature processing and format screening, to fully explore the classification options that historical data can provide, in preparation for subsequent model training.

[0109] S200: Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design.

[0110] A circuit model is a mathematical model used to describe the interactions and energy conversions between various components in a circuit. Circuit model metrics typically refer to a set of parameters and standards used to quantify, evaluate, or describe the performance, behavior, or characteristics of a circuit. Specifically, circuit model metrics can include electrical characteristic metrics, frequency response metrics, dynamic performance metrics, stability metrics, power consumption and efficiency metrics, noise and interference metrics, etc. When designing analog circuits, different circuit models are selected for analysis and design based on the specific application scenario and performance requirements. Here, the activation function type corresponding to the analog circuit design is selected based on the obtained training data. Specifically, in the analog circuit design process, it is mainly necessary to consider the performance and resource balance selection circuit controlled by transistors, switches or data, and analog control bits. Furthermore, the classification module can implement the required activation function circuit through forward selection, with resource-biased design for forward selection controlled by control bits. The activation function can also support backward selection for the processed classification module, with computational performance advantages considered for backward selection controlled by control bits.

[0111] S300: Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons.

[0112] For the initial neural network that needs to be trained, the number of its corresponding neurons is identified, and the processing mode and spatial distribution of the neuron circuit modules on the training dataset are determined based on the number of neurons.

[0113] Specifically, the formula for the on-current of a transistor (taking NMOS as an example) is as follows:

[0114]

[0115] This facilitates the processing of nonlinear characteristics of data within neurons; pattern classification considers the input signal voltage domain. Under stable transistor operating conditions, taking a combination of high and low input levels as an example, the circuit exhibits the following operating characteristics:

[0116] 1)V IN1 =V IN1，l The first branch input is low, V IN2 =V IN2，l The second branch input is low, V out ∝V IN1，l +2V IN2，l ;

[0117] 2)V IN1 =V IN1，l The first branch input is low, V IN2 =V IN2，h The second branch input is high level, V out ∝VIN1，l +V IN2，h ;

[0118] 3)V IN1 =V IN1，h The first branch input is high level, V IN2 =V IN2，l The second branch input is low, V out ∝2V IN1，h +2V IN2，l ;

[0119] 4)V IN1 =V IN1，h The first branch input is high level, V IN2 =V IN2，h The second branch input is high level, V out ∝2V IN1，h +V IN2，h ;

[0120] Set the working conditions to V IN1，l <V low1 <V high1 <V IN1，h and V IN2，l <V low2 <V high2 <V IN2，h The following relationship exists, influenced by the threshold setting:

[0121] V IN1，l <V IN2，l <<V IN1，h <V IN2，h

[0122] Further analysis reveals that:

[0123] V IN1，l +2V IN2，l <V IN1，l +V IN2，h <2V IN1，h +2V IN2，l <2V IN1，h +V IN2，h

[0124] Clearly, based on the above inequality, the circuit design achieves the goal of having a maximum of four classification scenarios under two inputs. The activation function selected by S200 can then complete the subsequent classification compression.

[0125] S400: Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group.

[0126] The simulation circuit is designed based on the activation function type, determined processing mode, and spatial distribution. This includes designing the number of network layers, the number of neurons per layer, and the intra-layer and inter-layer communication relationships and modes. Intra-layer parallel computation improves computational efficiency. Specifically, after circuit startup, the current signal is transmitted layer by layer according to the designed pattern, exhibiting significant intra-layer parallelism until the final output is obtained. In simpler terms, the processing mode here refers to transforming the 4-class classification into the 3-class, 2-class, etc., classification required by the current application scenario. Spatial distribution refers to retrieving the encapsulated neuron circuits, arranging and connecting them, and then implementing the simulation circuit design for subsequent processing. In the constructed multi-level complex neuron group neural network training circuit, the core neuron circuits have been pre-designed; subsequent simulation circuit design is then carried out based on the activation function type, determined processing mode, and spatial distribution for their use.

[0127] S500: The training circuit of a neural network with a multi-level complex neuron group is trained using the training dataset.

[0128] The training dataset obtained from S100 is used to train a neural network training circuit with a multi-level complex neuron group, resulting in a simulation-verified neural network circuit model. Specifically, during training, the network parameters in the neural network can be continuously adjusted based on the output and input signals until the preset training termination conditions are met, thus obtaining the simulation-verified neural network circuit model. After constructing the neural network training circuit with a multi-level complex neuron group, the entire circuit is started, and feedback adjustments are made based on the existing training data to continuously train the entire multi-level complex neuron group neural network training circuit, ultimately obtaining a simulation-verified neural network circuit model. This simulation-verified neural network circuit model represents the designed analog circuit.

[0129] The aforementioned neural network-based analog circuit design method involves: acquiring a training dataset for the analog circuit design; designing the activation function type corresponding to the analog circuit design based on the training dataset and circuit model metrics; identifying the number of neurons in the initial neural network and determining the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons; designing the analog circuit according to the activation function type and the determined processing mode and spatial distribution, constructing a multi-level complex neuron group neural network training circuit; training the multi-level complex neuron group neural network training circuit using the training dataset to obtain a simulation-verified neural network circuit model; and obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network. Throughout this process, the training dataset and activation function type are specifically acquired based on the actual situation of the analog circuit. Based on the selected activation function type and the determined processing mode and spatial distribution, a multi-level complex neuron group neural network training circuit is specifically constructed and trained, enabling efficient and accurate analog circuit design.

[0130] like Figure 6 As shown, in one embodiment, S100 includes:

[0131] S120: Obtain the necessary data and input voltage domain for analog circuit design.

[0132] Before constructing the training dataset, it is necessary to first determine which data is essential for training the model. This data typically includes, but is not limited to: circuit parameters: such as the values ​​of components like resistors, capacitors, and inductors, as well as model parameters of nonlinear components like transistors and diodes; operating environment parameters: such as power supply voltage, temperature, and frequency, which affect circuit performance; design specifications: such as target output voltage range, current limits, and power consumption requirements, which define the goals of the circuit design; and historical design data: past successful or unsuccessful design data can serve as a reference to help the model learn the effective and ineffective regions of the design space.

[0133] S140: Perform data mapping based on the required data and the input voltage domain to obtain the training dataset.

[0134] The input voltage domain refers to the range or target value of the output voltage that is of interest in the circuit design. This is typically determined by the design specifications; for example, an amplifier might need to output a specific voltage range to meet the requirements of subsequent circuitry. Determining the input voltage domain is a crucial step in building the training dataset, as it guides the data collection and preprocessing processes. Once the required data is acquired and the input voltage domain is determined, the next step is data mapping to construct the training dataset. Data mapping involves converting circuit parameters, operating environment parameters, and design specifications into a format that the model can understand and generating corresponding output labels (in this case, the output voltage or a value within the voltage domain).

[0135] like Figure 6 As shown, in one embodiment, S200 includes:

[0136] S220: Based on the training dataset and circuit model metrics, determine the types of components in the analog circuit and the operating modes of different components in the analog circuit.

[0137] First, it is necessary to carefully analyze the analog circuit information contained in the training dataset, especially the components of the circuit (such as resistors, capacitors, inductors, transistors, diodes, etc.) and the operating modes of these components in the circuit (such as linear region, saturation region, cutoff region, etc.). This information is crucial for understanding the behavior and characteristics of the circuit.

[0138] S240: Determine the type of target analog input signal based on the types of components in the analog circuit and the operating mode of the analog circuit.

[0139] After understanding the components and operating mode of the circuit, the next step is to determine the type of the target analog input signal. This typically depends on the circuit's design purpose and operating environment. For example, if the circuit is an amplifier, the target input signal might be some form of AC signal; if the circuit is a filter, the target input signal might contain frequency components that need to be filtered out.

[0140] S260: Select the activation function type corresponding to the analog circuit design based on the target analog input signal type.

[0141] Activation functions are used in neural networks to introduce nonlinearity so that the model can learn complex mappings. In analog circuit design, the concept of an "activation function" can be analogized to nonlinear elements or circuit characteristics that determine how the circuit responds to different input signals. Depending on the type of the target analog input signal and the characteristics of the circuit, a suitable "activation function type" can be selected or designed. This essentially means determining which nonlinear elements or characteristics in the circuit will dominate the circuit's response to the input signal. For example, if a transistor in a circuit operates in the saturation region, its output characteristic might resemble a hard-limiting function, meaning that the output remains unchanged when the input exceeds a certain threshold. If the circuit contains multiple cascaded amplifiers, its overall response might be a composite function of multiple amplification stages, similar to multi-layered activation functions in deep neural networks.

[0142] Based on the introduced CMOS principles and negative feedback systems, a core classification model was designed. Figure 7 This is a partial classification mode block diagram, in which the error amplifier EA with high amplification and the active linear resistor Ract1 constitute a feedforward transmission network; MOSFET switches MS1 and MS2 are controlled by signal V. ctrl1 Vctrl2 Under the influence of these signals, a feedback transmission network is formed; the input port of the error amplifier EA introduces a signal to achieve inverted summation.

[0143] Based on the aforementioned classification pattern block diagram design, two sets of feedback circuits were further designed. These circuits, while ensuring circuit safety and normal operation, together constitute the combined pattern circuit for data classification. To establish the connection between digital signal representation and this design, 0 and 1 logic signals can be considered as low and high levels of analog signal input for classification. Specifically, analog signal input voltage below the threshold V... low When the input voltage of the analog signal is higher than the threshold voltage V, the default level is low. high When the time is high, the default level is high.

[0144] Taking the specific implementation of analog circuits as an example:

[0145] I. PMOS + NMOS

[0146] M1's gate is connected to V G，PMOS1 Voltage, the gate of M2 is connected to V G，NMOS2 The drains of M1 and M2 are connected. The inverting input of the operational amplifier is connected to V. IN1 Voltage, set V G，PMOS1 =V G，NMOS2 =V IN1 The circuit has three configurable operating modes (as shown in Figure 8(a)).

[0147] 1. M1 is not working, M2 is working.

[0148] V IN1 When the input is high, the principle of this working mode is shown in Figure 8(b). When M1 is not working, it is equivalent to an open switch. When M2 is working, it is equivalent to a closed switch connected in series with a resistor. At this time, V fb1 =0, the high gain characteristic of the error operational amplifier EA will reduce the active resistance M. p1 The resistance value makes the output V out1 It is strongly pulled up to the power supply voltage V DD V was obtained through negative feedback adjustment of the circuit. out1 =V DD .

[0149] 2. Work M1, Work M2

[0150] V IN1 The input is at the intermediate level. The principle of this operating mode is shown in Figure 8(c). The PMOS and NMOS used can work simultaneously within a certain voltage range. When M1 and M2 are working, they can be equivalent to a closed switch connected in series with a resistor. The negative feedback regulation characteristic of the loop will adjust the active resistor M. p1The resistance value makes... Through design The dimensions ensure that the resistance values ​​of M1 and M2 are considered equal within the tolerance range, then R PMOS1 =R NMOS2 Therefore, V can be derived. out1 =2V IN1 .

[0151] 3. M1 is working, M2 is not working.

[0152] V IN1 When the input is low (voltage not equal to 0, the level is considered 0), the principle of this working mode is shown in Figure 8(d). When M2 is not working, it is equivalent to an open switch. When M1 is working, it is equivalent to a closed switch connected in series with a resistor. At this time, V fb1 =V out1 The high gain characteristic of the error operational amplifier EA will adjust the active resistor M. p1 The resistance value makes the output V out1 Can be equal to input V IN1 That is, V was obtained through negative feedback adjustment of the circuit. out1 =V IN1 .

[0153] II. NMOS + PMOS

[0154] M3's gate is connected to V G，NMOS3 Voltage, the gate of M4 is connected to V G，PMOS4 The sources of M3 and M4 are connected, and depletion-mode MOS devices are used. The inverting input of the operational amplifier is connected to V. IN2 Voltage, set V G,NMOS3 =V G,PMOS4 =V IN2 The circuit has three configurable operating modes (as shown in Figure 9(a)).

[0155] 1. M3 is working, M4 is not working.

[0156] V IN2 When the input is high, the principle of this working mode is shown in Figure 9(b). When M4 is not working, it is equivalent to an open switch. When M3 is working, it is equivalent to a closed switch connected in series with a resistor. At this time, V fb2 =V out2 The high gain characteristic of the error operational amplifier EA will adjust the active resistor M. p2 The resistance value makes the output V out2 Can be equal to input V IN2 That is, V was obtained through negative feedback adjustment of the circuit. out2 =V IN2 .

[0157] 2. M3 work, M4 work

[0158] V IN2 The input is at the intermediate level. The principle of this working mode is shown in Figure 9(c). Although the NMOS can work simultaneously with the PMOS within a certain voltage range, when M3 and M4 are working, they can be equivalent to a closed switch connected in series with a resistor. The negative feedback regulation characteristic of the loop will regulate the active resistor M. p2 The resistance value makes... Through design The dimensions ensure that the resistance values ​​of M3 and M4 are considered equal within the tolerance range, then R PMOS4 =R NMOS3 Therefore, V can be derived. out2 =2V IN2 .

[0159] 3. M3 is not working, M4 is working.

[0160] V IN2 When the input is low, the principle of this operating mode is shown in Figure 9(d). When M3 is not working, it is equivalent to an open switch. When M4 is working, it is equivalent to a closed switch connected in series with a resistor. At this time, V fb2 =0, the high gain characteristic of the error operational amplifier EA will reduce the active resistance M. p2 The resistance value makes the output V out2 It is strongly pulled up to the power supply voltage V DD V was obtained through negative feedback adjustment of the circuit. out2 =V DD .

[0161] In one embodiment, the analog circuit components include NMOS and PMOS;

[0162] Determining the target analog input signal type based on the types of components and operating mode of the analog circuit includes: determining the corresponding level signals of the input and output signals of the analog circuit based on the types of components and operating mode of the analog circuit; and determining the target analog input signal type based on the corresponding level signals.

[0163] First, it's necessary to understand how the various components of an analog circuit (such as resistors, capacitors, inductors, and transistors) affect signal transmission and transformation. This includes understanding the electrical characteristics of the components, such as voltage-current relationships and frequency response. Next, based on the circuit topology and the operating modes of the components, analyze how the input signal passes through each part of the circuit and how these parts process the signal (e.g., amplification, attenuation, filtering). During this process, special attention needs to be paid to signal level changes, i.e., the voltage or current levels of the signal in the circuit. Through the above analysis, the signal level ranges of the input and output signals in the analog circuit can be determined. This typically involves parameters such as signal amplitude, DC bias, and AC component. After determining the signal levels of the input and output signals, the next step is to determine the type of the target analog input signal based on these signal levels.

[0164] Continuing with the NMOS and PMOS examples above, in the analysis above, the output is V. DD The working mode will significantly affect the classification results and will not be considered. Therefore, characteristic analysis will be added, and V will be selected. IN1 Input intermediate level and V IN2 The input intermediate level is respectively used as V IN1 The upper bound of the high level and V IN2 The lower bound of the low level.

[0165] V out1 and V out2 Then, a voltage-to-current conversion circuit is connected. With a reasonably designed resistance value, the currents are added together through parallel circuitry. The final voltage output can be determined based on V. IN1 and V IN2 The logic signal values ​​were simplified and calculated, and the results are shown in Table 1.

[0166] Table 1 Classification of Circuit Operating Modes

[0167]

[0168] Analysis shows that,

[0169] V IN1，l <V IN1，h V IN2，l <V IN2，h

[0170] Due to V IN1，l <V low1 <V high1 <V IN1，h and V IN2,l <V low2 <V high2 <V IN2,h Further analysis reveals that, due to the influence of the threshold setting, the following results can be obtained:

[0171] V IN1,l <V IN2,l < <V IN1,h <V IN2,h

[0172] Based on the working modes listed in the table, the calculation yields:

[0173] V IN1,l +2V IN2,l <V IN1,l +V IN2,h <2V IN1,h +2V IN2,l <2V IN1,h +V IN2,h

[0174] There is a direct proportional mapping relationship between the overall output of the module and the output of the sub-modules. Multiplying each term in the inequality by the mapping coefficient defined by the subsequent module yields the following output relationships:

[0175] V out,ll <V out,lh <V out,hl <V out,hh

[0176] At this point, two different sets of analog input signals can be fully classified. By using different activation functions, the number of classifications can be compressed to the required number, completing the initial training effect of the neural network and enabling its application in the inference process during operation.

[0177] Based on the above processing, the following analysis is made regarding the activation function type.

[0178] The classification circuit can achieve full classification of multiple input signals. To facilitate signal transmission, calculation, and use, an activation function is used to compress the existing results to achieve a better classification effect. Taking the four-class classification results as an example, the compressed classification is shown in Table 2.

[0179] Table 2 Classification Patterns of Activation Function Compression

[0180]

[0181] Some classification methods are not shown in the results. For example, the classification method consisting of four categories does not require special activation function processing, as it completes the classification after the classification mode finishes working.

[0182] Commonly used activation functions include Sigmoid, Tanh, ReLU, etc. In addition to functions that perform nonlinear transformations on the input information, linear activation functions can also be used.

[0183] The expression for the Sigmoid function is:

[0184]

[0185] The analytical expression of the Tanh function is:

[0186]

[0187] The mathematical expression for the ReLU function is:

[0188] ReLU = max(0, x).

[0189] (1) The “4+0” and “3+1” modes can be classified by setting the threshold;

[0190] (2) The derivative of the S-shaped curve can be obtained in the form of a parabolic function, which can be used to realize the "2+2" pattern classification.

[0191] (3) The S-curve can easily classify the input into a “1+2+1” pattern.

[0192] The Sigmoid function is a typical S-shaped curve. Based on the VI nonlinear curve of the CMOS transistor, the Sigmoid approximation curve is composed of four nonlinear curves. Since the intermediate values ​​of the independent variable are not directly expressed linearly, more accurate differential design can be obtained in practical applications, improving the mapping accuracy of the activation function compression method.

[0193] For each pair of CMOS connections, the NMOS and PMOS are given different gradient gate bias voltages, resulting in two segments of change from OFF to saturation, exhibiting an S-curve effect. As the input changes from negative to positive, the NMOS and PMOS are successively turned on, experiencing the output voltage change process caused by the change in the equivalent resistance of the MOS transistors, resulting in four continuous nonlinear Sigmoid approximate function curves, completing the post-processing of the classification circuit.

[0194] In one embodiment, before obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network, the method further includes:

[0195] Obtain the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model for simulation verification. Using a negative feedback system to adjust the feedforward transmission, obtain the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model for simulation verification. Based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, and the input signal relationship function IN(s) and the output signal relationship function OUT(s), check whether the neural network circuit model for simulation verification is qualified. If it is not qualified, return to design the corresponding activation function type for the analog circuit design based on the training dataset and circuit model indicators.

[0196] Before applying the simulated neural network circuit model, it is necessary to check whether the simulated neural network circuit model is qualified. Specifically, this checking process includes: determining whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), satisfy the input signal relationship in the output signal domain; wherein, the input signal relationship in the output signal domain is:

[0197]

[0198] Furthermore, a negative feedback system is used to adjust the feedforward transmission content. The transfer function of the feedforward transmission network is defined as H(s), and the transfer function of the feedback transmission network is defined as G(s). According to the signal feedback path, after the feedback network detects the output change ΔOUT(s), it passes through the inverting unit and is added to the input signal at the adder to obtain the error signal IN(s) - G(s) * OUT(s). Subsequently, the error is amplified by the feedforward path, and the output is corrected, causing the output signal to return to the expected value.

[0199] The output signal relationship is as follows:

[0200] OUT n+1 (s)=H(s)*[IN(s)-G(s)*OUT n (s)]

[0201] After the feedback system has stabilized, the relationship between the output signal and the input signal can be obtained as follows:

[0202]

[0203] If it is found that the output signal and input signal in the simulated neural network circuit model do not satisfy the above relationship, it is necessary to return to the steps of designing the activation function type corresponding to the simulation circuit design based on the training dataset and circuit model indicators, and start training again.

[0204] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0205] Based on the same inventive concept, this application also provides a neural network-based analog circuit design apparatus for implementing the aforementioned neural network-based analog circuit design method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the neural network-based analog circuit design apparatus provided below can be found in the limitations of the neural network-based analog circuit design method described above, and will not be repeated here.

[0206] In one embodiment, such as Figure 10 As shown, a neural network-based analog circuit design device is provided, comprising:

[0207] Data set acquisition module 100 is used to acquire training datasets for analog circuit design;

[0208] Type selection module 200 is used to design the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators;

[0209] The identification module 300 is used to identify the number of neurons corresponding to the initial neural network, and to determine the processing mode and spatial distribution of the training dataset by the neuron circuit module based on the number of neurons.

[0210] The model building module 400 is used to design analog circuits based on the activation function type, the determined processing mode, and the spatial distribution, and to build a neural network training circuit with a multi-level complex neuron group.

[0211] The model training module 500 is used to train a neural network training circuit with a multi-level complex neuron group using a training dataset, so as to obtain a neural network circuit model that can be verified by simulation.

[0212] In one embodiment, the dataset acquisition module 100 is further configured to acquire the required data and input voltage domain for analog circuit design; and to perform data mapping based on the required data and input voltage domain to obtain a training dataset.

[0213] In one embodiment, the type selection module 200 is further configured to determine the types of components in the analog circuit and the operating modes of different components in the analog circuit based on the training dataset and circuit model metrics; determine the type of target analog input signal based on the types of components in the analog circuit and the operating modes of the analog circuit; and select the activation function type corresponding to the analog circuit design based on the type of target analog input signal.

[0214] In one embodiment, the analog circuit component types include NMOS and PMOS; the type selection module 200 is further configured to determine the level signals corresponding to the input and output signals of the analog circuit based on the analog circuit component types and the analog circuit operating mode; and determine the target analog input signal type based on the corresponding level signals.

[0215] In one embodiment, the activation functions include Sigmoid and Tanh.

[0216] In one embodiment, the aforementioned neural network-based analog circuit design device further includes: a design module, used to obtain the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model for simulation verification; to obtain the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model for simulation verification by adjusting the feedforward transmission using a negative feedback system; to detect whether the neural network circuit model for simulation verification is qualified based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, the input signal relationship function IN(s), and the output signal relationship function OUT(s); if it is not qualified, the control type selection module 200 re-executes the design of the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators.

[0217] In one embodiment, the design module is further configured to determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), satisfy the output signal domain input signal relationship; wherein, the output signal domain input signal relationship is:

[0218]

[0219] The modules in the aforementioned neural network-based analog circuit design device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0220] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 11 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores preset data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a neural network-based analog circuit design method.

[0221] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0222] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described neural network-based analog circuit design method.

[0223] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described neural network-based analog circuit design method.

[0224] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described neural network-based analog circuit design method.

[0225] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0226] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0227] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A neural network-based analog circuit design method, characterized in that, The method includes: Obtain the training dataset for analog circuit design; Based on the training dataset and circuit model metrics, design the activation function type corresponding to the analog circuit design; The number of neurons corresponding to the initial neural network is identified, and the processing mode and spatial distribution of the neuron circuit module for the training dataset are determined based on the number of neurons. The processing mode refers to transforming the 4-class classification into the 3-class and 2-class classification required by the current application scenario. The spatial distribution refers to retrieving the packaged neuron circuits for arrangement and connection in order to realize the analog circuit design in subsequent processing. Based on the activation function type and the determined processing mode and spatial distribution, an analog circuit is designed to construct a neural network training circuit with a multi-level complex neuron group. The neural network training circuit of the multi-level complex neuron group is trained using the training dataset to obtain a simulation-verified neural network circuit model. The process of obtaining the training dataset for the analog circuit design includes: acquiring the required data and input voltage domain for the analog circuit design; and performing data mapping based on the required data and input voltage domain to obtain the training dataset. The step of designing the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators includes: determining the types of components in the analog circuit and the operating modes of different components based on the training dataset and circuit model indicators; determining the target analog input signal type based on the types of components in the analog circuit and the operating modes of the analog circuit; and selecting the activation function type corresponding to the analog circuit design based on the target analog input signal type. After training the neural network training circuit of the multi-level complex neuron group using the training dataset to obtain the simulation-verified neural network circuit model, the method further includes: obtaining the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the simulation-verified neural network circuit model; adjusting the feedforward transmission using a negative feedback system to obtain the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the simulation-verified neural network circuit model; based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, and the input signal relationship function IN(s) and the output signal relationship function OUT(s), detecting whether the simulation-verified neural network circuit model is qualified; if it is not qualified, then returning to the step of designing the activation function type corresponding to the simulation circuit design based on the training dataset and circuit model indicators.

2. The method according to claim 1, characterized in that, The analog circuit components include NMOS and PMOS; Determining the target analog input signal type based on the types of components and operating mode of the analog circuit includes: Based on the types of components and operating mode of the analog circuit, determine the corresponding level signals for the input and output signals of the analog circuit; The type of the target analog input signal is determined based on the corresponding level signal.

3. The method according to claim 1, characterized in that, The activation functions include Sigmoid and Tanh.

4. The method according to claim 1, characterized in that, The method for detecting whether the simulated neural network circuit model is qualified, based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, the input signal relationship function IN(s), and the output signal relationship function OUT(s), includes: Determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), satisfy the input signal relationship in the output signal domain; wherein, the input signal relationship in the output signal domain is:

5. A neural network-based analog circuit design device, characterized in that, The device includes: The dataset acquisition module is used to acquire training datasets for analog circuit design. The type selection module is used to design the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators. The identification module is used to identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module on the training dataset based on the number of neurons. The processing mode refers to transforming the 4-class classification into the 3-class and 2-class classification required by the current application scenario. The spatial distribution refers to retrieving the encapsulated neuron circuits for arrangement and connection, so as to realize the analog circuit design in subsequent processing. The model building module is used to design analog circuits based on the activation function type and the determined processing mode and spatial distribution, and to build a neural network training circuit with a multi-level complex neuron group. The model training module is used to train the neural network training circuit of the multi-level complex neuron group using the training dataset to obtain a neural network circuit model for simulation verification. The dataset acquisition module is also used to acquire the required data and input voltage domain for analog circuit design; and to perform data mapping based on the required data and input voltage domain to obtain a training dataset. The type selection module is also used to determine the types of components in the analog circuit and the operating modes of different components in the analog circuit based on the training dataset and circuit model indicators; determine the type of target analog input signal based on the types of components in the analog circuit and the operating modes of the analog circuit; and select the activation function type corresponding to the analog circuit design based on the type of target analog input signal. The design module is used to obtain the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model for simulation verification. It then uses a negative feedback system to adjust the feedforward transmission, obtaining the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model for simulation verification. Based on the transfer function H(s) of the feedforward transmission network, the transfer function G(s) of the feedback transmission network, and the input signal relationship function IN(s) and the output signal relationship function OUT(s), the module checks whether the neural network circuit model for simulation verification is qualified. If it is not qualified, the control type selection module re-executes the design of the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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