Layout method, device and equipment for salient points in circuit and storage medium

Abstract

The invention provides a salient point layout method and device in a circuit, equipment and a storage medium, and relates to the technical field of circuit design. The salient point layout method in the circuit comprises the following steps: acquiring a preset salient point layout parameter; according to a pre-read chip database, information of a plurality of circuit modules in the target circuit is determined, and the chip database comprises the circuit modules of which layout planning is completed; and according to the information of the plurality of circuit modules and the salient point arrangement parameters, performing salient point layout planning on each circuit module in sequence until the salient point layout planning of the plurality of circuit modules is completed, and obtaining a target circuit after the salient point layout planning is completed. According to the information of the plurality of circuit modules in the chip database and the preset salient point arrangement parameters, salient point layout planning can be automatically carried out, the salient point layout efficiency in the circuit is improved, and the iteration time in the salient point layout process is effectively shortened.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a method, device, equipment and storage medium for placing bumps in a circuit. Background Art

[0002] With the development of integrated circuits, the scale of chips is getting larger and larger. Traditional packaging methods can no longer meet the packaging needs of large-scale chips. Advanced packaging has emerged, among which bumps are an advanced packaging method used for flip chips (a pinless structure). Using bumps and RDL (redistributed layer) to reconstruct the chip system can effectively improve the chip functional density and shorten the chip interconnection length. Therefore, the bump layout in the circuit has also become a research hotspot.

[0003] In the related technology, the localization of the bumps is restricted by many factors. Currently, there is no automated tool to implement the layout planning of the bumps. Designers can only do manual layout, which takes a lot of time. For hierarchical design, multiple rounds of iterations are required to optimize and adjust the bump positions.

[0004] In the related art, the bump layout is performed manually, resulting in low efficiency of the bump layout in the circuit. Summary of the invention

[0005] The purpose of this application is to provide a method, device, equipment and storage medium for layout of bumps in a circuit in order to solve the above-mentioned technical problems existing in the related art in view of the above-mentioned deficiencies in the prior art.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a method for layout of bumps in a circuit, comprising:

[0008] Get the preset convex point arrangement parameters;

[0009] Determine information of multiple circuit modules in the target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed;

[0010] According to the information of the multiple circuit modules and the bump arrangement parameters, bump layout planning is performed for each circuit module in turn until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

[0011] Optionally, the obtaining of preset convex point arrangement parameters includes:

[0012] Get the preset redistribution layer direction, bump arrangement shape, and bump spacing threshold.

[0013] Optionally, performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises:

[0014] If the information of the multiple circuit modules indicates that the circuit module is a non-multiplexed circuit module, then according to the information of the circuit module in the information of the multiple circuit modules and the bump spacing threshold, the initial bump arrangement information of the circuit module in the direction of the redistribution layer is calculated; wherein the circuit module is any circuit module among the multiple circuit modules;

[0015] According to the initial bump arrangement information, bump layout planning is performed on the circuit module to obtain target bump arrangement information of the circuit module, until bump layout planning of the multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

[0016] Optionally, the calculating the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit module in the information of the plurality of circuit modules and the bump spacing threshold comprises:

[0017] If the shape of the circuit module is a rectangle, the maximum number of bumps of the circuit module in the horizontal direction and the vertical direction and the position information of each bump are calculated respectively according to the size of the circuit module and the bump spacing threshold;

[0018] If the circuit module is of a special shape, constructing a virtual rectangle covering the circuit module;

[0019] Calculating the maximum number of bumps and position information of each bump in the horizontal and vertical directions of the circuit module according to the virtual rectangle and the bump spacing threshold;

[0020] The initial convex point arrangement information includes: the maximum number of convex points in the horizontal and vertical directions and the position information of each convex point.

[0021] Optionally, performing bump layout planning on the circuit module according to the initial bump arrangement information to obtain target bump arrangement information in the circuit module until the bump layout planning of the plurality of circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises:

[0022] Determine whether there is an anti-touch area in the circuit module, and obtain a determination result;

[0023] The initial bump arrangement information is updated according to the judgment result to obtain updated bump arrangement information of the circuit module;

[0024] According to the updated bump arrangement information, bump layout planning is performed on the circuit module to obtain target bump arrangement information of the circuit module, until bump layout planning of the multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

[0025] Optionally, updating the initial bump arrangement information according to the judgment result to obtain updated bump arrangement information of the circuit module includes:

[0026] If the judgment result indicates that the anti-touch area exists on the submodule of the circuit module, the bumps planned on the anti-touch area are deleted, and the initial bump arrangement information is updated to obtain the updated bump arrangement information;

[0027] If the judgment result indicates that the circuit module is a key module and the anti-touch area exists on the key module, the bumps planned on the anti-touch area are marked, and the initial bump arrangement information is updated to obtain the updated bump arrangement information.

[0028] Optionally, performing bump layout planning on the circuit module according to the updated bump arrangement information to obtain target bump arrangement information in the circuit module until the bump layout planning of the plurality of circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises:

[0029] Determining whether there is a channel in the circuit module;

[0030] If the channel exists, determining whether there are multiple voltage domains in the circuit module;

[0031] If the multiple voltage domains exist, judging whether there is a first bump corresponding to the working voltage and a second bump corresponding to the ground terminal voltage in the channel according to the updated bump arrangement information;

[0032] If the first bump and the second bump do not exist, marking the channel and the bump position in the updated bump arrangement information to obtain the target bump arrangement information of the circuit module;

[0033] A target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the plurality of circuit modules is completed, thereby obtaining the target circuit having completed the bump layout planning.

[0034] Optionally, the method further comprises:

[0035] If the channel does not exist, or the multi-voltage domain does not exist, or the first bump and the second bump exist, the target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

[0036] Optionally, performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises:

[0037] If the information of the plurality of circuit modules indicates that the circuit module is a multiplexed circuit module, the target bump arrangement information corresponding to the circuit module is determined according to the target bump arrangement information corresponding to the same circuit module; wherein the circuit module is any circuit module among the plurality of circuit modules;

[0038] A target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the plurality of circuit modules is completed, thereby obtaining the target circuit having completed the bump layout planning.

[0039] Optionally, the method further comprises:

[0040] The target bump arrangement information of the circuit module is written into a cache file.

[0041] In a second aspect, the present application also provides a bump layout device in a circuit, comprising:

[0042] An acquisition module is used to obtain preset convex point arrangement parameters;

[0043] A determination module, used to determine information of multiple circuit modules in the target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed;

[0044] The layout planning module is used to perform bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters, until the bump layout planning of the multiple circuit modules is completed, and the target circuit with completed bump layout planning is obtained.

[0045] Optionally, the acquisition module is specifically used to acquire a preset redistribution layer direction, a bump arrangement shape, and a bump spacing threshold.

[0046] Optionally, the layout planning module is specifically used to calculate the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit module in the information of the multiple circuit modules and the bump spacing threshold if the information of the multiple circuit modules indicates that the circuit module is a non-multiplexed circuit module; wherein the circuit module is any circuit module among the multiple circuit modules; according to the initial bump arrangement information, the circuit module is subjected to bump layout planning to obtain the target bump arrangement information of the circuit module, until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0047] Optionally, the layout planning module is specifically used to calculate the maximum number of bumps and the position information of each bump in the horizontal and vertical directions of the circuit module according to the size of the circuit module and the bump spacing threshold if the shape of the circuit module is a rectangle; if the shape of the circuit module is irregular, construct a virtual rectangle covering the circuit module; calculate the maximum number of bumps and the position information of each bump in the horizontal and vertical directions of the circuit module according to the virtual rectangle and the bump spacing threshold; wherein the initial bump arrangement information includes: the maximum number of bumps and the position information of each bump in the horizontal and vertical directions.

[0048] Optionally, the layout planning module is specifically used to determine whether there is an anti-touch area in the circuit module and obtain a determination result; update the initial bump arrangement information according to the determination result to obtain updated bump arrangement information of the circuit module; perform bump layout planning on the circuit module according to the updated bump arrangement information to obtain target bump arrangement information of the circuit module, until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0049] Optionally, the layout planning module is specifically used to delete the bumps planned on the anti-touch area and update the initial bump arrangement information to obtain the updated bump arrangement information if the judgment result indicates that the anti-touch area exists on the sub-module of the circuit module; if the judgment result indicates that the circuit module is a key module and the anti-touch area exists on the key module, mark the bumps planned on the anti-touch area and update the initial bump arrangement information to obtain the updated bump arrangement information.

[0050] Optionally, the layout planning module is specifically used to determine whether there is a channel in the circuit module; if the channel exists, determine whether there are multiple voltage domains in the circuit module; if the multiple voltage domains exist, determine whether there is a first bump corresponding to the operating voltage and a second bump corresponding to the ground terminal voltage in the channel according to the updated bump arrangement information; if the first bump and the second bump do not exist, mark the channel and the bump position in the updated bump arrangement information to obtain the target bump arrangement information of the circuit module; add a target anti-touch area of ​​the same size as the circuit module to the circuit module until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0051] Optionally, the device further comprises:

[0052] An adding module is used to add the target anti-touch area with the same size as the circuit module on the circuit module if the channel does not exist, or the multi-voltage domain does not exist, or the first bump and the second bump exist, until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

[0053] Optionally, the layout planning module is specifically used to determine the target bump arrangement information corresponding to the circuit module according to the target bump arrangement information corresponding to the same circuit module if the information of the multiple circuit modules indicates that the circuit module is a multiplexed circuit module; wherein the circuit module is any circuit module among the multiple circuit modules; and add a target anti-touch area with the same size as the circuit module to the circuit module until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit for which the bump layout planning is completed.

[0054] Optionally, the device further comprises:

[0055] The writing module is used to write the target bump arrangement information of the circuit module into the cache file.

[0056] In a third aspect, an embodiment of the present application further provides a device for placing bumps in a circuit, comprising: a memory and a processor, wherein the memory stores a computer program executable by the processor, and when the processor executes the computer program, the method for placing bumps in a circuit as described in any one of the first aspects above is implemented.

[0057] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is read and executed, the method for layout of bumps in a circuit as described in any one of the first aspects above is implemented.

[0058] The beneficial effects of the present application are as follows: the embodiment of the present application provides a method for layout of bumps in a circuit, the method for layout of bumps in a circuit comprising: obtaining preset bump arrangement parameters; determining information of multiple circuit modules in a target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed; performing bump layout planning for each circuit module in turn according to the information of multiple circuit modules and the bump arrangement parameters, until the bump layout planning of multiple circuit modules is completed, and a target circuit for which bump layout planning has been completed is obtained. According to the information of multiple circuit modules in the chip database and the preset bump arrangement parameters, bump layout planning can be performed automatically, thereby improving the efficiency of bump layout in the circuit and effectively shortening the iteration time in the bump layout process. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 1 ;

[0061] Figure 2 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 2 ;

[0062] Figure 3 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 3 ;

[0063] Figure 4 A schematic diagram of the position relationship of bumps in two circuit modules provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of constructing a virtual rectangle covering a circuit module provided in an embodiment of the present application;

[0065] Figure 6 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 4 ;

[0066] Figure 7 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 5 ;

[0067] Figure 8A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 6 ;

[0068] Fig. 9 A schematic diagram of the structure of a circuit module provided in an embodiment of the present application;

[0069] Fig.10 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 7 ;

[0070] Fig.11 A visual schematic diagram of the position of the bumps in the marking IP area provided in an embodiment of the present application;

[0071] Fig.12 A visual schematic diagram of the position of convex points in a channel region provided in an embodiment of the present application;

[0072] Fig.13 A schematic diagram of the structure of a bump layout device in a circuit provided in an embodiment of the present application;

[0073] Fig.14 A schematic diagram of the structure of a bump layout device in a circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0075] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0076] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0078] An embodiment of the present application provides a method for placing bumps in a circuit, which is applied to a device for placing bumps in a circuit. The device for placing bumps in a circuit may be a terminal device or a server. The terminal device may be any one of the following: a computer, a laptop computer, a tablet computer, or a smart phone.

[0079] The following is an explanation of a bump layout method in a circuit provided in an embodiment of the present application.

[0080] Figure 1 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the method may include:

[0081] S101, obtaining preset convex point arrangement parameters.

[0082] In some implementations, in response to the input setting operation, the preset bump arrangement parameters are obtained, wherein the bump arrangement parameters are used to characterize the set bump arrangement requirements, and subsequent operations can be facilitated based on the bump arrangement parameters.

[0083] In an embodiment of the present application, a chip database may be pre-read to set an anti-touch area for some sensitive circuit modules among multiple circuit modules in the chip database. Among them, the sensitive circuit module may be referred to as sensitive IP (some key technologies or modules related to security). Optionally, some sensitive circuit modules may include: PLL (Phase Locked Loop), PVT-sensor (a sensor for monitoring the internal process, voltage and temperature conditions of the chip), etc.

[0084] In addition, a convex point can also be called a bump.

[0085] S102: Determine information of multiple circuit modules in the target circuit according to the pre-read chip database.

[0086] The chip database includes circuit modules that have completed layout planning. The target circuit may be a target chip circuit, and the information of multiple circuit modules may include: the name, direction, size, etc. of the circuit module. The size of the circuit module may be recorded in the form of W*H, that is, width*height.

[0087] In some embodiments, a preset tool is used to read in a chip database that has initialized the floorplan; information of multiple circuit modules in the target circuit is determined from the chip database, and the information of the multiple circuit modules is written into a file in a top-down manner. In the subsequent S103, traversal can be performed based on the list in the file, and the format of the list can be set according to actual needs. For example, the information of a circuit module in the list can occupy one line.

[0088] It should be noted that whether there is a multiplexed module among the multiple circuit modules can be determined based on the names of the multiple circuit modules. Circuit modules with the same name are multiplexed circuit modules. For multiplexed circuit modules, a multiplexing flag can be added after their names.

[0089] Optionally, the preset tool may be an EDA (Electronic design automation) tool.

[0090] S103, performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters, until the bump layout planning of the multiple circuit modules is completed, and a target circuit with the bump layout planning completed is obtained.

[0091] In some embodiments, based on the information of multiple circuit modules in the above list, the traversal order of the circuit modules is determined; using a preset bump layout planning algorithm, according to the information of multiple circuit modules, bump arrangement parameters and traversal order, bump layout planning is performed for each circuit module in turn, and then the target bump arrangement information of each circuit module can be obtained in turn, and the target circuit of the bump layout planning is completed.

[0092] The traversal order of the circuit modules may be a bottom-up traversal order in the list.

[0093] In summary, the embodiment of the present application provides a method for layout of bumps in a circuit, the method comprising: obtaining preset bump arrangement parameters; determining information of multiple circuit modules in a target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed; performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters, until the bump layout planning of the multiple circuit modules is completed, and a target circuit for which bump layout planning has been completed is obtained. According to the information of the multiple circuit modules in the chip database and the preset bump arrangement parameters, bump layout planning can be automatically performed, thereby improving the efficiency of bump layout in the circuit and effectively shortening the iteration time in the bump layout process.

[0094] Optionally, the process of obtaining the preset convex point arrangement parameters in S101 may include:

[0095] Get the preset redistribution layer direction, bump arrangement shape, and bump spacing threshold.

[0096] Among them, the direction of the redistribution layer can be called the RDL direction (ReDistribution Layer). The direction of the redistribution layer is related to the process of the target circuit. After the process of the target circuit is confirmed, the direction of the redistribution layer is unique.

[0097] In addition, the bump spacing threshold can be obtained from the process document, the bump spacing threshold can be denoted as T, and the bump size can be denoted as B_s.

[0098] It should be noted that the directions of the redistribution layer are divided into two types: X (horizontal) and Y (vertical), and the bump arrangement shapes can be divided into two types: rhombus and rectangle. If a rhombus bump arrangement is selected, the horizontal and vertical spacing of the bumps can be obtained at the same time, which can be based on P_h and P_v respectively. If a rectangular bump arrangement is selected, the horizontal and vertical spacing of the bumps can be obtained at the same time, which can be based on P_h and P_v respectively. Among them, the size of the circuit module can be recorded as W*H, which is used for the calculation of horizontal and vertical bumps respectively.

[0099] Optionally, Figure 2 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 2 ,like Figure 2 As shown, the process of performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters in the above S103 until the bump layout planning of the multiple circuit modules is completed and the target circuit with the bump layout planning completed is obtained may include:

[0100] S201. If the information of the multiple circuit modules indicates that the circuit module is a non-multiplexed circuit module, calculate the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit modules in the information of the multiple circuit modules and the bump spacing threshold.

[0101] The circuit module is any circuit module among the multiple circuit modules. The information of the multiple circuit modules includes: information of the circuit modules.

[0102] In an embodiment of the present application, the initial bump arrangement information of the circuit module in the direction of the redistribution layer may include: the position information of the bumps in the horizontal and vertical directions of the circuit module, denoted as C_h and C_v. The position information of the bumps in the circuit module can be considered as the coordinate information of the bumps in the circuit module.

[0103] In addition, the bump spacing threshold is based on the initial bump arrangement information of the circuit module, thereby achieving the optimization of the number of bumps in the circuit module and the RDL routing optimization.

[0104] S202, performing bump layout planning on the circuit module according to the initial bump arrangement information to obtain target bump arrangement information of the circuit module, until bump layout planning of multiple circuit modules is completed to obtain a target circuit with completed bump layout planning.

[0105] In some embodiments, the initial bump arrangement information of the circuit module can be updated and optimized according to at least one of the preset PA optimization rules, RDL routing optimization rules, and IP sensitive area optimization rules to complete the bump layout planning of the circuit module and obtain the target bump arrangement information of the circuit module.

[0106] Among them, the circuit module is any circuit module among multiple circuit modules. After completing the bump layout planning of the circuit module, a similar method is used to carry out the bump layout planning of the next circuit module until the bump layout planning of multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

[0107] Optionally, Figure 3 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 3 ,like Figure 3 As shown, the process of calculating the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit module in the information of the multiple circuit modules and the bump spacing threshold in the above S201 may include:

[0108] S301, if the shape of the circuit module is a rectangle, then according to the size of the circuit module and the threshold of the bump spacing, respectively calculate the maximum number of bumps of the circuit module in the horizontal direction and the vertical direction and the position information of each bump.

[0109] The information of the circuit module may include the size of the circuit module and the shape of the circuit module. The direction of the redistribution layer may include horizontal and vertical directions.

[0110] In some embodiments, if the shape of the circuit module is rectangular, a semi-rule is used to calculate the maximum number of bumps and the position information of each bump in the horizontal and vertical directions of the circuit module according to the size of the circuit module and the bump spacing threshold. The position information of each bump can be recorded as C_h and C_v.

[0111] It should be noted that semi-regularity refers to half of meeting a specific requirement. For example, if the spacing requirement between bumps is L, that is, the bump spacing threshold is L, then the semi-regularity is L / 2. Figure 4 A schematic diagram of the position relationship of bumps in two circuit modules provided in an embodiment of the present application, such as Figure 4 As shown, circuit module A is adjacent to circuit module B, and the rightmost convex point in circuit module A and the leftmost convex point in circuit module B are both at a distance of L / 2 from the boundary. Thus, when circuit module A and circuit module B are seamlessly spliced ​​together, the spacing between the two convex points is exactly L, which meets the requirement. If the rightmost convex point in circuit module A and the leftmost convex point in circuit module B are less than L / 2 from the boundary, then when circuit module A and circuit module B are spliced ​​together, the convex spacing will be less than L, thus failing to meet the requirement.

[0112] S302: If the shape of the circuit module is irregular, construct a virtual rectangle covering the circuit module.

[0113] The virtual rectangle needs to completely cover the circuit module.

[0114] Figure 5 A schematic diagram of constructing a virtual rectangle covering a circuit module provided in an embodiment of the present application, such as Figure 5 As shown, a virtual rectangle is constructed for the irregular circuit module, and the virtual rectangle includes the irregular circuit module and the shadow part.

[0115] In practical applications, an anti-touch area may be added to the non-circuit module portion of the virtual rectangle, wherein the anti-touch area may also be called blockage (referring to an area that is prevented from being touched by a tool).

[0116] S303, calculating the maximum number of bumps of the circuit module in the horizontal direction and the vertical direction and the position information of each bump according to the virtual rectangle and the bump spacing threshold.

[0117] The initial convex point arrangement information includes: the maximum number of convex points in the horizontal and vertical directions and the position information of each convex point.

[0118] In the embodiment of the present application, according to the virtual rectangle and the bump spacing threshold, a semi-rule is used to calculate the maximum number of bumps in the horizontal and vertical directions of the circuit module and the position information of each bump. The position information of each bump can be recorded as C_h and C_v.

[0119] Optionally, Figure 6 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 4 ,like Figure 6 As shown, in the above S202, according to the initial bump arrangement information, the bump layout planning is performed on the circuit module to obtain the target bump arrangement information in the circuit module, until the bump layout planning of multiple circuit modules is completed to obtain the target circuit with the bump layout planning completed, which may include:

[0120] S401, determining whether there is an anti-touch area in the circuit module, and obtaining a determination result.

[0121] Among them, some sensitive circuit modules among the multiple circuit modules are provided with anti-touch areas. The judgment result is used to indicate that there is an anti-touch area in the circuit module and the specific location of the anti-touch area, or that there is no anti-touch area in the circuit module.

[0122] S402, updating the initial bump arrangement information according to the judgment result to obtain updated bump arrangement information of the circuit module.

[0123] Among them, the IP sensitive area optimization rule can be used to update the initial bump arrangement information according to the judgment result to obtain the updated bump arrangement information of the circuit module.

[0124] It should be noted that, based on the judgment result, part of the bump information in the initial bump arrangement information is deleted, or part of the bump information in the initial bump arrangement information is marked. Of course, other methods can also be used to update the initial bump arrangement information to obtain the updated bump arrangement information of the circuit module. The embodiments of the present application do not impose specific restrictions on this.

[0125] S403, performing bump layout planning on the circuit module according to the updated bump arrangement information to obtain target bump arrangement information of the circuit module, until bump layout planning of multiple circuit modules is completed to obtain a target circuit for which bump layout planning is completed.

[0126] In some embodiments, PA optimization rules can be used to perform bump layout planning on the circuit module based on the updated bump arrangement information to obtain the target bump arrangement information of the circuit module; then a similar method is used to perform bump layout planning on the next circuit module until the bump layout planning of multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

[0127] Among them, the target bump arrangement information of each circuit module in the plurality of circuit modules can be obtained.

[0128] Optionally, Figure 7 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 5 ,like Figure 7 As shown, the process of updating the initial bump arrangement information according to the judgment result in the above S402 to obtain the updated bump arrangement information of the circuit module may include:

[0129] S501. If the judgment result indicates that there is an anti-touch area on the submodule of the circuit module, the bumps planned on the anti-touch area are deleted, and the initial bump arrangement information is updated to obtain updated bump arrangement information.

[0130] In an embodiment of the present application, if the judgment result indicates that the circuit module has an anti-touch area, and the anti-touch area is on a sub-module of the circuit module, the bumps planned on the anti-touch area are deleted, and the initial bump arrangement information is updated, that is, the bump information in C_h and C_v is updated to obtain the updated bump arrangement information.

[0131] S502: If the judgment result indicates that the circuit module is a key module and there is an anti-touch area on the key module, the bumps planned on the anti-touch area are marked, and the initial bump arrangement information is updated to obtain updated bump arrangement information.

[0132] Among them, the key module refers to the sensitive IP circuit module.

[0133] In the embodiment of the present application, when marking the convex points planned on the anti-touch area, the names and coordinates of the convex points planned on the anti-touch area can be recorded. The updated convex point arrangement information includes: the names and coordinates of the convex points planned on the anti-touch area.

[0134] In the embodiment of the present application, the process of updating the initial bump arrangement information in the above S501 to S502 can be considered as the process of optimizing the IP sensitive area, wherein the IP sensitive area refers to some IP circuit modules where some circuits are sensitive to changes in the surrounding environment / surrounding signals, including the distance of the surrounding units, the winding distance, etc., and the influence of the surrounding environment on this part of the circuit needs to be avoided as much as possible, and the bumps should also be avoided as much as possible. Therefore, the bumps planned on the anti-touch area in the sub-module of the circuit module should be deleted, and the bumps planned on the anti-touch area in the key module should be marked so that the designer can make further confirmation, adjust the position of these key modules, or delete the bumps planned on the anti-touch area on the key module.

[0135] Optionally, Figure 8A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 6 ,like Figure 8 As shown, in the above S403, according to the updated bump arrangement information, the circuit module is subjected to bump layout planning to obtain the target bump arrangement information in the circuit module, until the bump layout planning of multiple circuit modules is completed, and the process of obtaining the target circuit with the bump layout planning completed may include:

[0136] S601. Determine whether there is a channel in the circuit module.

[0137] Among them, the channel can also be called chanel, which refers to the gap between circuit modules.

[0138] Fig. 9 A schematic diagram of a circuit module provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, it includes: circuit module 1, circuit module 2, circuit module 3, circuit module 4, circuit module 5, circuit module 6, and circuit module 7. The shaded parts between the circuit modules are channels.

[0139] S602: If a channel exists, determine whether there are multiple voltage domains in the circuit module.

[0140] S603: If there are multiple voltage domains, determine whether there is a first bump corresponding to the working voltage and a second bump corresponding to the ground voltage in the channel according to the updated bump arrangement information.

[0141] In the embodiment of the present application, according to the updated bump arrangement information, it is determined whether there is a pair of bumps in the channel region; wherein the pair of bumps needs to include: a first bump corresponding to the working voltage (VDD) and a second bump corresponding to the ground terminal voltage (VSS). Only when there is a pair of bumps can the PA problem of the unit in the channel region be met.

[0142] S604: If the first bump and the second bump do not exist, mark the channel and the bump position in the updated bump arrangement information to obtain the target bump arrangement information of the circuit module.

[0143] It should be noted that when marking the channel and the bump position, the channel name and the bump name corresponding to the bump position may be recorded. The target bump arrangement information of the circuit module may record the channel name and the bump name corresponding to the bump position.

[0144] S605 , adding a target anti-touch area having the same size as the circuit module to the circuit module, until the bump layout planning of multiple circuit modules is completed, thereby obtaining a target circuit with the bump layout planning completed.

[0145] After the bump layout planning is completed for each circuit module, a target anti-touch area having the same size as the circuit module can be added to the circuit module.

[0146] Optionally, the method may further include:

[0147] If there is no channel, or there is no multi-voltage domain, or there are first bumps and second bumps, a target anti-touch area with the same size as the circuit module is added to the circuit module until the bump layout planning of multiple circuit modules is completed to obtain a target circuit with completed bump layout planning.

[0148] It should be noted that a target anti-touch area of ​​the same size as the circuit module is added to the circuit module. The circuit module in the embodiment of the present application is traversed from bottom to top, which can facilitate the bump planning of the circuit module of the previous level until the bump layout planning of all modules is completed.

[0149] Optionally, Fig.10 A schematic diagram of a method for placing bumps in a circuit provided in an embodiment of the present application Figure 7 ,like Fig.10 As shown, the process of performing bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters in the above S103 until the bump layout planning of the multiple circuit modules is completed and the target circuit with the bump layout planning completed is obtained may include:

[0150] S701. If the information of multiple circuit modules indicates that the circuit modules are multiplexed circuit modules, determine the target bump arrangement information corresponding to the circuit modules according to the target bump arrangement information corresponding to the same circuit modules.

[0151] The circuit module is any circuit module among the multiple circuit modules. The same circuit module is a circuit module that is the same as the circuit module and is located before the circuit module.

[0152] In some embodiments, if the information of a circuit module in the information of multiple circuit modules indicates that there is a reuse marking bit after the name of the circuit module, it can be determined that the circuit module is a reused circuit module, and then the target bump arrangement information of the circuit module can directly reuse the target bump arrangement information corresponding to the same circuit module previously determined.

[0153] S702, adding a target anti-touch area having the same size as the circuit module on the circuit module until the bump layout planning of multiple circuit modules is completed, thereby obtaining a target circuit with the bump layout planning completed.

[0154] It should be noted that a target anti-touch area of ​​the same size as the circuit module is added to the circuit module. The circuit module in the embodiment of the present application is traversed from bottom to top, which can facilitate the bump planning of the circuit module of the previous level until the bump layout planning of all modules is completed.

[0155] Optionally, the method may further include:

[0156] Write the target bump arrangement information of the circuit module into the cache file.

[0157] In the embodiment of the present application, each time the target bump arrangement information of a circuit module is obtained, the target bump arrangement information of the circuit module can be written into a cache file until the bump layout planning of all circuit modules is completed.

[0158] The target bump arrangement information of the circuit module includes the position and quantity of the horizontal bumps and the position and quantity of the vertical bumps in the circuit module.

[0159] In some implementations, a file of position information of all the marked bumps can be written out so that the designer can view the file directly, or the file can be directly read into the database through the EDA tool, and the position information of the marked bumps can be viewed from the graphical user interface, so as to quickly make an optimization plan. Among them, the file of position information of all the bumps can be written out, which can be an IO file (a structure used to represent file input / output operations) or a file in DEF format (a file format used to describe the physical layout in digital integrated circuit design), which can be directly read into the database through the EDA tool.

[0160] Fig.11 A visual schematic diagram of a bump position marking IP area provided in an embodiment of the present application, such as Fig.11 As shown in the figure, each circle is a bump, and because the target bump is on the IP sensitive area, the target bump carries a mark, which makes it easier for designers to quickly make further optimization plans.

[0161] Fig.12 A visual schematic diagram of the position of the convex point in the channel area provided in an embodiment of the present application, such as Fig.12 As described above, each circle is a bump, there is only one channel between circuit module C and circuit module D, and there is only one column of bumps on the channel, namely, the marked target bumps, which can indicate the risk of power supply voltage drop (IR_drop).

[0162] In actual applications, after the necessary parameters are input in the embodiment of the present application, the entire bump design and optimization are automatically executed through the script, and finally an executable file is written to achieve semi-automatic bump layout and optimization.

[0163] In summary, the embodiment of the present application provides a method for layout of bumps in a circuit. According to the information of multiple circuit modules in the chip database and the pre-set bump arrangement parameters, the bump layout planning can be automatically performed, thereby improving the efficiency of the bump layout in the circuit and effectively shortening the iteration time in the bump layout process. Moreover, the bump layout is performed on each circuit module in a bottom-up manner. The present application takes into account the optimization of the number of bumps, PA optimization, RDL routing optimization, and IP sensitive area optimization, and can output the suggestions in the bump design in text or visual form for designers to review. The present method can effectively shorten the iteration time in the bump layout process, improve design efficiency, and shorten the sign-off time.

[0164] The following describes the circuit bump layout device, equipment and storage medium used to execute the circuit bump layout method provided by the present application. Its specific implementation process and technical effects can be found in the relevant content of the above-mentioned circuit bump layout method, which will not be repeated below.

[0165] Fig.13 A schematic diagram of a bump layout device in a circuit provided in an embodiment of the present application is shown in FIG. Fig.13 As shown, the device may include:

[0166] An acquisition module 101 is used to acquire preset convex point arrangement parameters;

[0167] A determination module 102 is used to determine information of multiple circuit modules in the target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed;

[0168] The layout planning module 103 is used to perform bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters, until the bump layout planning of the multiple circuit modules is completed, and the target circuit with completed bump layout planning is obtained.

[0169] Optionally, the acquisition module 101 is specifically used to acquire a preset redistribution layer direction, a bump arrangement shape, and a bump spacing threshold.

[0170] Optionally, the layout planning module 103 is specifically used to calculate the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit module in the information of the multiple circuit modules and the bump spacing threshold if the information of the multiple circuit modules indicates that the circuit module is a non-multiplexed circuit module; wherein the circuit module is any circuit module among the multiple circuit modules; according to the initial bump arrangement information, perform bump layout planning on the circuit module to obtain target bump arrangement information of the circuit module, until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0171] Optionally, the layout planning module 103 is specifically used to calculate the maximum number of bumps and the position information of each bump in the horizontal and vertical directions of the circuit module according to the size of the circuit module and the bump spacing threshold if the shape of the circuit module is a rectangle; if the shape of the circuit module is irregular, construct a virtual rectangle covering the circuit module; calculate the maximum number of bumps and the position information of each bump in the horizontal and vertical directions of the circuit module according to the virtual rectangle and the bump spacing threshold; wherein the initial bump arrangement information includes: the maximum number of bumps and the position information of each bump in the horizontal and vertical directions.

[0172] Optionally, the layout planning module 103 is specifically used to determine whether there is an anti-touch area in the circuit module and obtain a determination result; update the initial bump arrangement information according to the determination result to obtain updated bump arrangement information of the circuit module; perform bump layout planning on the circuit module according to the updated bump arrangement information to obtain target bump arrangement information of the circuit module, until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0173] Optionally, the layout planning module 103 is specifically used to delete the bumps planned on the anti-touch area and update the initial bump arrangement information to obtain the updated bump arrangement information if the judgment result indicates that the anti-touch area exists on the sub-module of the circuit module; if the judgment result indicates that the circuit module is a key module and the anti-touch area exists on the key module, mark the bumps planned on the anti-touch area and update the initial bump arrangement information to obtain the updated bump arrangement information.

[0174] Optionally, the layout planning module 103 is specifically used to determine whether there is a channel in the circuit module; if the channel exists, determine whether there are multiple voltage domains in the circuit module; if the multiple voltage domains exist, determine whether there is a first bump corresponding to the working voltage and a second bump corresponding to the ground terminal voltage in the channel according to the updated bump arrangement information; if the first bump and the second bump do not exist, mark the channel and the bump position in the updated bump arrangement information to obtain the target bump arrangement information of the circuit module; add a target anti-touch area of ​​the same size as the circuit module to the circuit module until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed.

[0175] Optionally, the device further comprises:

[0176] An adding module is used to add the target anti-touch area with the same size as the circuit module on the circuit module if the channel does not exist, or the multi-voltage domain does not exist, or the first bump and the second bump exist, until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

[0177] Optionally, the layout planning module 103 is specifically used to determine the target bump arrangement information corresponding to the circuit module according to the target bump arrangement information corresponding to the same circuit module if the information of the multiple circuit modules indicates that the circuit module is a multiplexed circuit module; wherein the circuit module is any circuit module among the multiple circuit modules; and add a target anti-touch area with the same size as the circuit module to the circuit module until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

[0178] Optionally, the device further comprises:

[0179] The writing module is used to write the target bump arrangement information of the circuit module into the cache file.

[0180] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0181] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0182] Fig.14 A schematic diagram of a structure of a bump placement device in a circuit provided in an embodiment of the present application, such as Fig.14 As shown, the bump layout device in the circuit includes: a processor 201 and a memory 202.

[0183] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0184] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0185] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0186] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0187] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0188] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0189] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for placing bumps in a circuit, characterized in that: include: Get the preset convex point arrangement parameters; Determine information of multiple circuit modules in the target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed; According to the information of the multiple circuit modules and the bump arrangement parameters, bump layout planning is performed for each circuit module in turn until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

2. The method according to claim 1, characterized in that: The step of obtaining the preset convex point arrangement parameters includes: Get the preset redistribution layer direction, bump arrangement shape, and bump spacing threshold.

3. The method according to claim 2, characterized in that According to the information of the multiple circuit modules and the bump arrangement parameters, bump layout planning is performed for each circuit module in turn until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, including: If the information of the multiple circuit modules indicates that the circuit module is a non-multiplexed circuit module, then according to the information of the circuit module in the information of the multiple circuit modules and the bump spacing threshold, the initial bump arrangement information of the circuit module in the direction of the redistribution layer is calculated; wherein the circuit module is any circuit module among the multiple circuit modules; According to the initial bump arrangement information, bump layout planning is performed on the circuit module to obtain target bump arrangement information of the circuit module, until bump layout planning of the multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

4. The method according to claim 3, characterized in that The calculating the initial bump arrangement information of the circuit module in the direction of the redistribution layer according to the information of the circuit module in the information of the plurality of circuit modules and the bump spacing threshold comprises: If the shape of the circuit module is a rectangle, the maximum number of bumps of the circuit module in the horizontal direction and the vertical direction and the position information of each bump are calculated respectively according to the size of the circuit module and the bump spacing threshold; If the circuit module is of a special shape, constructing a virtual rectangle covering the circuit module; Calculating the maximum number of bumps and position information of each bump in the horizontal and vertical directions of the circuit module according to the virtual rectangle and the bump spacing threshold; The initial convex point arrangement information includes: the maximum number of convex points in the horizontal and vertical directions and the position information of each convex point.

5. The method according to claim 3, characterized in that: The method of performing bump layout planning on the circuit module according to the initial bump arrangement information to obtain target bump arrangement information in the circuit module, until the bump layout planning of the plurality of circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises: Determine whether there is an anti-touch area in the circuit module, and obtain a determination result; The initial bump arrangement information is updated according to the judgment result to obtain updated bump arrangement information of the circuit module; According to the updated bump arrangement information, bump layout planning is performed on the circuit module to obtain target bump arrangement information of the circuit module, until bump layout planning of the multiple circuit modules is completed to obtain the target circuit with completed bump layout planning.

6. The method according to claim 5, characterized in that The updating of the initial bump arrangement information according to the judgment result to obtain the updated bump arrangement information of the circuit module includes: If the judgment result indicates that the anti-touch area exists on the submodule of the circuit module, the bumps planned on the anti-touch area are deleted, and the initial bump arrangement information is updated to obtain the updated bump arrangement information; If the judgment result indicates that the circuit module is a key module and the anti-touch area exists on the key module, the bumps planned on the anti-touch area are marked, and the initial bump arrangement information is updated to obtain the updated bump arrangement information.

7. The method according to claim 5, characterized in that The method of performing bump layout planning on the circuit module according to the updated bump arrangement information to obtain target bump arrangement information in the circuit module, until the bump layout planning of the plurality of circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, comprises: Determining whether there is a channel in the circuit module; If the channel exists, determining whether there are multiple voltage domains in the circuit module; If the multiple voltage domains exist, judging whether there is a first bump corresponding to the working voltage and a second bump corresponding to the ground terminal voltage in the channel according to the updated bump arrangement information; If the first bump and the second bump do not exist, marking the channel and the bump position in the updated bump arrangement information to obtain the target bump arrangement information of the circuit module; A target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the plurality of circuit modules is completed, thereby obtaining the target circuit having completed the bump layout planning.

8. The method according to claim 7, characterized in that The method further comprises: If the channel does not exist, or the multi-voltage domain does not exist, or the first bump and the second bump exist, the target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the multiple circuit modules is completed, thereby obtaining the target circuit with completed bump layout planning.

9. The method according to claim 2, characterized in that: According to the information of the multiple circuit modules and the bump arrangement parameters, bump layout planning is performed for each circuit module in turn until the bump layout planning of the multiple circuit modules is completed to obtain the target circuit for which the bump layout planning is completed, including: If the information of the plurality of circuit modules indicates that the circuit module is a multiplexed circuit module, the target bump arrangement information corresponding to the circuit module is determined according to the target bump arrangement information corresponding to the same circuit module; wherein the circuit module is any circuit module among the plurality of circuit modules; A target anti-touch area having the same size as the circuit module is added to the circuit module until the bump layout planning of the plurality of circuit modules is completed, thereby obtaining the target circuit having completed the bump layout planning.

10. The method according to claim 5, characterized in that The method further comprises: The target bump arrangement information of the circuit module is written into a cache file.

11. A bump layout device in a circuit, characterized in that: include: An acquisition module is used to obtain preset convex point arrangement parameters; A determination module, used to determine information of multiple circuit modules in the target circuit according to a pre-read chip database, wherein the chip database includes circuit modules for which layout planning has been completed; The layout planning module is used to perform bump layout planning for each circuit module in turn according to the information of the multiple circuit modules and the bump arrangement parameters, until the bump layout planning of the multiple circuit modules is completed, and the target circuit with completed bump layout planning is obtained.

12. A bump placement device in a circuit, characterized in that: include: A memory and a processor, wherein the memory stores a computer program executable by the processor, and when the processor executes the computer program, the method for placing bumps in a circuit as described in any one of claims 1 to 10 is implemented.

13. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is read and executed, the method for placing bumps in a circuit as described in any one of claims 1 to 10 is implemented.

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