Calculation unit for simulating computer chip and control method thereof

Abstract

The invention discloses a computing unit for simulating a computer chip and a control method of the computing unit, and relates to the field of artificial intelligence chips. The computing unit comprises a current-level computing unit, and the current-level computing unit comprises a current-level arithmetic unit and a current-level storage unit; the level arithmetic unit comprises a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1. The storage unit at the same level is connected with the drain electrode of the third switch tube M3, and the drain electrode of the third switch tube M3 outputs a first current IC to the storage unit at the same level and generates a coupling voltage VZ at the drain electrode end of the third switch tube M3; and a third control voltage VG is also accessed to the storage unit at the same level so as to adjust the size of the first current IC. The calculation unit does not need to use a traditional adder structure, accumulation operation of signals can be achieved only through a small number of analog components, the size of an artificial intelligence chip is reduced, the operation speed is increased, and power consumption is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence chips, and in particular to a computing unit simulating a computer chip and a control method thereof. Background Art

[0002] With the development of artificial intelligence (AI) technology, performance requirements for AI chips are increasing. Existing AI chips are typically based on digital computer chips, whose core computing units utilize digital operations. Each core computing unit requires tens to hundreds of thousands of transistors, resulting in existing AI chips typically accommodating only a few thousand core computing units. These core computing units typically consist of a storage unit and an arithmetic unit. The storage unit first performs a linear transformation on the input data, then applies a nonlinear transformation to the transformed data using an activation function. This is then accumulated by the arithmetic unit, which consists of an adder, before entering the next linear transformation, and repeating this cycle.

[0003] Therefore, to simultaneously compute tens of thousands or even hundreds of millions of data points, a large number of core computing units must be used for parallel processing. This requirement results in existing AI chips based on digital computer chips being large, slow, and power-hungry, limiting their development and application in high-performance computing. Summary of the Invention

[0004] The purpose of the present invention is to provide a computing unit of an analog computer chip and a control method thereof, which realizes signal accumulation operation by adopting a small number of analog components instead of the traditional adder structure, effectively reducing the size of the artificial intelligence chip, improving the operation speed, and reducing power consumption.

[0005] To achieve the above objectives, the present invention discloses the following technical solutions: In a first aspect of the present invention, a computing unit of an analog computer chip is provided, the computing unit comprising a current-stage computing unit, the current-stage computing unit comprising a current-stage arithmetic unit and a current-stage storage unit; wherein the current-stage arithmetic unit comprises a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, and a first capacitor C1; In the arithmetic unit of this stage, the first switch M1 and the second switch M2 form a current mirror structure. The control terminal of the first switch M1 is connected to the control terminal of the second switch M2 and to the drain of the first switch M1. The drain of the first switch M1 is connected to the source of the third switch M3, and the drain of the second switch M2 is connected to the drain of the fourth switch M4 and the drain of the fifth switch M5, respectively. The control terminal of the third switch M3 is connected to the control terminal of the fourth switch M4 and to the first control voltage VC. The source of the fifth switch M5 is connected to the source and drain of the sixth switch M6, and the control terminal of the fifth switch M5 is connected to the second control voltage VD, and the control terminal of the sixth switch M6 is connected to the second inverted control voltage VD-1. The low voltage terminal of the first capacitor C1 is connected to the source of the fourth switch M4 and to ground. The high voltage terminal of the first capacitor C1 is connected to the source of the fifth switch M5 and to generate the output voltage VG' of the arithmetic unit of this stage. The storage unit at this stage is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs the first current IC to the storage unit at this stage and generates a coupling voltage VZ at its drain end; the storage unit at this stage is also connected to a third control voltage VG for adjusting the magnitude of the first current IC.

[0006] In a possible implementation, the first switch transistor M1 , the second switch transistor M2 , and the third switch transistor M3 are all PMOS transistors, and the fourth switch transistor M4 , the fifth switch transistor M5 , and the sixth switch transistor M6 are all NMOS transistors.

[0007] In a possible implementation, the calculation unit further includes a current source unit, which is used to control the first switch tube M1 and the second switch tube M2 to always be in an on state; The current source unit includes a seventh switch tube M7, an eighth switch tube M8, and a first current source B1. The seventh switch tube M7 and the eighth switch tube M8 form a current mirror structure. The control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are connected and connected to the drain of the seventh switch tube M7. The current input end of the first current source B1 is connected to the source of the first switch tube M1 and the source of the second switch tube M2 and is connected to the input voltage VIN. The current output end of the first current source B1 is connected to the drain of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the drain of the first switch tube M1. The source of the seventh switch tube M7 and the source of the eighth switch tube M8 are connected and grounded.

[0008] In a possible implementation, the first current source B1 always generates a current source current, which is used to pull up the voltages at the control terminals of the seventh switch tube M7 and the eighth switch tube M8, thereby turning on the seventh switch tube M7 and the eighth switch tube M8, and generating a pull-down current in the eighth switch tube M8 to pull down the voltages at the control terminals of the first switch tube M1 and the second switch tube M2, thereby keeping the first switch tube M1 and the second switch tube M2 always in the on state. When the computing unit of this stage is in the charging stage, at the moment when the fourth switch tube M4 is turned off and the third switch tube M3 and the fifth switch tube M5 are turned on, a charging current ICC related to the magnitude of the first current IC immediately flows through the second switch tube M2 to charge the first capacitor C1. When the computing unit of this stage is in the discharging stage, the third switch tube M3 is turned off, the first current IC is not generated in the first switch tube M1, and the charging current ICC is not generated in the second switch tube M2, so that the first capacitor C1 is discharged smoothly.

[0009] In a possible implementation, the computing unit at this level is one computing unit, and the storage unit at this level is a set of all storage units connected to the computing unit at this level, including one or more storage units.

[0010] In a possible implementation, one of the storage units includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11, and a twelfth switch tube M12; In the memory cell, the source of the ninth switch tube M9 is connected to its drain and is connected to the third control voltage VG, and the source of the tenth switch tube M10 is connected to its drain and is connected to the first voltage VE; the control terminal of the ninth switch tube M9 and the control terminal of the tenth switch tube M10 are connected to the control terminal of the eleventh switch tube M11, and the control terminal of the twelfth switch tube M12 is connected to the fourth control voltage VH; the drain of the eleventh switch tube M11 is connected to the coupling voltage VZ, the source of the eleventh switch tube M11 is connected to the drain of the twelfth switch tube M12, and a first sub-current IC11 of the first current IC flows through the eleventh switch tube M11. The source of the twelfth switch tube M12 is connected to the second voltage VS.

[0011] In a possible implementation, the ninth switch tube M9 and the tenth switch tube M10 are both PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are both NMOS tubes.

[0012] In one possible implementation, when the storage unit is a first-level storage unit, the third control voltage VG is an input external voltage; when the storage unit is not a first-level storage unit, the third control voltage VG is an output voltage of a previous-level computing unit; The first voltage VE is 0V; the coupling voltage VZ is a voltage generated by the mutual coupling between the operation unit of this stage and the storage unit of this stage; and the second voltage VS is a fixed value.

[0013] In a possible implementation, the transfer function of the storage unit is: ; Where, represents the first sub-current IC11 of the first current IC flowing through the eleventh switch tube M11, represents the third control voltage VG, 、 and are the electron mobility, oxide layer capacitance, and width-to-length ratio of the eleventh switch tube M11, CC1 is the equivalent capacitance of the ninth switch tube M9, and CC2 is the equivalent capacitance of the tenth switch tube M10. is the turn-on threshold voltage of the eleventh switch tube M11; The transfer function of the memory cell is determined by the turn-on threshold voltage Make adjustments; After the transfer function of the storage unit is adjusted, the magnitude of the first sub-current IC11 of the storage unit is determined by the magnitude of the third control voltage VG.

[0014] In one possible implementation, the analog computer chip includes multiple levels of computing units, each level of computing units includes one or more computing units, and the number of computing units in each level of computing units is the same or different; The computing unit at this level is a computing unit, the computing unit at this level is a computing unit, and the storage unit at this level is a set of all storage units connected to the computing unit at this level, including one or more storage units; The current source unit is connected to the computing units in the same level or different levels, so that multiple computing units in the same level share one current source unit, or multiple computing units in different levels share one current source unit.

[0015] Another aspect of the present invention provides a control method for a computing unit simulating a computer chip, which is applied to the computing unit according to the first aspect, and the method comprises: Inputting a first control voltage VC to the control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off states of the third switch tube M3 and the fourth switch tube M4; Inputting a second control voltage VD to the control terminal of the fifth switch tube M5, and inputting a second inverted control voltage VD-1 having a level opposite to the second control voltage VD to the control terminal of the sixth switch tube M6, so as to control the on and off states of the fifth switch tube M5 and the sixth switch tube M6; Inputting a third control voltage VG to the storage unit of this stage to adjust the magnitude of the first current IC; Controlling the working state of the computing unit at this stage according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5; The working states of the computing unit at this level include a preparation stage, a charging stage, a power supply stage and a discharge stage.

[0016] In one possible implementation, when the computing unit at this stage is in a preparatory stage, a high-level first control voltage VC, a high-level second control voltage VD, a low-level second inverted control voltage VD-1, and a low-level third control voltage VG are first input to turn on the fourth switch M4 and the fifth switch M5, and turn off the first switch M1, the second switch M2, the third switch M3, and the sixth switch M6. The first capacitor C1 is discharged through the fifth switch M5 and the fourth switch M4. After the voltage across the first capacitor C1 is discharged to 0V, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on. The voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit begins to enter the charging stage.

[0017] In one possible implementation, when the computing unit at this stage is in the charging stage, the first control voltage VC is first switched to a low-level state, and the third control voltage VG is synchronously raised. When the first control voltage VC is completely lowered, the second control voltage VD is raised, so that the fourth switch M4 is turned off and the third switch M3 and the fifth switch M5 are turned on. As a result, the control terminal voltages of the first switch M1 and the second switch M2 are lowered by the third switch M3, so that the first switch M1 and the second switch M2 are turned on. Consequently, a first current IC flows through the branch formed by the first switch M1 and the third switch M3, and a charging current ICC related to the magnitude of the first current IC flows through the second switch M2 to charge the first capacitor C1. When the charging time reaches TC, the second control voltage VD is switched to a low level state, and when the second control voltage VD is completely pulled down, the computing unit at this stage begins to enter the power supply stage.

[0018] In one possible implementation, when the computing unit at this level is in a power supply phase, the second control voltage VD is in a low-level state, the first capacitor C1 supplies power to the outside, and when the second control voltage VD is completely pulled low, the first control voltage VC is pulled high, and the third control voltage VG is synchronously pulled low, so that the first switch tube M1, the second switch tube M2, and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0 A; When the time for the second control voltage VD to maintain the low level state reaches TG, the computing unit at this stage begins to enter the discharge stage.

[0019] In a possible implementation, when the current-stage computing unit is in the power supply stage, the output voltage VG′ of the first capacitor C1 is: ; Wherein, ICC is a charging current related to the magnitude of the first current IC, TC is the charging time of the first capacitor C1 by the charging current ICC, and C1 is the capacitance value of the first capacitor C1; The output voltage VG′ is regulated by the first current IC.

[0020] In one possible implementation, when the computing unit at this stage is in the discharging stage, the second control voltage VD is first switched to a high level state to turn on the fifth switch M5, and the first control voltage VC is switched to a high level state to turn on the fourth switch M4. The first capacitor C1 is discharged to 0 V through the fifth switch M5 and the fourth switch M4. When the discharge time reaches TF, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on. The voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit enters the next charging stage.

[0021] In a possible implementation, the charging time TC is set to 100 ns, and the discharging time TF is set to 10 ns.

[0022] In another aspect of the present invention, a control method for a multi-stage computing unit of an analog computer chip is provided, which is applied to the multi-stage computing unit described above, wherein the multi-stage computing unit includes a computing unit at a current level and a computing unit at a lower level, and each computing unit at the same level shares a current source unit. The method comprises: driving the first current source B1 to generate a current source current to control the on / off states of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8; driving the twenty-first current source B21 to generate a current source current to control the on / off states of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28; A control voltage VC1 is input to the control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off states of the third switch tube M3 and the fourth switch tube M4; a control voltage VC2 is input to the control terminals of the twenty-third switch tube M23 and the twenty-fourth switch tube M24 to control the on / off states of the twenty-third switch tube M23 and the twenty-fourth switch tube M24; A control voltage VD1 is input to the control terminal of the fifth switch M5, and an inverted control voltage VD1-1 having a level opposite to that of the control voltage VD1 is input to the control terminal of the sixth switch M6, so as to control the on / off states of the fifth switch M5 and the sixth switch M6. A control voltage VD2 is input to the control terminal of the twenty-fifth switch M25, and an inverted control voltage VD2-1 having a level opposite to that of the control voltage VD2 is input to the control terminal of the twenty-sixth switch M26, so as to control the on / off states of the twenty-fifth switch M25 and the twenty-sixth switch M26. Input a control voltage VG1 to the current level calculation unit to control the magnitude of the current IC1, and the output voltage VG1' of the current level calculation unit is the control voltage of the next level calculation unit to control the magnitude of the current IC2; controlling the operating state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25; Among them, the working states of the multi-level computing units include the preparation stage, the charging stage of the current-level computing unit, the power supply stage of the current-level computing unit and the charging stage of the lower-level computing unit, the discharge stage of the current-level computing unit and the power supply stage of the lower-level computing unit, and the discharge stage of the lower-level computing unit.

[0023] In one possible implementation, when the multi-stage computing unit is in the preparation stage, the first current source B1 and the twenty-first current source B21 are driven to always generate current source current, the eighth switch tube M8 generates a pull-down current so that the first switch tube M1 and the second switch tube M2 are always in the on state, and the twenty-eighth switch tube M28 generates a pull-down current so that the twenty-first switch tube M21 and the twenty-second switch tube M22 are always in the on state. The input control voltages VC1 and VC2 are in a high-level state, the control voltages VD1 and VD2 are in a high-level state, the inverted control voltages VD1-1 and VD2-1 are in a low-level state, and the control voltage VG1 is in a low-level state, so that the fourth switch M4, the fifth switch M5, the twenty-fourth switch M24, and the twenty-fifth switch M25 are all turned on, and the third switch M3, the sixth switch M6, the twenty-third switch M23, and the twenty-sixth switch M26 are all turned off. The first capacitor C1 is discharged through the fifth switch M5 and the fourth switch M4, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch M25 and the twenty-fourth switch M24. After the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are discharged to 0V, the control voltage VD1 and the control voltage VD2 are switched to a low level state, and the inverted control voltage VD1-1 and the inverted control voltage VD2-1 are synchronously switched to a high level state, so that the fifth switch M5 and the twenty-fifth switch M25 are turned off, and the sixth switch M6 and the twenty-sixth switch M26 are turned on. The voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are maintained at 0V until the computing unit at this stage begins to enter the charging stage.

[0024] In one possible implementation, when the computing unit of the current stage is in the charging stage, the control voltage VC1 of the computing unit of the current stage is switched to a low level state, and the control voltage VG1 of the storage unit of the current stage is simultaneously pulled high. When the control voltage VC1 is completely pulled low, the control voltage VD1 is pulled high, so that the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, and the charging current ICC1 related to the magnitude of the current IC1 immediately flows through the second switch tube M2 to charge the first capacitor C1. When the charging time reaches TC, the control voltage VD1 is switched to a low level state, and the control voltage VC2 of the lower-level computing unit is synchronously switched to a low level state. When the control voltage VD1 and the control voltage VC2 are completely pulled low, the computing unit at this level begins to enter the power supply stage, and the lower-level computing unit enters the charging stage.

[0025] In one possible implementation, when the computing unit at the current stage is in a power supply phase and the computing unit at the lower stage is in a charging phase, the control voltage VC1 is pulled high and the control voltage VG1 is synchronously pulled low, so that the third switch M3 is turned off, the fourth switch M4 is turned on, the control voltage VD1 and the control voltage VC2 are in a low-level state, the fifth switch M5 and the twenty-fourth switch M24 are turned off, and the twenty-third switch M23 is turned on. The output voltage VG1′ of the computing unit at the current stage supplies power to the storage unit at the lower stage, and a current IC2 is generated in the twenty-third switch M23. When the current computing unit is in the power supply phase and the lower computing unit is in the charging phase, the control voltage VD2 is increased to turn on the twenty-fifth switch M25. A charging current ICC2 related to the current IC2 immediately flows through the twenty-second switch M22 to charge the twenty-first capacitor C21. When the charging time reaches TC, the control voltage VD2 is switched to a low level state. When the control voltage VD2 is completely pulled down, the control voltage VD1 remains in a low level state for TG. The current level computing unit begins to enter the discharge stage, and the lower level computing unit enters the power supply stage.

[0026] In a possible implementation, when the computing unit at this stage is in the power supply stage, the output voltage VG1′ of the computing unit at this stage is: ; Wherein, ICC1 is a charging current related to the magnitude of the current IC1, TC is the charging time of the first capacitor C1 by the charging current ICC1, and C1 is the capacitance value of the first capacitor; The output voltage VG1 ′ is regulated by the current IC1 .

[0027] In a possible implementation, when the computing unit at this stage is in the power supply stage, the power supply time of the computing unit at this stage is: ; Wherein, TG is the time during which the control voltage VD1 remains at a low level, T0 is the sum of the rising edge time and the falling edge time of the control voltage VD2, and TC is the charging time of the charging current ICC2 to charge the twenty-first capacitor C21.

[0028] In one possible implementation, when the current-stage computing unit is in the discharging stage and the lower-stage computing unit is in the power supply stage, the control voltage VD1 is switched to a high-level state, so that the fifth switch tube M5 is turned on, the control voltage VC1 is in a high-level state, the control voltage VG1 is in a low-level state, the fourth switch tube M4 is turned on, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4; When the discharge time reaches TF, the control voltage VD1 is switched to a low level state, and the inverted control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch M5 is turned off and the sixth switch M6 is turned on. The voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit enters the next charging stage. When the computing unit at this level is in the discharging stage and the computing unit at the next level is in the power supply stage, the control voltage VC2 is pulled high, so that the twenty-third switch tube M23 is turned off and the twenty-fourth switch tube M24 is turned on. The control voltage VD2 is in a low-level state, and the twenty-fifth switch tube M25 is turned off. The output voltage VG2' of the computing unit at the next level supplies power to the computing unit at the next level, and a current IC3 is generated in the computing unit at the next level. When the control voltage VD2 maintains the low level state for a period of time reaching TG, it is switched to the high level state, and the lower-level computing unit begins to enter the discharge stage.

[0029] In a possible implementation, when the lower-level computing unit is in the power supply stage, the output voltage VG2′ of the lower-level computing unit is: ; Wherein, ICC2 is a charging current related to the magnitude of the current IC2, TC is the charging time of the twenty-first capacitor C21 by the charging current ICC2, and C21 is the capacitance value of the twenty-first capacitor; The output voltage VG2 ′ is regulated by the current IC2 .

[0030] In one possible implementation, when the lower-level computing unit is in the discharging stage, the control voltage VD2 is first switched to a high-level state, turning on the 25th switch M25. The control voltage VC2 is also in a high-level state, turning on the 24th switch M24. The 21st capacitor C21 is discharged to 0 V through the 25th switch M25 and the 24th switch M24. When the discharge time reaches TF, the control voltage VD2 is switched to a low level state, and the inverted control voltage VD-2 is synchronously switched to a high level state, so that the twenty-fifth switch tube M25 is turned off and the twenty-sixth switch tube M26 is turned on, and the voltage across the twenty-first capacitor C21 is maintained at 0V until the lower-level computing unit enters the next charging stage.

[0031] In a possible implementation, the power supply time TG is set to 101 ns, the charging time TC is set to 100 ns, the discharging time TF is set to 10 ns, and T0 is set to 1 ns.

[0032] The effects provided in the summary of the invention are only the effects of the embodiments, not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects: The present application provides a computing unit of an analog computer chip and a control method thereof, wherein the computing unit includes a current-level computing unit and a current-level storage unit. The current-level computing unit includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, and a first capacitor C1; the current-level storage unit is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs a first current IC to the current-level storage unit and generates a coupling voltage VZ at its drain end; the current-level storage unit is also connected to a third control voltage VG for adjusting the magnitude of the first current IC. The computing unit of the present application does not need to use a traditional adder structure, and can realize signal accumulation operations with only a small number of analog components, significantly reducing the size of the artificial intelligence chip, improving the computing speed, and effectively reducing power consumption, thereby improving the overall performance of the artificial intelligence chip and meeting the needs of high-efficiency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0034] Figure 1 This is a schematic diagram of the structure of a computing unit of an analog computer chip according to one embodiment of the present application; Figure 2 for Figure 1 A flow chart of a control method for a computing unit of a simulated computer chip; Figure 3 for Figure 1 Schematic diagram of the control voltage waveform of the computing unit of the analog computer chip; Figure 4 This is a schematic diagram of the structure of a computing unit of an analog computer chip according to another embodiment of the present application; Figure 5 This is an example of a structural block diagram of an analog computer chip according to an embodiment of the present application; Figure 6 for Figure 5 A circuit schematic diagram of a storage unit in FIG. Figure 7 for Figure 4 A circuit schematic diagram of a computing unit in an analog computer chip; Figure 8 This is a schematic diagram of the structure of a multi-level computing unit of an analog computer chip according to an embodiment of the present application; Figure 9 for Figure 8A flow chart of a control method for a multi-level computing unit in a simulated computer chip; Figure 10 for Figure 8 Schematic diagram of the control voltage waveform of the multi-level computing unit of the simulated computer chip. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] It should be noted that references to "one embodiment," "an embodiment," "an example embodiment," etc., in this specification indicate that the described embodiment may include specific features, structures, or characteristics. However, not every embodiment must include these specific features, structures, or characteristics. In addition, such references do not necessarily refer to the same embodiment. Furthermore, when specific features, structures, or characteristics are described in conjunction with an embodiment, whether or not explicitly described, it is indicated that it is within the knowledge of those skilled in the art to incorporate such features, structures, or characteristics into other embodiments.

[0037] As described in the background, existing AI chips have many limitations in terms of size, speed, and power consumption. Based on this, the present invention provides a computing unit for an analog computer chip and a control method thereof. This method aims to achieve signal calculation and transmission by using a small number of analog components instead of traditional digital components, thereby effectively reducing the size of the AI ​​chip, increasing the computing speed, significantly reducing power consumption, and improving the overall performance of the AI ​​chip.

[0038] refer to Figure 1 , Figure 1 A schematic diagram of the computing unit structure of an analog computer chip according to one embodiment of the present application is shown. The computing unit includes a current-level computing unit, which includes a current-level arithmetic unit and a current-level storage unit. The current-level arithmetic unit includes a first switch M1, a second switch M2, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, and a first capacitor C1.

[0039] In the operation unit at this level, the first switch tube M1 and the second switch tube M2 form a current mirror structure. The control end of the first switch tube M1 is connected to the control end of the second switch tube M2 and is connected to the drain of the first switch tube M1. The source of the first switch tube M1 is connected to the source of the second switch tube M2 and is connected to the voltage VIN. The drain of the first switch tube M1 is connected to the source of the third switch tube M3, and the drain of the second switch tube M2 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5 respectively. The drain of the third switch tube M3 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5 respectively. The control terminal is connected to the control terminal of the fourth switch M4 and receives a first control voltage VC. The source of the fifth switch M5 is connected to the source and drain of the sixth switch M6, and the control terminal of the fifth switch M5 receives a second control voltage VD, while the control terminal of the sixth switch M6 receives a second inverted control voltage VD-1. The low-voltage terminal of the first capacitor C1 is connected to the source of the fourth switch M4 and to ground, while the high-voltage terminal of the first capacitor C1 is connected to the source of the fifth switch M5 and generates the output voltage VG' of the current-stage arithmetic unit. The storage unit of this stage is connected to the drain of the third switch M3, which outputs a first current IC to the storage unit of this stage and generates a coupling voltage VZ at its drain. The storage unit of this stage is also connected to the third control voltage VG for adjusting the magnitude of the first current IC.

[0040] In some embodiments, the first switch transistor M1 , the second switch transistor M2 , and the third switch transistor M3 are all PMOS transistors, and the fourth switch transistor M4 , the fifth switch transistor M5 , and the sixth switch transistor M6 are all NMOS transistors.

[0041] based on Figure 1 The circuit structure of the computing unit of the analog computer chip in the embodiment, the embodiment of the present application also provides a control method of the computing unit of the analog computer chip, which is applied to the computing unit of the above embodiment. Figure 2 、 Figure 3 , Figure 2 for Figure 1 Schematic diagram of the control method flow of the computing unit of the simulated computer chip, Figure 3 for Figure 1 A schematic diagram of a control voltage waveform for a computing unit in a simulated computer chip. The method comprises the following steps: S210, inputting a first control voltage VC to the control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off states of the third switch tube M3 and the fourth switch tube M4; S220, inputting a second control voltage VD to the control terminal of the fifth switch M5, and inputting a second inverted control voltage VD-1, which is opposite in level to the second control voltage VD, to the control terminal of the sixth switch M6, to control the on / off states of the fifth switch M5 and the sixth switch M6; S230, inputting a third control voltage VG to the storage unit of this stage to adjust the magnitude of the first current IC; S240, controlling the working state of the computing unit at this stage according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5; The working states of the computing unit at this level include the preparation stage, the charging stage, the power supply stage and the discharge stage.

[0042] In some embodiments, when the computing unit of this stage is in a preparatory phase, it first inputs a high-level first control voltage VC, a high-level second control voltage VD, a low-level second inverted control voltage VD-1, and a low-level third control voltage VG. At this point, the fourth switch M4 and the fifth switch M5 are in an on-state, while the first switch M1, the second switch M2, the third switch M3, and the sixth switch M6 are in an off-state. Therefore, the first capacitor C1 is discharged to 0V through the fifth and fourth switches M5 and M4. Thereafter, the second control voltage VD is switched to a low-level state, turning off the fifth switch M5. Because the fifth switch M5 releases a small amount of charge into the first capacitor C1 when it is turned off, causing the voltage across the first capacitor C1 to be greater than 0V, it is necessary to simultaneously switch the second inverted control voltage VD-1 to a high-level state when the second control voltage VD is switched to a low-level state. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a voltage state of 0V until the current level computing unit begins to enter the charging stage.

[0043] In some embodiments, when the computing unit of this stage is in the charging phase, upon commencing operation, the first control voltage VC of the computing unit of this stage is first switched to a low level, and the third control voltage VG of the storage unit of this stage is simultaneously pulled high, and the computing unit of this stage begins operation. Only when the first control voltage VC is completely pulled low does the second control voltage VD begin to increase to prevent the fourth switch M4 and the fifth switch M5 from being simultaneously turned on, which would result in an inability to accurately control the charging time of the first capacitor C1. At this point, the fourth switch M4 is turned off, and the third and fifth switches M3 and M5 are turned on. As a result, the control terminal voltages of the first and second switches M1 and M2 are pulled low by the third switch M3, turning on the first and second switches M1 and M2. At this time, the first current IC flows through the branch formed by the first switch tube M1 and the third switch tube M3. Since the first switch tube M1 and the second switch tube M2 form a current mirror structure, a charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2. This charging current flows into the first capacitor C1 to charge the first capacitor C1.

[0044] At this time, it is known from common knowledge in the field that the capacitance , where I is the charging current, which is ICC, T is the charging time, C is the capacitance of the first capacitor, which is C1, and V is the capacitor voltage after charging, which is VG'. Thus, the output voltage At this time, since the capacitance of the first capacitor C1 is fixed, the charging current ICC can be used to control the output voltage VG' by fixing the charging time T. That is, at this time, the time for the second control voltage VD to maintain a high level is set to TC, which is preferably 100ns. The charging time of the charging current ICC on the first capacitor C1 is TC. Therefore, it can be obtained that Therefore, the output voltage VG' varies with the charging current ICC, that is, with the first current IC. After the second control voltage VD remains at a high level for a period of time TC, the second control voltage VD begins to switch to a low level. When the second control voltage VD is completely pulled down, the charging phase ends and the computing unit at this level begins to enter the power supply phase.

[0045] In some embodiments, when the computing unit of this level is in the power supply phase, the second control voltage VD is in a low state, the first capacitor C1 supplies power to the outside, and the supply voltage is equal to the output voltage VG'. When the second control voltage VD is completely pulled low, the first control voltage VC is pulled high, and the third control voltage VG is simultaneously pulled low to prevent the fourth switch tube M4 and the fifth switch tube M5 from being turned on at the same time, causing the first capacitor C1 to be briefly discharged. At the same time, it can prevent the third switch tube M3 and the fifth switch tube M5 from being turned on at the same time, causing the first capacitor C1 to be briefly charged. At this time, the first switch tube M1, the second switch tube M2, and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0A. When the second control voltage VD remains in a low state for a period of time TG, that is, the computing unit of this level is in the power supply phase for a period of time TG, it then enters the discharge phase.

[0046] In some embodiments, when the computing unit at this level is in the discharge phase, the second control voltage VD is first switched to a high level, turning on the fifth switch M5. At this time, since the first control voltage VC is also in a high level, both the fourth switch M4 and the fifth switch M5 are in an on state, and the first capacitor C1 is discharged through the fifth switch M5 and the fourth switch M4. The discharge time is set to TF, which is preferably 10ns. At this time, the voltage across the first capacitor C1 is discharged to 0V. After the discharge time TF, the second control voltage VD is switched back to a low level, turning off the fifth switch M5. Since the fifth switch M5 releases a small amount of charge into the first capacitor C1 when it is turned off, causing the voltage across the first capacitor C1 to be greater than 0V, when the second control voltage VD is switched to a low level, the second inverting control voltage VD-1 needs to be switched to a high level simultaneously. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a voltage state of 0V until the current level computing unit enters the next charging stage.

[0047] From the above analysis, it can be seen that when the computing unit of this stage is in the charging phase, the control terminal voltages of the first and second switching transistors M1 and M2 must first be pulled down by the third switching transistor M3 before the first and second switching transistors M1 and M2 are turned on. At this time, if the pull-down current of the third switching transistor M3, i.e., the first current IC, is small, the turn-on response speed of the first and second switching transistors M1 and M2 will be slow, resulting in the time the computing unit of this stage is in the charging phase being less than the charging time TC, causing the output voltage VG' of the computing unit of this stage to be relatively low. Therefore, in order to improve the response speed and output voltage accuracy of the computing unit of this stage, a current source unit can be further added to the computing unit of this stage, thereby obtaining a computing unit of an analog computer chip according to another embodiment of the present application.

[0048] refer to Figure 4 , Figure 4 FIG1 shows a schematic diagram of the structure of a computing unit of an analog computer chip according to another embodiment of the present application. Figure 4 In the embodiment, the computing unit at this level includes Figure 1In addition to the arithmetic unit and storage unit of this stage shown in the embodiment, a current source unit is also included, which is used to control the first switch M1 and the second switch M2 to always be in the on state. The current source unit includes a seventh switch M7, an eighth switch M8, and a first current source B1. The seventh switch M7 and the eighth switch M8 form a current mirror structure, with the control terminal of the seventh switch M7 and the control terminal of the eighth switch M8 connected to the drain of the seventh switch M7. The current mirror ratio is determined according to the current value required by the actual circuit. The current input terminal of the first current source B1 is connected to the source of the first switch M1 and the source of the second switch M2, and is connected to the input voltage VIN. The current output terminal of the first current source B1 is connected to the drain of the seventh switch M7, and the drain of the eighth switch M8 is connected to the drain of the first switch M1. The source of the seventh switch M7 and the source of the eighth switch M8 are connected to ground.

[0049] In some embodiments, the seventh switch M7 and the eighth switch M8 are NMOS transistors. The first current source B1 continuously generates a current source current, which pulls up the control terminal voltages of the seventh and eighth switches M7 and M8, turning on the seventh and eighth switches M7 and M8. Therefore, at this time, a first pull-down current is continuously generated in the eighth switch M8 to pull down the control terminal voltages of the first and second switches M1 and M2, thereby keeping the first and second switches M1 and M2 in a constant on state.

[0050] From the above analysis, it can be seen that when the computing unit of this stage is in the charging phase, that is, the first control voltage VC of the computing unit of this stage is switched to a low level, the third control voltage VG of the storage unit of this stage is synchronously pulled high, and when the computing unit of this stage begins operation, the first switch M1 and the second switch M2 are already in the on state. Therefore, when the fourth switch M4 is turned off and the third switch M3 and the fifth switch M5 are turned on, a charging current ICC related to the magnitude of the first current IC immediately flows through the second switch M2, thereby ensuring that the computing unit of this stage is in the charging phase for a period equal to TC, thereby improving the response speed of the computing unit of this stage and the accuracy of the output voltage. Simultaneously, when the first capacitor C1 is in the discharging phase, the first control voltage VC is in a high state, and at this time, the third switch M3 is turned off. Therefore, although the first switch tube M1 and the second switch tube M2 are in the on state, the first current IC is not generated in the branch formed by the first switch tube M1 and the third switch tube M3, so that the second switch tube M2 does not generate the charging current ICC, ensuring that the first capacitor C1 is discharged smoothly, thereby improving the reliability of the calculation unit at this level.

[0051] It should be noted that multiple levels of computing units can be set in the analog computer chip. In this case, only one Figure 4The current source unit shown in the figure can be connected to all computing units in the analog computer chip; or a current source unit can be set in each level of computing unit, in which case each current source unit is only connected to the computing unit at the same level.

[0052] refer to Figure 5 , Figure 5 The following illustrates an example block diagram of an analog computer chip according to an embodiment of the present application. The analog computer chip includes an input terminal, n-level computing units, and an output terminal, where n is a positive integer. The input terminal includes one or more input interfaces (in1, in2, in3) for inputting external voltage signals. Each computing unit level includes one or more computing units, and the output terminal includes one or more output interfaces (out1, out2, out3) for outputting the n-level voltage signal.

[0053] In actual use, each level of computing unit may include one or more computing units, and the number of computing units in each level of computing unit may be the same or different, that is, the number of computing units in each level of computing unit may be any number. The computing unit at this level is a computing unit, including the computing unit at this level and the storage unit at this level. The computing unit at this level is an computing unit, and the storage unit at this level is the collection of all storage units connected to the computing unit at this level, that is, the storage unit at this level may include one or more storage units. Figure 5 As shown, in this embodiment, each level of computing unit is provided with three computing units, each computing unit includes an operation unit and three storage units, and the operation unit is connected to the three storage units. Figure 5 For example, when the arithmetic unit of this level is arithmetic unit 11, the storage units of this level are three storage units connected to arithmetic unit 11, and these three storage units and arithmetic unit 11 together constitute Figure 1 The computational unit shown in .

[0054] refer to Figure 6 , Figure 6 for Figure 5A circuit schematic diagram of a memory cell in FIG. The memory cell includes a ninth switch M9, a tenth switch M10, an eleventh switch M11, and a twelfth switch M12. The source of the ninth switch M9 is connected to its drain and is connected to a third control voltage VG, while the source of the tenth switch M10 is connected to its drain and is connected to a first voltage VE. The control terminal of the ninth switch M9, the control terminal of the tenth switch M10, and the control terminal of the eleventh switch M11 are connected, while the control terminal of the twelfth switch M12 is connected to a fourth control voltage VH. The drain of the eleventh switch M11 is connected to a coupling voltage VZ, the source of the eleventh switch M11 is connected to the drain of the twelfth switch M12, and a first sub-current IC11 of the first current flows in the branch formed by the eleventh switch M11 and the twelfth switch M12. The source of the twelfth switch M12 is connected to a second voltage VS.

[0055] In some embodiments, the ninth switch transistor M9 and the tenth switch transistor M10 are both PMOS transistors, and the eleventh switch transistor M11 and the twelfth switch transistor M12 are both NMOS transistors.

[0056] In some embodiments, when the storage cell is a first-level storage cell, the third control voltage VG is an external voltage input through the input interface. When the storage cell is not a first-level storage cell, the third control voltage VG is the output voltage of the previous-level computing unit. The coupling voltage VZ is the voltage generated by the coupling between the current-level computing unit and the current-level storage cell. Preferably, the first voltage VE is 0V; the second voltage VS is a fixed value, preferably GND.

[0057] based on Figure 6 The circuit structure of the storage unit in the figure and its working principle are as follows: When the memory cell is in regulation mode, the external regulation circuit is connected to the memory cell, the fourth control voltage VH is at a low level, and the twelfth switch M12 is in the off state. At this time, the external regulation circuit changes the floating gate charge of the eleventh switch M11 by controlling the magnitude of the third control voltage VG and the operating time of the regulation circuit, thereby adjusting the turn-on threshold voltage of the eleventh switch M11.

[0058] When the storage unit is in transfer mode, the external regulation circuit is not connected to the storage unit, the fourth control voltage VH is at a high level, and the twelfth switch tube M12 is always in the on state. At this time, when the third control voltage VG switches to a high level, the gate voltage of the eleventh switch tube M11 is pulled up, the eleventh switch tube M11 is turned on, and the first sub-current IC11 of the first current flows through the eleventh switch tube M11. At the same time, when designing the circuit, the equivalent capacitance CC1 of the ninth switch tube M9 and the equivalent capacitance CC2 of the tenth switch tube M10 are known. Therefore, it can be obtained that the gate voltage of the eleventh switch tube M11 is It is also known from common technical knowledge in this field that the first sub-current of the first current flowing through the eleventh switch tube M11 is ,in, is the electron mobility, is the oxide layer capacitance, is the ratio of the width to the length of the MOS tube, is the voltage difference between the gate and the source, is the turn-on threshold voltage. 、 and are all fixed values, and the gate-source voltage difference of the eleventh switch tube M11 is ,in, The second voltage VS is a fixed value. Therefore, for a specific input third control voltage VG, the turn-on threshold voltage can be adjusted To achieve the regulation of the first sub-current IC11 of the first current.

[0059] From the above analysis, it can be seen that when the first sub-current IC11 of the first current is recorded as y and the third control voltage VG is recorded as x, it can be obtained that , this function can be regarded as the transfer function of the storage unit. At this time, when the turn-on threshold voltage is adjusted Furthermore, after the transfer function is adjusted, the first sub-current IC11 can be adjusted by adjusting the magnitude of the third control voltage VG in the transfer mode.

[0060] Combined with the above analysis, according to Figure 5 Example of a block diagram of a computer chip in the simulation Figure 6 The circuit structure of the storage unit in Figure 4 A specific circuit structure of the computing unit in Figure 7 As shown. Figure 7 It can be seen that the storage unit at this level includes three Figure 6 The storage unit shown. Figure 7 After the calculation unit begins operation, it obtains a corresponding first sub-current IC11 of the first current based on the control voltage VG1 and the turn-on threshold voltage of the switch M111. That is, the first sub-current IC11 of the first current is obtained according to the first transfer function. Similarly, the second sub-current IC12 of the first current can be obtained according to the second transfer function, and the third sub-current IC13 of the first current can be obtained according to the third transfer function. At this point, by adding the first sub-current IC11, the second sub-current IC12, and the third sub-current IC13, the first current IC flowing out of the third switch M3 can be obtained. Therefore, it can be seen that the calculation unit in this application can perform signal accumulation operations without the need for an additional adder.

[0061] From the above analysis, it can be seen that the output voltage VG' of the calculation unit can be obtained according to the first current IC. The output voltage VG' is input to the storage unit of the next level. The storage unit of the next level obtains the corresponding sub-current according to its own transfer function. And so on, finally obtaining the voltage output by the n-th level calculation unit through the output interface.

[0062] In addition, according to Figure 5 Example of a block diagram of a computer chip in the simulation Figure 1 The circuit structure of the computing unit in the middle is used to obtain a circuit structure of a multi-level computing unit that simulates a computer chip. Figure 8 As shown. The multi-level computing unit includes a current-level computing unit and a lower-level computing unit. The output voltage VG1' of the current-level computing unit serves as the control voltage for the lower-level computing unit. Meanwhile, the current source unit is configured such that "one current source unit is provided in each level of computing unit, and each current source unit is connected only to multiple computing units in the same level."

[0063] based on Figure 8 The circuit structure of the multi-level computing unit of the analog computer chip in the embodiment, the embodiment of the present application also provides a control method for the multi-level computing unit of the analog computer chip, which is applied to Figure 8 In the multi-level computing unit of the embodiment. Figure 9 、 Figure 10 , Figure 9 for Figure 8 Schematic diagram of the control method flow of the multi-level computing unit of the simulated computer chip, Figure 10 for Figure 8 A schematic diagram of the control voltage waveform of a multi-level computing unit in a simulated computer chip. The method includes the following steps: S910: Drive the first current source B1 to generate a current source current to control the on / off states of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8; drive the twenty-first current source B21 to generate a current source current to control the on / off states of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28; S920, inputting a control voltage VC1 to the control terminals of the third switch M3 and the fourth switch M4 to control the on / off states of the third switch M3 and the fourth switch M4, and inputting a control voltage VC2 to the control terminals of the twenty-third switch M23 and the twenty-fourth switch M24 to control the on / off states of the twenty-third switch M23 and the twenty-fourth switch M24; S930: Input the control voltage VD1 to the control terminal of the fifth switch M5, and input the inverted control voltage VD1-1, which is of a level opposite to the control voltage VD1, to the control terminal of the sixth switch M6, to control the on / off states of the fifth switch M5 and the sixth switch M6. Input the control voltage VD2 to the control terminal of the twenty-fifth switch M25, and input the inverted control voltage VD2-1, which is of a level opposite to the control voltage VD2, to the control terminal of the twenty-sixth switch M26, to control the on / off states of the twenty-fifth switch M25 and the twenty-sixth switch M26. S940 , inputting a control voltage VG1 to the current level computing unit to control the magnitude of the current IC1 , and the output voltage VG1 ′ of the current level computing unit serves as the control voltage of the next level computing unit to control the magnitude of the current IC2 ; S950, controlling the working state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25; Among them, the working states of the multi-level computing units include the preparation stage, the charging stage of the current-level computing unit, the power supply stage of the current-level computing unit and the charging stage of the lower-level computing unit, the discharge stage of the current-level computing unit and the power supply stage of the lower-level computing unit, and the discharge stage of the lower-level computing unit.

[0064] In some embodiments, when the multi-stage computing unit is in a preparatory phase, the first current source B1 and the twenty-first current source B21 are driven to continuously generate current source currents. At this time, the current source currents raise the control terminal voltages of the seventh and eighth switches M7 and M8, as well as the control terminal voltages of the twenty-seventh and twenty-eighth switches M27 and M28, thereby turning on the seventh and eighth switches M7, M8, and the twenty-seventh and twenty-eighth switches M27 and M28. At this time, the eighth switch M8 continuously generates a pull-down current to lower the control terminal voltages of the first and second switches M1 and M2, thereby keeping the first and second switches M1 and M2 in a continuously turned-on state. The twenty-eighth switch M28 continuously generates a pull-down current to lower the control terminal voltages of the twenty-first and second switches M21 and M22, thereby keeping the twenty-first and second switches M21 and M22 in a continuously turned-on state.

[0065] At the same time, the input control voltages VC1 and VC2 are in a high-level state, the control voltages VD1 and VD2 are in a high-level state, the inverted control voltages VD1-1 and VD2-1 are in a low-level state, and the control voltage VG1 is in a low-level state. At this time, the fourth switch tube M4, the fifth switch tube M5, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25 are all in the on-state, and the third switch tube M3, the sixth switch tube M6, the twenty-third switch tube M23, and the twenty-sixth switch tube M26 are all in the off-state.

[0066] At this time, the first capacitor C1 is discharged to 0V through the fifth switch M5 and the fourth switch M4, and the twenty-first capacitor C21 is discharged to 0V through the twenty-fifth switch M25 and the twenty-fourth switch M24. Thereafter, the control voltages VD1 and VD2 are switched to a low level, turning off the fifth switch M5 and the twenty-fifth switch M25. Since the fifth switch M5 and the twenty-fifth switch M25 release a small amount of charge into the first capacitor C1 and the twenty-first capacitor C21, respectively, when they are turned off, causing the voltages across the first capacitor C1 and the twenty-first capacitor C21 to be greater than 0V, when the control voltages VD1 and VD2 are switched to a low level, it is necessary to simultaneously switch the inverted control voltages VD1-1 and VD2-1 to a high level. At this time, the sixth switch tube M6 and the twenty-sixth switch tube M26 are turned on, thereby respectively absorbing a small amount of charge released when the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, ensuring that the first capacitor C1 and the twenty-first capacitor C21 maintain a 0V voltage state until the computing unit at this level begins to enter the charging stage.

[0067] In some embodiments, when the computing unit of this stage is in the charging phase, the control voltage VC1 of the computing unit of this stage is first switched to a low state, and the control voltage VG1 of the storage unit of this stage is simultaneously pulled high, and the computing unit of this stage begins operation. Only when the control voltage VC1 is completely pulled low does the control voltage VD1 begin to be pulled high to prevent the fourth switch M4 and the fifth switch M5 from being simultaneously turned on, which would result in an inability to accurately control the charging time of the first capacitor C1. At this time, the fourth switch M4 is turned off, and the third switch M3 and the fifth switch M5 are turned on. Since the first switch M1 and the second switch M2 are already in the on state, after the fourth switch M4 is turned off, the third switch M3 is turned on, and the fifth switch M5 is turned on, a charging current ICC1 related to the magnitude of current IC1 immediately flows through the second switch M2, thereby ensuring that the time the computing unit of this stage is in the charging phase is equal to TC, which is preferably 100 ns. This charging current ICC1 flows into the first capacitor C1 to charge the first capacitor C1.

[0068] At this time, it is known from common knowledge in the art that the output voltage of the first capacitor C1 is Since the capacitance value and charging time TC of the first capacitor C1 are both fixed values, the output voltage VG1' changes with the charging current ICC1, that is, with the change of the current IC1. When the control voltage VD1 maintains a high level for a time period of TC, the control voltage VD1 begins to switch to a low level. At the same time, the control voltage VC2 of the lower-level computing unit also begins to switch to a low level synchronously. When the control voltage VD1 and the control voltage VC2 of the lower-level computing unit are completely pulled down, the charging stage of the current-level computing unit ends, the current-level computing unit begins to enter the power supply stage, and the lower-level computing unit enters the charging stage.

[0069] In some embodiments, when the current computing unit is in the power supply phase and the lower computing unit is in the charging phase, the control voltage VD1 and the control voltage VC2 are at a low level, turning off the fifth switch M5 and the twenty-fourth switch M24 and turning on the twenty-third switch M23. At this point, the control voltage VC1 begins to increase, the control voltage VG1 begins to decrease, and the control voltage VD2 of the lower computing unit begins to increase. After the control voltage VC1 is fully increased, the third switch M3 is turned off and the fourth switch M4 is turned on. This prevents the fourth and fifth switches M4, M5 from being turned on simultaneously, which would cause a brief discharge of the first capacitor C1. This also prevents the third and fifth switches M3, M5 from being turned on simultaneously, which would cause a brief charge of the first capacitor C1. At this point, the output voltage VG1' of the current computing unit supplies power to the lower storage unit, generating a current IC2 in the twenty-third switch M23.

[0070] At the same time, when the control voltage VC1 is fully pulled up and the control voltage VG1 is fully pulled down, the control voltage VD2 of the lower-level operation unit is fully pulled up, and the Figure 10 It can be seen that the control voltage VD2 does not begin to increase until the control voltage VC2 is completely pulled low, to prevent the twenty-fourth switch M24 and the twenty-fifth switch M25 from being turned on simultaneously, which would result in an inability to accurately control the charging time of the twenty-first capacitor C21. At this time, the twenty-fourth switch M24 is turned off, and the twenty-third switch M23 and the twenty-fifth switch M25 are turned on. Since the twenty-first switch M21 and the twenty-second switch M22 are already in the on state, a charging current ICC2 related to the magnitude of the current IC2 immediately flows through the twenty-second switch M22, thereby ensuring that the time the lower-level computing unit is in the charging phase is equal to TC, which is preferably 100 ns. This charging current ICC2 flows into the twenty-first capacitor C21, charging the twenty-first capacitor C21 of the lower-level computing unit.

[0071] At this time, it is known from common knowledge in the art that the output voltage of the twenty-first capacitor C21 is Because the capacitance and charging time TC of the twenty-first capacitor C21 are both fixed, the output voltage VG2' varies with the charging current ICC2, that is, with the current IC2. After the control voltage VD2 remains at a high level for a period of time TC, the control voltage VD2 begins to switch to a low level. When the control voltage VD2 is completely pulled down, the charging phase of the lower-level computing unit ends. At this point, the twenty-first capacitor C21 supplies power to the next-level computing unit (not shown in the figure), and the power supply voltage is equal to the output voltage VG2'.

[0072] When the control voltage VD2 is completely pulled down, the control voltage VD1 and the control voltage VC2 start to switch from low level to high level, the current level calculation unit starts to enter the discharge stage, and the lower level calculation unit starts to enter the power supply stage. Figure 10 It can be seen that the time that the control voltage VD1 remains at a low level is TG, that is, the time that the computing unit of this level is in the power supply stage is TG. Since the sum of the rising edge time and the falling edge time of the control voltage VD2 is T0, it can be obtained that the power supply time TG = TC + T0. Preferably, T0 is 1ns and TC is 100ns, that is, TG is 101ns.

[0073] In some embodiments, when the current-level computing unit is in the discharge phase and the lower-level computing unit is in the power supply phase, the control voltage VD1 is switched back to a high state after remaining at a low level for a period of time TG, turning on the fifth switch M5. At this point, since the control voltage VC1 is also at a high level, both the fourth switch M4 and the fifth switch M5 are in an on state, and the first capacitor C1 is discharged through the fifth and fourth switches M5 and M4. The discharge time is set to TF, preferably 10 ns. At this point, the voltage across the first capacitor C1 is discharged to 0V. After the time TF, the control voltage VD1 is switched back to a low state, turning off the fifth switch M5. Since the fifth switch M5 releases a small amount of charge into the first capacitor C1 when it is turned off, causing the voltage across the first capacitor C1 to be greater than 0V, when the control voltage VD1 is switched to a low state, the inverted control voltage VD1-1 is simultaneously switched to a high state. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a voltage state of 0V until the current level computing unit enters the next charging stage.

[0074] Meanwhile, when the computing unit at this level is in the discharge phase, the control voltage VC1 is at a high level, and the third switch M3 is turned off. Therefore, although the first switch M1 and the second switch M2 are on, no current IC1 is generated in the branch formed by the first switch M1 and the third switch M3. Consequently, the second switch M2 also does not generate a charging current ICC1, ensuring that the first capacitor C1 is discharged smoothly.

[0075] From the above analysis, it can be seen that when the control voltage VD2 is fully pulled low, the charging phase of the lower-level computing unit ends. At this point, the 25th switch M25 is turned off, and the 21st capacitor C21 supplies power to the next-level computing unit (not shown). The power supply voltage is equal to the output voltage VG2', generating a current IC3 (not shown) in the next-level computing unit. Simultaneously, the control voltage VC2 begins to increase. Once the control voltage VC2 is fully pulled high, the 23rd switch M23 is turned off, and the 24th switch M24 is turned on. This prevents the 24th and 25th switches M24 and M25 from being simultaneously turned on, which would cause the 21st capacitor C21 to briefly discharge. This also prevents the 23rd and 25th switches M23 and M25 from being simultaneously turned on, which would cause the 21st capacitor C21 to briefly charge. When the control voltage VD2 remains low for a period of TG, i.e., the lower-level computing unit remains in the power supply phase for TG, it then enters the discharge phase.

[0076] In some embodiments, when the lower-level computing unit is in the discharge phase, the control voltage VD2 is first switched to a high level, turning on the twenty-fifth switch M25. At this point, because the control voltage VC2 is also high, both the twenty-fourth switch M24 and the twenty-fifth switch M25 are turned on, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch M25 and the twenty-fourth switch M24. The discharge time is set to TF, preferably 10 ns. At this point, the voltage across the twenty-first capacitor C21 is discharged to 0 V. After the discharge time TF, the control voltage VD2 is switched back to a low level, turning off the twenty-fifth switch M25. Since a small amount of charge is released into the twenty-first capacitor C21 when the twenty-fifth switch tube M25 is turned off, causing the voltage across the twenty-first capacitor C21 to be greater than 0V, when the control voltage VD2 is switched to a low-level state, the inverted control voltage VD2-1 needs to be synchronously switched to a high-level state. At this time, the twenty-sixth switch tube M26 is turned on to absorb the small amount of charge released when the twenty-fifth switch tube M25 is turned off, ensuring that the voltage of the twenty-first capacitor C21 remains at 0V until the lower-level computing unit enters the next charging stage.

[0077] Meanwhile, when the lower-level computing unit is in the discharge phase, the control voltage VC2 is at a high level, and the twenty-third switch M23 is turned off. Therefore, although the twenty-first switch M21 and the twenty-second switch M22 are in the on state, no current IC2 is generated in the branch formed by the twenty-first switch M21 and the twenty-third switch M23. Consequently, no charging current ICC2 is generated by the twenty-second switch M22, ensuring that the twenty-first capacitor C21 is discharged smoothly.

[0078] Similarly, when Figure 8 When the circuit structure of the multi-level computing unit shown is three-level, four-level or even N-level, the above-mentioned control method can be used to control it, which will not be described in detail here.

[0079] In summary, the computing unit of the analog computer chip provided in the embodiment of the present application replaces the traditional adder structure with a small number of analog components to realize the accumulation operation of signals, significantly reducing the size of the artificial intelligence chip, speeding up the operation speed, and effectively reducing power consumption. In addition, the present application also sets a current source unit in the computing unit, and by optimizing the conduction sequence of the switch tube, ensures that the time the computing unit is in the charging stage is equal to the charging time TC, thereby improving the response speed of the computing unit and the accuracy of the output voltage. At the same time, the computing unit of the present application is provided with an absorption switch tube, which can absorb the excess charge released when the switch tube is turned off, ensuring that the capacitor is maintained at 0V state, thereby improving the accuracy of the computing unit. In addition, the present application also provides a control method for the computing unit, which ensures the safety and reliability of the capacitor discharge and charging by setting a reasonable switch logic sequence. Furthermore, the present application also obtains a high-precision and high-reliability output voltage through the coordinated control of multi-level computing units, providing a stable performance guarantee for the analog computer chip.

[0080] It should be noted that the computing unit structure of the analog computer chip provided in this embodiment is merely a preferred circuit structure for achieving the purpose of the present invention. In other embodiments, each circuit module or device may also use other circuit structures that can achieve equivalent functions, and this application is not limited thereto.

[0081] The above description is merely a preferred embodiment of the present invention and does not constitute any other form of limitation to the present invention. Any person skilled in the art may utilize the technical contents disclosed above to change or modify them into equivalent embodiments with equivalent changes for application in other fields. However, any simple modification, equivalent change, and modification of the above embodiments made in accordance with the technical essence of the present invention without departing from the technical solution of the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A computing unit simulating a computer chip, characterized in that: The present-stage computing unit includes a present-stage computing unit and a present-stage storage unit; wherein the present-stage computing unit includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1; In the operation unit of the present stage, the first switch tube M1 and the second switch tube M2 form a current mirror structure, the control end of the first switch tube M1 is connected to the control end of the second switch tube M2 and connected to the drain of the first switch tube M1, and the drain of the first switch tube M1 is connected to the source of the third switch tube M3, and the drain of the second switch tube M2 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5 respectively; the control end of the third switch tube M3 is connected to the control end of the fourth switch tube M4 and connected to the first control voltage VC; the source of the fifth switch tube M5 is connected to the source and drain of the sixth switch tube M6, and the control end of the fifth switch tube M5 is connected to the second control voltage VD, and the control end of the sixth switch tube M6 is connected to the second inverting control voltage VD-1; the low voltage end of the first capacitor C1 is connected to the source of the fourth switch tube M4 and grounded, and the high voltage end of the first capacitor C1 is connected to the source of the fifth switch tube M5 and generates the output voltage VG' of the operation unit of the present stage; The storage unit at this stage is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs the first current IC to the storage unit at this stage and generates a coupling voltage VZ at its drain end; the storage unit at this stage is also connected to a third control voltage VG for adjusting the size of the first current IC.

2. The calculation unit according to claim 1, characterized in that The first switch tube M1 , the second switch tube M2 , and the third switch tube M3 are all PMOS tubes, and the fourth switch tube M4 , the fifth switch tube M5 , and the sixth switch tube M6 are all NMOS tubes.

3. The calculation unit according to claim 1, characterized in that It also includes a current source unit for controlling the first switch tube M1 and the second switch tube M2 to always be in a conducting state; The current source unit includes a seventh switch tube M7, an eighth switch tube M8 and a first current source B1; the seventh switch tube M7 and the eighth switch tube M8 form a current mirror structure, the control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are connected and connected to the drain of the seventh switch tube M7, the current input end of the first current source B1 is connected to the source of the first switch tube M1 and the source of the second switch tube M2 and is connected to the input voltage VIN; the current output end of the first current source B1 is connected to the drain of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the drain of the first switch tube M1; the source of the seventh switch tube M7 and the source of the eighth switch tube M8 are connected and grounded.

4. The calculation unit according to claim 3, characterized in that The seventh switch tube M7 and the eighth switch tube M8 are both NMOS tubes.

5. The calculation unit according to claim 4, characterized in that The first current source B1 always generates a current source current, which is used to pull up the control terminal voltages of the seventh switch tube M7 and the eighth switch tube M8, so that the seventh switch tube M7 and the eighth switch tube M8 are turned on, so as to generate a pull-down current in the eighth switch tube M8 to pull down the control terminal voltages of the first switch tube M1 and the second switch tube M2, so that the first switch tube M1 and the second switch tube M2 are always in a turned-on state; When the calculation unit at this level is in the charging stage, at the moment when the fourth switch tube M4 is turned off and the third switch tube M3 and the fifth switch tube M5 are turned on, the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 immediately to charge the first capacitor C1; when the calculation unit at this level is in the discharging stage, the third switch tube M3 is turned off, the first current IC is not generated in the first switch tube M1, and the charging current ICC is not generated in the second switch tube M2, so that the first capacitor C1 is discharged smoothly.

6. The computing unit according to any one of claims 3 to 5, characterized in that: The computing unit at this level is one computing unit, and the storage unit at this level is a collection of all storage units connected to the computing unit at this level, including one or more storage units.

7. The calculation unit according to claim 6, characterized in that One of the storage units includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11 and a twelfth switch tube M12; In the storage unit, the source of the ninth switch tube M9 is connected to its drain and connected to the third control voltage VG, the source of the tenth switch tube M10 is connected to its drain and connected to the first voltage VE; the control end of the ninth switch tube M9 and the control end of the tenth switch tube M10 are connected to the control end of the eleventh switch tube M11, and the control end of the twelfth switch tube M12 is connected to the fourth control voltage VH; the drain of the eleventh switch tube M11 is connected to the coupling voltage VZ, the source of the eleventh switch tube M11 is connected to the drain of the twelfth switch tube M12, and the first sub-current IC11 of the first current IC flows through the eleventh switch tube M11, and the source of the twelfth switch tube M12 is connected to the second voltage VS.

8. The calculation unit according to claim 7, characterized in that The ninth switch tube M9 and the tenth switch tube M10 are both PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are both NMOS tubes.

9. The calculation unit according to claim 8, characterized in that When the storage unit is a first-level storage unit, the third control voltage VG is an input external voltage; when the storage unit is not a first-level storage unit, the third control voltage VG is an output voltage of a previous-level calculation unit; The first voltage VE is 0V; the coupling voltage VZ is a voltage generated by the mutual coupling between the operation unit at this stage and the storage unit at this stage; and the second voltage VS is a fixed value.

10. The calculation unit according to claim 9, characterized in that The transfer function of the storage unit is: ； In the formula, represents a first sub-current IC11 of the first current IC flowing through the eleventh switch tube M11, represents the third control voltage VG, , and are respectively the electron mobility, oxide layer capacitance and the ratio of the width to the length of the MOS tube of the eleventh switch tube M11, CC1 is the equivalent capacitance of the ninth switch tube M9, CC2 is the equivalent capacitance of the tenth switch tube M10, is the turn-on threshold voltage of the eleventh switch tube M11; The transfer function of the memory cell is determined by the turn-on threshold voltage Make adjustments; After the transfer function of the storage unit is adjusted, the magnitude of the first sub-current IC11 of the storage unit is determined by the magnitude of the third control voltage VG.

11. The computing unit according to any one of claims 7 to 10, characterized in that: The analog computer chip includes multiple levels of computing units, each level of computing units includes one or more computing units, and the number of computing units in each level of computing units is the same or different; The computing unit at this level is a computing unit, the computing unit at this level is a computing unit, and the storage unit at this level is a set of all storage units connected to the computing unit at this level, including one or more storage units; The current source unit is connected to the computing units in the same level or different levels, so that multiple computing units in the same level share one current source unit, or multiple computing units in different levels share one current source unit.

12. A control method for a computing unit simulating a computer chip, characterized in that: Applied to the computing unit as claimed in claim 1 or 2, the method comprises: Inputting a first control voltage VC to control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4; Input a second control voltage VD to the control end of the fifth switch tube M5, and input a second inverted control voltage VD-1 having a level opposite to the second control voltage VD to the control end of the sixth switch tube M6, so as to control the on and off states of the fifth switch tube M5 and the sixth switch tube M6; Inputting a third control voltage VG to the storage unit of this stage to adjust the magnitude of the first current IC; Controlling the working state of the computing unit at this level according to the on / off states of the third switch tube M3, the fourth switch tube M4 and the fifth switch tube M5; The working state of the computing unit at this level includes a preparation stage, a charging stage, a power supply stage and a discharging stage.

13. The control method according to claim 12, characterized in that: When the current level calculation unit is in the preparation stage, firstly, the first control voltage VC in the high level state, the second control voltage VD in the high level state, the second inverted control voltage VD-1 in the low level state, and the third control voltage VG in the low level state are input, so that the fourth switch tube M4 and the fifth switch tube M5 are turned on, the first switch tube M1, the second switch tube M2, the third switch tube M3, and the sixth switch tube M6 are all turned off, and the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4; After the voltage across the first capacitor C1 is discharged to 0V, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit begins to enter the charging stage.

14. The control method according to claim 13, characterized in that: When the computing unit at this level is in the charging stage, the first control voltage VC is first switched to a low level state, the third control voltage VG is synchronously pulled up, and when the first control voltage VC is completely pulled down, the second control voltage VD is pulled up, so that the fourth switch tube M4 is turned off, and the third switch tube M3 and the fifth switch tube M5 are turned on, so that the control terminal voltages of the first switch tube M1 and the second switch tube M2 are pulled down by the third switch tube M3, so that the first switch tube M1 and the second switch tube M2 are turned on, and then the first current IC flows through the branch formed by the first switch tube M1 and the third switch tube M3, and the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 to charge the first capacitor C1; When the charging time reaches TC, the second control voltage VD is switched to a low level state, and when the second control voltage VD is completely pulled down, the computing unit at this level begins to enter the power supply stage.

15. The control method according to claim 14, characterized in that: When the computing unit at this level is in the power supply stage, the second control voltage VD is in a low level state, the first capacitor C1 supplies power to the outside, and when the second control voltage VD is completely pulled down, the first control voltage VC is pulled up, and the third control voltage VG is pulled down synchronously, so that the first switch tube M1, the second switch tube M2 and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0A; When the time for which the second control voltage VD remains in the low level state reaches TG, the computing unit at this stage begins to enter the discharge stage.

16. The control method according to claim 15, characterized in that: When the current-stage computing unit is in the power supply stage, the output voltage VG' of the first capacitor C1 is: ； Wherein, ICC is a charging current related to the magnitude of the first current IC, TC is a charging time of the charging current ICC for the first capacitor C1, and C1 is a capacitance value of the first capacitor C1; The output voltage VG′ is regulated by the first current IC.

17. The control method according to claim 15 or 16, characterized in that: When the current level calculation unit is in the discharge stage, the second control voltage VD is first switched to a high level state to turn on the fifth switch tube M5, and the first control voltage VC is in a high level state to turn on the fourth switch tube M4, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4; When the discharge time reaches TF, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit enters the next charging stage.

18. The control method according to claim 17, characterized in that: The charging time TC is set to 100 ns, and the discharging time TF is set to 10 ns.

19. A control method for a multi-level computing unit simulating a computer chip, characterized in that: Applied to the multi-level computing unit as claimed in claim 11, the multi-level computing unit includes a computing unit at the same level and a computing unit at the next level, and each computing unit at the same level shares a current source unit; the method includes: The first current source B1 is driven to generate a current source current, so as to control the on / off state of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8; the twenty-first current source B21 is driven to generate a current source current, so as to control the on / off state of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28; A control voltage VC1 is input to the control ends of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4; a control voltage VC2 is input to the control ends of the twenty-third switch tube M23 and the twenty-fourth switch tube M24 to control the on / off state of the twenty-third switch tube M23 and the twenty-fourth switch tube M24; A control voltage VD1 is input to the control end of the fifth switch tube M5, and an inverted control voltage VD1-1 having a level opposite to that of the control voltage VD1 is input to the control end of the sixth switch tube M6, so as to control the on / off states of the fifth switch tube M5 and the sixth switch tube M6; a control voltage VD2 is input to the control end of the twenty-fifth switch tube M25, and an inverted control voltage VD2-1 having a level opposite to that of the control voltage VD2 is input to the control end of the twenty-sixth switch tube M26, so as to control the on / off states of the twenty-fifth switch tube M25 and the twenty-sixth switch tube M26; A control voltage VG1 is input to the current level calculation unit to control the magnitude of the current IC1, and the output voltage VG1' of the current level calculation unit is the control voltage of the next level calculation unit to control the magnitude of the current IC2; Controlling the working state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25; Among them, the working states of the multi-level computing units include a preparation stage, a charging stage of the computing unit at this level, a power supply stage of the computing unit at this level and a charging stage of the lower-level computing unit, a discharge stage of the computing unit at this level and a power supply stage of the lower-level computing unit, and a discharge stage of the lower-level computing unit.

20. The control method according to claim 19, characterized in that: When the multi-stage computing unit is in the preparation stage, the first current source B1 and the twenty-first current source B21 are driven to always generate current source current, the eighth switch tube M8 generates a pull-down current so that the first switch tube M1 and the second switch tube M2 are always in a conducting state, and the twenty-eighth switch tube M28 generates a pull-down current so that the twenty-first switch tube M21 and the twenty-second switch tube M22 are always in a conducting state; The input control voltages VC1 and VC2 are in a high-level state, the control voltages VD1 and VD2 are in a high-level state, the inverted control voltages VD1-1 and VD2-1 are in a low-level state, and the control voltage VG1 is in a low-level state, so that the fourth switch tube M4, the fifth switch tube M5, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25 are all turned on, the third switch tube M3, the sixth switch tube M6, the twenty-third switch tube M23, and the twenty-sixth switch tube M26 are all turned off, the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24; After the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are discharged to 0V, the control voltage VD1 and the control voltage VD2 are switched to a low level state, and the inverted control voltage VD1-1 and the inverted control voltage VD2-1 are synchronously switched to a high level state, so that the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, and the sixth switch tube M6 and the twenty-sixth switch tube M26 are turned on, and the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are maintained at 0V until the current-stage computing unit begins to enter the charging stage.

21. The control method according to claim 20, characterized in that: When the computing unit of this stage is in the charging stage, the control voltage VC1 of the computing unit of this stage is switched to a low level state, the control voltage VG1 of the storage unit of this stage is pulled up synchronously, and when the control voltage VC1 is completely pulled down, the control voltage VD1 is pulled up, so that the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, and the charging current ICC1 related to the current IC1 flows through the second switch tube M2 immediately to charge the first capacitor C1; When the charging time reaches TC, the control voltage VD1 is switched to a low level state, and the control voltage VC2 of the lower-level computing unit is synchronously switched to a low level state. When the control voltage VD1 and the control voltage VC2 are completely pulled low, the computing unit at this level begins to enter the power supply stage, and the lower-level computing unit enters the charging stage.

22. The control method according to claim 21, characterized in that: When the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VC1 is pulled high and the control voltage VG1 is pulled low synchronously, so that the third switch tube M3 is turned off, the fourth switch tube M4 is turned on, the control voltage VD1 and the control voltage VC2 are in a low level state, the fifth switch tube M5 and the twenty-fourth switch tube M24 are turned off, the twenty-third switch tube M23 is turned on, and the output voltage VG1' of the current computing unit supplies power to the lower storage unit, and a current IC2 is generated in the twenty-third switch tube M23; When the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VD2 is pulled high to turn on the twenty-fifth switch tube M25, and the charging current ICC2 related to the current IC2 flows through the twenty-second switch tube M22 immediately to charge the twenty-first capacitor C21; When the charging time reaches TC, the control voltage VD2 is switched to a low level state, and when the control voltage VD2 is completely pulled down, the control voltage VD1 remains in a low level state for TG, and the current level computing unit begins to enter the discharge stage, while the lower level computing unit enters the power supply stage.

23. The control method according to claim 22, characterized in that: When the computing unit at this stage is in the power supply stage, the output voltage VG1' of the computing unit at this stage is: ； Wherein, ICC1 is a charging current related to the current IC1, TC is a charging time of the first capacitor C1 by the charging current ICC1, and C1 is a capacitance value of the first capacitor; The output voltage VG1 ′ is regulated by the current IC1 .

24. The control method according to claim 23, characterized in that: When the computing unit at this level is in the power supply stage, the power supply time of the computing unit at this level is: ； Wherein, TG is the time that the control voltage VD1 maintains a low level, T0 is the sum of the rising edge time and the falling edge time of the control voltage VD2, and TC is the charging time of the charging current ICC2 on the twenty-first capacitor C21.

25. The control method according to any one of claims 22 to 24, characterized in that: When the current computing unit is in the discharge stage and the lower computing unit is in the power supply stage, the control voltage VD1 is switched to a high level state, so that the fifth switch tube M5 is turned on, the control voltage VC1 is in a high level state, the control voltage VG1 is in a low level state, the fourth switch tube M4 is turned on, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4; When the discharge time reaches TF, the control voltage VD1 is switched to a low level state, and the inverted control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current level calculation unit enters the next charging stage; When the computing unit of the current level is in the discharge stage and the computing unit of the next level is in the power supply stage, the control voltage VC2 is pulled high, so that the twenty-third switch tube M23 is turned off, the twenty-fourth switch tube M24 is turned on, the control voltage VD2 is in a low level state, the twenty-fifth switch tube M25 is turned off, and the output voltage VG2' of the computing unit of the next level supplies power to the computing unit of the next level, and generates a current IC3 in the computing unit of the next level; When the control voltage VD2 maintains the low level state for a period of time reaching TG, it is switched to the high level state, and the lower-level computing unit begins to enter the discharge stage.

26. The control method according to claim 25, characterized in that: When the lower-level computing unit is in the power supply stage, the output voltage VG2' of the lower-level computing unit is: ； Wherein, ICC2 is a charging current related to the current IC2, TC is a charging time of the charging current ICC2 on the twenty-first capacitor C21, and C21 is a capacitance value of the twenty-first capacitor; The output voltage VG2 ′ is regulated by the current IC2 .

27. The control method according to claim 26, characterized in that: When the lower computing unit is in the discharge stage, the control voltage VD2 is first switched to a high level state, so that the twenty-fifth switch tube M25 is turned on, the control voltage VC2 is in a high level state, the twenty-fourth switch tube M24 is turned on, and the twenty-first capacitor C21 is discharged to 0V through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24; When the discharge time reaches TF, the control voltage VD2 is switched to a low level state, and the inverting control voltage VD-2 is synchronously switched to a high level state, so that the twenty-fifth switch tube M25 is turned off, the twenty-sixth switch tube M26 is turned on, and the voltage across the twenty-first capacitor C21 is maintained at 0V until the lower-level computing unit enters the next charging stage.

28. The control method according to claim 27, characterized in that: The power supply time TG is set to 101ns, the charging time TC is set to 100ns, the discharging time TF is set to 10ns, and T0 is set to 1ns.

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