A computing unit simulating a computer chip and a control method thereof

Abstract

The present application discloses a computing unit of an analog computer chip and a control method thereof, and relates to the field of artificial intelligence chips. The computing unit includes a computing unit at this level, and the computing unit at this level includes an operation unit at this level and a storage unit at this level; the operation unit at this level includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1. The storage unit at this level is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs a first current IC to the storage unit at this level and generates a coupling voltage VZ at its drain end; the storage unit at this level is also connected to a third control voltage VG to adjust the size of the first current IC. The computing unit does not need to use a traditional adder structure, and can realize the accumulation operation of signals only through a small number of analog components, which reduces the size of the artificial intelligence chip, improves the operation speed, and effectively reduces power consumption.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence chips, and in particular to a computing unit simulating a computer chip and a control method thereof. Background Art

[0002] With the development of artificial intelligence technology, the performance requirements for artificial intelligence chips are increasing. Artificial intelligence chips in the prior art are usually based on digital computer chips, and their core computing units use digital computing methods. Each core computing unit requires tens of thousands to hundreds of thousands of transistors, so that existing artificial intelligence chips can usually only accommodate a few thousand core computing units. These core computing units are usually composed of storage units and computing units. Among them, the storage unit first performs a linear transformation on the input data, and then performs a nonlinear transformation on the linearly transformed data through an activation function, and then accumulates it through a computing unit composed of an adder, and then enters the next linear transformation, and so on.

[0003] Therefore, in order to realize the simultaneous calculation of tens of thousands or even hundreds of millions of data, it is necessary to rely on a large number of core computing units for parallel processing. This requirement has led to the problems of large size, slow speed and high power consumption of artificial intelligence chips based on digital computer chips in the existing technology, which has limited its development and application in high-performance computing. Summary of the invention

[0004] The purpose of the present invention is to provide a computing unit of an analog computer chip and a control method thereof, which realizes the accumulation operation of signals by adopting a small number of analog components to replace the traditional adder structure, effectively reduces the size of the artificial intelligence chip, improves the operation speed, and reduces power consumption.

[0005] To achieve the above object, the present invention discloses the following technical solution:

[0006] In a first aspect of the present invention, a computing unit of an analog computer chip is provided, the computing unit comprising a current-stage computing unit, the current-stage computing unit comprising a current-stage operation unit and a current-stage storage unit; wherein the current-stage operation unit comprises a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1;

[0007] In the operation unit of the present stage, the first switch tube M1 and the second switch tube M2 form a current mirror structure, the control end of the first switch tube M1 is connected to the control end of the second switch tube M2 and connected to the drain of the first switch tube M1, and the drain of the first switch tube M1 is connected to the source of the third switch tube M3, and the drain of the second switch tube M2 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5 respectively; the control end of the third switch tube M3 is connected to the control end of the fourth switch tube M4 and connected to the first control voltage VC; the source of the fifth switch tube M5 is connected to the source and drain of the sixth switch tube M6, and the control end of the fifth switch tube M5 is connected to the second control voltage VD, and the control end of the sixth switch tube M6 is connected to the second inverting control voltage VD-1; the low voltage end of the first capacitor C1 is connected to the source of the fourth switch tube M4 and grounded, and the high voltage end of the first capacitor C1 is connected to the source of the fifth switch tube M5 and generates the output voltage VG' of the operation unit of the present stage;

[0008] The storage unit at this stage is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs the first current IC to the storage unit at this stage and generates a coupling voltage VZ at its drain end; the storage unit at this stage is also connected to a third control voltage VG for adjusting the size of the first current IC.

[0009] In a possible implementation, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are all PMOS tubes, and the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are all NMOS tubes.

[0010] In a possible implementation, the calculation unit further includes a current source unit, which is used to control the first switch tube M1 and the second switch tube M2 to always be in a conducting state;

[0011] The current source unit includes a seventh switch tube M7, an eighth switch tube M8 and a first current source B1; the seventh switch tube M7 and the eighth switch tube M8 form a current mirror structure, the control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are connected and connected to the drain of the seventh switch tube M7, the current input end of the first current source B1 is connected to the source of the first switch tube M1 and the source of the second switch tube M2 and is connected to the input voltage VIN; the current output end of the first current source B1 is connected to the drain of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the drain of the first switch tube M1; the source of the seventh switch tube M7 and the source of the eighth switch tube M8 are connected and grounded.

[0012] In a possible implementation, the first current source B1 always generates a current source current, which is used to pull up the control terminal voltages of the seventh switch tube M7 and the eighth switch tube M8, so that the seventh switch tube M7 and the eighth switch tube M8 are turned on, so as to generate a pull-down current in the eighth switch tube M8 to pull down the control terminal voltages of the first switch tube M1 and the second switch tube M2, so that the first switch tube M1 and the second switch tube M2 are always in a turned-on state;

[0013] When the calculation unit at this level is in the charging stage, at the moment when the fourth switch tube M4 is turned off and the third switch tube M3 and the fifth switch tube M5 are turned on, the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 immediately to charge the first capacitor C1; when the calculation unit at this level is in the discharging stage, the third switch tube M3 is turned off, the first current IC is not generated in the first switch tube M1, and the charging current ICC is not generated in the second switch tube M2, so that the first capacitor C1 is discharged smoothly.

[0014] In a possible implementation, the computing unit at this stage is one computing unit, and the storage unit at this stage is a set of all storage units connected to the computing unit at this stage, including one or more storage units.

[0015] In a possible implementation, one of the storage units includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11, and a twelfth switch tube M12;

[0016] In the storage unit, the source of the ninth switch tube M9 is connected to its drain and connected to the third control voltage VG, the source of the tenth switch tube M10 is connected to its drain and connected to the first voltage VE; the control end of the ninth switch tube M9 and the control end of the tenth switch tube M10 are connected to the control end of the eleventh switch tube M11, and the control end of the twelfth switch tube M12 is connected to the fourth control voltage VH; the drain of the eleventh switch tube M11 is connected to the coupling voltage VZ, the source of the eleventh switch tube M11 is connected to the drain of the twelfth switch tube M12, and the first sub-current IC11 of the first current IC flows through the eleventh switch tube M11, and the source of the twelfth switch tube M12 is connected to the second voltage VS.

[0017] In a possible implementation, the ninth switch tube M9 and the tenth switch tube M10 are both PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are both NMOS tubes.

[0018] In a possible implementation, when the storage unit is a first-level storage unit, the third control voltage VG is an input external voltage, and when the storage unit is not a first-level storage unit, the third control voltage VG is an output voltage of a previous-level computing unit;

[0019] The first voltage VE is 0V; the coupling voltage VZ is a voltage generated by the mutual coupling between the operation unit at this stage and the storage unit at this stage; and the second voltage VS is a fixed value.

[0020] In a possible implementation, the transfer function of the storage unit is:

[0021] ;

[0022] In the formula, represents a first sub-current IC11 of the first current IC flowing through the eleventh switch tube M11, represents the third control voltage VG, , and are respectively the electron mobility, oxide layer capacitance and the ratio of the width to the length of the MOS tube of the eleventh switch tube M11, CC1 is the equivalent capacitance of the ninth switch tube M9, CC2 is the equivalent capacitance of the tenth switch tube M10, is the turn-on threshold voltage of the eleventh switch tube M11;

[0023] The transfer function of the memory cell is determined by the turn-on threshold voltage Make adjustments;

[0024] After the transfer function of the storage unit is adjusted, the magnitude of the first sub-current IC11 of the storage unit is determined by the magnitude of the third control voltage VG.

[0025] In a possible implementation, the analog computer chip includes multiple levels of computing units, each level of computing units includes one or more computing units, and the number of computing units in each level of computing units is the same or different;

[0026] The computing unit at this level is a computing unit, the computing unit at this level is a computing unit, and the storage unit at this level is a set of all storage units connected to the computing unit at this level, including one or more storage units;

[0027] The current source unit is connected to the computing units in the same level or different levels, so that multiple computing units in the same level share one current source unit, or multiple computing units in different levels share one current source unit.

[0028] Another aspect of the present invention provides a control method for a computing unit simulating a computer chip, which is applied to the computing unit as described in the first aspect, and the method comprises:

[0029] Inputting a first control voltage VC to control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4;

[0030] Input a second control voltage VD to the control end of the fifth switch tube M5, and input a second inverted control voltage VD-1 having a level opposite to the second control voltage VD to the control end of the sixth switch tube M6, so as to control the on and off states of the fifth switch tube M5 and the sixth switch tube M6;

[0031] Inputting a third control voltage VG to the storage unit of this stage to adjust the magnitude of the first current IC;

[0032] Controlling the working state of the computing unit at this level according to the on / off states of the third switch tube M3, the fourth switch tube M4 and the fifth switch tube M5;

[0033] The working state of the computing unit at this level includes a preparation stage, a charging stage, a power supply stage and a discharging stage.

[0034] In a possible implementation, when the computing unit at this level is in the preparatory stage, firstly, a first control voltage VC in a high level state, a second control voltage VD in a high level state, a second inverted control voltage VD-1 in a low level state, and a third control voltage VG in a low level state are input, so that the fourth switch tube M4 and the fifth switch tube M5 are turned on, the first switch tube M1, the second switch tube M2, the third switch tube M3, and the sixth switch tube M6 are all turned off, and the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4;

[0035] After the voltage across the first capacitor C1 is discharged to 0V, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit begins to enter the charging stage.

[0036] In a possible implementation, when the computing unit at this level is in the charging stage, the first control voltage VC is first switched to a low level state, the third control voltage VG is synchronously pulled high, and when the first control voltage VC is completely pulled low, the second control voltage VD is pulled high, so that the fourth switch tube M4 is turned off, and the third switch tube M3 and the fifth switch tube M5 are turned on, so that the control terminal voltages of the first switch tube M1 and the second switch tube M2 are pulled low by the third switch tube M3, so that the first switch tube M1 and the second switch tube M2 are turned on, and then the first current IC flows through the branch formed by the first switch tube M1 and the third switch tube M3, and the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 to charge the first capacitor C1;

[0037] When the charging time reaches TC, the second control voltage VD is switched to a low level state, and when the second control voltage VD is completely pulled down, the computing unit at this level begins to enter the power supply stage.

[0038] In a possible implementation, when the computing unit at this level is in the power supply stage, the second control voltage VD is in a low level state, the first capacitor C1 supplies power to the outside, and when the second control voltage VD is completely pulled down, the first control voltage VC is pulled up, and the third control voltage VG is synchronously pulled down, so that the first switch tube M1, the second switch tube M2 and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0A;

[0039] When the time for which the second control voltage VD remains in the low level state reaches TG, the computing unit at this stage begins to enter the discharge stage.

[0040] In a possible implementation, when the current-stage computing unit is in the power supply stage, the output voltage VG′ of the first capacitor C1 is:

[0041] ;

[0042] Wherein, ICC is a charging current related to the magnitude of the first current IC, TC is a charging time of the charging current ICC for the first capacitor C1, and C1 is a capacitance value of the first capacitor C1;

[0043] The output voltage VG′ is regulated by the first current IC.

[0044] In a possible implementation, when the computing unit at this level is in the discharge stage, the second control voltage VD is first switched to a high level state to turn on the fifth switch tube M5, the first control voltage VC is in a high level state to turn on the fourth switch tube M4, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4;

[0045] When the discharge time reaches TF, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit enters the next charging stage.

[0046] In a possible implementation, the charging time TC is set to 100 ns, and the discharging time TF is set to 10 ns.

[0047] In another aspect of the present invention, a control method for a multi-level computing unit of an analog computer chip is provided, which is applied to the multi-level computing unit as described above, wherein the multi-level computing unit includes a computing unit of the same level and a computing unit of a lower level, and each computing unit in the same level shares a current source unit; the method comprises:

[0048] The first current source B1 is driven to generate a current source current, so as to control the on / off state of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8; the twenty-first current source B21 is driven to generate a current source current, so as to control the on / off state of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28;

[0049] A control voltage VC1 is input to the control ends of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4; a control voltage VC2 is input to the control ends of the twenty-third switch tube M23 and the twenty-fourth switch tube M24 to control the on / off state of the twenty-third switch tube M23 and the twenty-fourth switch tube M24;

[0050] A control voltage VD1 is input to the control end of the fifth switch tube M5, and an inverted control voltage VD1-1 having a level opposite to that of the control voltage VD1 is input to the control end of the sixth switch tube M6, so as to control the on / off states of the fifth switch tube M5 and the sixth switch tube M6; a control voltage VD2 is input to the control end of the twenty-fifth switch tube M25, and an inverted control voltage VD2-1 having a level opposite to that of the control voltage VD2 is input to the control end of the twenty-sixth switch tube M26, so as to control the on / off states of the twenty-fifth switch tube M25 and the twenty-sixth switch tube M26;

[0051] A control voltage VG1 is input to the current level calculation unit to control the magnitude of the current IC1, and the output voltage VG1' of the current level calculation unit is the control voltage of the next level calculation unit to control the magnitude of the current IC2;

[0052] Controlling the working state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25;

[0053] Among them, the working states of the multi-level computing units include a preparation stage, a charging stage of the computing unit at this level, a power supply stage of the computing unit at this level and a charging stage of the lower-level computing unit, a discharge stage of the computing unit at this level and a power supply stage of the lower-level computing unit, and a discharge stage of the lower-level computing unit.

[0054] In a possible implementation, when the multi-stage computing unit is in the preparation stage, the first current source B1 and the twenty-first current source B21 are driven to always generate current source current, the eighth switch tube M8 generates a pull-down current so that the first switch tube M1 and the second switch tube M2 are always in a conducting state, and the twenty-eighth switch tube M28 generates a pull-down current so that the twenty-first switch tube M21 and the twenty-second switch tube M22 are always in a conducting state;

[0055] The input control voltages VC1 and VC2 are in a high-level state, the control voltages VD1 and VD2 are in a high-level state, the inverted control voltages VD1-1 and VD2-1 are in a low-level state, and the control voltage VG1 is in a low-level state, so that the fourth switch tube M4, the fifth switch tube M5, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25 are all turned on, the third switch tube M3, the sixth switch tube M6, the twenty-third switch tube M23, and the twenty-sixth switch tube M26 are all turned off, the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24;

[0056] After the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are discharged to 0V, the control voltage VD1 and the control voltage VD2 are switched to a low level state, and the inverted control voltage VD1-1 and the inverted control voltage VD2-1 are synchronously switched to a high level state, so that the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, and the sixth switch tube M6 and the twenty-sixth switch tube M26 are turned on, and the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are maintained at 0V until the current-stage computing unit begins to enter the charging stage.

[0057] In a possible implementation, when the computing unit at this stage is in the charging stage, the control voltage VC1 of the computing unit at this stage is switched to a low level state, the control voltage VG1 of the storage unit at this stage is synchronously pulled high, and when the control voltage VC1 is completely pulled low, the control voltage VD1 is pulled high, so that the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, and the charging current ICC1 related to the current IC1 immediately flows through the second switch tube M2 to charge the first capacitor C1;

[0058] When the charging time reaches TC, the control voltage VD1 is switched to a low level state, and the control voltage VC2 of the lower-level computing unit is synchronously switched to a low level state. When the control voltage VD1 and the control voltage VC2 are completely pulled low, the computing unit at this level begins to enter the power supply stage, and the lower-level computing unit enters the charging stage.

[0059] In a possible implementation, when the computing unit at the current level is in the power supply stage and the computing unit at the lower level is in the charging stage, the control voltage VC1 is pulled high and the control voltage VG1 is pulled low synchronously, so that the third switch tube M3 is turned off, the fourth switch tube M4 is turned on, the control voltage VD1 and the control voltage VC2 are in a low level state, the fifth switch tube M5 and the twenty-fourth switch tube M24 are turned off, the twenty-third switch tube M23 is turned on, and the output voltage VG1' of the computing unit at the current level supplies power to the lower level storage unit, and generates a current IC2 in the twenty-third switch tube M23;

[0060] When the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VD2 is pulled high to turn on the twenty-fifth switch tube M25, and the charging current ICC2 related to the current IC2 flows through the twenty-second switch tube M22 immediately to charge the twenty-first capacitor C21;

[0061] When the charging time reaches TC, the control voltage VD2 is switched to a low level state, and when the control voltage VD2 is completely pulled down, the control voltage VD1 remains in a low level state for TG, and the current level computing unit begins to enter the discharge stage, while the lower level computing unit enters the power supply stage.

[0062] In a possible implementation, when the computing unit at this stage is in the power supply stage, the output voltage VG1' of the computing unit at this stage is:

[0063] ;

[0064] Wherein, ICC1 is a charging current related to the current IC1, TC is a charging time of the first capacitor C1 by the charging current ICC1, and C1 is a capacitance value of the first capacitor;

[0065] The output voltage VG1 ′ is regulated by the current IC1 .

[0066] In a possible implementation, when the computing unit at the current stage is in the power supply stage, the power supply time of the computing unit at the current stage is:

[0067] ;

[0068] Wherein, TG is the time that the control voltage VD1 maintains a low level, T0 is the sum of the rising edge time and the falling edge time of the control voltage VD2, and TC is the charging time of the charging current ICC2 on the twenty-first capacitor C21.

[0069] In a possible implementation, when the current-level computing unit is in the discharging stage and the lower-level computing unit is in the power supply stage, the control voltage VD1 is switched to a high-level state, so that the fifth switch tube M5 is turned on, the control voltage VC1 is in a high-level state, the control voltage VG1 is in a low-level state, the fourth switch tube M4 is turned on, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4;

[0070] When the discharge time reaches TF, the control voltage VD1 is switched to a low level state, and the inverted control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current level calculation unit enters the next charging stage;

[0071] When the computing unit of the current level is in the discharge stage and the computing unit of the next level is in the power supply stage, the control voltage VC2 is pulled high, so that the twenty-third switch tube M23 is turned off, the twenty-fourth switch tube M24 is turned on, the control voltage VD2 is in a low level state, the twenty-fifth switch tube M25 is turned off, and the output voltage VG2' of the computing unit of the next level supplies power to the computing unit of the next level, and generates a current IC3 in the computing unit of the next level;

[0072] When the control voltage VD2 maintains the low level state for a period of time reaching TG, it is switched to the high level state, and the lower-level computing unit begins to enter the discharge stage.

[0073] In a possible implementation, when the lower-level computing unit is in the power supply stage, the output voltage VG2′ of the lower-level computing unit is:

[0074] ;

[0075] Wherein, ICC2 is a charging current related to the current IC2, TC is a charging time of the charging current ICC2 on the twenty-first capacitor C21, and C21 is a capacitance value of the twenty-first capacitor;

[0076] The output voltage VG2 ′ is regulated by the current IC2 .

[0077] In a possible implementation, when the lower computing unit is in the discharge stage, the control voltage VD2 is first switched to a high level state, so that the twenty-fifth switch tube M25 is turned on, the control voltage VC2 is in a high level state, the twenty-fourth switch tube M24 is turned on, and the twenty-first capacitor C21 is discharged to 0V through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24;

[0078] When the discharge time reaches TF, the control voltage VD2 is switched to a low level state, and the inverting control voltage VD-2 is synchronously switched to a high level state, so that the twenty-fifth switch tube M25 is turned off, the twenty-sixth switch tube M26 is turned on, and the voltage across the twenty-first capacitor C21 is maintained at 0V until the lower-level computing unit enters the next charging stage.

[0079] In a possible implementation, the power supply time TG is set to 101 ns, the charging time TC is set to 100 ns, the discharging time TF is set to 10 ns, and T0 is set to 1 ns.

[0080] The effects provided in the content of the invention are only the effects of the embodiments, not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0081] The present application provides a computing unit of an analog computer chip and a control method thereof, wherein the computing unit includes a computing unit at this level and a storage unit at this level. The computing unit at this level includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1; the storage unit at this level is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs a first current IC to the storage unit at this level and generates a coupling voltage VZ at its drain end; the storage unit at this level is also connected to a third control voltage VG for adjusting the magnitude of the first current IC. The computing unit of the present application does not need to use a traditional adder structure, and can realize the accumulation operation of signals only through a small number of analog components, which significantly reduces the size of the artificial intelligence chip, improves the operation speed, and effectively reduces the power consumption, thereby improving the overall performance of the artificial intelligence chip and meeting the needs of high-efficiency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0083] Figure 1 A schematic diagram of the structure of a computing unit simulating a computer chip according to an embodiment of the present application;

[0084] Figure 2 for Figure 1 A schematic flow chart of a control method for a computing unit of a simulated computer chip;

[0085] Figure 3 for Figure 1 A schematic diagram of the control voltage waveform of the computing unit of the simulated computer chip;

[0086] Figure 4 A schematic diagram of the structure of a computing unit simulating a computer chip according to another embodiment of the present application;

[0087] Figure 5 This is an example of a structural block diagram of an analog computer chip according to an embodiment of the present application;

[0088] Figure 6 for Figure 5 A circuit schematic diagram of a storage unit in FIG.

[0089] Figure 7 for Figure 4 A circuit schematic of a computing unit in a simulated computer chip;

[0090] Figure 8 This is a schematic diagram of the structure of a multi-level computing unit of an analog computer chip according to an embodiment of the present application;

[0091] Fig. 9 for Figure 8 A schematic flow chart of a control method for a multi-level computing unit of a simulated computer chip;

[0092] Fig.10 for Figure 8 Schematic diagram of the control voltage waveform of the multi-level computing unit of the simulated computer chip. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0094] It should be noted that references to "one embodiment", "embodiment", "example embodiment", etc. in this specification refer to the embodiment being described which may include specific features, structures or characteristics, but not every embodiment must include these specific features, structures or characteristics. In addition, such expressions do not refer to the same embodiment. Furthermore, when describing specific features, structures or characteristics in conjunction with an embodiment, whether or not there is an explicit description, it is indicated that incorporating such features, structures or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0095] As described in the background technology, the existing artificial intelligence chips have many limitations in terms of size, speed, power consumption, etc. Based on this, the embodiment of the present application provides a computing unit of an analog computer chip and a control method thereof, aiming to realize signal calculation and transmission by using a small number of analog components instead of traditional digital devices, thereby effectively reducing the size of the artificial intelligence chip, increasing the calculation speed, significantly reducing power consumption, and improving the overall performance of the artificial intelligence chip.

[0096] refer to Figure 1 , Figure 1 A schematic diagram of the structure of a computing unit of an analog computer chip of an embodiment of the present application is shown. The computing unit includes a current-level computing unit, and the current-level computing unit includes a current-level operation unit and a current-level storage unit. The current-level operation unit includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1.

[0097] In the operation unit at this level, the first switch tube M1 and the second switch tube M2 form a current mirror structure, the control end of the first switch tube M1 is connected to the control end of the second switch tube M2 and connected to the drain of the first switch tube M1, the source of the first switch tube M1 is connected to the source of the second switch tube M2 and connected to the voltage VIN, and the drain of the first switch tube M1 is connected to the source of the third switch tube M3, the drain of the second switch tube M2 is respectively connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5; the drain of the third switch tube M3 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5; The control end is connected to the control end of the fourth switch tube M4 and connected to the first control voltage VC; the source of the fifth switch tube M5 is connected to the source and drain of the sixth switch tube M6, and the control end of the fifth switch tube M5 is connected to the second control voltage VD, and the control end of the sixth switch tube M6 is connected to the second inverting control voltage VD-1; the low voltage end of the first capacitor C1 is connected to the source of the fourth switch tube M4 and grounded, and the high voltage end of the first capacitor C1 is connected to the source of the fifth switch tube M5 and generates the output voltage VG' of the current level operation unit. The storage unit of this level is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs the first current IC to the storage unit of this level and generates a coupling voltage VZ at its drain end; the storage unit of this level is also connected to the third control voltage VG, which is used to adjust the size of the first current IC.

[0098] In some embodiments, the first switch tube M1 , the second switch tube M2 , and the third switch tube M3 are all PMOS tubes, and the fourth switch tube M4 , the fifth switch tube M5 , and the sixth switch tube M6 are all NMOS tubes.

[0099] based on Figure 1 The circuit structure of the computing unit of the simulated computer chip in the embodiment, the embodiment of the present application also provides a control method of the computing unit of the simulated computer chip, which is applied to the computing unit of the above embodiment. Figure 2 , Figure 3 , Figure 2 for Figure 1 A flow chart of a control method for a computing unit simulating a computer chip, Figure 3 for Figure 1 A schematic diagram of a control voltage waveform of a computing unit of a simulated computer chip is provided. The method comprises the following steps:

[0100] S210, inputting a first control voltage VC to the control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4;

[0101] S220, inputting a second control voltage VD to the control end of the fifth switch tube M5, and inputting a second inverted control voltage VD-1 having a level opposite to the second control voltage VD to the control end of the sixth switch tube M6, so as to control the on and off states of the fifth switch tube M5 and the sixth switch tube M6;

[0102] S230, inputting a third control voltage VG to the storage unit at this stage to adjust the magnitude of the first current IC;

[0103] S240, controlling the working state of the computing unit at this stage according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5;

[0104] Among them, the working states of the computing unit at this level include a preparation stage, a charging stage, a power supply stage and a discharge stage.

[0105] In some embodiments, when the current level calculation unit is in the preparatory stage, the first control voltage VC in the high level state, the second control voltage VD in the high level state, the second inverted control voltage VD-1 in the low level state, and the third control voltage VG in the low level state are first input. At this time, the fourth switch tube M4 and the fifth switch tube M5 are in the on state, and the first switch tube M1, the second switch tube M2, the third switch tube M3 and the sixth switch tube M6 are in the off state. Therefore, the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4. Afterwards, the second control voltage VD is switched to the low level state, so that the fifth switch tube M5 is turned off. Since a small amount of charge will be released into the first capacitor C1 when the fifth switch tube M5 is turned off, the voltage value across the first capacitor C1 is greater than 0V. Therefore, when the second control voltage VD is switched to the low level state, the second inverted control voltage VD-1 needs to be synchronously switched to the high level state. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a 0V voltage state until the current level computing unit begins to enter the charging stage.

[0106] In some embodiments, when the computing unit of this stage is in the charging stage, after starting to work, the first control voltage VC of the computing unit of this stage is first switched to a low level state, the third control voltage VG of the storage unit of this stage is synchronously pulled up, and the computing unit of this stage starts to work. When the first control voltage VC is completely pulled down, the second control voltage VD starts to be pulled up to prevent the fourth switch tube M4 and the fifth switch tube M5 from being turned on at the same time, resulting in the inability to accurately control the charging time of the first capacitor C1. At this time, the fourth switch tube M4 is turned off, and the third switch tube M3 and the fifth switch tube M5 are turned on, so that the control terminal voltages of the first switch tube M1 and the second switch tube M2 are pulled down through the third switch tube M3, so that the first switch tube M1 and the second switch tube M2 are turned on. At this time, the first current IC flows through the branch formed by the first switch tube M1 and the third switch tube M3. Since the first switch tube M1 and the second switch tube M2 form a current mirror structure, a charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2. The charging current flows into the first capacitor C1 to charge the first capacitor C1.

[0107] At this time, it is known from the common knowledge in the field that the capacitor charge , where I is the charging current, that is, ICC, T is the charging time, C is the capacitance of the first capacitor, that is, C1, and V is the capacitor voltage after charging, that is, VG'. It can be obtained that the output voltage At this time, since the capacitance value of the first capacitor C1 is a fixed value, the charging current ICC can control the output voltage VG' by fixing the charging time T. That is, at this time, the time for the second control voltage VD to maintain a high level is set to TC, TC is preferably 100ns, and the charging time of the charging current ICC on the first capacitor C1 is TC. Therefore, it can be obtained that Therefore, the output voltage VG' changes with the charging current ICC, that is, with the change of the first current IC. When the second control voltage VD maintains a high level for a time period of TC, the second control voltage VD starts to switch to a low level, and when the second control voltage VD is completely pulled down, the charging stage ends, and the current level computing unit starts to enter the power supply stage.

[0108] In some embodiments, when the computing unit at this level is in the power supply stage, the second control voltage VD is in a low level state, the first capacitor C1 supplies power to the outside, and the power supply voltage is equal to the output voltage VG'. When the second control voltage VD is completely pulled down, the first control voltage VC is pulled up, and the third control voltage VG is pulled down synchronously to prevent the fourth switch tube M4 and the fifth switch tube M5 from being turned on at the same time, causing the first capacitor C1 to be discharged briefly, and at the same time, the third switch tube M3 and the fifth switch tube M5 can be prevented from being turned on at the same time, causing the first capacitor C1 to be charged briefly. At this time, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0A. When the time for the second control voltage VD to maintain a low level state reaches TG, that is, the time for the computing unit at this level to be in the power supply stage is TG, and then it starts to enter the discharge stage.

[0109] In some embodiments, when the current level computing unit is in the discharge stage, the second control voltage VD is first switched to a high level state to turn on the fifth switch tube M5. At this time, since the first control voltage VC is also in a high level state, the fourth switch tube M4 and the fifth switch tube M5 are both in a conduction state, and the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4. The discharge time is set to TF, and TF is preferably 10ns. At this time, the voltage across the first capacitor C1 is discharged to 0V. After the discharge time TF, the second control voltage VD is switched back to a low level state again, so that the fifth switch tube M5 is turned off. Since a small amount of charge is released into the first capacitor C1 when the fifth switch tube M5 is turned off, the voltage value across the first capacitor C1 is greater than 0V. Therefore, when the second control voltage VD is switched to a low level state, it is necessary to synchronize the second inverting control voltage VD-1 to a high level state. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a 0V voltage state until the current level computing unit enters the next charging stage.

[0110] From the above analysis, it can be known that when the computing unit of this level is in the charging stage, the control terminal voltage of the first switch tube M1 and the second switch tube M2 needs to be pulled down by the third switch tube M3 before the first switch tube M1 and the second switch tube M2 are turned on. At this time, if the pull-down current of the third switch tube M3, that is, the first current IC, is small, it will cause the turn-on response speed of the first switch tube M1 and the second switch tube M2 to be slow, so that the time when the computing unit of this level is in the charging stage is less than the charging time TC, resulting in the output voltage VG' of the computing unit of this level being too small. Therefore, in order to improve the response speed of the computing unit of this level and the accuracy of the output voltage, a current source unit can be further added to the computing unit of this level, thereby obtaining a computing unit of an analog computer chip in another embodiment of the present application.

[0111] refer to Figure 4 , Figure 4 FIG. 2 shows a schematic diagram of a computing unit structure of an analog computer chip according to another embodiment of the present application. Figure 4 In the embodiment, the computing unit at this level includes Figure 1 In addition to the current-stage operation unit and the current-stage storage unit shown in the embodiment, a current source unit is also included, which is used to control the first switch tube M1 and the second switch tube M2 to always be in a conducting state. The current source unit includes a seventh switch tube M7, an eighth switch tube M8 and a first current source B1. Among them, the seventh switch tube M7 and the eighth switch tube M8 form a current mirror structure, the control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are connected and connected to the drain of the seventh switch tube M7, and the ratio of the current mirror is determined according to the current value required by the actual circuit; the current input end of the first current source B1 is connected to the source of the first switch tube M1 and the source of the second switch tube M2 and connected to the input voltage VIN; the current output end of the first current source B1 is connected to the drain of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the drain of the first switch tube M1; the source of the seventh switch tube M7 and the source of the eighth switch tube M8 are connected and grounded.

[0112] In some embodiments, the seventh switch tube M7 and the eighth switch tube M8 are NMOS tubes. The first current source B1 always generates a current source current, which pulls up the control terminal voltage of the seventh switch tube M7 and the eighth switch tube M8, so that the seventh switch tube M7 and the eighth switch tube M8 are turned on. Therefore, at this time, the first pull-down current is always generated in the eighth switch tube M8 to pull down the control terminal voltage of the first switch tube M1 and the second switch tube M2, so that the first switch tube M1 and the second switch tube M2 are always in a conducting state.

[0113] From the above analysis, it can be known that when the computing unit of this level is in the charging stage, that is, the first control voltage VC of the computing unit of this level is switched to a low level, the third control voltage VG of the storage unit of this level is synchronously pulled up, and when the computing unit of this level starts to work, the first switch tube M1 and the second switch tube M2 are already in the on state. Therefore, when the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 immediately, thereby ensuring that the time of the computing unit of this level in the charging stage is equal to TC, thereby improving the response speed of the computing unit of this level and the accuracy of the output voltage. At the same time, when the first capacitor C1 is in the discharging stage, the first control voltage VC is in a high level state, and at this time, the third switch tube M3 is turned off. Therefore, although the first switch tube M1 and the second switch tube M2 are in the on state, the first current IC will not be generated in the branch formed by the first switch tube M1 and the third switch tube M3, so that the second switch tube M2 will not generate the charging current ICC, ensuring that the first capacitor C1 is discharged smoothly, thereby improving the reliability of the calculation unit at this level.

[0114] It should be noted that multiple levels of computing units can be set in the analog computer chip. In this case, only one Figure 4 The current source unit shown in the figure can be connected to all computing units in the analog computer chip; or a current source unit can be set in each level of computing unit, in which case each current source unit is only connected to the computing unit at the same level.

[0115] refer to Figure 5 , Figure 5 An example of a block diagram of an analog computer chip according to an embodiment of the present application is shown. The analog computer chip includes an input terminal, n-level computing units, and an output terminal, where n is a positive integer. The input terminal includes one or more input interfaces (in1, in2, in3) for inputting external voltage signals. Each level of computing units includes one or more computing units, and the output terminal includes one or more output interfaces (out1, out2, out3) for outputting the n-th level voltage signal.

[0116] In actual use, each level of computing unit may include one or more computing units, and the number of computing units in each level of computing unit may be the same or different, that is, the number of computing units in each level of computing unit may be any number. The computing unit of this level is a computing unit, including the computing unit of this level and the storage unit of this level. The computing unit of this level is a computing unit, and the storage unit of this level is a collection of all storage units connected to the computing unit of this level, that is, the storage unit of this level may include one or more storage units. Figure 5As shown, in this embodiment, each level of computing unit is provided with three computing units, each computing unit includes an operation unit and three storage units, and the operation unit is connected to the three storage units. Figure 5 For example, when the computing unit at this level is computing unit 11, the storage units at this level are three storage units connected to computing unit 11, and these three storage units and computing unit 11 together constitute Figure 1 The computational unit shown in .

[0117] refer to Figure 6 , Figure 6 for Figure 5 A circuit schematic diagram of a storage unit in the embodiment. The storage unit includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11 and a twelfth switch tube M12. Among them, the source of the ninth switch tube M9 is connected to its drain and connected to the third control voltage VG, the source of the tenth switch tube M10 is connected to its drain and connected to the first voltage VE; the control end of the ninth switch tube M9, the control end of the tenth switch tube M10 and the control end of the eleventh switch tube M11 are connected, and the control end of the twelfth switch tube M12 is connected to the fourth control voltage VH; the drain of the eleventh switch tube M11 is connected to the coupling voltage VZ, the source of the eleventh switch tube M11 is connected to the drain of the twelfth switch tube M12, and the first sub-current IC11 of the first current flows in the branch formed by the eleventh switch tube M11 and the twelfth switch tube M12, and the source of the twelfth switch tube M12 is connected to the second voltage VS.

[0118] In some embodiments, the ninth switch tube M9 and the tenth switch tube M10 are both PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are both NMOS tubes.

[0119] In some embodiments, when the storage unit is a first-level storage unit, the third control voltage VG is an external voltage input through the input interface, and when the storage unit is not a first-level storage unit, the third control voltage VG is the output voltage of the previous-level computing unit. The coupling voltage VZ is the voltage generated by the mutual coupling between the current-level computing unit and the current-level storage unit. Preferably, the first voltage VE is 0V; the second voltage VS is a fixed value, and is preferably GND.

[0120] based on Figure 6 The circuit structure of the storage unit in FIG. 1 and its working principle are as follows:

[0121] When the storage unit is in the adjustment mode, the external adjustment circuit is connected to the storage unit, the fourth control voltage VH is at a low level, and the twelfth switch tube M12 is in an off state. At this time, the external adjustment circuit changes the floating gate charge value of the eleventh switch tube M11 by controlling the magnitude of the third control voltage VG and the working time of the adjustment circuit, thereby adjusting the turn-on threshold voltage of the eleventh switch tube M11.

[0122] When the storage unit is in the transfer mode, the external adjustment circuit is not connected to the storage unit, the fourth control voltage VH is at a high level, and the twelfth switch tube M12 is always in a conducting state. At this time, when the third control voltage VG is switched to a high level, the gate voltage of the eleventh switch tube M11 is pulled up, the eleventh switch tube M11 is turned on, and the first sub-current IC11 of the first current flows through the eleventh switch tube M11. At the same time, when designing the circuit, the size of the equivalent capacitance CC1 of the ninth switch tube M9 and the equivalent capacitance CC2 of the tenth switch tube M10 is known, so at this time, it can be obtained that the gate voltage of the eleventh switch tube M11 is It is also known from common technical knowledge in the art that the first sub-current of the first current flowing through the eleventh switch tube M11 is ,in, is the electron mobility, is the oxide layer capacitance, is the ratio of the width to the length of the MOS tube, is the voltage difference between the gate and the source, is the turn-on threshold voltage. , and are all fixed values, and the gate-source voltage difference of the eleventh switch tube M11 is ,in, and the second voltage VS are both fixed values. Therefore, for a specific input third control voltage VG, the turn-on threshold voltage can be adjusted To achieve the regulation of the first sub-current IC11 of the first current.

[0123] From the above analysis, it can be seen that when the first sub-current IC11 of the first current is recorded as y and the third control voltage VG is recorded as x, it can be obtained that , this function can be regarded as the transfer function of the storage unit. At this time, when the turn-on threshold voltage is adjusted When the transfer function is adjusted, the first sub-current IC11 can be adjusted by adjusting the magnitude of the third control voltage VG in the transfer mode.

[0124] Combined with the above analysis, according to Figure 5 Example of a block diagram of a simulated computer chip and Figure 6The circuit structure of the storage unit in Figure 4 A specific circuit structure of the computing unit in Figure 7 As shown. Figure 7 It can be seen that the storage unit at this level includes three Figure 6 The storage unit shown. Figure 7 After the calculation unit shown starts working, the first sub-current IC11 of the corresponding first current is obtained according to the control voltage VG1 and the turn-on threshold voltage of the switch tube M111, that is, the first sub-current IC11 of the first current is obtained according to the first transfer function. Similarly, the second sub-current IC12 of the first current can be obtained according to the second transfer function, and the third sub-current IC13 of the first current can be obtained according to the third transfer function. At this time, after adding the first sub-current IC11, the second sub-current IC12 and the third sub-current IC13, the first current IC flowing out of the third switch tube M3 can be obtained. Therefore, it can be seen that the calculation unit in the present application can realize the accumulation operation of the signal without using an additional adder.

[0125] From the above analysis, it can be seen that the output voltage VG' of the calculation unit can be obtained according to the first current IC, and the output voltage VG' is input to the storage unit of the next level. The storage unit of the next level obtains the corresponding sub-current according to its own transfer function, and so on, and finally obtains the voltage output by the n-th level calculation unit through the output interface.

[0126] In addition, according to Figure 5 Example of a block diagram of a simulated computer chip and Figure 1 The circuit structure of the computing unit in the example is as follows: Figure 8 As shown. The multi-level computing unit includes a computing unit at this level and a computing unit at a lower level. The output voltage VG1' of the computing unit at this level is the control voltage of the computing unit at the lower level. At the same time, the current source unit is arranged in a manner of "arranging a current source unit in each computing unit at each level, and each current source unit is only connected to multiple computing units at the same level".

[0127] based on Figure 8 The circuit structure of the multi-level computing unit of the analog computer chip in the embodiment, the embodiment of the present application also provides a control method for the multi-level computing unit of the analog computer chip, which is applied to Figure 8 In the multi-level computing unit of the embodiment. Fig. 9 , Fig.10 , Fig. 9 for Figure 8 A flow chart of a control method for a multi-level computing unit simulating a computer chip, Fig.10 for Figure 8A schematic diagram of a control voltage waveform of a multi-level computing unit in a simulated computer chip. The method comprises the following steps:

[0128] S910, driving the first current source B1 to generate a current source current, so as to control the on / off states of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8, and driving the twenty-first current source B21 to generate a current source current, so as to control the on / off states of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28;

[0129] S920, inputting a control voltage VC1 to the control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off states of the third switch tube M3 and the fourth switch tube M4, and inputting a control voltage VC2 to the control terminals of the twenty-third switch tube M23 and the twenty-fourth switch tube M24 to control the on / off states of the twenty-third switch tube M23 and the twenty-fourth switch tube M24;

[0130] S930, input the control voltage VD1 to the control end of the fifth switch tube M5, and input the inverted control voltage VD1-1 with a level opposite to the control voltage VD1 to the control end of the sixth switch tube M6, so as to control the on / off states of the fifth switch tube M5 and the sixth switch tube M6, input the control voltage VD2 to the control end of the twenty-fifth switch tube M25, and input the inverted control voltage VD2-1 with a level opposite to the control voltage VD2 to the control end of the twenty-sixth switch tube M26, so as to control the on / off states of the twenty-fifth switch tube M25 and the twenty-sixth switch tube M26;

[0131] S940, inputting a control voltage VG1 to the computing unit of this stage to control the magnitude of the current IC1, and the output voltage VG1' of the computing unit of this stage is the control voltage of the computing unit of the next stage to control the magnitude of the current IC2;

[0132] S950, controlling the working state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25;

[0133] Among them, the working states of the multi-level computing units include the preparation stage, the charging stage of the computing unit at this level, the power supply stage of the computing unit at this level and the charging stage of the lower-level computing unit, the discharge stage of the computing unit at this level and the power supply stage of the lower-level computing unit, and the discharge stage of the lower-level computing unit.

[0134] In some embodiments, when the multi-level computing unit is in the preparatory stage, the first current source B1 and the twenty-first current source B21 are driven to generate current source current all the time. At this time, the current source current pulls up the control terminal voltage of the seventh switch tube M7 and the eighth switch tube M8 and the control terminal voltage of the twenty-seventh switch tube M27 and the twenty-eighth switch tube M28, so that the seventh switch tube M7 and the eighth switch tube M8 and the twenty-seventh switch tube M27 and the twenty-eighth switch tube M28 are turned on. At this time, the eighth switch tube M8 always generates a pull-down current to pull down the control terminal voltage of the first switch tube M1 and the second switch tube M2, so that the first switch tube M1 and the second switch tube M2 are always in the on state. The twenty-eighth switch tube M28 always generates a pull-down current to pull down the control terminal voltage of the twenty-first switch tube M21 and the second switch tube M22, so that the twenty-first switch tube M21 and the second switch tube M22 are always in the on state.

[0135] At the same time, the input control voltage VC1 and the control voltage VC2 are in a high level state, the control voltage VD1 and the control voltage VD2 are in a high level state, the inverted control voltage VD1-1 and the inverted control voltage VD2-1 are in a low level state, and the control voltage VG1 is in a low level state. At this time, the fourth switch tube M4, the fifth switch tube M5, the twenty-fourth switch tube M24 and the twenty-fifth switch tube M25 are all in the on state, and the third switch tube M3, the sixth switch tube M6, the twenty-third switch tube M23 and the twenty-sixth switch tube M26 are all in the off state.

[0136] At this time, the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4, and the twenty-first capacitor C21 is discharged to 0V through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24. Afterwards, the control voltage VD1 and the control voltage VD2 are switched to a low level state, so that the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off. Since a small amount of charge will be released to the first capacitor C1 and the twenty-first capacitor C21 respectively when the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, so that the voltage value across the first capacitor C1 and the twenty-first capacitor C21 is greater than 0V, when the control voltage VD1 and the control voltage VD2 are switched to a low level state, it is necessary to synchronize the inverted control voltage VD1-1 and the inverted control voltage VD2-1 to a high level state. At this time, the sixth switch tube M6 and the twenty-sixth switch tube M26 are turned on, thereby respectively absorbing a small amount of charge released when the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, ensuring that the first capacitor C1 and the twenty-first capacitor C21 maintain a 0V voltage state until the current level computing unit begins to enter the charging stage.

[0137] In some embodiments, when the computing unit of this stage is in the charging stage, the control voltage VC1 of the computing unit of this stage is first switched to a low level state, the control voltage VG1 of the storage unit of this stage is synchronously pulled up, and the computing unit of this stage starts to work. When the control voltage VC1 is completely pulled down, the control voltage VD1 starts to be pulled up to prevent the fourth switch tube M4 and the fifth switch tube M5 from being turned on at the same time, resulting in the inability to accurately control the charging time of the first capacitor C1. At this time, the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, and since the first switch tube M1 and the second switch tube M2 are already in the on state, when the fourth switch tube M4 is turned off, the third switch tube M3 is turned on, and the fifth switch tube M5 is turned on, the charging current ICC1 related to the magnitude of the current IC1 immediately flows through the second switch tube M2, thereby ensuring that the time when the computing unit of this stage is in the charging stage is equal to TC, and TC is preferably 100ns. The charging current ICC1 flows into the first capacitor C1 to charge the first capacitor C1.

[0138] At this time, it is known from common knowledge in the art that the output voltage of the first capacitor C1 is . Since the capacitance value and charging time TC of the first capacitor C1 are both fixed values, the output voltage VG1' changes with the charging current ICC1, that is, with the change of the current IC1. When the control voltage VD1 maintains a high level for a time period of TC, the control voltage VD1 starts to switch to a low level, and at the same time, the control voltage VC2 of the lower-level computing unit also starts to switch to a low level synchronously, and when the control voltage VD1 and the control voltage VC2 of the lower-level computing unit are completely pulled down, the charging stage of the computing unit at this level ends, and the computing unit at this level starts to enter the power supply stage, and the lower-level computing unit enters the charging stage at the same time.

[0139] In some embodiments, when the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VD1 and the control voltage VC2 are at a low level, so that the fifth switch tube M5 and the twenty-fourth switch tube M24 are turned off, and the twenty-third switch tube M23 is turned on. At this time, the control voltage VC1 starts to increase, the control voltage VG1 starts to decrease, and the control voltage VD2 of the lower computing unit starts to increase. After the control voltage VC1 is completely increased, the third switch tube M3 is turned off and the fourth switch tube M4 is turned on to prevent the fourth switch tube M4 and the fifth switch tube M5 from being turned on at the same time, causing the first capacitor C1 to be discharged briefly, and at the same time, the third switch tube M3 and the fifth switch tube M5 are also prevented from being turned on at the same time, causing the first capacitor C1 to be charged briefly. At this time, the output voltage VG1' of the current computing unit supplies power to the lower storage unit, and generates a current IC2 in the twenty-third switch tube M23.

[0140] At the same time, when the control voltage VC1 is fully pulled up and the control voltage VG1 is fully pulled down, the control voltage VD2 of the lower-level operation unit is fully pulled up, and Fig.10 It can be seen that the control voltage VD2 starts to increase only when the control voltage VC2 is completely pulled down, so as to prevent the twenty-fourth switch tube M24 and the twenty-fifth switch tube M25 from being turned on at the same time, thereby making it impossible to accurately control the charging time of the twenty-first capacitor C21. At this time, the twenty-fourth switch tube M24 is turned off, and the twenty-third switch tube M23 and the twenty-fifth switch tube M25 are turned on. Since the twenty-first switch tube M21 and the twenty-second switch tube M22 are already in the on state, at this time, the charging current ICC2 related to the magnitude of the current IC2 immediately flows through the twenty-second switch tube M22, thereby ensuring that the time when the lower-level computing unit is in the charging stage is equal to TC, and TC is preferably 100ns. The charging current ICC2 flows into the twenty-first capacitor C21 to charge the twenty-first capacitor C21 of the lower-level computing unit.

[0141] At this time, it is known from common technical knowledge in this field that the output voltage of the twenty-first capacitor C21 is . Since the capacitance value and charging time TC of the twenty-first capacitor C21 are fixed values, the output voltage VG2' changes with the charging current ICC2, that is, with the change of the current IC2. When the control voltage VD2 maintains a high level for a time period of TC, the control voltage VD2 starts to switch to a low level, and when the control voltage VD2 is completely pulled down, the charging stage of the lower-level computing unit ends. At this time, the twenty-first capacitor C21 supplies power to the next-level computing unit (not shown in the figure), and the power supply voltage is equal to the output voltage VG2'.

[0142] When the control voltage VD2 is completely pulled down, the control voltage VD1 and the control voltage VC2 start to switch from low level to high level, the current level calculation unit starts to enter the discharge stage, and the lower level calculation unit starts to enter the power supply stage. Fig.10 It can be seen that the time that the control voltage VD1 maintains a low level is TG, that is, the time that the computing unit at this level is in the power supply stage is TG, and since the sum of the rising edge time and the falling edge time of the control voltage VD2 is T0, it can be obtained that the power supply time TG=TC+T0. Preferably, T0 is 1ns, TC is 100ns, that is, TG is 101ns.

[0143] In some embodiments, when the current level computing unit is in the discharge stage and the lower level computing unit is in the power supply stage, when the control voltage VD1 maintains a low level time of TG, it is switched back to a high level state again, so that the fifth switch tube M5 is turned on. At this time, since the control voltage VC1 is also in a high level state, the fourth switch tube M4 and the fifth switch tube M5 are both in a conducting state, and the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4. The discharge time is set to TF, and TF is preferably 10ns. At this time, the voltage across the first capacitor C1 is discharged to 0V. After the time TF, the control voltage VD1 is switched back to a low level state again, so that the fifth switch tube M5 is turned off. Since a small amount of charge is released into the first capacitor C1 when the fifth switch tube M5 is turned off, the voltage value across the first capacitor C1 is greater than 0V, so when the control voltage VD1 is switched to a low level state, the inverted control voltage VD1-1 is synchronously switched to a high level state. At this time, the sixth switch tube M6 is turned on, thereby absorbing a small amount of charge released when the fifth switch tube M5 is turned off, ensuring that the first capacitor C1 maintains a 0V voltage state until the current level computing unit enters the next charging stage.

[0144] At the same time, when the current level calculation unit is in the discharge stage, the control voltage VC1 is in a high level state, and at this time, the third switch tube M3 is turned off. Therefore, although the first switch tube M1 and the second switch tube M2 are in the on state, the current IC1 will not be generated in the branch formed by the first switch tube M1 and the third switch tube M3, so that the second switch tube M2 will not generate a charging current ICC1, ensuring that the first capacitor C1 is discharged smoothly.

[0145] From the above analysis, it can be known that when the control voltage VD2 is completely pulled down, the charging stage of the lower-level computing unit ends. At this time, the twenty-fifth switch tube M25 is turned off, and the twenty-first capacitor C21 supplies power to the next-level computing unit (not shown in the figure), and the power supply voltage is equal to the output voltage VG2', and a current IC3 (not shown in the figure) is generated in the next-level computing unit. At the same time, the control voltage VC2 starts to increase, and when the control voltage VC2 is completely pulled up, the twenty-third switch tube M23 is turned off, and the twenty-fourth switch tube M24 is turned on to prevent the twenty-fourth switch tube M24 and the twenty-fifth switch tube M25 from being turned on at the same time, thereby causing the twenty-first capacitor C21 to be discharged briefly, and at the same time, the twenty-third switch tube M23 and the twenty-fifth switch tube M25 are also prevented from being turned on at the same time, thereby causing the twenty-first capacitor C21 to be charged briefly. When the control voltage VD2 maintains a low level state for a time of TG, that is, the time the lower-level computing unit is in the power supply stage is TG, and then it begins to enter the discharge stage.

[0146] In some embodiments, when the lower computing unit is in the discharge stage, the control voltage VD2 is first switched to a high level state to turn on the twenty-fifth switch tube M25. At this time, since the control voltage VC2 is also in a high level state, the twenty-fourth switch tube M24 and the twenty-fifth switch tube M25 are both in a conduction state, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24. The discharge time is set to TF, and TF is preferably 10ns. At this time, the voltage across the twenty-first capacitor C21 is discharged to 0V. After the discharge time TF, the control voltage VD2 is switched back to a low level state again to turn off the twenty-fifth switch tube M25. Since a small amount of charge will be released into the twenty-first capacitor C21 when the twenty-fifth switch tube M25 is turned off, so that the voltage value across the twenty-first capacitor C21 is greater than 0V, when the control voltage VD2 is switched to a low level state, it is necessary to make the inverting control voltage VD2-1 synchronously switch to a high level state. At this time, the twenty-sixth switch tube M26 is turned on, thereby absorbing the small amount of charge released when the twenty-fifth switch tube M25 is turned off, ensuring that the twenty-first capacitor C21 maintains a 0V voltage state until the lower-level computing unit enters the next charging stage.

[0147] Meanwhile, when the lower computing unit is in the discharge stage, the control voltage VC2 is in a high level state, and at this time, the twenty-third switch tube M23 is turned off. Therefore, although the twenty-first switch tube M21 and the twenty-second switch tube M22 are in the on state, the current IC2 will not be generated in the branch formed by the twenty-first switch tube M21 and the twenty-third switch tube M23, so that the twenty-second switch tube M22 will not generate a charging current ICC2, ensuring that the twenty-first capacitor C21 is discharged smoothly.

[0148] Similarly, when Figure 8 When the circuit structure of the multi-level computing unit shown is three-level, four-level or even N-level, the above-mentioned control method can be used to control it, which will not be repeated here.

[0149] In summary, the computing unit of the analog computer chip provided by the embodiment of the present application replaces the traditional adder structure with a small amount of analog components to realize the accumulation operation of signals, significantly reduce the volume of the artificial intelligence chip, speed up the operation speed, and effectively reduce the power consumption. In addition, the present application also sets a current source unit in the computing unit, and by optimizing the conduction sequence of the switch tube, ensures that the time when the computing unit is in the charging stage is equal to the charging time TC, thereby improving the response speed of the computing unit and the accuracy of the output voltage. At the same time, the computing unit of the present application is provided with an absorption switch tube, which can absorb the excess charge released when the switch tube is turned off, ensure that the capacitor is maintained in the 0V state, and improve the accuracy of the computing unit. In addition, the present application also provides a control method for the computing unit, which ensures the safety and reliability of the capacitor discharge and charging by setting a reasonable switch logic sequence. Further, the present application also obtains a high-precision and high-reliability output voltage through the coordinated control of multi-level computing units, providing a stable performance guarantee for the analog computer chip.

[0150] It should be noted that the computing unit structure of the analog computer chip provided in this embodiment is only a preferred circuit structure for achieving the purpose of the present invention. In other embodiments, each circuit module or device may also use other circuit structures that can achieve the same function, and the present application is not limited thereto.

[0151] The above description is only a preferred embodiment of the present invention and does not limit the present invention in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes and apply it to other fields. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A computing unit simulating a computer chip, characterized in that: The present-stage computing unit includes a present-stage computing unit and a present-stage storage unit; wherein the present-stage computing unit includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a first capacitor C1; In the operation unit of the present stage, the first switch tube M1 and the second switch tube M2 form a current mirror structure, the control end of the first switch tube M1 is connected to the control end of the second switch tube M2 and connected to the drain of the first switch tube M1, and the drain of the first switch tube M1 is connected to the source of the third switch tube M3, and the drain of the second switch tube M2 is connected to the drain of the fourth switch tube M4 and the drain of the fifth switch tube M5 respectively; the control end of the third switch tube M3 is connected to the control end of the fourth switch tube M4 and connected to the first control voltage VC; the source of the fifth switch tube M5 is connected to the source and drain of the sixth switch tube M6, and the control end of the fifth switch tube M5 is connected to the second control voltage VD, and the control end of the sixth switch tube M6 is connected to the second inverting control voltage VD-1; the low voltage end of the first capacitor C1 is connected to the source of the fourth switch tube M4 and grounded, and the high voltage end of the first capacitor C1 is connected to the source of the fifth switch tube M5 and generates the output voltage VG' of the operation unit of the present stage; The storage unit at this stage is connected to the drain of the third switch tube M3, and the drain of the third switch tube M3 outputs the first current IC to the storage unit at this stage and generates a coupling voltage VZ at its drain end; the storage unit at this stage is also connected to a third control voltage VG for adjusting the size of the first current IC.

2. The calculation unit according to claim 1, characterized in that The first switch tube M1 , the second switch tube M2 , and the third switch tube M3 are all PMOS tubes, and the fourth switch tube M4 , the fifth switch tube M5 , and the sixth switch tube M6 are all NMOS tubes.

3. The calculation unit according to claim 1, characterized in that It also includes a current source unit for controlling the first switch tube M1 and the second switch tube M2 to always be in a conducting state; The current source unit includes a seventh switch tube M7, an eighth switch tube M8 and a first current source B1; the seventh switch tube M7 and the eighth switch tube M8 form a current mirror structure, the control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are connected and connected to the drain of the seventh switch tube M7, the current input end of the first current source B1 is connected to the source of the first switch tube M1 and the source of the second switch tube M2 and is connected to the input voltage VIN; the current output end of the first current source B1 is connected to the drain of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the drain of the first switch tube M1; the source of the seventh switch tube M7 and the source of the eighth switch tube M8 are connected and grounded.

4. The calculation unit according to claim 3, characterized in that The seventh switch tube M7 and the eighth switch tube M8 are both NMOS tubes.

5. The calculation unit according to claim 4, characterized in that The first current source B1 always generates a current source current, which is used to pull up the control terminal voltages of the seventh switch tube M7 and the eighth switch tube M8, so that the seventh switch tube M7 and the eighth switch tube M8 are turned on, so as to generate a pull-down current in the eighth switch tube M8 to pull down the control terminal voltages of the first switch tube M1 and the second switch tube M2, so that the first switch tube M1 and the second switch tube M2 are always in a turned-on state; When the calculation unit at this level is in the charging stage, at the moment when the fourth switch tube M4 is turned off and the third switch tube M3 and the fifth switch tube M5 are turned on, the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 immediately to charge the first capacitor C1; when the calculation unit at this level is in the discharging stage, the third switch tube M3 is turned off, the first current IC is not generated in the first switch tube M1, and the charging current ICC is not generated in the second switch tube M2, so that the first capacitor C1 is discharged smoothly.

6. The computing unit according to any one of claims 3 to 5, characterized in that: The computing unit at this level is one computing unit, and the storage unit at this level is a collection of all storage units connected to the computing unit at this level, including one or more storage units.

7. The calculation unit according to claim 6, characterized in that One of the storage units includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11 and a twelfth switch tube M12; In the storage unit, the source of the ninth switch tube M9 is connected to its drain and connected to the third control voltage VG, the source of the tenth switch tube M10 is connected to its drain and connected to the first voltage VE; the control end of the ninth switch tube M9 and the control end of the tenth switch tube M10 are connected to the control end of the eleventh switch tube M11, and the control end of the twelfth switch tube M12 is connected to the fourth control voltage VH; the drain of the eleventh switch tube M11 is connected to the coupling voltage VZ, the source of the eleventh switch tube M11 is connected to the drain of the twelfth switch tube M12, and the first sub-current IC11 of the first current IC flows through the eleventh switch tube M11, and the source of the twelfth switch tube M12 is connected to the second voltage VS.

8. The calculation unit according to claim 7, characterized in that The ninth switch tube M9 and the tenth switch tube M10 are both PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are both NMOS tubes.

9. The calculation unit according to claim 8, characterized in that When the storage unit is a first-level storage unit, the third control voltage VG is an input external voltage; when the storage unit is not a first-level storage unit, the third control voltage VG is an output voltage of a previous-level calculation unit; The first voltage VE is 0V; the coupling voltage VZ is a voltage generated by the mutual coupling between the operation unit at this stage and the storage unit at this stage; and the second voltage VS is a fixed value.

10. The calculation unit according to claim 9, characterized in that The transfer function of the storage unit is: ； In the formula, represents a first sub-current IC11 of the first current IC flowing through the eleventh switch tube M11, represents the third control voltage VG, , and are respectively the electron mobility, oxide layer capacitance and the ratio of the width to the length of the MOS tube of the eleventh switch tube M11, CC1 is the equivalent capacitance of the ninth switch tube M9, CC2 is the equivalent capacitance of the tenth switch tube M10, is the turn-on threshold voltage of the eleventh switch tube M11; The transfer function of the memory cell is determined by the turn-on threshold voltage Make adjustments; After the transfer function of the storage unit is adjusted, the magnitude of the first sub-current IC11 of the storage unit is determined by the magnitude of the third control voltage VG.

11. The computing unit according to any one of claims 7 to 10, characterized in that: The analog computer chip includes multiple levels of computing units, each level of computing units includes one or more computing units, and the number of computing units in each level of computing units is the same or different; The computing unit at this level is a computing unit, the computing unit at this level is a computing unit, and the storage unit at this level is a set of all storage units connected to the computing unit at this level, including one or more storage units; The current source unit is connected to the computing units in the same level or different levels, so that multiple computing units in the same level share one current source unit, or multiple computing units in different levels share one current source unit.

12. A control method for a computing unit simulating a computer chip, characterized in that: Applied to the computing unit as claimed in claim 1 or 2, the method comprises: Inputting a first control voltage VC to control terminals of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4; Input a second control voltage VD to the control end of the fifth switch tube M5, and input a second inverted control voltage VD-1 having a level opposite to the second control voltage VD to the control end of the sixth switch tube M6, so as to control the on and off states of the fifth switch tube M5 and the sixth switch tube M6; Inputting a third control voltage VG to the storage unit of this stage to adjust the magnitude of the first current IC; Controlling the working state of the computing unit at this level according to the on / off states of the third switch tube M3, the fourth switch tube M4 and the fifth switch tube M5; The working state of the computing unit at this level includes a preparation stage, a charging stage, a power supply stage and a discharging stage.

13. The control method according to claim 12, characterized in that: When the current level calculation unit is in the preparation stage, firstly, the first control voltage VC in the high level state, the second control voltage VD in the high level state, the second inverted control voltage VD-1 in the low level state, and the third control voltage VG in the low level state are input, so that the fourth switch tube M4 and the fifth switch tube M5 are turned on, the first switch tube M1, the second switch tube M2, the third switch tube M3, and the sixth switch tube M6 are all turned off, and the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4; After the voltage across the first capacitor C1 is discharged to 0V, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit begins to enter the charging stage.

14. The control method according to claim 13, characterized in that: When the computing unit at this level is in the charging stage, the first control voltage VC is first switched to a low level state, the third control voltage VG is synchronously pulled up, and when the first control voltage VC is completely pulled down, the second control voltage VD is pulled up, so that the fourth switch tube M4 is turned off, and the third switch tube M3 and the fifth switch tube M5 are turned on, so that the control terminal voltages of the first switch tube M1 and the second switch tube M2 are pulled down by the third switch tube M3, so that the first switch tube M1 and the second switch tube M2 are turned on, and then the first current IC flows through the branch formed by the first switch tube M1 and the third switch tube M3, and the charging current ICC related to the magnitude of the first current IC flows through the second switch tube M2 to charge the first capacitor C1; When the charging time reaches TC, the second control voltage VD is switched to a low level state, and when the second control voltage VD is completely pulled down, the computing unit at this level begins to enter the power supply stage.

15. The control method according to claim 14, characterized in that: When the computing unit at this level is in the power supply stage, the second control voltage VD is in a low level state, the first capacitor C1 supplies power to the outside, and when the second control voltage VD is completely pulled down, the first control voltage VC is pulled up, and the third control voltage VG is pulled down synchronously, so that the first switch tube M1, the second switch tube M2 and the third switch tube M3 are gradually turned off, the fourth switch tube M4 is gradually turned on, and the charging current ICC gradually becomes 0A; When the time for which the second control voltage VD remains in the low level state reaches TG, the computing unit at this stage begins to enter the discharge stage.

16. The control method according to claim 15, characterized in that: When the current-stage computing unit is in the power supply stage, the output voltage VG' of the first capacitor C1 is: ； Wherein, ICC is a charging current related to the magnitude of the first current IC, TC is a charging time of the charging current ICC for the first capacitor C1, and C1 is a capacitance value of the first capacitor C1; The output voltage VG′ is regulated by the first current IC.

17. The control method according to claim 15 or 16, characterized in that: When the current level calculation unit is in the discharge stage, the second control voltage VD is first switched to a high level state to turn on the fifth switch tube M5, and the first control voltage VC is in a high level state to turn on the fourth switch tube M4, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4; When the discharge time reaches TF, the second control voltage VD is switched to a low level state, and the second inverting control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current-stage computing unit enters the next charging stage.

18. The control method according to claim 17, characterized in that: The charging time TC is set to 100 ns, and the discharging time TF is set to 10 ns.

19. A control method for a multi-level computing unit simulating a computer chip, characterized in that: Applied to the multi-level computing unit as claimed in claim 11, the multi-level computing unit includes a computing unit at the same level and a computing unit at the next level, and each computing unit at the same level shares a current source unit; the method includes: The first current source B1 is driven to generate a current source current, so as to control the on / off state of the first switch tube M1 and the second switch tube M2 through the eighth switch tube M8; the twenty-first current source B21 is driven to generate a current source current, so as to control the on / off state of the twenty-first switch tube M21 and the twenty-second switch tube M22 through the twenty-eighth switch tube M28; A control voltage VC1 is input to the control ends of the third switch tube M3 and the fourth switch tube M4 to control the on / off state of the third switch tube M3 and the fourth switch tube M4; a control voltage VC2 is input to the control ends of the twenty-third switch tube M23 and the twenty-fourth switch tube M24 to control the on / off state of the twenty-third switch tube M23 and the twenty-fourth switch tube M24; A control voltage VD1 is input to the control end of the fifth switch tube M5, and an inverted control voltage VD1-1 having a level opposite to that of the control voltage VD1 is input to the control end of the sixth switch tube M6, so as to control the on / off states of the fifth switch tube M5 and the sixth switch tube M6; a control voltage VD2 is input to the control end of the twenty-fifth switch tube M25, and an inverted control voltage VD2-1 having a level opposite to that of the control voltage VD2 is input to the control end of the twenty-sixth switch tube M26, so as to control the on / off states of the twenty-fifth switch tube M25 and the twenty-sixth switch tube M26; A control voltage VG1 is input to the current level calculation unit to control the magnitude of the current IC1, and the output voltage VG1' of the current level calculation unit is the control voltage of the next level calculation unit to control the magnitude of the current IC2; Controlling the working state of the multi-stage computing unit according to the on / off states of the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, and the twenty-third switch tube M23, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25; Among them, the working states of the multi-level computing units include a preparation stage, a charging stage of the computing unit at this level, a power supply stage of the computing unit at this level and a charging stage of the lower-level computing unit, a discharge stage of the computing unit at this level and a power supply stage of the lower-level computing unit, and a discharge stage of the lower-level computing unit.

20. The control method according to claim 19, characterized in that: When the multi-stage computing unit is in the preparation stage, the first current source B1 and the twenty-first current source B21 are driven to always generate current source current, the eighth switch tube M8 generates a pull-down current so that the first switch tube M1 and the second switch tube M2 are always in a conducting state, and the twenty-eighth switch tube M28 generates a pull-down current so that the twenty-first switch tube M21 and the twenty-second switch tube M22 are always in a conducting state; The input control voltages VC1 and VC2 are in a high-level state, the control voltages VD1 and VD2 are in a high-level state, the inverted control voltages VD1-1 and VD2-1 are in a low-level state, and the control voltage VG1 is in a low-level state, so that the fourth switch tube M4, the fifth switch tube M5, the twenty-fourth switch tube M24, and the twenty-fifth switch tube M25 are all turned on, the third switch tube M3, the sixth switch tube M6, the twenty-third switch tube M23, and the twenty-sixth switch tube M26 are all turned off, the first capacitor C1 is discharged through the fifth switch tube M5 and the fourth switch tube M4, and the twenty-first capacitor C21 is discharged through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24; After the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are discharged to 0V, the control voltage VD1 and the control voltage VD2 are switched to a low level state, and the inverted control voltage VD1-1 and the inverted control voltage VD2-1 are synchronously switched to a high level state, so that the fifth switch tube M5 and the twenty-fifth switch tube M25 are turned off, and the sixth switch tube M6 and the twenty-sixth switch tube M26 are turned on, and the voltage across the first capacitor C1 and the voltage across the twenty-first capacitor C21 are maintained at 0V until the current-stage computing unit begins to enter the charging stage.

21. The control method according to claim 20, characterized in that: When the computing unit of this stage is in the charging stage, the control voltage VC1 of the computing unit of this stage is switched to a low level state, the control voltage VG1 of the storage unit of this stage is pulled up synchronously, and when the control voltage VC1 is completely pulled down, the control voltage VD1 is pulled up, so that the fourth switch tube M4 is turned off, the third switch tube M3 and the fifth switch tube M5 are turned on, and the charging current ICC1 related to the current IC1 flows through the second switch tube M2 immediately to charge the first capacitor C1; When the charging time reaches TC, the control voltage VD1 is switched to a low level state, and the control voltage VC2 of the lower-level computing unit is synchronously switched to a low level state. When the control voltage VD1 and the control voltage VC2 are completely pulled low, the computing unit at this level begins to enter the power supply stage, and the lower-level computing unit enters the charging stage.

22. The control method according to claim 21, characterized in that: When the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VC1 is pulled high and the control voltage VG1 is pulled low synchronously, so that the third switch tube M3 is turned off, the fourth switch tube M4 is turned on, the control voltage VD1 and the control voltage VC2 are in a low level state, the fifth switch tube M5 and the twenty-fourth switch tube M24 are turned off, the twenty-third switch tube M23 is turned on, and the output voltage VG1' of the current computing unit supplies power to the lower storage unit, and a current IC2 is generated in the twenty-third switch tube M23; When the current computing unit is in the power supply stage and the lower computing unit is in the charging stage, the control voltage VD2 is pulled high to turn on the twenty-fifth switch tube M25, and the charging current ICC2 related to the current IC2 flows through the twenty-second switch tube M22 immediately to charge the twenty-first capacitor C21; When the charging time reaches TC, the control voltage VD2 is switched to a low level state, and when the control voltage VD2 is completely pulled down, the control voltage VD1 remains in a low level state for TG, and the current level computing unit begins to enter the discharge stage, while the lower level computing unit enters the power supply stage.

23. The control method according to claim 22, characterized in that: When the computing unit at this stage is in the power supply stage, the output voltage VG1' of the computing unit at this stage is: ； Wherein, ICC1 is a charging current related to the current IC1, TC is a charging time of the first capacitor C1 by the charging current ICC1, and C1 is a capacitance value of the first capacitor; The output voltage VG1 ′ is regulated by the current IC1 .

24. The control method according to claim 23, characterized in that: When the computing unit at this level is in the power supply stage, the power supply time of the computing unit at this level is: ； Wherein, TG is the time that the control voltage VD1 maintains a low level, T0 is the sum of the rising edge time and the falling edge time of the control voltage VD2, and TC is the charging time of the charging current ICC2 on the twenty-first capacitor C21.

25. The control method according to any one of claims 22 to 24, characterized in that: When the current computing unit is in the discharge stage and the lower computing unit is in the power supply stage, the control voltage VD1 is switched to a high level state, so that the fifth switch tube M5 is turned on, the control voltage VC1 is in a high level state, the control voltage VG1 is in a low level state, the fourth switch tube M4 is turned on, and the first capacitor C1 is discharged to 0V through the fifth switch tube M5 and the fourth switch tube M4; When the discharge time reaches TF, the control voltage VD1 is switched to a low level state, and the inverted control voltage VD-1 is synchronously switched to a high level state, so that the fifth switch tube M5 is turned off, and the sixth switch tube M6 is turned on, and the voltage across the first capacitor C1 is maintained at 0V until the current level calculation unit enters the next charging stage; When the computing unit of the current level is in the discharge stage and the computing unit of the next level is in the power supply stage, the control voltage VC2 is pulled high, so that the twenty-third switch tube M23 is turned off, the twenty-fourth switch tube M24 is turned on, the control voltage VD2 is in a low level state, the twenty-fifth switch tube M25 is turned off, and the output voltage VG2' of the computing unit of the next level supplies power to the computing unit of the next level, and generates a current IC3 in the computing unit of the next level; When the control voltage VD2 maintains the low level state for a period of time reaching TG, it is switched to the high level state, and the lower-level computing unit begins to enter the discharge stage.

26. The control method according to claim 25, characterized in that: When the lower-level computing unit is in the power supply stage, the output voltage VG2' of the lower-level computing unit is: ； Wherein, ICC2 is a charging current related to the current IC2, TC is a charging time of the charging current ICC2 on the twenty-first capacitor C21, and C21 is a capacitance value of the twenty-first capacitor; The output voltage VG2 ′ is regulated by the current IC2 .

27. The control method according to claim 26, characterized in that: When the lower computing unit is in the discharge stage, the control voltage VD2 is first switched to a high level state, so that the twenty-fifth switch tube M25 is turned on, the control voltage VC2 is in a high level state, the twenty-fourth switch tube M24 is turned on, and the twenty-first capacitor C21 is discharged to 0V through the twenty-fifth switch tube M25 and the twenty-fourth switch tube M24; When the discharge time reaches TF, the control voltage VD2 is switched to a low level state, and the inverting control voltage VD-2 is synchronously switched to a high level state, so that the twenty-fifth switch tube M25 is turned off, the twenty-sixth switch tube M26 is turned on, and the voltage across the twenty-first capacitor C21 is maintained at 0V until the lower-level computing unit enters the next charging stage.

28. The control method according to claim 27, characterized in that: The power supply time TG is set to 101ns, the charging time TC is set to 100ns, the discharging time TF is set to 10ns, and T0 is set to 1ns.

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