Method for controlling a quantum chip, quantum control system and quantum computer

Abstract

The application discloses a quantum chip control method, a quantum control system and a quantum computer. A three-dimensional analysis model including coupling relationships between same-category elements on a quantum chip and coupling relationships between different-category elements is constructed, and then a working point of a quantum bit in the quantum chip to be measured is adjusted based on the three-dimensional analysis model. The scheme provided in the application can meet the demand of a large-scale quantum chip by constructing a three-dimensional analysis model of coupling relationships between an analysis reading bus layer, a resonant cavity layer and a quantum bit layer, and can meet the demand of the large-scale quantum chip from the overall structure and environment of the chip, and can make up for the blank of the prior art.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a control method for a quantum chip, a quantum control system, and a quantum computer. Background Technology

[0002] Quantum computing and quantum information is an interdisciplinary field that uses the principles of quantum mechanics to perform computational and information processing tasks. It is closely related to quantum physics, computer science, and informatics. It has experienced rapid development in the last two decades. Quantum algorithms based on quantum computers, such as factorization and unstructured search, have demonstrated performance far exceeding that of existing algorithms based on classical computers, leading to expectations that this field will surpass current computing capabilities. Because quantum computing has the potential to far exceed the performance of classical computers in solving specific problems, realizing a quantum computer requires a quantum chip containing a sufficient number and quality of qubits, capable of performing high-fidelity quantum logic gate operations and readouts on these qubits. The quantum chip is to a quantum computer what a CPU is to a traditional computer; it is the core component of a quantum computer, the processor that performs quantum computations. Before each quantum chip is officially put into use, the parameters of the qubits within the chip must be tested and characterized.

[0003] To enable the most computations to be performed within the finite lifetime of each qubit in a quantum chip, the fastest possible qubit logic gates are required. Generally, the execution time of a qubit logic gate is three to four orders of magnitude faster than the qubit's lifetime. However, fast qubit logic gate operations can lead to errors during execution. There are many reasons for qubit logic gate errors, such as parasitic coupling between nearest and second nearest neighbor qubits, spectral spread two-level system (TLS) defects, parasitic microwave modes, coupling with control lines and readout resonators, noise from frequency control electronics, frequency control pulse distortion, microwave control pulse distortion, and microwave carrier leakage. When each qubit in the quantum chip is at a suitable operating point, the effects of these interferences can be effectively reduced. Currently, in order to improve the accuracy of quantum chips in performing quantum computing tasks, the operating point of a few qubits is generally considered. There is a lack of solutions that consider the quantum chip as a whole. Existing solutions are feasible when the number of qubits in the quantum chip is small, such as only a few or a dozen qubits. However, in the foreseeable future, the number of quantum chips will inevitably increase significantly. At that time, existing solutions will not be able to meet the needs of large-scale quantum chips.

[0004] Therefore, a scheme is needed to adjust the operating point of qubits from the perspective of the entire quantum chip.

[0005] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a control method for quantum chips, a quantum control system, and a quantum computer to solve the problem that existing solutions cannot meet the needs of large-scale quantum chips.

[0007] To address the above technical problems, this invention proposes a control method for a quantum chip, comprising:

[0008] A three-dimensional analysis model is constructed, including the coupling relationships between components of the same type and the coupling relationships between components of different types on the quantum chip. The components include all readout buses of the sub-chip under test, all resonant cavities of the sub-chip under test, and all qubits of the sub-chip under test.

[0009] The operating point of the qubits in the sub-chip to be measured is adjusted based on the three-dimensional analysis model.

[0010] Optionally, the construction of a three-dimensional analysis model including the coupling relationships between components of the same type and between components of different types on the quantum chip includes:

[0011] Obtain the first coupling relationship between read buses, the first coupling relationship including the coupling relationship between adjacent read buses.

[0012] Optionally, the first coupling relationship is obtained by the following formula:

[0013]

[0014] Where b1 and b2 are two adjacent read buses, ω b1 ω is the frequency of the signal read from b1. b2 C is the frequency at which the signal is read from b2. bus Let be the parasitic capacitance between b1 and b2, v1 be the speed of light in b1, v2 be the speed of light in b2, c1 be the capacitance per unit length of the transmission line in b1, c2 be the capacitance per unit length of the transmission line in b2, and λ(ω) be the capacitance between b1 and b2. b1 ω b2 ) represents the coupling strength between b1 and b2.

[0015] Optionally, the construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, further includes:

[0016] Obtain a second coupling relationship between the read bus and the resonant cavity, the second coupling relationship including the coupling relationship between the read bus and an adjacent resonant cavity.

[0017] Optionally, the second coupling relationship is obtained by the following formula:

[0018]

[0019] Among them, C bus-reson To read the parasitic capacitance between the bus and the resonant cavity, c is the capacitance per unit length of the transmission line on the bus, Cr is the capacitance of the resonant cavity, and ω... r ω is the frequency of the signal in the resonant cavity, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

[0020] Optionally, the construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, further includes:

[0021] Obtain the third coupling relationship between resonant cavities. The third coupling relationship includes the coupling relationship between two adjacent or second-adjacent resonant cavities. Second-adjacent means that the two resonant cavities are diagonally related in the physical structure of the chip under test.

[0022] Optionally, the relationship of the third coupler is obtained by the following formula:

[0023]

[0024] Where r1 and r2 are two adjacent or next-adjacent resonant cavities, ω r1 ω r2 C represents the frequency of the two resonant cavities, Cr1 and Cr2 represent the capacitance of the two resonant cavities, and C... reson J is the size of the parasitic capacitance between the two resonant cavities. ωr1，ωr2 The coupling strength between the two resonant cavities.

[0025] Optionally, the construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, further includes:

[0026] A fourth coupling relationship is obtained between the resonant cavity and the qubit. The fourth coupling relationship includes the coupling relationship between the resonant cavity and the corresponding first qubit, and the coupling relationship between the resonant cavity and the second qubit. The resonant cavity is used to read the information carried by the first qubit, and the second qubit is another qubit that is adjacent to the first qubit.

[0027] Optionally, the fourth coupling relationship is obtained by the following formula:

[0028]

[0029] Where, ω r ω is the frequency of the resonant cavity. q / c C is the frequency of the first or second qubit. reson-qc C is the coupling capacitance between the resonant cavity and the first or second qubit. r C is the capacitance of the resonator. q / c J is the capacitance of the first or second qubit. ωr，ωq / c The coupling strength between the resonant cavity and the first or second qubit is denoted as .

[0030] Optionally, the construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, further includes:

[0031] The fifth coupling relationship between qubits is obtained. The fifth coupling relationship includes the coupling relationship between two adjacent qubits and the coupling relationship between two next-nearest qubits. The two adjacent qubits are two qubits that have a direct coupling relationship in the chip under test, and the two next-nearest qubits are two qubits that do not have a direct coupling relationship in the chip under test.

[0032] Optionally, the fifth coupling relationship is obtained by the following formula:

[0033]

[0034] Where ω1 and ω2 are the frequencies of two adjacent qubits or two next-nearest qubits, and C qc J represents the coupling capacitance between two adjacent qubits or two next-nearest qubits, where C1 and C2 are the capacitances between the two adjacent qubits or two next-nearest qubits. ω1，ω2 The coupling strength is the coupling strength between two adjacent qubits or two next-nearest qubits.

[0035] Optionally, adjusting the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model includes:

[0036] The constraints on the operating point of the target quantum bit are constructed based on the three-dimensional analysis model. The constraints are used to limit the target quantum bit from the coupling effect of surrounding elements. The target quantum bit is any quantum bit in the sub-chip to be measured.

[0037] The operating point of each quantum bit in the sub-chip to be measured is assigned using the constraints.

[0038] Based on the same inventive concept, this invention also proposes a control device for a quantum chip, comprising:

[0039] The model building unit is used to build a three-dimensional analysis model that includes the coupling relationships between components of the same type and the coupling relationships between components of different types on the quantum chip. The components include all readout buses of the sub-chip under test, all resonant cavities of the sub-chip under test, and all qubits of the sub-chip under test.

[0040] The operating point adjustment unit is used to adjust the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model.

[0041] Based on the same inventive concept, the present invention also proposes a quantum control system, which utilizes a control method for a quantum chip as described in any of the above-described features, or a control device that includes a quantum chip as described in the above-described features.

[0042] Based on the same inventive concept, the present invention also proposes a quantum computer, including the quantum control system described in the above feature description.

[0043] Based on the same inventive concept, the present invention also proposes a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the control method of the quantum chip described in any of the above features.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The quantum chip control method proposed in this invention constructs a three-dimensional analysis model including the coupling relationships between components of the same type and between components of different types on the quantum chip. Then, based on the three-dimensional analysis model, the operating point of the qubits in the sub-chip under test is adjusted. The solution proposed in this application, by constructing a three-dimensional analysis model analyzing the coupling relationships between the readout bus layer, resonant cavity layer, and qubit layer, and considering the overall chip structure and environment, can meet the needs of large-scale quantum chips, filling a gap in the prior art.

[0046] The quantum chip control device, quantum control system, quantum computer, and readable storage medium proposed in this invention belong to the same inventive concept as the quantum chip control method, and therefore have the same beneficial effects, which will not be elaborated here. Attached Figure Description

[0047] Figure 1 This is a flowchart illustrating the control method for a quantum chip proposed in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the three-dimensional analysis model structure proposed in an embodiment of the present invention;

[0049] Figure 3 This is a simplified structural diagram of the control device for a quantum chip proposed in another embodiment of the present invention. Detailed Implementation

[0050] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0051] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0053] Please refer to Figure 1 This invention provides a method for controlling a quantum chip, comprising:

[0054] S100: Construct a three-dimensional analysis model that includes the coupling relationships between components of the same type and between components of different types on the quantum chip, wherein the components include all readout buses of the sub-chip under test, all resonant cavities of the sub-chip under test, and all qubits of the sub-chip under test;

[0055] S200: Adjust the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model.

[0056] Unlike existing technologies, the quantum chip control method proposed in this invention constructs a three-dimensional analysis model that includes the coupling relationships between components of the same type and between components of different types on the quantum chip. Then, based on this three-dimensional analysis model, the operating point of the qubits in the sub-chip under test is adjusted. The solution proposed in this application, by constructing a three-dimensional analysis model analyzing the coupling relationships between the readout bus layer, resonant cavity layer, and qubit layer, considers the overall chip structure and environment, and can meet the needs of large-scale quantum chips, filling a gap in existing technologies. Those skilled in the art will understand that, in this embodiment, the operating point of the qubit refers to the operating frequency of the qubit.

[0057] To address the issue of qubit operating point allocation in quantum chips, existing schemes consider two types of influencing factors: qubits and couplers. Simply put, these schemes use the magnitude of the mutual influence between qubits and between qubits and couplers as constraints to select and adjust the operating point of the qubits. However, the applicant has discovered that in practical applications of quantum chips, many other factors interact, including but not limited to the influence between adjacent qubits, between resonant cavities and qubits, between adjacent resonant cavities, and between the resonant cavity and the readout bus. Some interactions are desirable; for example, when two adjacent qubits execute a two-qubit logic gate, we want their coupling strength to be as high as possible to support the operation of the two-qubit logic gate. Other interactions are undesirable; for example, when a qubit executes a single-qubit logic gate, we want the coupling strength of surrounding qubits to be as low as possible to ensure the accurate execution of the single-qubit logic gate. Based on the above considerations, the applicant has proposed a three-dimensional analysis model that includes the coupling relationships between components of the same type and between components of different types on a quantum chip. The three-dimensional analysis model is used to allocate and adjust the operating point of the qubit. Compared with existing solutions, the solution of this application considers more influencing factors and is more in line with the actual situation of quantum chips. The three-dimensional analysis model can be used to allocate the operating point of the qubit to a more realistic level. In addition, the three-dimensional analysis model can be used to more accurately characterize the qubit.

[0058] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a three-dimensional analysis model proposed in this embodiment. The main idea is to divide the specific structure of the quantum chip into three layers for layer-by-layer analysis. The top layer is the read bus layer containing the read bus 10, the middle layer is the resonant cavity layer containing the resonant cavity 11, and the bottom layer is the quantum bit layer containing the quantum bits 12 and the coupler 13.

[0059] In this embodiment, the applicant considered the coupling effect between two adjacent read buses. The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, includes:

[0060] Obtain the first coupling relationship between read buses, the first coupling relationship including the coupling relationship between adjacent read buses.

[0061] Specifically, the first coupling relationship is obtained through the following formula:

[0062]

[0063] Where b1 and b2 are two adjacent read buses, ω b1 ω is the frequency of the signal read from b1. b2 C is the frequency at which the signal is read from b2. bus Let be the parasitic capacitance between b1 and b2, v1 be the speed of light in b1, v2 be the speed of light in b2, c1 be the capacitance per unit length of the transmission line in b1, c2 be the capacitance per unit length of the transmission line in b2, and λ(ω) be the capacitance between b1 and b2. b1 ω b2 ) represents the coupling strength between b1 and b2.

[0064] In this embodiment, the applicant also considers the coupling effect between the read bus and the resonant cavity. The construction of the three-dimensional analysis model, which includes the coupling relationship between components of the same type and the coupling relationship between components of different types on the quantum chip, further includes:

[0065] A second coupling relationship is obtained between the read bus and the resonant cavity. This second coupling relationship includes the coupling relationship between the read bus and an adjacent resonant cavity. It should be noted that a single read bus is typically used to read multiple resonant cavities. In this embodiment, the second coupling relationship may only consider the coupling relationship between the resonant cavity read by the same read bus and the read bus itself, or it may consider the coupling relationship between the resonant cavity not currently read by the read bus and the current read bus. There are no restrictions here, and the settings can be configured according to actual needs.

[0066] Specifically, the second coupling relationship is obtained through the following formula:

[0067]

[0068] Among them, C bus-reson To read the parasitic capacitance between the bus and the resonant cavity, c is the capacitance per unit length of the transmission line on the bus, Cr is the capacitance of the resonant cavity, and ω... rω is the frequency of the signal in the resonant cavity, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

[0069] In this embodiment, the applicant also considers the coupling effect between resonant cavities. The construction of the three-dimensional analysis model, which includes the coupling relationship between components of the same type and the coupling relationship between components of different types on the quantum chip, further includes:

[0070] Obtain the third coupling relationship between resonant cavities. The third coupling relationship includes the coupling relationship between two adjacent or second-adjacent resonant cavities. Second-adjacent means that the two resonant cavities are diagonally related in the physical structure of the chip under test.

[0071] Specifically, the relationship of the third coupler is obtained through the following formula:

[0072]

[0073] Where r1 and r2 are two adjacent or next-adjacent resonant cavities, ω r1 ω r2 C represents the frequency of the two resonant cavities, Cr1 and Cr2 represent the capacitance of the two resonant cavities, and C... reson J is the size of the parasitic capacitance between the two resonant cavities. ωr1，ωr2 The coupling strength between the two resonant cavities.

[0074] In this embodiment, the applicant also considered the coupling effect between the resonant cavity and the quantum bit. The construction of the three-dimensional analysis model, which includes the coupling relationship between components of the same type and the coupling relationship between components of different types on the quantum chip, further includes:

[0075] A fourth coupling relationship is obtained between the resonant cavity and the qubit. The fourth coupling relationship includes the coupling relationship between the resonant cavity and the corresponding first qubit, and the coupling relationship between the resonant cavity and the second qubit. The resonant cavity is used to read the information carried by the first qubit, and the second qubit is another qubit that is adjacent to the first qubit.

[0076] Specifically, the fourth coupling relationship is obtained through the following formula:

[0077]

[0078] Where, ω r ω is the frequency of the resonant cavity. q / c C is the frequency of the first or second qubit. reson-qc C is the coupling capacitance between the resonant cavity and the first or second qubit.r C is the capacitance of the resonator. q / c J is the capacitance of the first or second qubit. ωr，ωq / c ω represents the coupling strength between the resonant cavity and the first or second qubit. It should be noted that the applicant has also discovered that, in addition to the coupling effect between the resonant cavity and the qubit, it may also have a coupling effect with the coupler. Therefore, in this embodiment, ω... q / c Besides being the frequency of the first or second qubit, it can also be the frequency of the coupler. Similarly, C reson-qc Besides being the coupling capacitance between the resonant cavity and the first or second qubit, C can also be the coupling capacitance between the resonant cavity and the coupler. q / c It can be the capacitance of the first or second quantum bit, or it can be the capacitance of the coupler.

[0079] In this embodiment, the applicant also considered the coupling effect between qubits. The construction of the three-dimensional analysis model, which includes the coupling relationship between components of the same type and the coupling relationship between components of different types on the quantum chip, further includes:

[0080] The fifth coupling relationship between qubits is obtained. The fifth coupling relationship includes the coupling relationship between two adjacent qubits and the coupling relationship between two next-nearest qubits. The two adjacent qubits are two qubits that have a direct coupling relationship in the chip under test, and the two next-nearest qubits are two qubits that do not have a direct coupling relationship in the chip under test.

[0081] Specifically, the fifth coupling relationship is obtained through the following formula:

[0082]

[0083] Where ω1 and ω2 are the frequencies of two adjacent qubits or two next-nearest qubits, and C qc J represents the coupling capacitance between two adjacent qubits or two next-nearest qubits, where C1 and C2 are the capacitances between the two adjacent qubits or two next-nearest qubits. ω1，ω2 The coupling strength is the coupling strength between two adjacent qubits or two next-nearest qubits.

[0084] Specifically, in this embodiment, adjusting the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model includes:

[0085] The constraints on the operating point of the target qubit are constructed based on the three-dimensional analysis model. The constraints are used to limit the target qubit from being affected by the coupling of surrounding elements. The target qubit is any qubit in the chip to be measured.

[0086] Specifically, in this embodiment, adjusting the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model further includes:

[0087] Using the physical topology and the constraints, the operating point of each qubit in the sub-chip to be measured is assigned, wherein the physical topology is the physical layout of each device in the sub-chip to be measured.

[0088] It should be noted that in this embodiment, the five coupling relationships mentioned above are mainly considered when allocating the operating points of the qubits. Therefore, the five coupling relationships already obtained are used when constructing constraints. In this embodiment, the constraints can be understood as constraint equations, that is, constraint equations are constructed. The constraint equations include λ(ω) b1 ω b2 ),λ(ω), J ωr1，ωr2 J ωr，ωq / c J ω1，ω2 These five parameters need to be assigned weight coefficients according to the degree of influence of these coupling relationships. The type of constraint equation is not limited and can be configured according to the actual situation. In this embodiment, the constraint equation Func is assumed to be:

[0089] Func=aλ(ω b1 ω b2 )+bλ(ω)+cJ ωr1，ωr2 +dJ ωr，ωq / c +eJ ω1，ω2 Among them, a, b, c, d, e

[0090] For each coupling relationship, weight coefficients are provided. Those skilled in the art will understand that a, b, c, d, and e can be positive or negative. When constructing constraints, a target value needs to be set. The constraint equation is considered to meet the requirements when the set target value is reached. It should be noted that the weight coefficients need to be determined based on the actual situation of the quantum chip under test, and no restrictions are imposed here. By constructing such constraints, we can minimize the noise interference experienced by the final quantum bit, making it easier to characterize the various parameters of the quantum bit during the testing phase of the quantum chip.

[0091] Specifically, in this embodiment, the physical topology and the constraint model can be used to sequentially allocate the operating points of each qubit in the quantum chip according to a set order.

[0092] Furthermore, in this embodiment, the operating points of qubits closer to the center of the physical topology can be obtained first, followed by the operating points of qubits farther from the center. This approach maximizes the performance of the quantum chip, ensuring that qubits whose suitable operating points cannot be determined appear at the edges of the physical topology, effectively improving resource utilization. It should be noted that when several qubits are equidistant from the center of the physical topology, the corresponding operating points are obtained from these qubits in a random order.

[0093] Based on the same inventive concept, this invention also proposes a control device for a quantum chip, please refer to... Figure 3 The control device for the quantum chip includes:

[0094] The model building unit 100 is used to build a three-dimensional analysis model including the coupling relationship between components of the same type and the coupling relationship between components of different types on the quantum chip. The components include a read bus layer, a resonant cavity layer, and a qubit layer. The read bus layer includes all read buses of the sub-chip under test, the resonant cavity layer includes all resonant cavities of the sub-chip under test, and the qubit layer includes all qubits of the sub-chip under test.

[0095] The operating point adjustment unit 200 is used to adjust the operating point of the qubits in the sub-chip to be measured based on the three-dimensional analysis model.

[0096] It is understood that the model building unit 100 and the operating point adjustment unit 200 can be implemented in a single device, or any module therein can be split into multiple sub-modules. Alternatively, at least some of the functions of one or more modules of the model building unit 100 and the operating point adjustment unit 200 can be combined with at least some of the functions of other modules and implemented in a single functional module. According to embodiments of the present invention, at least one of the model building unit 100 and the operating point adjustment unit 200 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable manner of integrating or packaging the circuit, or in a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the model building unit 100 and the operating point adjustment unit 200 can be at least partially implemented as a computer program module, which, when run by a computer, can execute the functions of the corresponding module.

[0097] Based on the same inventive concept, embodiments of the present invention also propose a quantum control system, utilizing a control method for a quantum chip as described in any of the above-described features, or a control device including the quantum chip described in the above-described features.

[0098] Based on the same inventive concept, embodiments of the present invention also propose a quantum computer, including the quantum control system described in the above feature description.

[0099] Based on the same inventive concept, embodiments of the present invention also propose a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the control method of the quantum chip described in any of the above features.

[0100] The readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage in a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0101] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0102] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0103] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0104] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A control method for a quantum chip, characterized in that, include: A three-dimensional analysis model is constructed, including the coupling relationships between components of the same type and the coupling relationships between components of different types on the quantum chip. The three-dimensional analysis model is constructed by dividing the specific structure of the quantum chip into three layers for layer-by-layer analysis. The top layer is the read bus layer containing the read bus, the middle layer is the resonant cavity layer containing the resonant cavity, and the bottom layer is the quantum bit layer containing the qubits and couplers. The components include all read buses of the sub-chip under test, all resonant cavities of the sub-chip under test, and all qubits of the sub-chip under test. Based on the three-dimensional analysis model, constraints are constructed for the operating point of the target qubit, and the operating point of each qubit in the sub-chip to be measured is allocated using the constraints; wherein, the constraints are used to limit the target qubit from being affected by the coupling of surrounding elements, and the constraints are constraint equations constructed using the coupling relationships between elements of the same type and between elements of different types, and the target qubit is any qubit in the sub-chip to be measured.

2. The method as described in claim 1, characterized in that, The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, includes: Obtain the first coupling relationship between read buses, the first coupling relationship including the coupling relationship between adjacent read buses.

3. The method as described in claim 2, characterized in that, The first coupling relationship is obtained through the following formula: Where b1 and b2 are two adjacent read buses, ω b1 ω is the frequency of the signal read from b1. b2 C is the frequency at which the signal is read from b2. bus Let be the parasitic capacitance between b1 and b2, v1 be the speed of light in b1, v2 be the speed of light in b2, c1 be the capacitance per unit length of the transmission line in b1, c2 be the capacitance per unit length of the transmission line in b2, and λ(ω) be the capacitance between b1 and b2. b1 ω b2 ) represents the coupling strength between b1 and b2.

4. The method as described in claim 2, characterized in that, The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, also includes: Obtain a second coupling relationship between the read bus and the resonant cavity, the second coupling relationship including the coupling relationship between the read bus and an adjacent resonant cavity.

5. The method as described in claim 4, characterized in that, The second coupling relationship is obtained through the following formula: Among them, C bus-reson To read the parasitic capacitance between the bus and the resonant cavity, c is the capacitance per unit length of the transmission line on the bus, Cr is the capacitance of the resonant cavity, and ω... r ω is the frequency of the signal in the resonant cavity, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

6. The method as described in claim 4, characterized in that, The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, also includes: Obtain the third coupling relationship between resonant cavities. The third coupling relationship includes the coupling relationship between two adjacent or second-adjacent resonant cavities. Second-adjacent means that the two resonant cavities are diagonally related in the physical structure of the chip under test.

7. The method as described in claim 6, characterized in that, The third coupling relationship is obtained through the following formula: Where r1 and r2 are two adjacent or next-adjacent resonant cavities, ω r1 ω r2 C represents the frequency of the two resonant cavities, Cr1 and Cr2 represent the capacitance of the two resonant cavities, and C... reson J is the size of the parasitic capacitance between the two resonant cavities. ωr1，ωr2 The coupling strength between the two resonant cavities.

8. The method as described in claim 6, characterized in that, The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, also includes: A fourth coupling relationship is obtained between the resonant cavity and the qubit. The fourth coupling relationship includes the coupling relationship between the resonant cavity and the corresponding first qubit, and the coupling relationship between the resonant cavity and the second qubit. The resonant cavity is used to read the information carried by the first qubit, and the second qubit is another qubit that is adjacent to the first qubit.

9. The method as described in claim 8, characterized in that, The fourth coupling relationship is obtained through the following formula: Where, ω r ω is the frequency of the resonant cavity. q / c C is the frequency of the first or second qubit. reson-qc C is the coupling capacitance between the resonant cavity and the first or second qubit. r C is the capacitance of the resonator. q / c J is the capacitance of the first or second qubit. ωr，ωq / c The coupling strength between the resonant cavity and the first or second qubit is denoted as .

10. The method as described in claim 8, characterized in that, The construction of the three-dimensional analysis model, which includes the coupling relationships between components of the same type and between components of different types on the quantum chip, also includes: The fifth coupling relationship between qubits is obtained. The fifth coupling relationship includes the coupling relationship between two adjacent qubits and the coupling relationship between two next-nearest qubits. The two adjacent qubits are two qubits that have a direct coupling relationship in the chip under test, and the two next-nearest qubits are two qubits that do not have a direct coupling relationship in the chip under test.

11. The method as described in claim 10, characterized in that, The fifth coupling relationship is obtained through the following formula: Where ω1 and ω2 are the frequencies of two adjacent qubits or two next-nearest qubits, and C qc J represents the coupling capacitance between two adjacent qubits or two next-nearest qubits, where C1 and C2 are the capacitances between the two adjacent qubits or two next-nearest qubits. ω1，ω2 The coupling strength is the coupling strength between two adjacent qubits or two next-nearest qubits.

12. A control device for a quantum chip, characterized in that, include: The model building unit is used to construct a three-dimensional analysis model that includes the coupling relationships between components of the same type and the coupling relationships between components of different types on the quantum chip. The three-dimensional analysis model is constructed layer by layer based on the specific structure of the quantum chip. The top layer is the read bus layer containing the read bus, the middle layer is the resonant cavity layer containing the resonant cavity, and the bottom layer is the quantum bit layer containing the qubits and couplers. The components include all read buses of the sub-chip under test, all resonant cavities of the sub-chip under test, and all qubits of the sub-chip under test. The operating point adjustment unit is used to construct constraints on the operating point of the target qubit based on the three-dimensional analysis model, and to allocate the operating point of each qubit in the sub-chip to be measured using the constraints; wherein, the constraints are used to limit the target qubit from being affected by the coupling of surrounding elements, and the constraints are constraint equations constructed using the coupling relationships between elements of the same type and between elements of different types, and the target qubit is any qubit in the sub-chip to be measured.

13. A quantum control system, characterized in that, The control method of the quantum chip as described in any one of claims 1-11, or the control device including the quantum chip as described in claim 12.

14. A quantum computer, characterized in that, Including the quantum control system as described in claim 13.

15. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can implement the control method of the quantum chip according to any one of claims 1 to 11.

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