Quantum logic gate, quadratic function quantum state preparation method and related device

Abstract

The invention discloses a quantum logic gate, a quadratic function quantum state preparation method and a related device, and the quadratic function quantum state preparation method comprises the steps: determining a quantum bit for preparing a quadratic function quantum state; a target quantum circuit is constructed, the target quantum circuit is provided with first quantum logic gates and second quantum logic gates which act on the quantum bits, each action time sequence comprises one first quantum logic gate, and each first quantum logic gate acts on three quantum bits; the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits; and operating the target quantum circuit to prepare a quadratic function quantum state. Compared with the prior art, according to the quadratic function quantum state preparation method provided by the invention, the depth of a circuit only needs an O (n) layer or an O (logn) layer, and the running time of a quantum computer can be effectively compressed.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to a quantum logic gate, a method for preparing a quadratic function quantum state, and related devices. Background Art

[0002] Quantum computing is a new computing model that follows the laws of quantum mechanics to control quantum information units for computing. Unlike classical computing, quantum computing follows the laws of quantum mechanics and is a new computing model that can break through the bottleneck of classical computing power. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they have the ability to process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time to crack RSA keys from hundreds of years to hours.

[0003] Since the quadratic function is the first non-trivial polynomial function, its efficient preparation can play an important role and significance in the subsequent polynomial preparation. The quadratic function can effectively approximate a large class of quantum states, thereby completing the efficient generation scheme of some other functions. How to efficiently prepare the quadratic function quantum state in quantum computing has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a quantum logic gate, a method for preparing a quadratic function quantum state and related devices to solve the technical problems in the prior art, which can realize the efficient preparation of quadratic function quantum states in quantum computing.

[0005] In a first aspect, the present invention provides a quantum logic gate, comprising a CX gate and a controlled RY gate acting on a preset quantum bit, wherein the action timing of the controlled RY gate is between the action timings of the two CX gates, the target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate.

[0006] A quantum logic gate as described above, wherein preferably, the preset quantum bit includes a first quantum bit, a second quantum bit and a third quantum bit, the CX gate includes a first CX gate, a second CX gate, a third CX gate and a fourth CX gate, the controlled RY gate includes a first controlled RY gate and a second controlled RY gate, the action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, the action timing of the second controlled RY gate is between the action timings of the third CX gate and the fourth CX gate, and the action timing of the third CX gate is after the action timing of the second CX gate, wherein:

[0007] The target bits of the first CX gate and the second CX gate are both the first quantum bit, and the control bits of the first CX gate and the second CX gate are both the second quantum bit;

[0008] The target bits of the third CX gate and the fourth CX gate are both the first quantum bit, and the control bits of the third CX gate and the fourth CX gate are both the third quantum bit;

[0009] The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit;

[0010] The target bit of the second controlled RY gate is the third quantum bit, and the control bits of the second controlled RY gate are the first quantum bit and the second quantum bit.

[0011] A quantum logic gate as described above, wherein, preferably, the parameter value of the first controlled RY gate is expressed as The parameter value of the second controlled RY gate is expressed as

[0012] A quantum logic gate as described above, wherein preferably, the preset quantum bit includes a first quantum bit and a second quantum bit, the CX gate includes a first CX gate and a second CX gate, the controlled RY gate includes a first controlled RY gate, and the action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, wherein:

[0013] The target bits of the first CX gate and the second CX gate are both the first quantum bit, and the control bits of the first CX gate and the second CX gate are both the second quantum bit;

[0014] The target bit of the first controlled RY gate is the second quantum bit, and the control bit of the first controlled RY gate is the first quantum bit.

[0015] A quantum logic gate as described above, wherein, preferably, the parameter value of the first controlled RY gate is expressed as

[0016] In a second aspect, the present invention provides a method for preparing a quadratic function quantum state, the method comprising:

[0017] Determining the quantum bits used to prepare the quadratic function quantum state;

[0018] Construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on a quantum bit, wherein:

[0019] The first quantum logic gate is the aforementioned quantum logic gate, each action sequence includes one of the first quantum logic gates, each of the first quantum logic gates acts on three of the quantum bits, and the quantum bits are arranged from the highest-order quantum bit to the lowest-order quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers, and along the action sequence, the first quantum logic gate in the next action sequence acts on a quantum bit with a serial number reduced by one compared to the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order quantum bit;

[0020] The second quantum logic gate is the aforementioned quantum logic gate, the action sequence of the second quantum logic gate is located after the action sequence of the plurality of the first quantum logic gates, and the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits;

[0021] The target quantum circuit is run to prepare the quadratic function quantum state.

[0022] A method for preparing a quadratic function quantum state as described above, wherein preferably, the target quantum circuit also includes an H gate acting on all quantum bits, wherein the H gate is located after the multi-layer action sequence of the first quantum logic gate and the second quantum logic gate on the quantum bit.

[0023] In a third aspect, the present invention provides a quadratic function quantum state preparation device, the device comprising:

[0024] An acquisition module, used for determining a quantum bit used to prepare a quadratic function quantum state;

[0025] A target quantum circuit construction module is used to construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on a quantum bit, each action sequence includes one of the first quantum logic gates, each of the first quantum logic gates acts on three of the quantum bits, and the quantum bits are arranged from the highest-order quantum bit to the lowest-order quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers, and along the action sequence, the first quantum logic gate in the next action sequence acts on the quantum bit with a serial number reduced by one compared with the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order quantum bit; the action sequence of the second quantum logic gate is located after the action sequences of the first quantum logic gates, and the first quantum logic gate acts on the lowest-order quantum bit and the adjacent quantum bits;

[0026] An operation module is used to operate the target quantum circuit to prepare the quadratic function quantum state.

[0027] In a fourth aspect, the present invention provides a storage medium storing a computer program, wherein the computer program is configured to implement the aforementioned method when run.

[0028] In a fifth aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the aforementioned method.

[0029] Compared with the prior art, the quadratic function quantum state preparation method provided by the present invention only requires a circuit depth of O (n) Layer or O (logn) Layer, which can effectively compress the running time of quantum computers. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a network block diagram of a quantum circuit construction system provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the structure of a first quantum logic gate provided by an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the structure of a second quantum logic gate provided by an embodiment of the present invention;

[0033] Figure 4 is a flow chart of a method for preparing a quadratic function quantum state provided by an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of a target quantum circuit provided by an embodiment of the present invention

[0035] Figure 6 A schematic diagram of the structure of a quadratic function quantum state preparation device provided by an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of the structure of a de-entanglement quantum logic gate provided by an embodiment of the present invention;

[0037] Figure 8 A schematic diagram of the structure of a de-entangled quantum circuit provided by an embodiment of the present invention;

[0038] Fig. 9 A schematic diagram of the structure of another target quantum circuit provided by an embodiment of the present invention;

[0039] Fig.10 A schematic diagram of the structure of another de-entanglement quantum circuit provided by an embodiment of the present invention;

[0040] Fig.11 A schematic diagram of the structure of another target quantum circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0042] [Structure of the quantum circuit construction system]

[0043] Figure 1 1 is a network block diagram of a quantum circuit construction system provided in an embodiment of the present application. The quantum circuit construction system may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0044] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit construction system, including but not limited to the Internet, corporate intranet, local area network, mobile communication network and their combination. The connection method can be wired, wireless communication links or optical fiber cables.

[0045] The server 120 and the client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0046] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 162 (application 173). The application 162 (application 173) may be used to implement a quantum algorithm compiled according to the quantum circuit construction method provided in an embodiment of the present application.

[0047] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum calculations.

[0049] The classical processing system 160 and the quantum processing system 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum applications through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0050] In the classic processing system 160 based on silicon chips, the unit of the classic processor 161 is a CMOS tube. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and is available at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, for example: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0051] Unlike this logic unit in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0052] Based on these differences, the design of the logical function on the quantum bit (including the design of whether the quantum bit is used and the design of the efficiency of each quantum bit) is the key to improving the computing performance of quantum computers, and requires special design. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face.

[0053] [Structure of quantum logic gate and preparation method of quadratic function quantum state]

[0054] The quadratic function is the first non-trivial polynomial function. Its efficient preparation can play an important role and significance in the subsequent polynomial preparation. The embodiments provided by the present invention are intended to achieve Efficient preparation of state.

[0055] x 2 The form after Walsh transformation is as follows (unnormalized)

[0056]

[0057] Now consider the Walsh transformation of the function again:

[0058]

[0059] Then we can integrate these two parts to solve, and we can see that the comprehensive results of the last two parts can be expressed in the following form:

[0060]

[0061] make

[0062] in

[0063] Then it can be deduced that:

[0064]

[0065] And for an initial input state: |0> n-d |1> d , what needs to be built is

[0066] Similar SCSPP n,k The matrix is ​​defined as follows:

[0067] SCSPP n,k |0> k+1 =|0> k+1

[0068] SCSPPn,k |0> k-d |0>|1> d =|0> k-d SCSP n,d |0>|1> d

[0069] SCSPP n,k |1> k+1 =|1> k+1

[0070] in

[0071] Assume the input is:

[0072] |0> n-d |1> d , through SCSPP n,k After the matrix, the quantum state becomes:

[0073]

[0074] At this time, U acts on the first n-1 quantum bits. n-1 The gate, then we can get the following equation:

[0075]

[0076] So we used SCSPP n,k The matrix can be synthesized recursively to U n The door is ready.

[0077] SCSPP is given below n,k The matrix preparation method is a quadratic function, so the input is at most two |1> states, SCSPP n,k The matrix is ​​a quantum logic gate, including a CX gate and a controlled RY gate acting on a preset quantum bit. The number of the preset quantum bits is 2 or 3, and no more than 3. The action timing of the controlled RY gate is between the action timings of the two CX gates. The target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate.

[0078] SCSPP n,k The matrix can be a first quantum logic gate acting on three qubits or a second quantum logic gate acting on two qubits, where:

[0079] When SCSPP n,kWhen the matrix is ​​a first quantum logic gate acting on three quantum bits, the preset quantum bits include the first quantum bit, the second quantum bit and the third quantum bit. Each quantum bit in the quantum circuit needs to be uniquely identified, so each quantum bit will be assigned a unique number to distinguish different quantum bits. In the embodiment provided by the present invention, the quantum bits in the quantum circuit are numbered in sequence from the highest bit to the lowest bit. For example, refer to Figure 2 As shown, the quantum circuit used to construct the first quantum logic gate has three quantum bits. The three quantum bits are numbered from 1 to 3 from the highest bit to the lowest bit. The first quantum bit is located at the bottom of the diagram and is also the highest quantum bit. The third quantum bit is located at the top of the diagram, which is the lowest quantum bit.

[0080] The CX gate includes a first CX gate, a second CX gate, a third CX gate and a fourth CX gate, and the controlled RY gate includes a first controlled RY gate and a second controlled RY gate. The action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, the action timing of the second controlled RY gate is between the action timings of the third CX gate and the fourth CX gate, and the action timing of the third CX gate is after the action timing of the second CX gate, wherein:

[0081] The target bits of the first CX gate and the second CX gate are both the first quantum bit, the control bits of the first CX gate and the second CX gate are both the second quantum bit, the target bits of the third CX gate and the fourth CX gate are both the first quantum bit, and the control bits of the third CX gate and the fourth CX gate are both the third quantum bit.

[0082] The target bit of the first controlled RY gate is the second qubit, the control bit of the first controlled RY gate is the first qubit, the target bit of the second controlled RY gate is the third qubit, and the control bits of the second controlled RY gate are the first qubit and the second qubit.

[0083] In a feasible implementation manner, the parameter value of the first controlled RY gate is expressed as The parameter value of the second controlled RY gate is expressed as The parameter values ​​of the first controlled RY gate and the second controlled RY gate represent the ratio of the RY gate to the |0> state division, that is, The corresponding value.

[0084] When SCSPP n,k When the matrix is ​​the first quantum logic gate acting on three qubits, refer to Figure 3As shown, the preset quantum bit includes a first quantum bit and a second quantum bit, the CX gate includes a first CX gate and a second CX gate, the controlled RY gate includes a first controlled RY gate, and the action timing of the first controlled RY gate is between the action timing of the first CX gate and the second CX gate, wherein:

[0085] The target bits of the first CX gate and the second CX gate are both the first qubit, and the control bits of the first CX gate and the second CX gate are both the second qubit. The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit.

[0086] In a feasible implementation manner, the parameter value of the first controlled RY gate is expressed as The parameter value of the first controlled RY gate represents the ratio of the RY gate division, that is, The corresponding value.

[0087] Reference Figure 4 as well as Figure 5 As shown, the present invention provides a method for preparing a quadratic function quantum state, the method comprising:

[0088] Step S101: Determine the quantum bits used to prepare the quadratic function quantum state.

[0089] The number of quantum bits corresponding to the quadratic function quantum state can be predetermined and can be determined based on the number of quantum bits supported by the quantum device. It is generally less than or equal to the number of quantum bits supported. When the number of quantum bits supported by the quantum device is relatively large, the number of quantum bits required for preparation can be selected as appropriate.

[0090] Step S102: construct a target quantum circuit, where the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the quantum bit, wherein:

[0091] Each quantum bit in the target quantum circuit needs to be uniquely identified, so each quantum bit will be assigned a unique number to distinguish different quantum bits. In the embodiment provided by the present invention, the quantum bits in the target quantum circuit are numbered from the highest bit to the lowest bit, and in each action sequence, the quantum bits will be renumbered, and the subsequent action sequence will ignore the quantum bit with the first number in the previous action sequence and the quantum bits that have been ignored in the previous action sequence. For example, the highest quantum bit in the initial action sequence is the first quantum bit, and the highest quantum bit is ignored in the second action sequence, and the second highest quantum bit is used as the first quantum bit. In the third action sequence, the highest and second highest quantum bits are ignored, and the third highest quantum bit is used as the first quantum bit, and so on.

[0092] It should be noted that the target quantum circuit for preparing the quadratic function quantum state includes a first quantum logic gate located at n-2 different action time sequences and a second quantum logic gate located after the first quantum logic gate, wherein n is the number of quantum bits of the target quantum circuit for preparing the quadratic function quantum state, each first quantum logic gate acts on three quantum bits arranged in sequence, and n-2 first quantum logic gates act on n quantum bits in sequence. The target quantum circuit undergoes a first quantum logic gate so that the quantum bit representing the quantum state of the quadratic function output by the target quantum circuit in this time sequence is reduced by one compared to the quantum bit representing the quantum state of the quadratic function input, and then after n-2 first quantum logic gates, the quantum state of the quadratic function can be represented in 2 quantum bits, which effectively reduces the quantum bit resources required for preparing the quantum state of the quadratic function, and saves the classical hardware resources of quantum computing simulation or the quantum hardware resources of quantum computing quantum hardware real machine calculation.

[0093] Specifically, each action sequence includes a first quantum logic gate, and each first quantum logic gate acts on three quantum bits, which are arranged from the highest quantum bit to the lowest quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits. Along the action sequence, the quantum bit number acted on by the first quantum logic gate of the next action sequence is reduced by one compared with the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest quantum bit.

[0094] That is, starting from the highest-order quantum bit, the sequence numbers are 1, 2...n. In the first action sequence, quantum bits 1, 2, and 3 are all acted on by the first quantum logic gate. Quantum bits 1, 2, and 3 are used as the first quantum bit, the second quantum bit, and the third quantum bit in the first quantum logic gate, respectively. In the second action sequence, the first quantum logic gate is also used. Since the quantum bit sequence number acted on by the first quantum logic gate in the latter action sequence is one less than that acted on by the first quantum logic gate in the previous action sequence, in the second action sequence, the first quantum logic gate acts on quantum bits 2, 3, and 4. Quantum bits 3 and 4 act as the first, second and third quantum bits in the first quantum logic gate respectively. In the third action sequence, a first quantum logic gate is also acted on. Since the quantum bit number acted on by the first quantum logic gate in the latter action sequence is one less than that acted on by the first quantum logic gate in the previous action sequence, in the third action sequence, the first quantum logic gate acts on quantum bits 3, 4 and 5. Quantum bits 3, 4 and 5 act as the first, second and third quantum bits in the first quantum logic gate respectively, and so on, until the first quantum logic gate acts on the lowest-order quantum bit.

[0095] According to the aforementioned first quantum logic gate, the first quantum logic gate includes a first CX gate, a second CX gate, a third CX gate, a fourth CX gate, a first controlled RY gate and a second controlled RY gate. Within the action timing of the first quantum logic gate, the action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, the action timing of the second controlled RY gate is between the action timings of the third CX gate and the fourth CX gate, and the action timing of the third CX gate is after the action timing of the second CX gate, wherein:

[0096] The target bits of the first CX gate and the second CX gate are both the first qubit, and the control bits of the first CX gate and the second CX gate are both the second qubit; the target bits of the third CX gate and the fourth CX gate are both the first qubit, and the control bits of the third CX gate and the fourth CX gate are both the third qubit; the target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit; the target bit of the second controlled RY gate is the third qubit, and the control bits of the second controlled RY gate are the first qubit and the second qubit.

[0097] After all the first quantum logic gates have been acted upon, a second quantum logic gate acts on the lowest-order quantum bit and the adjacent quantum bits, the second quantum logic gate comprising a first CX gate, a second CX gate and a first controlled RY gate, within the action sequence of the second quantum logic gate, the action sequence of the first controlled RY gate is between the action sequence of the first CX gate and the second CX gate, wherein: the second lowest-order quantum bit and the lowest-order quantum bit are used as the first quantum bit and the second quantum bit in the second quantum logic gate respectively, the target bits of the first CX gate and the second CX gate are both the second lowest-order quantum bits, and the control bits of the first CX gate and the second CX gate are both the lowest-order quantum bits; the target bit of the first controlled RY gate is the lowest-order quantum bit, and the control bit of the first controlled RY gate is the second lowest-order quantum bit.

[0098] The target quantum circuit also includes an H gate acting on all quantum bits, wherein the H gate is located after the multi-layer action sequence of the first quantum logic gate and the second quantum logic gate on the quantum bits.

[0099] Step S103: Run the target quantum circuit to prepare a quadratic function quantum state. In the specific preparation, first obtain the target quantum circuit, then run the quantum operation corresponding to the target quantum circuit on the quantum chip, and then the quadratic function quantum state can be prepared.

[0100] Based on the quadratic function quantum state preparation method provided in the above embodiment, the circuit depth only requires O(n) layers, which can effectively shorten the running time of the quantum computer.

[0101]

Device for preparing quadratic function quantum states

[0102] See also Figure 6 As shown, the quadratic function quantum state preparation device includes:

[0103] An acquisition module, used for determining a quantum bit used to prepare a quadratic function quantum state;

[0104] A target quantum circuit construction module is used to construct a target quantum circuit. The target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on a quantum bit. Each action sequence includes a first quantum logic gate. Each first quantum logic gate acts on three quantum bits, which are arranged from the highest quantum bit to the lowest quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers. Along the action sequence, the first quantum logic gate of the next action sequence acts on a quantum bit with a serial number reduced by one compared to the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest quantum bit. The action sequence of the second quantum logic gate is located after the action sequences of the multiple first quantum logic gates, and the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits.

[0105] The running module is used to run the target quantum circuit to prepare the quadratic function quantum state.

[0106] Among them, the operation module is a quantum system that can run the quantum circuit. Exemplarily, the quantum hardware including a quantum processor and a quantum measurement and control system with communication connection is a system, wherein the quantum processor refers to a quantum chip, and the quantum measurement and control system is used to provide an analog signal for realizing the quantum logic gate in the quantum circuit. The analog signal acts on the quantum chip to realize the operation of the quantum circuit.

[0107]

Storage medium structure

[0108] An embodiment of the present invention further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to implement the steps of any of the above method embodiments when running.

[0109] Specifically, in this embodiment, the above storage medium may be configured to store a computer program for implementing the following steps:

[0110] Step S101: Determine the quantum bits used to prepare the quadratic function quantum state.

[0111] Step S102: construct a target quantum circuit, the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the quantum bit, each action sequence includes a first quantum logic gate, each first quantum logic gate acts on three quantum bits, and is arranged from the highest quantum bit to the lowest quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers. Along the action sequence, the quantum bit serial number acted by the first quantum logic gate of the next action sequence is reduced by one compared with the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest quantum bit; the action sequence of the second quantum logic gate is located after the action sequence of multiple first quantum logic gates, and the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits.

[0112] Step S103: running the target quantum circuit to prepare a quadratic function quantum state.

[0113]

Structure of electronic devices

[0114] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to implement the steps in any one of the above method embodiments.

[0115] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0116] Specifically, in this embodiment, the processor may be configured to implement the following steps through a computer program:

[0117] Step S101: Determine the quantum bits used to prepare the quadratic function quantum state.

[0118] Step S102: construct a target quantum circuit, the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the quantum bit, each action sequence includes a first quantum logic gate, each first quantum logic gate acts on three quantum bits, and is arranged from the highest quantum bit to the lowest quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers. Along the action sequence, the quantum bit serial number acted by the first quantum logic gate of the next action sequence is reduced by one compared with the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest quantum bit; the action sequence of the second quantum logic gate is located after the action sequence of multiple first quantum logic gates, and the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits.

[0119] Step S103: running the target quantum circuit to prepare a quadratic function quantum state.

[0120]

Method for constructing de-entangled quantum logic gates

[0121] In the embodiment provided by the present invention, a de-entanglement quantum logic gate is also provided. This entanglement quantum logic gate is used to realize the controlled rotation operation between two entangled quantum bits, and the quantum states of the two quantum bits are converted between the |01> state and the |10> state.

[0122] The de-entangled quantum logic gate constructed by it refers to Figure 7 As shown, the construction method includes:

[0123] S201: Determine two quantum bits, and obtain the first H gate, the parameterized RY gate, and the second H gate acting on each quantum bit in turn; wherein, the angle parameters of the parameterized RY gates of the two quantum bits are opposite numbers, and the absolute value of the angle parameters of the parameterized RY gates is jointly determined by the quantum state amplitude value on each quantum bit.

[0124] S202: A first controlled rotary gate is constructed at the first evolutionary timing and the second evolutionary timing on the two quantum bits. Preferably, the first controlled rotary gate is a controlled Z-gate, and the control bits of the two first controlled rotary gates are on the same quantum bit, wherein the first evolutionary timing is the timing between the first H gate and the parameter-containing RY gate, and the second evolutionary timing is the timing between the parameter-containing RY gate and the second H gate.

[0125] [A method for preparing a quadratic function quantum state with a shallower circuit depth]

[0126] Assume that the initial state of a certain deentangled quantum circuit is the quadratic function quantum state to be prepared; then, by deentanglement of the quadratic function quantum state, a quantum circuit that evolves the target quantum state to the state can be obtained. The above steps are classical processing procedures and can be implemented using a quantum simulator.

[0127] Furthermore, we can construct the inverse circuit of the above de-entangled quantum circuit to obtain the target quantum circuit, run the target quantum circuit and apply it to the initial state |0> n The preparation of quadratic function quantum states can be realized on real quantum chips.

[0128] In a feasible implementation manner, the present invention provides a method for preparing a quadratic function quantum state, comprising the following steps:

[0129] Step S301: Determine the quantum bits used to prepare the quadratic function quantum state.

[0130] Step S302: A plurality of de-entanglement quantum logic gates act on the quantum bits whose initial state is a quadratic function quantum state to obtain a de-entanglement quantum circuit, which is used to evolve the quadratic function quantum state into |0> n The deentanglement quantum logic gate is constructed using the aforementioned method, wherein the action relationship between the deentanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the deentanglement quantum logic gate and the quantum bit in the previous layer of action sequence.

[0131] In the deentanglement quantum circuit, each deentanglement quantum logic gate acts on two preset quantum bits, which can be two adjacent quantum bits or two spaced quantum bits, depending on the setting of the circuit. It is not limited here. Along the action sequence, multiple deentanglement quantum logic gates are distributed in multiple layers, and each layer of deentanglement quantum logic gates includes at least one deentanglement quantum logic gate. The deentanglement quantum logic gates in the same layer of deentanglement quantum logic gates all act on the same action sequence.

[0132] In the disentanglement quantum circuit, the disentanglement quantum logic gate plays the role of disentangling two quantum bits. After the disentanglement quantum circuit is applied to the two quantum bits, the disentanglement of the two quantum bits is completed. After each layer of the action sequence of the disentanglement quantum logic gate, the quantum bits of the target quantum state are partially disentangled with each other, until after all the action sequences, an approximate |0> n state.

[0133] Step S303: Determine the inverse circuit of the disentangled quantum circuit as the target quantum circuit. The target quantum circuit has a target quantum logic gate, which is determined based on the disentangled quantum logic gate, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next action sequence.

[0134] The number of target quantum logic gates of the target quantum circuit is the same as the number of disentanglement quantum logic gates of the disentanglement quantum circuit, and the execution timing of the multiple target quantum logic gates is opposite to that of the multiple disentanglement quantum logic gates.

[0135] The target quantum circuit is obtained by inverting the deentanglement quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset quantum bits. These two quantum bits can be two adjacent quantum bits or two spaced quantum bits. The two quantum bits can be freely set. At the same time, the maximum parallel executable quantum gate pairs need to be satisfied, so as to efficiently complete the deentanglement. Along the action sequence, multiple target quantum logic gates are distributed in multiple layers. Each layer of target quantum logic gates includes at least one target quantum logic gate. The target quantum logic gates in the same layer of target quantum logic gates all act on the same action sequence.

[0136] In the target quantum circuit, the role of the target quantum logic gate is to generate a preset entangled state between two quantum bits, with the initial state being |0> n After each quantum bit in the state passes through a layer of target quantum logic gates, some of the quantum bits will become entangled with each other until a quadratic function quantum state is obtained after all the action sequences have passed.

[0137] Step S204: Run the target quantum circuit to prepare a quadratic function quantum state. During the specific preparation, first obtain the target quantum circuit to be prepared, and then run the quantum operation corresponding to the target quantum circuit on the quantum chip to prepare the quadratic function quantum state.

[0138] Based on the quadratic function quantum state preparation method provided in the above embodiment, the circuit depth only requires O(logn) layers, thereby realizing the logarithmic level preparation scheme of bits of quadratic function quantum states, which can effectively compress the running time of quantum computers.

[0139] Furthermore, the specific method of determining the action relationship between the de-entangled quantum logic gate and the quantum bit in the latter action sequence by the action relationship between the de-entangled quantum logic gate and the quantum bit in the previous action sequence is as follows:

[0140] Each quantum bit in the de-entangled quantum circuit needs to be uniquely identified, so each quantum bit will be assigned a unique number to distinguish different quantum bits. In the embodiment provided by the present invention, the quantum bits in the de-entangled quantum circuit are numbered from the lowest bit to the highest bit. For example, refer to Figure 8 As shown, the deentanglement quantum circuit has 8 quantum bits, and the 8 quantum bits are numbered from 1 to 8. Quantum bit 1 is located at the top of the diagram and is also the lowest-order quantum bit. Quantum bit 8 is located at the bottom of the diagram and is the highest-order quantum bit.

[0141] In each layer of action sequence, the quantum bits are reorganized to form several quantum bit pairs. Each quantum bit pair includes a first quantum bit and a second quantum bit. The first quantum bit is at a lower position than the second quantum bit. In each layer of action sequence, each quantum bit pair is acted upon by a de-entanglement quantum logic gate.

[0142] In the first layer of action sequence, the qubits from the lowest to the highest are grouped in sequence, and every two qubits form a qubit pair. The two qubits can be two qubits at adjacent positions or two qubits at spaced positions. Preferably, every two adjacent qubits form a qubit pair, and each qubit pair acts on a de-entanglement quantum logic gate to de-entangle the two qubits. After the de-entanglement quantum logic gate acts on the two qubits, the de-entanglement of the two qubits is completed, and the first qubit or the second qubit is evolved into the |0> state.

[0143] In other layers of action sequences, a number of quantum bits are regrouped according to the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous layer of action sequence to form a quantum bit set. The quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit in the quantum bit pair in each previous layer of action sequence that has not evolved to the |0> state. The quantum bits in the quantum bit set are grouped in sequence from low to high, and every two quantum bits form a quantum bit pair. The two quantum bits can be two adjacent quantum bits or two quantum bits at intervals. Preferably, every two adjacent quantum bits form a quantum bit pair, and each quantum bit pair acts on a de-entanglement quantum logic gate.

[0144] After each layer of disentanglement quantum logic gates, some of the quantum bits in the target quantum state are disentangled with each other until the initial approximate state is obtained after all the action sequences. n state.

[0145] The de-entanglement quantum circuit provided by the present invention can directly de-entangle the first layer qubits, half the number of bits left after deentanglement at the second level entanglement. By following this method, all entanglements can be completed eventually, and the depth of the circuit only needs O(logn) layers.

[0146] In a feasible implementation mode, referring to Figure 8 As shown, a de-entangled quantum circuit with 8 qubits is used as an example:

[0147] In the first level of action sequence, every two adjacent quantum bits are grouped into four quantum bit pairs, namely [1,2], [3,4], [5,6] and [7,8]. Each quantum bit pair is acted upon by a deentanglement quantum logic gate, which limits the second quantum bit in the quantum bit pair to evolve into an approximate |0> state, that is, quantum bits 2, 4, 6 and 7 are in an approximate |0> state after being acted upon.

[0148] After the first layer of action sequence, the amplitude approximately exists on quantum bits No. 1, No. 3, No. 5 and No. 7. At this time, in the second layer of action sequence, the remaining quantum bits are reorganized. This time there are two quantum bit pairs, [1,3] and [5,7]. Each quantum bit pair is acted on by a deentanglement quantum logic gate, which limits the second quantum bit in the quantum bit pair to evolve into an approximate |0> state, that is, quantum bits No. 3 and No. 7 are in an approximate |0> state after being acted on.

[0149] After the second level of action sequence, the amplitude only exists on quantum bits No. 1 and No. 5. At this time, in the third level of action sequence, it is only necessary to act on quantum bits No. 1 and No. 5 with the de-entanglement quantum logic gate to completely collapse the quantum states on quantum bits No. 1 and No. 5 to the |0> state.

[0150] For n qubits, first assume that it is an exponential power of 2, that is, n = 2 m , where m is a positive integer. In the first-level action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1,2], [3,4], [5,6]......[2 m -1,2 m ].

[0151] The second qubit in the limited qubit pair is evolved to the approximate |0> state. After the first layer of action sequence, the remaining qubits with amplitude are 1, 3, and 2. m -1 qubit, in the second layer of action sequence, regroups the remaining qubits to obtain the following qubit pairs: [1,3], [5,7]......[2 m -3,2 m -1].

[0152] This continues until the last layer, when only two quantum bits are left to be grouped, and a total of m=logn layers of pairing are required.

[0153] When considering that n quantum bits are not an exponent of 2, the highest-order quantum bits are not grouped during the first-level action sequence, and are included in the grouping range only during the second-level action sequence.

[0154] Let's take 7 qubits as an example:

[0155] Reference Fig.10 As shown, in the first layer of action sequence, there are three quantum bit pairs: [1,2], [3,4], [5,6], and the remaining quantum bit No. 7 is not grouped.

[0156] In the second-level action sequence, quantum bit No. 7 begins to be included in the grouping range, and there are two quantum bit pairs: [1,3], [5,7].

[0157] In the third-level action sequence, the quantum bit pair is [1,5].

[0158] In the embodiment provided by the present invention, the specific method for determining the action relationship between the target quantum logic gate and the quantum bit in the previous action sequence of the target quantum circuit by the action relationship between the target quantum logic gate and the quantum bit in the next action sequence is:

[0159] In each layer of action sequence, the quantum bits are reorganized to form several quantum bit pairs. Different quantum bit pairs include different quantum bits. Each quantum bit pair includes a first quantum bit and a second quantum bit. The first quantum bit is at a lower position than the second quantum bit. In each layer of action sequence, each quantum bit pair is acted upon by a target quantum logic gate.

[0160] In the last layer of action sequence, the quantum bits from the lowest to the highest are grouped in sequence, and every two adjacent quantum bits form a quantum bit pair. In the last layer of action sequence, every two adjacent quantum bits from the lowest to the highest quantum bits are acted upon by a target quantum logic gate. Since the target quantum circuit is obtained by reverse deduction based on the deentanglement quantum circuit, the quantum bit pair acted upon by the target quantum logic gate in the last layer of action sequence is the same as the quantum bit pair acted upon by the deentanglement quantum logic gate in the first layer of action sequence of the deentanglement quantum circuit.

[0161] In other layers of action sequences, several quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence to form a quantum bit set, and the quantum bits in the quantum bit set are grouped in sequence from low to high to form quantum bit pairs. This can be derived from the disentanglement quantum circuit. For example, in the penultimate layer of action sequence, the quantum bit pair acted on by the target quantum logic gate is the same as the quantum bit pair acted on by the disentanglement quantum logic gate in the second layer of action sequence of the disentanglement quantum circuit. By analogy, the quantum bit pairs of all action sequences of the target quantum circuit are obtained.

[0162] After each quantum bit in the initial state passes through a layer of target quantum logic gates, some of the quantum bits will become entangled with each other until a quadratic function quantum state is obtained after all the action sequences have passed.

[0163] In a feasible implementation mode, referring to Fig. 9 As shown, a target quantum circuit with 8 qubits is used as an example:

[0164] In the last layer of action sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6] and [7,8], and each qubit pair is acted upon by a target quantum logic gate.

[0165] In the penultimate layer of action sequence, there are two quantum bit pairs, [1,3] and [5,7], and each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0166] In the first layer of action sequence, the target quantum logic gate is applied to quantum bits No. 1 and No. 5.

[0167] For n qubits, first assume that it is an exponential power of 2, that is, n = 2 m , where m is a positive integer. In the last layer of action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1,2], [3,4], [5,6]......[2 m -1,2 m ].

[0168] In the penultimate layer of action sequence, the qubits are reorganized to obtain the following qubit pairs: [1,3], [5,6]......[2 m -3,2 m -1].

[0169] By analogy to the first level of action sequence, only two quantum bits are left to be grouped, and a total of m=logn levels of pairing are required.

[0170] When considering that n quantum bits are not an exponent of 2, the highest-order quantum bits are not grouped in the last layer of action sequence.

[0171] Let's take 7 qubits as an example:

[0172] Reference Fig.11 As shown, in the last layer of action sequence, there are three quantum bit pairs: [1,2], [3,4], [5,6], and the remaining quantum bit No. 7 is not grouped.

[0173] At the second-to-last level, quantum bit No. 7 is included in the grouping range, and there are two quantum bit pairs: [1,3] and [5,7].

[0174] In the first layer of action sequence, the quantum bit pair is [1,5].

[0175] Through the quantum state preparation method provided in the above embodiment, the circuit depth only requires O(logn) layers, thereby realizing a logarithmic preparation scheme for quadratic function quantum states, which can effectively compress the running time of quantum computers.

[0176] Furthermore, the de-entanglement quantum circuit further comprises a second controlled rotating gate acting behind each de-entanglement quantum gate, the control bit of the second controlled rotating gate is the target bit of the first controlled rotating gate, the target bit of the second controlled rotating gate is the control bit of the first controlled rotating gate, and preferably, the second controlled rotating gate is a controlled X gate. Figure 7 For example, the control bits of the first controlled revolving gate are quantum bits 1, 3, 5, and 7, and the target bits are quantum bits 2, 4, 6, and 8, while the control bits of the second controlled revolving gate are quantum bits 2, 4, 6, and 8, and the target bits are quantum bits 1, 3, 5, and 7.

[0177] In the embodiments provided by the present invention, the quantum state to be prepared is firstly considered to be: Then when n is an even number, we can disentangle the quantum logic gates from left to right, and it actually becomes the following quantum state:

[0178]

[0179] Then the controlled X gate is controlled from left to right, so it can be written as follows:

[0180]

[0181] For ease of understanding, the following gives the corresponding situations of 6 bits:

[0182] At 6 bits,

[0183] By acting on bits [1,2], [3,4], [5,6], the disentangled quantum logic gate becomes

[0184] First, assume that the input quantum state is on an even number of quantum bits, but if the basis of the quantum state corresponding to the last bit is 1, then it needs to be multiplied by a coefficient a at the same time. At this time, consider the corresponding parallel lines and consider the quantum state as follows:

[0185]

[0186] The quantum state after the quantum state passes through m parallel de-entanglement quantum logic gates is:

[0187]

[0188] For example:

[0189] Applying the disentangled quantum logic gate on bits [1,2], [3,4], [5,6] and then applying the controlled CX gate, we get

[0190] The right side of the above formula is in the form It can correspond to input of this form, except that m may be an odd number, and only the basis of quantum states on odd bits is considered.

[0191] If the number of quantum bits to be processed is an odd number, then the de-entanglement quantum logic gate and the controlled X gate are first applied to the last bit, and the quantum state is now

[0192]

[0193] becomes:

[0194]

[0195] in Then the format of the first n-1 bits is the same as the format of the first n bits. If n is an odd number, it can be turned into an even number through this method, thereby completing the parallel disentanglement quantum logic gate. Through this method, the final quantum state is a one-hot quantum state. The one-hot quantum state can be encoded in logarithmic depth, so we have completed the corresponding special 2-hot encoding. After passing through the H gate, it can be restored to a quadratic function.

[0196] In fact, it is necessary to perform one-hot transformation encoding of the items. Here, a logarithmic linear function is used to perform LCU combined 2-hot encoding and one-hot encoding at the same time, thus completing the corresponding logarithmic depth preparation process. Since LCU consists of two parts, its success probability is above 0.5.

[0197] Those skilled in the art will know that Figure 8-11 Some of the single gates in can be merged, but in order to fully demonstrate the derivation process of the formula, the merger is not completed here.

[0198] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the drawings. Any changes made according to the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present invention.

Claims

1. A quantum logic gate, characterized in that: It includes a CX gate and a controlled RY gate acting on a preset quantum bit, the action timing of the controlled RY gate is between the action timings of the two CX gates, the target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate.

2. The quantum logic gate according to claim 1, characterized in that The preset quantum bits include a first quantum bit, a second quantum bit, and a third quantum bit, the CX gate includes a first CX gate, a second CX gate, a third CX gate, and a fourth CX gate, the controlled RY gate includes a first controlled RY gate and a second controlled RY gate, the action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, the action timing of the second controlled RY gate is between the action timings of the third CX gate and the fourth CX gate, and the action timing of the third CX gate is after the action timing of the second CX gate, wherein: The target bits of the first CX gate and the second CX gate are both the first quantum bit, and the control bits of the first CX gate and the second CX gate are both the second quantum bit; The target bits of the third CX gate and the fourth CX gate are both the first quantum bit, and the control bits of the third CX gate and the fourth CX gate are both the third quantum bit; The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit; The target bit of the second controlled RY gate is the third quantum bit, and the control bits of the second controlled RY gate are the first quantum bit and the second quantum bit.

3. The quantum logic gate according to claim 2, characterized in that: The parameter value of the first controlled RY gate is expressed as The parameter value of the second controlled RY gate is expressed as 4. The quantum logic gate according to claim 1, characterized in that The preset quantum bit includes a first quantum bit and a second quantum bit, the CX gate includes a first CX gate and a second CX gate, the controlled RY gate includes a first controlled RY gate, and the action timing of the first controlled RY gate is between the action timings of the first CX gate and the second CX gate, wherein: The target bits of the first CX gate and the second CX gate are both the first quantum bit, and the control bits of the first CX gate and the second CX gate are both the second quantum bit; The target bit of the first controlled RY gate is the second quantum bit, and the control bit of the first controlled RY gate is the first quantum bit.

5. The quantum logic gate according to claim 4, characterized in that: The parameter value of the first controlled RY gate is expressed as 6. A method for preparing a quadratic function quantum state, characterized in that: The method comprises: Determining the quantum bits used to prepare the quadratic function quantum state; Construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on a quantum bit, wherein: The first quantum logic gate is the quantum logic gate according to claim 2, each action sequence includes one of the first quantum logic gates, each of the first quantum logic gates acts on three of the quantum bits, and the quantum bits are arranged from the highest-order quantum bit to the lowest-order quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers. Along the action sequence, the first quantum logic gate in the next action sequence acts on a quantum bit with a serial number reduced by one compared to the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order quantum bit. The second quantum logic gate is the quantum logic gate according to claim 4, the action sequence of the second quantum logic gate is located after the action sequence of the plurality of the first quantum logic gates, and the first quantum logic gate acts on the lowest quantum bit and the adjacent quantum bits; The target quantum circuit is run to prepare the quadratic function quantum state.

7. The method for preparing a quadratic function quantum state according to claim 5, characterized in that: The target quantum circuit further comprises an H gate acting on all quantum bits, wherein the H gate is located after the multi-layer action sequence of the first quantum logic gate and the second quantum logic gate on the quantum bits.

8. A quadratic function quantum state preparation device, characterized in that: The device comprises: An acquisition module, used for determining a quantum bit used to prepare a quadratic function quantum state; A target quantum circuit construction module is used to construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on a quantum bit, each action sequence includes one of the first quantum logic gates, each of the first quantum logic gates acts on three of the quantum bits, and the quantum bits are arranged from the highest-order quantum bit to the lowest-order quantum bit. In the initial action sequence, the first quantum logic gate acts on the first three quantum bits with serial numbers, and along the action sequence, the first quantum logic gate in the next action sequence acts on the quantum bit with a serial number reduced by one compared with the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order quantum bit; the action sequence of the second quantum logic gate is located after the action sequences of the first quantum logic gates, and the first quantum logic gate acts on the lowest-order quantum bit and the adjacent quantum bits; An operation module is used to operate the target quantum circuit to prepare the quadratic function quantum state.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to implement the method according to any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the computer program to implement the method according to any one of claims 1 to 7.

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