Chip array positioning method, system and device and medium

Abstract

The invention relates to a chip array positioning method, system and device and a medium, and the method comprises the steps: carrying out the image threshold segmentation of a chip image, and obtaining a threshold image of a chip array region; performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized feature; drawing a circumscribed rectangle of the chip array area on the threshold image, and obtaining a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle; grouping the chips in the chip array area according to the pixel positions and the deflection angles; and according to the grouping information and the pixel positions of the chips and the reference row and column spacing of the chips selected from the threshold image, updating the row and column spacing of the adjacent chips in the chip array area to obtain the array position of each chip. The technical problem that the chip taking requirement of a chip product cannot be met due to the fact that the scanning and taking accuracy is poor in the AOI detection process of the chip is solved.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to a chip array positioning method, system, equipment and medium. Background Art

[0002] AOI, the full name of Automatic Optical Inspection, is a technology that uses optical principles to automatically detect chips. Its working principle is quite simple and efficient: first, the image of the chip to be inspected is collected through high-precision optical equipment; then, these images are compared and analyzed with the pre-set standard chip images; finally, the appearance anomalies that may exist in the chip, such as scratches, contamination, defects, etc., are automatically identified based on the comparison results. The application of AOI technology has greatly improved the efficiency and accuracy of chip detection: First, AOI can complete the inspection of a large number of chips in a very short time, greatly shortening the delivery cycle; second, due to the use of automated and intelligent detection methods, AOI can identify tiny defects that are difficult to detect manually, thereby improving the quality and reliability of the product; third, AOI can also record and analyze the detection data in real time, providing strong support for the optimization and improvement of the production process.

[0003] In AOI inspection, before taking photos of each side of the chip, the chips in the tray need to be picked up and inspected in order. When picking chips from the tray, in order to improve the reliability of picking, the tray needs to be pre-scanned. In addition, since the row and column spacing of chips on the same tray is fixed, it is generally necessary to scan the entire tray according to the preset row and column spacing, and combine the scanning results with the mapping relationship of the map data to obtain the chip picking information of each chip.

[0004] For the pre-scanning and film-taking process in AOI detection, template matching methods or target detection methods are currently used to implement pre-scanning and film-taking of chips. Template matching method is a common technology in the field of image processing. Its main purpose is to find the area that is most similar to a given small image (template image) in a larger image (source image). In the template matching method in the application field of AOI detection, first, a known template is set. The known template is a real image or a minimum repeating unit image without defects in AOI detection; then, the collected chip image located in the tray is overlapped and compared with the known template, and the best matching score and the corresponding angle are calculated to determine the chip position; finally, the known template is translated to the next chip unit in the chip image for the same overlap comparison, until the last chip unit completes the overlap ratio with the known template, and the chip position of the chip image is obtained.

[0005] However, even if the template matching method performs multiple matches, there are still cases where it is difficult to judge, and increasing the number and range of comparisons will greatly reduce the calculation efficiency, and when there are high requirements for chip angle accuracy, it will also increase the calculation burden. Based on target detection to determine the chip position, due to the inherent characteristics of the convolutional neural network, it is insensitive to the size information of the detection target, so the recognition performance of closely arranged targets is poor, and multiple chip targets are easily recognized. In addition, the target detection method based on the rectangular anchor frame cannot accurately identify the contour of the rotating target.

[0006] In addition, the chips may not be arranged neatly, may be tilted as a whole, or may be missing. This may cause the traditional chip spacing scanning method to fail to extract accurate chip information for some chips, and thus fail to meet the chip product's chip picking requirements. Summary of the invention

[0007] 1. Technical issues to be resolved

[0008] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a chip array positioning method, system, device and medium, which solves the technical problem that the chip cannot meet the chip product picking requirements due to poor scanning accuracy during the AOI inspection process.

[0009] (II) Technical solution

[0010] In order to achieve the above object, the main technical solutions adopted by the present invention include:

[0011] In a first aspect, an embodiment of the present invention provides a chip array positioning method, which is applied to a pre-scanning chip picking process in chip AOI detection, and the method includes:

[0012] Performing image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area;

[0013] Performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized features;

[0014] Draw a circumscribed rectangle of the chip array area on the threshold image, and obtain a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle;

[0015] Grouping the chips in the chip array area according to the pixel position and the deflection angle to determine distribution information of each row of chips in the chip array area;

[0016] According to the chip grouping information and pixel positions, and the reference row and column spacing of the chip selected from the threshold image, the row and column spacing of adjacent chips in the chip array area is updated to obtain the array position of each chip.

[0017] Optionally, the quad-core filter includes: a binary segmentation operator filter core, an image corrosion filter core, a closing operation filter core, and an opening operation filter core;

[0018] The binary segmentation operator filter kernel is used to remove background burr interference in the chip image and convert the chip image into a threshold image;

[0019] The image erosion filter kernel is used to widen the interval between chips in the chip image;

[0020] The closing operation filter kernel is used to fill the intervals between the chip arrays to obtain the outer contour of the chip array;

[0021] The open operation filter kernel is used to remove the burr interference of the outer contour of the chip array.

[0022] Optionally, performing image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area includes:

[0023] Acquire a chip image photographed through backlighting, wherein the chips in the chip image are distributed in an array;

[0024] Using the binary segmentation operator filter kernel and the image corrosion filter kernel, the background burr interference of the chip image is eliminated and the interval between chips is widened to obtain a first threshold image;

[0025] The closed operation filter kernel and the open operation filter kernel are used to fill the intervals between chip arrays in the first threshold image to obtain a second threshold image.

[0026] Optionally, performing feature recognition on each chip in the threshold image, and determining a pixel position of the chip in the threshold image according to the recognized features includes:

[0027] Identifying the target area in the threshold image and marking the successfully identified target area;

[0028] Extracting features of the marked target regions to obtain feature points of each marked target region, the feature points including area, center position, rotation angle, and shape factor;

[0029] Based on the feature points, each marked target area is screened to determine that the screened target area is a pixel area of ​​the chip;

[0030] The center position of each screened target area is determined as the pixel position of the corresponding chip.

[0031] Optionally, drawing a circumscribed rectangle of the chip array area on the threshold image, and acquiring a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle includes:

[0032] The deflection angle of the chip array area is obtained according to the following formula (1);

[0033]

[0034] (1) In the formula, Angle chips represents the deflection angle of the chip array area, and θ represents the rotation angle of the circumscribed rectangle of the chip array area.

[0035] Optionally, grouping the chips in the chip array area according to the pixel position and the deflection angle to determine the distribution information of each row of chips in the chip array area includes:

[0036] Establishing a plane coordinate system with the corner point of the threshold image as the origin;

[0037] After correcting the direction of the chip array area according to the deflection angle, obtaining the coordinates of each chip in the plane coordinate system according to the pixel position of each chip;

[0038] The chips in the chip array area are grouped according to the coordinate information of each chip to determine the distribution information of each row of chips in the chip array area.

[0039] Optionally, updating the row and column spacings of adjacent chips in the chip array region according to the chip grouping information and pixel positions, and the reference row and column spacings of the chips selected from the threshold image, and obtaining the array position of each chip includes:

[0040] The row and column spacing of adjacent chips in the chip array area is updated according to the following formula (2);

[0041]

[0042] (2) In the formula, DX n Represents the row spacing between adjacent chips after the nth iteration. When n=1, DX n-1 Represents the chip's baseline row spacing, DY n represents the column spacing between adjacent chips after the nth iteration. When n=1, DY n-1 represents the reference column spacing of the chip, α represents the weight coefficient, x represents the row number of the chip, y represents the column number of the chip, and c (x,y) Represents the pixel position of the chip at row x and column y.

[0043] In a second aspect, an embodiment of the present invention provides a chip array positioning system, which includes:

[0044] An image preprocessing module is used to perform image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area;

[0045] A chip pixel position acquisition module, used to perform feature recognition on each chip in the threshold image, and determine the pixel position of the chip in the threshold image according to the recognized features;

[0046] A deflection angle acquisition module, used for drawing a circumscribed rectangle of a chip array area on the threshold image, and acquiring a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle;

[0047] A chip grouping module, used for grouping the chips in the chip array area according to the pixel position and the deflection angle, so as to determine the distribution information of each row of chips in the chip array area;

[0048] The chip array position acquisition module is used to update the row and column spacing of adjacent chips in the chip array area according to the chip grouping information and pixel position and the reference row and column spacing of the chip selected from the threshold image to obtain the array position of each chip.

[0049] In a third aspect, an embodiment of the present invention provides an electronic device, comprising:

[0050] processor;

[0051] A memory stores steps of a positioning method for the processor to control the chip array described above.

[0052] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium having computer-executable instructions stored thereon, and when the executable instructions are executed by a processor, the above-mentioned steps of a chip array positioning method are implemented.

[0053] (III) Beneficial effects

[0054] The present invention proposes a chip array positioning method, which uses the position information of each chip to update the row and column spacing of adjacent chips in real time, thereby completing the technical solution of accurate positioning scanning of each chip in the chip array. Compared with the prior art, it has the following specific advantages.

[0055] Beneficial effects:

[0056] Firstly, the present invention completes the chip pre-scanning work by directly acquiring the position of each chip in the array area, so that each chip does not need to be compared with the template image, thereby improving the accuracy of chip pre-scanning.

[0057] Secondly, the present invention directly selects the row-column spacing from the threshold image as the reference row-column spacing to update the row-column spacing of adjacent chips, thereby avoiding manual misjudgment and input of erroneous data.

[0058] Furthermore, the present invention updates the row and column spacing between adjacent chips in real time according to the actual position of the chips, thereby avoiding the cumulative error that may be generated by fixing the input row and column spacing.

[0059] Finally, the present invention groups all the chips in the chip image to determine the distribution information of each row of chips, so that the chip fetching information can be correctly extracted when the chips are not arranged neatly. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of a flow chart of a chip array positioning method provided by one embodiment of the present invention;

[0061] Figure 2 A schematic diagram of an algorithm flow of a chip array positioning method provided by one embodiment of the present invention;

[0062] Figure 3 A chip image having 9 chip array regions provided by an embodiment of the present invention;

[0063] Figure 4 An embodiment of the present invention provides Figure 3 A first threshold map of the chip image shown;

[0064] Figure 5 An embodiment of the present invention provides Figure 3 A second threshold map of the chip image shown;

[0065] Figure 6 An embodiment of the present invention provides Figure 3 Schematic diagram of the effect of chip array encoding in the middle chip;

[0066] Figure 7 An embodiment of the present invention provides Figure 6 A partial schematic diagram of

[0067] Figure 8 A chip image having one chip array area provided by an embodiment of the present invention;

[0068] Fig. 9 An embodiment of the present invention provides Figure 8 A first threshold map of the chip image shown;

[0069] Fig.10 An embodiment of the present invention provides Figure 8 A second threshold map of the chip image shown;

[0070] Fig.11 An embodiment of the present invention provides a pair Figure 8 Schematic diagram of the effect of chip array encoding on the chip. DETAILED DESCRIPTION

[0071] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0072] refer to Figure 1-2 As shown, a chip array positioning method, system, device and medium proposed in an embodiment of the present invention are applied to the pre-scanning and film-taking process in chip AOI detection, which includes: S1, performing image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area; S2, performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized features; S3, drawing a circumscribed rectangle of the chip array area on the threshold image, and obtaining the deflection angle of the chip array area based on the rotation angle of the circumscribed rectangle; S4, grouping the chips in the chip array area according to the pixel position and the deflection angle to determine the distribution information of each row of chips in the chip array area; S5, updating the row and column spacing of adjacent chips in the chip array area according to the grouping information and pixel position of the chip, and the reference row and column spacing of the chip selected from the threshold image to obtain the array position of each chip.

[0073] This embodiment uses a technical solution that updates the row and column spacing of adjacent chips in real time based on the position information of each chip, thereby completing the precise positioning and scanning of each chip in the chip array. Compared with the prior art, it has the following specific beneficial effects:

[0074] First, this embodiment completes the chip pre-scanning by directly acquiring the position of each chip in the array area, so that each chip does not need to be compared with the template image, thereby improving the accuracy of chip pre-scanning.

[0075] Secondly, this embodiment directly selects the row-column spacing from the threshold image as the reference row-column spacing to update the row-column spacing of adjacent chips, thereby avoiding manual misjudgment and input of erroneous data.

[0076] Furthermore, this embodiment updates the row and column spacing between adjacent chips in real time according to the actual position of the chips, thereby avoiding the cumulative error that may be caused by fixing the input row and column spacing.

[0077] Finally, this embodiment groups all the chips in the chip image to determine the distribution information of each row of chips, so that the chip fetching information can be correctly extracted when the chips are not arranged neatly.

[0078] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0079] Specifically, refer to Figure 1 As shown, an embodiment of the present invention provides a positioning method for a chip array, which is applied to the pre-scanning and chip picking process in chip AOI detection. The method is used to accurately position the chips in rows and columns in sequence to meet the pre-scanning and chip picking requirements. The method may include the following steps:

[0080] S1. Perform image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area.

[0081] Under backlight shooting conditions, the chip image of the chip in the tray is obtained through the camera. The chip image is as follows Figure 3 and Figure 8 As shown, Figure 3 For chip images with 9 chip array areas, Figure 8 The chip image has one chip array area. Then, the chip image is segmented by threshold using an improved quad-core filter to remove the image background burr interference, thereby reducing the effect of adhesion between chips and further determining the chip array area.

[0082] In this embodiment, the quad-core filter may include: a binary segmentation operator filter core, an image corrosion filter core, a closing operation filter core, and an opening operation filter core; the binary segmentation operator filter core is used to remove background burr interference in the chip image and convert the chip image into a threshold image; the image corrosion filter core is used to widen the interval between chips in the chip image; the closing operation filter core is used to fill the interval between the chip arrays to obtain the outer contour of the chip array; the opening operation filter core is used to remove burr interference from the outer contour of the chip array. When all four filter cores in the quad-core filter are enabled, the quad-core filter has the following working scenarios:

[0083] (1) Using a binary segmentation operator filter kernel and an image corrosion filter kernel, the background burr interference in the initial chip image is eliminated and the interval between chips in the initial chip image is widened to obtain a first threshold image capable of determining chip position information. The mathematical expression of this process is as follows:

[0084] I1=B*(A*I)

[0085] Among them, I represents the initial chip image, I1 represents the first threshold image, A represents the binary segmentation operator filter kernel, and B represents the image corrosion filter kernel.

[0086] (2) Using a closed operation filter kernel and an open operation filter kernel, fill the gaps between the chip arrays in the first threshold image to obtain the outer contour of the chip array, and after removing the burr interference of the outer contour of the chip array, obtain a second threshold image that can determine the chip array position and chip array angle. The mathematical expression of this process is as follows:

[0087] I2=D*(C*I1)

[0088] Wherein, I2 represents the second threshold image, C represents the closed operation filter kernel, and D represents the open operation filter kernel.

[0089] (3) According to the binary segmentation operator filter kernel, the chip area and the background area are threshold segmented. The mathematical expression of this process is as follows:

[0090]

[0091] Among them, I (a,b) represents the gray value of the pixel at the coordinate (a, b) in the initial chip image, and thr represents the segmentation threshold.

[0092] Furthermore, in this embodiment, step S1 may include the following sub-steps S11 to S13:

[0093] S11, acquiring a chip image photographed through backlighting, wherein the chips in the chip image are distributed in an array.

[0094] S12, using the binary segmentation operator filter kernel and the image corrosion filter kernel to eliminate background burr interference of the chip image and widen the interval between chips to obtain a first threshold image;

[0095] S13. Use the closing operation filter kernel and the opening operation filter kernel to fill the intervals between chip arrays in the first threshold image to obtain a second threshold image.

[0096] In a specific implementation, Figure 3The chip image in the image is subjected to image threshold segmentation. First, a binary segmentation operator filter kernel and an image corrosion filter kernel are used to eliminate the background burr interference in the initial chip image and widen the interval between the chips in the initial chip image to obtain a first threshold image. The first threshold image is shown in FIG. Figure 4 Next, a closed operation filter kernel is used to fill the gaps between the chip arrays in the first threshold image to obtain the outer contour of the chip array. Finally, an open operation filter kernel is used to remove the burr interference of the outer contour of the chip array to obtain the second threshold image. The second threshold image is shown in Figure 5 shown.

[0097] S2. Perform feature recognition on each chip in the threshold image, and determine the pixel position of the chip in the threshold image according to the recognized features.

[0098] In this embodiment, step S2 may include the following sub-steps S21 to S24:

[0099] S21, identifying the target area in the threshold image, and marking the successfully identified target area.

[0100] S22, extracting features from the marked target areas to obtain feature points of each marked target area, the feature points including area, center position, perimeter and shape factor.

[0101] S23. Based on the feature points, each marked target area is screened, and the screened target area is determined to be a pixel area of ​​the chip.

[0102] S24, determining the center position of each screened target area as the pixel position of the corresponding chip.

[0103] In a specific embodiment, a Blob (Binary Large OBject) detection method is used to obtain the pixel position of the chip in the threshold image. The specific process is as follows:

[0104] (1) In the first threshold image (such as Figure 4 ), use the contour extraction algorithm to identify all target areas, the target area is composed of continuous black pixels, and the target area is recorded as Blob.

[0105] (2) Calculate the features of each Blob, such as area, center position, rotation angle, and shape factor.

[0106] (3) According to the preset threshold (including area range and shape convexity range, etc.), the detected blobs are screened and the blobs that meet the threshold conditions are marked as pixel areas of the chip.

[0107] (4) The center position of the marked Blob is determined as the pixel position of the chip to which it belongs, and the pixel position of the chip is recorded in the form of coordinates.

[0108] S3. Draw a circumscribed rectangle of the chip array area on the threshold image, and obtain a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle.

[0109] In this embodiment, in the second threshold image (such as Figure 5 ) is drawn on the chip array area. After determining the direction of the circumscribed rectangle (generally clockwise is the positive direction), the deflection angle of the chip array area can be directly obtained based on the rotation angle of the circumscribed rectangle and combined with the following formula (1).

[0110]

[0111] (1) In the formula, Angle chips represents the deflection angle of the chip array area, and θ represents the rotation angle of the circumscribed rectangle of the chip array area.

[0112] It is worth mentioning that the positive and negative values ​​of the deflection angle of the chip array area are determined by the rotation direction of the circumscribed rectangle. When the rotation direction of the circumscribed rectangle is clockwise, the value of the deflection angle is positive, and when the rotation direction of the circumscribed rectangle is counterclockwise, the value of the deflection angle is negative.

[0113] S4. Group the chips in the chip array area according to the pixel positions and the deflection angles to determine the distribution information of each row of chips in the chip array area.

[0114] For example, step S4 may include the following steps S41 to S43:

[0115] S41. Establish a plane coordinate system with the corner point of the threshold image as the origin.

[0116] S42, after correcting the direction of the chip array area according to the deflection angle, obtain the coordinates of each chip in the plane coordinate system according to the pixel position of each chip.

[0117] S43. Group the chips in the chip array area according to the coordinate information of each chip to determine the distribution information of each row of chips in the chip array area.

[0118] For example, when grouping the chips in the chip array area according to the coordinate information in the coordinates of each chip, first, select the coordinates of a chip from each row of chips as the reference coordinates, and then, based on the reference coordinates of each row, set a number of continuous row coordinate deviation ranges. Finally, by determining the row coordinate deviation range where the row coordinates of each chip are located, the chip grouping work is completed to obtain the distribution information of each row of chips in the chip array area. This embodiment groups all the chips in the chip image to determine the distribution information of each row of chips (such as the number of chips and the chip position information), so that the chip fetching information of all chips can be correctly extracted when the chip is not neatly arranged.

[0119] S5. Update the row and column spacing of adjacent chips in the chip array area according to the chip grouping information and pixel position, and the reference row and column spacing of the chip selected from the threshold image, to obtain the array position of each chip.

[0120] In this embodiment, the specific process of selecting the reference row and column spacing of the chip from the threshold image is as follows: first, three adjacent chips without missing chips are selected from the threshold image, and are recorded as c0, c1 and c2 respectively. In the chip array area, c0 and c1 are adjacent to each other vertically, and c0 and c2 are adjacent to each other horizontally. Then, the spacing between c0 and c1 is obtained as the reference row spacing, and the spacing between c0 and c2 is obtained as the reference column spacing.

[0121] In this embodiment, the row and column spacing of adjacent chips in the chip array area is updated according to the following formula (2). In addition, when a chip is missing, the position point is marked as a missing chip; when a chip position is offset, the chip row and column spacing is updated in real time based on the actual position of the chip obtained.

[0122]

[0123] (2) In the formula, DX n Represents the row spacing between adjacent chips after the nth iteration. When n=1, DX n-1 Represents the chip's baseline row spacing, DY n represents the column spacing between adjacent chips after the nth iteration. When n=1, DY n-1 represents the reference column spacing of the chip, α represents the weight coefficient, x represents the row number of the chip, y represents the column number of the chip, and c (x,y) Represents the pixel position of the chip at row x and column y.

[0124] In a specific embodiment, Figure 3 When performing pre-scanning of the array-distributed chip image shown in the figure, first, all filtering checks are performed using the quad-core filter. Figure 3The chip image shown in the figure is subjected to image threshold segmentation to obtain the first threshold image of the chip array area ( Figure 4 ) and the second threshold image ( Figure 5 ). Secondly, each chip is identified in the first threshold image to obtain the pixel position of each chip, and the deflection angle of each chip array area is determined in the second threshold image; then, the chips are grouped based on the deflection angle of the chip array area and the pixel position of the chip; finally, based on the chip grouping information, pixel position and reference row and column spacing, the row and column spacing of adjacent chips is updated to obtain the array position of each chip, and the final result is displayed as follows Figure 6 In this embodiment, Figure 6 In the last chip array area, the positions of two chips in the last row are offset, but they can be correctly identified in the end. For the case where there is a missing chip in the middle position, only the corresponding row and column number is performed at this position, and no color mark is performed to identify the chip at this position, such as Figure 7 As shown. And, reference Figures 3 to 7 As shown, it can be seen that the spacing between adjacent chips is small. This embodiment detects the center position of each chip to represent the position of the chip in the image, and then obtains the spacing between adjacent chips through the position, so as to accurately complete the array positioning of each chip and reduce the risk of identifying multiple chips as one target chip.

[0125] In another specific embodiment, Figure 8 When performing pre-scanning of the array-distributed chip image shown in the figure, first, a binary segmentation operator of a quad-core filter is used for filtering and checking. Figure 5 The chip image shown in the figure is subjected to image threshold segmentation to obtain the first threshold image of the chip array area ( Fig. 9 ) and the second threshold image ( Fig.10 ). Secondly, each chip is identified in the first threshold image to obtain the pixel position of each chip, and the deflection angle of each chip array area is determined in the second threshold image; then, the chips are grouped based on the deflection angle of the chip array area and the pixel position of the chip; finally, based on the chip grouping information, pixel position and reference row and column spacing, the row and column spacing of adjacent chips is updated to obtain the array position of each chip, and the final result is displayed as follows Fig.11 In this embodiment, the chips in row 5, column 14, row 6, column 14 and row 10 are greatly offset, and there is a missing chip in the last row. Not only the position of each chip is accurately identified and located, the row and column number coding is completed, but also the positions where there are chips are marked with green dots, and the positions where there are no chips are marked with red dots, completing the accurate scanning and positioning of the chips.

[0126] In addition, this embodiment also provides a chip array positioning system, which includes:

[0127] The image preprocessing module is used to perform image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain the threshold image of the chip array area.

[0128] The chip pixel position acquisition module is used to perform feature recognition on each chip in the threshold image and determine the pixel position of the chip in the threshold image according to the recognized features.

[0129] The deflection angle acquisition module is used to draw a circumscribed rectangle of the chip array area on the threshold image, and acquire the deflection angle of the chip array area based on the rotation angle of the circumscribed rectangle.

[0130] The chip grouping module is used to group the chips in the chip array area according to the pixel position and the deflection angle to determine the distribution information of each row of chips in the chip array area.

[0131] The chip array position acquisition module is used to update the row and column spacing of adjacent chips in the chip array area according to the chip grouping information and pixel position, and the reference row and column spacing of the chip selected from the threshold image, to obtain the array position of each chip.

[0132] In addition, this embodiment further proposes an electronic device, including: a processor; and a memory storing steps of a positioning method for a chip array controlled by the processor.

[0133] It is important to understand that the processor, as the core component of the electronic device, undertakes key tasks such as data processing and instruction execution. Its powerful computing power and efficient processing speed provide a strong guarantee for the overall performance of the device. The memory plays an important role in data storage. In electronic devices, the memory not only has large-capacity and high-speed storage characteristics, but more importantly, it is specifically used to store the positioning method steps of a specific chip array. These method steps are precisely controlled by the processor to achieve precise positioning of each chip in the chip array. This design not only improves the data processing efficiency of the device, but also enhances its adaptability and stability in complex application scenarios.

[0134] Therefore, the electronic device proposed in this embodiment achieves efficient control and precise execution of the steps of the chip array positioning method through the close cooperation between the processor and the memory, further enhancing the overall performance and stability of the device.

[0135] Finally, this embodiment also provides a computer-readable medium. This medium stores specific computer executable instructions, which, when executed by the processor, can implement the steps of a chip array positioning method described previously. This computer-readable medium not only provides a convenient and efficient solution for the positioning of the chip array, but also ensures the accuracy and reliability of the positioning process through the executable instructions stored therein. In short, the combination of this computer-readable medium and the processor brings unprecedented convenience and accuracy to the chip array positioning, and further promotes the development and application of related technologies.

[0136] Specifically, in the pre-scanning chip picking process in chip detection, accurate positioning of the chip array is crucial. The computer-readable medium stores executable instructions for implementing the chip array positioning method. When these instructions are executed by the processor, it can ensure that the chip array can be accurately picked up. This improves the efficiency of picking up chips during chip detection, thereby improving the accuracy of chip detection.

[0137] In the automated chip detection pipeline, the computer-readable medium can be used as a key link and integrated with other equipment on the pipeline. By executing the instructions stored on the medium, the processor can control the robotic arms, sensors and other equipment on the pipeline to achieve automatic positioning and identification of the chip array in the tray, thereby improving the intelligence level and detection efficiency of the chip detection pipeline.

[0138] In summary, the present invention proposes a positioning method, system, device and medium for a chip array, and the method is applied to the pre-scanning film-taking process in chip AOI detection. The method comprises: first, performing image threshold segmentation on the chip image to obtain a threshold image of the chip array area. Secondly, performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized features. Next, drawing a circumscribed rectangle of the chip array area on the threshold image, and obtaining the deflection angle of the chip array area based on the rotation angle of the circumscribed rectangle. Then, the chips in the chip array area are grouped according to the pixel position and the deflection angle. Finally, according to the grouping information and pixel position of the chip, and the reference row and column spacing of the chip selected from the threshold image, the row and column spacing of adjacent chips in the chip array area is updated to obtain the array position of each chip. The present invention updates and locates the spacing between adjacent chips in real time through the position information of each chip in the array area, thereby completing the pre-scanning of the chip, which improves the accuracy of chip pre-scanning film-taking. At the same time, the present invention further improves the accuracy of chip pre-scanning film-taking by setting a reference row and column spacing and grouping all chips.

[0139] Since the system / device described in the above embodiments of the present invention is a system / device used to implement the method of the above embodiments of the present invention, a person skilled in the art can understand the specific structure and deformation of the system / device based on the method described in the above embodiments of the present invention, and thus will not be described in detail here. All systems / devices used in the method of the above embodiments of the present invention belong to the scope of protection of the present invention.

[0140] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0141] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram and the combination of the processes and / or boxes in the flowchart and / or block diagram can be implemented by computer program instructions.

[0142] It should be noted that in the claims, any reference numerals placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In the claims enumerating several means, several of these means may be embodied by the same hardware. The use of the words first, second, third, etc., is for convenience of expression only and does not indicate any order. These words may be understood as part of the component name.

[0143] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0144] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments after knowing the basic creative concept. Therefore, the claims should be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0145] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention should also include these modifications and variations.

Claims

1. A chip array positioning method, characterized in that: The method is applied to the pre-scanning and chip picking process in chip AOI detection, and the method comprises: Performing image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area; Performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized features; Draw a circumscribed rectangle of the chip array area on the threshold image, and obtain a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle; Grouping the chips in the chip array area according to the pixel position and the deflection angle to determine distribution information of each row of chips in the chip array area; According to the chip grouping information and pixel positions, and the reference row and column spacing of the chip selected from the threshold image, the row and column spacing of adjacent chips in the chip array area is updated to obtain the array position of each chip.

2. The method according to claim 1, characterized in that The quad-core filter includes: a binary segmentation operator filter core, an image corrosion filter core, a closing operation filter core, and an opening operation filter core; The binary segmentation operator filter kernel is used to remove background burr interference in the chip image and convert the chip image into a threshold image; The image erosion filter kernel is used to widen the interval between chips in the chip image; The closing operation filter kernel is used to fill the intervals between the chip arrays to obtain the outer contour of the chip array; The open operation filter kernel is used to remove the burr interference of the outer contour of the chip array.

3. The method according to claim 2, characterized in that The acquired chip image is subjected to image threshold segmentation according to the improved quad-core filter, and the threshold image of the chip array area is obtained, including: Acquire a chip image photographed through backlighting, wherein the chips in the chip image are distributed in an array; Using the binary segmentation operator filter kernel and the image corrosion filter kernel, the background burr interference of the chip image is eliminated and the interval between chips is widened to obtain a first threshold image; The closed operation filter kernel and the open operation filter kernel are used to fill the intervals between chip arrays in the first threshold image to obtain a second threshold image.

4. The method according to claim 1, characterized in that Performing feature recognition on each chip in the threshold image, and determining the pixel position of the chip in the threshold image according to the recognized features includes: Identifying the target area in the threshold image and marking the successfully identified target area; Extracting features of the marked target regions to obtain feature points of each marked target region, the feature points including area, center position, rotation angle, and shape factor; Based on the feature points, each marked target area is screened to determine that the screened target area is a pixel area of ​​the chip; The center position of each screened target area is determined as the pixel position of the corresponding chip.

5. The method according to claim 1, characterized in that Drawing a circumscribed rectangle of the chip array area on the threshold image, and acquiring a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle includes: The deflection angle of the chip array area is obtained according to the following formula (1); (1) In the formula, Angle chips represents the deflection angle of the chip array area, and θ represents the rotation angle of the circumscribed rectangle of the chip array area.

6. The method according to claim 1, characterized in that The chips in the chip array area are grouped according to the pixel position and the deflection angle to determine the distribution information of each row of chips in the chip array area, including: Establishing a plane coordinate system with the corner point of the threshold image as the origin; After correcting the direction of the chip array area according to the deflection angle, obtaining the coordinates of each chip in the plane coordinate system according to the pixel position of each chip; The chips in the chip array area are grouped according to the coordinate information of each chip to determine the distribution information of each row of chips in the chip array area.

7. The method according to claim 1, characterized in that According to the chip grouping information and pixel position, and the reference row and column spacing of the chip selected from the threshold image, the row and column spacing of adjacent chips in the chip array area is updated to obtain the array position of each chip, including: The row and column spacing of adjacent chips in the chip array area is updated according to the following formula (2); (2) In the formula, DX n Represents the row spacing between adjacent chips after the nth iteration. When n=1, DX n-1 Represents the chip's baseline row spacing, DY n represents the column spacing between adjacent chips after the nth iteration. When n=1, DY n-1 represents the reference column spacing of the chip, α represents the weight coefficient, x represents the row number of the chip, y represents the column number of the chip, and c (x,y) Represents the pixel position of the chip at row x and column y.

8. A chip array positioning system, characterized in that: include: An image preprocessing module is used to perform image threshold segmentation on the acquired chip image according to the improved quad-core filter to obtain a threshold image of the chip array area; A chip pixel position acquisition module, used to perform feature recognition on each chip in the threshold image, and determine the pixel position of the chip in the threshold image according to the recognized features; A deflection angle acquisition module, used for drawing a circumscribed rectangle of the chip array area on the threshold image, and acquiring a deflection angle of the chip array area based on a rotation angle of the circumscribed rectangle; A chip grouping module, used for grouping the chips in the chip array area according to the pixel position and the deflection angle, so as to determine the distribution information of each row of chips in the chip array area; The chip array position acquisition module is used to update the row and column spacing of adjacent chips in the chip array area according to the chip grouping information and pixel position and the reference row and column spacing of the chip selected from the threshold image to obtain the array position of each chip.

9. An electronic device, characterized in that: include: processor; A memory storing steps of a positioning method for a chip array as described in any one of claims 1 to 7, which is used by the processor to control the positioning method.

10. A computer-readable medium having computer-executable instructions stored thereon, characterized in that: When the executable instructions are executed by the processor, the steps of a chip array positioning method as described in any one of claims 1 to 7 are implemented.

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