Three-dimensional NOR memory device for multiply-accumulate operation

Abstract

Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells are described. In one method, a memory cell array has memory cells vertically stacked over a semiconductor substrate. Each memory cell stores a weight. A local digital line is connected to a terminal of the memory cell. The local number lines extend vertically over the substrate. A select transistor is connected to the local digital line. A select line controls the select transistor and is used to encode an input mode to multiply by the stored weight. Accumulation circuitry sums the output currents from the memory cells. In one example, each memory cell is formed using a transistor including a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) surrounds a circumference of the semiconductor layer. A word line applies a gate voltage to the transistor. Each word line has a respective portion surrounding a circumference of the gate layer of each transistor.

Description

[0001] Related Applications

[0002] This application claims priority to and the benefit of Provisional U.S. Patent Application No. 63 / 514,495, filed on July 19, 2023, the entirety of which is hereby incorporated by reference into this disclosure. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory devices and more particularly, but not limited to, memory devices having a three dimensional array of memory cells in a NOR configuration for performing multiplication and other operations. Background Art

[0004] Limited memory bandwidth is a significant problem in machine learning systems. For example, DRAM devices used in current systems store the large number of weights and activations used in deep neural networks (DNNs).

[0005] In one example, a deep learning machine (e.g., those supporting processing for convolutional neural networks (CNNs)) performs processing to determine a large number of calculations per second. For example, input / output data, deep learning network training parameters, and intermediate results are constantly extracted from and stored in one or more memory devices (e.g., DRAM). When large storage density (e.g., storage density greater than 100MB) is involved, DRAM-type memory is generally used due to its cost advantage. In one example of a deep learning hardware system, a computing unit (e.g., a system on a chip (SOC), FPGA, CPU, or GPU) is attached to (several) memory devices (e.g., DRAM devices).

[0006] Existing computer architectures use processor chips dedicated to serial processing and DRAM optimized for high-density memory. The interface between these two devices is a major bottleneck, introducing latency and bandwidth limitations and adding considerable power consumption overhead. On-chip memory is area expensive and it is not possible to add large amounts of memory to the CPU and GPU processors currently used to train and deploy DNNs.

[0007] Memory in a neural network is used to store input data, weight parameters, and activations as the inputs propagate through the network. During training, activations from the forward path must be retained until they can be used to calculate error gradients in the reverse path. As an example, a network may have 26 million weight parameters and calculate 16 million activations in the forward path. If 32-bit floating point values ​​are used to store each weight and activation, this corresponds to a total storage requirement of 168MB.

[0008] GPUs and other machines require significant memory for the weights and activations of neural networks. GPUs cannot directly perform the small convolutions used in deep neural networks efficiently, so they require significant activation or weight storage. Finally, memory is also needed to store input data, temporary values, and program instructions. For example, a high-performance GPU may require more than 7GB of local DRAM.

[0009] It is not possible to keep large amounts of storage data on a GPU processor. In many cases, a high-performance GPU processor may have only 1KB of memory associated with each of the processor cores that can be read fast enough to saturate the floating point data path. Therefore, at each layer of the DNN, the GPU needs to save the state to external DRAM, load the next layer of the network, and then reload the data. As a result, the off-chip memory interface suffers from the burden of constantly reloading weights and saving and retrieving activations. This significantly reduces training time and increases power consumption.

[0010] In one example, image and other sensors are used and generate large amounts of data. In some applications, it is inefficient to transfer certain types of data from the sensors to a general purpose microprocessor (e.g., a central processing unit (CPU)) for processing. For example, it is inefficient to transfer image data from an image sensor to a microprocessor for image segmentation, object recognition, feature extraction, etc.

[0011] Some image processing may include intensive computations involving multiplication of columns or matrices of elements for accumulation. Some specialized circuits have been developed to accelerate multiplication and accumulation operations. For example, a multiplier-accumulator (MAC unit) may be implemented using a set of parallel computational logic circuits to achieve higher computational performance than a general-purpose microprocessor. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which reference characters indicate similar elements.

[0013] Figure 1 An integrated circuit device having an array of image sensing pixels, an array of memory cells with tiles, and circuits to perform inference calculations according to one embodiment is shown.

[0014] Figure 2 A computation is shown that multiplies a column of weight bits by a column of input bits to provide an accumulated result, according to one embodiment.

[0015] Figure 3 A method of calculation in an integrated circuit device based on summing output currents from memory cells according to one embodiment is presented.

[0016] Figure 4An analog weight-fixed architecture for matrix-vector multiplication (MVM) is presented according to one embodiment.

[0017] Figure 5 A three dimensional memory cell array having floating gate memory cells in a NOR configuration is shown according to one embodiment.

[0018] Figure 6 An architecture with resistive random access memory (RRAM) or NOR memory cells arranged in a parallel configuration for performing multiplication is shown according to one embodiment.

[0019] Figure 7 Memory cells are shown arranged in parallel with current terminals connected to a common global digit line through select transistors according to one embodiment.

[0020] Figure 8 Yes Fig. 9 0026] A cross-sectional view (indicated by "XX") taken as illustrated in FIG. 1 and showing a memory device having NOR flash memory cells stacked vertically in pillars above a semiconductor substrate (not shown) according to one embodiment.

[0021] Fig. 9 A device is shown having multiple pillars of memory cells electrically isolated by one or more dielectric materials according to one embodiment. Figure 8 A top view of a memory device.

[0022] Fig.10 Example matrices of memory cells are shown according to one embodiment, with each matrix having multiple tiles and each tile having multiple pillars.

[0023] Fig.11 Demonstrating an embodiment Fig.10 A top view of a tile in an example matrix of FIG.

[0024] Fig.12 A memory device having global digit lines connecting memory cells of different tiles in an array of memory cells to accumulation circuitry is shown according to one embodiment.

[0025] Fig.13 Demonstrating an embodiment Fig.12 A top view of a memory device.

[0026] Fig.14 is a top view of a memory device according to one embodiment, the memory device having Fig. 9 A similar structure, except that each of the memory cells in each pillar has one of its two current terminals connected to a common local digit line (LDL').

[0027] Fig.15 is a cross-sectional view of a memory device according to one embodiment, the memory device having Figure 8 A similar structure except that a portion of the memory cells in the pillars have their word lines electrically shorted together so the memory cells turn on and off as a unit.

[0028] Figures 16 to 18 Example structures for configuring local digit lines and memory cells of a memory device are shown (using simplified block form for purposes of illustration only) according to various embodiments.

[0029] Fig.19 A global digit line is shown that sums the output currents from selected memory cells of a tile in a memory array according to one embodiment.

[0030] Figures 20 to 21 Demonstrating various embodiments Fig.19 A top view of the memory array.

[0031] Fig. 22 A method for performing multiplication using memory cells located in selected portions of one or more tiles is shown according to one embodiment. DETAILED DESCRIPTION

[0032] The following disclosure describes various embodiments of a three-dimensional array of memory cells in a NOR configuration that is used to perform multiplication and other operations in a memory device. The memory device may, for example, store data used by a host device (e.g., a computing device of an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0033] In one example, selected memory cell tiles are dynamically configured as computations for a neural network progress (e.g., moving from one layer to another). For example, these computations include matrix-vector multiplications (MVMs) for each layer of the neural network. The weights of the neural network are stored in a memory cell array and multiplications using the weights are performed in the memory cell array itself based on output currents from memory cells in the array. The output currents are digitized and used by a controller to support MVMs.

[0034] Improved power efficiency is particularly desirable for use of neural networks on mobile devices and automobiles. Storing the weights of the neural network in a memory device and performing multiplications in the memory device avoids or reduces the need to move the weights to a central processing unit or other processing device. This reduces the power consumption required to move data to and from memory and also reduces the memory bandwidth issues described herein.

[0035] Various memory device structures can be used to form memory cell arrays. For example, several hardware accelerators based on in-memory computing can use SRAM, RRAM, or NAND flash memory. However, even with these example accelerators, energy efficiency (power) is still the main bottleneck for inference applications. In addition, planar NOR-based solutions exhibit lower density.

[0036] More generally, neural networks are one of the most popular classes of machine learning algorithms (e.g., modeled after our understanding of how the brain works). For example, a network has a large number of neurons that independently perform fairly simple calculations but together can learn complex and nonlinear functions. For example, a neuron calculation is basically a number of input values ​​multiplied by a neuron weight (which represents the importance of each input to the calculation) and the results are summed. The weights are learned during network training. Each result is then passed through a nonlinear activation function to allow the neuron to learn complex relationships.

[0037] In terms of computational burden, multiplying all input values ​​by the neuron weights of all neurons in the network is the most demanding use of processing power. For example, depending on the network design, this multiplication may account for 90% or more of the computational requirements. When scaling to a full layer of a neural network, the calculation is vectorized and becomes a matrix-vector multiplication problem. The calculation is sometimes also called a dot product or sum of products (SOP) calculation.

[0038] Deep learning technology is an example implementation of neural networks and plays an important role in a variety of applications such as image classification, object detection, speech recognition, natural language processing, recommendation systems, automatic generation and robotics, etc. Many domain-specific deep learning accelerators (DLAs) such as GPUs, TPUs, and embedded NPUs have been introduced to provide the required efficient implementation of deep neural networks (DNNs) from the cloud to the edge. However, due to the frequent data back and forth movement between the computing unit and the memory in deep learning, limited memory bandwidth remains a key challenge, especially for energy-constrained systems and applications such as edge AI.

[0039] Conventional Von-Neumann computer architectures have been developed with processor chips dedicated to serial processing and DRAM optimized for high-density memory. The interface between these two devices is a major bottleneck that introduces latency and bandwidth limitations and adds considerable power consumption overhead. As the demand for higher accuracy and higher speed in AI applications continues to grow, larger DNN models are developed and implemented using a large number of weights and activations. The resulting bottlenecks in memory bandwidth and power consumption for data movement between chips are significant technical issues.

[0040] As time goes by, the complexity of neural networks continues to grow exponentially, which means that much more computation is required. This makes the performance of traditional computing architectures inadequate. For example, MVM operations require specially built computing blocks to meet the performance requirements (GPUs, digital accelerators). Moreover, neuron weights must be fetched from memory, which both causes performance bottlenecks and is energy inefficient, as mentioned above.

[0041] In some cases, the precision of the computations can be reduced to address these issues. For example, the choice of neural network training type can achieve approximately equivalent neural network accuracy with significantly lower precision. The lower precision can improve the performance and / or energy efficiency of the neural network implementation. Moreover, using lower precision can support storing weights in memory and performing multiplications in memory, as described herein.

[0042] The neural network design itself usually dictates the size of the MVM operation at each layer of the network. Each layer may have a different number of features and neurons. In one embodiment, the MVM calculation will be performed in a portion of the memory array. This portion is represented in the array as one or more selected tiles.

[0043] To address these and other technical issues, a memory device integrates memory and processing. In one example, the memory and inference computing processing are integrated into the same integrated circuit device. In some embodiments, the memory device is an integrated circuit device having an image sensing pixel array, a memory cell array, and one or more circuits for using the memory cell array to perform inference computing on image data from an image sensor. In some embodiments, the memory device includes or is used with other types of sensors (e.g., LIDAR, radar, sound).

[0044] Existing methods of matrix-vector multiplication use digital logic gates. Compared to the various embodiments described below, digital logic implementations are more complex, consume more silicon area and dissipate more power. These embodiments effectively reduce the multiplication of memory access functions that can be parallelized in an array. The accumulation function is implemented by wires connecting these memory elements, which can also be parallelized in an array. By combining these two features in an array, matrix-vector multiplication can be performed more efficiently than methods using digital logic gates.

[0045] In one embodiment, a three-dimensional NOR-based accelerator is used to perform multiply-accumulate (MAC) to alleviate power consumption challenges. For example, this approach significantly increases tera operations / watt (TOPS / W) and improves energy efficiency (e.g., by 5 to 10 times or more).

[0046] In one embodiment, the image sensor is configured with analog capabilities to support inference computations, such as computations of artificial neural networks, by using matrix-vector multiplication. The image sensor may be implemented as an integrated circuit device having an image sensor chip and a memory chip. The memory chip may have a 3D memory array configured to support multiplication and accumulation operations. The integrated circuit device includes one or more logic circuits configured to process images from the image sensor chip and operate memory cells in the memory chip to perform multiplication and accumulation operations.

[0047] The memory chip may have multiple layers of memory cells. Each memory cell may be programmed to store a bit of a binary representation of an integer weight. Each input line may have a voltage applied to it according to the bit of the integer. Columns of memory cells may be used to store bits of a weight matrix; and a set of input lines may be used to control a voltage driver to apply a read voltage to a row of memory cells according to the bits of an input vector.

[0048] The threshold voltage or state of the memory cell used for the multiplication and accumulation operation can be programmed so that the current through the memory cell subjected to a predetermined read voltage is a predetermined amount representing the value of one stored in the memory cell, or is negligible to represent the value of zero stored in the memory cell. When the predetermined read voltage is not applied, the current through the memory cell is negligible regardless of the value stored in the memory cell. As a result of the configuration, the current through the memory cell corresponds to the result of the 1-bit weight as stored in the memory cell multiplied by the 1-bit input, the result corresponding to the presence or absence of the predetermined read voltage driven by the voltage driver controlled by the 1-bit input.

[0049] The output currents of the memory cells representing the results of columns of 1-bit weights stored in the memory cells multiplied by columns of 1-bit inputs, respectively, are connected to a common line (e.g., a global digit line or GDL) for summing. The summed current in the common line is a multiple of a predetermined amount; and the multiple can be digitized and determined using an analog-to-digital converter or other digitizer. Such results of 1-bit to 1-bit multiplication and accumulation can be performed for different significant bits of the weights and different significant bits of the inputs. The results of different significant bits can be shifted (e.g., shifted to the left) to apply the weights of the corresponding significant bits for summing to obtain the results of multiplication and accumulation of multi-bit weights and multi-bit inputs.

[0050] Using the ability to perform multiplication and accumulation operations implemented via the memory cell array, the logic circuit can be configured to perform inference calculations, such as those of artificial neural networks.

[0051] In one embodiment, a three-dimensional NOR memory device includes a memory cell array having vertically stacked memory cells (e.g., stacked into vertical pillars with multiple levels). Each memory cell stores a weight used in a multiplication (e.g., MVM) or other operation. A local digit line is connected to a current terminal of the memory cell. The local digit line extends vertically above a semiconductor substrate. A select transistor is connected to the local digit line. The select line is used to control the select transistor and encode an input pattern to multiply by the stored weight. An accumulation circuit system accumulates the output currents from the memory cells to determine the result of the multiplication.

[0052] In one embodiment, a three-dimensional NOR memory device includes a memory cell array having memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight for multiplication or other operations. Each memory cell has a current channel extending in a horizontal direction (parallel to the top surface of the semiconductor substrate). A word line is connected to the gate of the memory cell. The word line is used to encode an input pattern to multiply the stored weight. The accumulation circuit system accumulates the output currents from the memory cells to determine the result of the multiplication.

[0053] In one embodiment, a memory device includes a semiconductor substrate and transistors stacked vertically into pillars above the substrate. Each transistor has a semiconductor layer providing a channel and a gate layer (e.g., an ONO stack) surrounding at least half or all of the circumference of the semiconductor layer. Word lines are used to apply gate voltages to the transistors. In one embodiment, a portion of each word line surrounds at least half of the circumference of the gate layer of each transistor. In one example, the word line completely surrounds the gate layer of each transistor.

[0054] Various embodiments of memory devices that perform multiplication using the logic states of memory cells are described below. The memory devices typically have memory cells configured in an array, where each memory cell is programmed to, for example, allow a certain amount of current to pass when a voltage is applied in a predetermined voltage region to represent a first logic state (e.g., a first value stored in the memory cell), or to allow a negligible amount of current to pass to represent a second logic state (e.g., a second value stored in the memory cell).

[0055] The memory device performs calculations based on applying voltages digitally in the form of whether to apply input voltages to produce currents for summing on a line (e.g., a bit line of a memory array). The total current on the line will be a multiple of the amount of current allowed for cells programmed with a first value. In one example, an analog-to-digital converter is used to convert the current to a digital result of the sum of the bitwise multiplications.

[0056] The memory cells in the array are NOR flash memory cells. In one example, a floating gate or charge trap memory device in a NOR memory configuration is used.

[0057] In one embodiment, a memory device (e.g., integrated circuit device 101) includes a memory cell array having memory cells. Each memory cell is programmable to store a respective weight for performing a multiplication. The integrated circuit device also includes a voltage driver configured to apply an input voltage to the memory cell for performing a multiplication. The input voltage represents an input to be multiplied by the respective weight of each memory cell.

[0058] The integrated circuit device has a common line coupled to the memory cells. The common line is configured to sum the output current from each of the memory cells caused by the application of an input voltage. The integrated circuit device has a digitizer configured to generate a result of multiplication based on the summed output currents.

[0059] In one embodiment, the memory device implements unsigned 1-bit to 1-bit multiplication. Each memory cell can be programmed to a "1-state" such that a predetermined amount of current can pass through the memory cell when a voltage V is applied across the memory cell (e.g., across two terminals of the memory cell). Alternatively, the memory cell can be programmed to a "0-state" such that only a negligible amount of current can pass through the memory cell when the same voltage V is applied. Thus, the memory cell can be programmed to a "1-state" or a "0-state" to represent a stored weight of "1" or "0", respectively.

[0060] An input voltage of V may be used to represent an input "1"; and an input voltage of 0 may be used to represent an input "0." Alternatively, another voltage may be used to represent an input "0" when it is lower than V but only causes a negligible amount of current to pass through the memory cell (regardless of the programmed state of the memory cell).

[0061] When a voltage configured to represent an input 1 or 0 as described above is applied to a memory cell programmed to a "1 state" or a "0 state" to represent a weight 1 or 0 as discussed above, the amount of current passing through the memory cell is a predetermined amount (representing an output "1") or a negligible amount (representing an output "0"). In addition, the input, weight, and output relationship satisfies a 1-bit input multiplied by a 1-bit weight to produce a 1-bit output in all possible variations of the input and weight.

[0062] Thus, the memory cell is used to perform unsigned 1-bit to multi-bit multiplication by being programmed to store a 1-bit weight, applying an input voltage to represent the 1-bit input and determining the 1-bit output from sensing whether the current through the memory cell (the output current from the memory cell) is a predetermined amount.

[0063] The summation of the results represented by the output currents from the memory cells can be implemented by connecting the currents to a common line (e.g., a local digit line or a global digit line). The summation of the results can be digitized to provide a digital output. In one example, an analog-to-digital converter is used to measure the sum as a multiple of a predetermined current amount and provide a digital output.

[0064] In one embodiment, the memory device implements unsigned 1-bit to multi-bit multiplication. The multi-bit weight can be implemented via multiple memory cells. Each of the memory cells is configured to store one of the bits of the multi-bit weight, as just described above. The voltage represented by the 1-bit input can be applied individually to the multiple memory cells to obtain the result of the unsigned 1-bit to 1-bit multiplication as described above.

[0065] In one embodiment, each memory cell has a position corresponding to its stored bit in the binary representation of the multi-bit weight. Its digitized output (e.g., the sum of the output currents from the memory cells originating on a common line) can be shifted left according to its position in the binary representation to obtain a shifted result. For example, the digitized output of the memory cell storing the least significant bit of the multi-bit weight is shifted by 0 bits; the digitized output of the memory cell storing the second least significant bit of the multi-bit weight is shifted by 1 bit; the digitized output of the memory cell storing the third least significant bit of the multi-bit weight is shifted by 2 bits; etc. The shifted results can be summed to obtain the result of a 1-bit input multiplied by the multi-bit weight stored in multiple memory cells.

[0066] The summation of the results represented by the output currents from groups of memory cells (each group representing a separate multi-bit weight) can be summed bit by bit for different bit positions in the multi-bit weight via currents connected in common lines. For example, the current from the memory cell storing the least significant bit is connected to the first common line to form a summed output of the result derived from the least significant bit; the current from the memory cell storing the second least significant bit is connected to the second common line to form a summed output of the result derived from the second least significant bit; the current from the memory cell storing the third least significant bit is connected to the third common line to form a summed output of the result derived from the third least significant bit; etc. The summed outputs can be converted to digital form and then shifted and summed in digital form. Alternatively, the corresponding currents can be scaled before digitization.

[0067] In one embodiment, the memory device implements time-sliced ​​unsigned multi-bit to multi-bit multiplication. An input represented by a binary number having a predetermined number of bits (e.g., 4 bits) may be applied one bit at a time (e.g., applied at times T0, T1, T2, etc.) over the same predetermined number of clock cycles. Each cycle produces an output as described above for unsigned 1-bit to multi-bit multiplication.

[0068] The result of the unsigned 1-bit to multi-bit multiplication obtained for each clock cycle (e.g., as discussed above) may be shifted left according to the position of the bits of the input applied in that clock cycle. For example, the result of the clock cycle in which the least significant bit of the input is applied is not shifted; the result for the second least significant bit is shifted left by 1 bit; the result for the third least significant bit is shifted left by 2 bits; etc. The shifted results from the clock cycles are summed in digital form.

[0069] Figure 1 An integrated circuit device 101 is shown having an image sensing pixel array 111, a memory cell array 113 with tiles 141 and 142, and circuits to perform inference calculations according to one embodiment. Figure 1 In the embodiment, the integrated circuit device 101 has an integrated circuit die 109 with logic circuits 121 and 123 , an integrated circuit die 103 with an image sensing pixel array 111 , and an integrated circuit die 105 with a memory cell array 113 .

[0070] In one example, the memory cell array 113 includes NOR flash memory cells. The memory cells are stacked vertically into pillars. Each transistor uses a semiconductor layer to provide a channel extending in a horizontal direction relative to the vertical pillar. Each transistor has a gate layer (e.g., ONO stack) surrounding the periphery of the semiconductor layer. Word lines (e.g., WL1, WL2) are used to apply gate voltages to transistors. A portion of each word line surrounds the periphery of the gate layer of each transistor. An isolation layer electrically separates the word lines associated with each transistor in a given pillar. The pillar extends vertically above a semiconductor substrate. The channel extends in a horizontal direction relative to the substrate.

[0071] In one example, integrated circuit die 109 with logic circuits 121 and 123 is a logic chip; integrated circuit die 103 with image sensing pixel array 111 is an image sensor chip; and integrated circuit die 105 with memory cell array 113 is a memory chip.

[0072] exist Figure 1 In the embodiment, the integrated circuit die 105 having the memory cell array 113 further includes a voltage driver 115 and a current digitizer 117 (e.g., accumulation circuitry to generate a digital result from the MVM). For example, the voltage driver 115 applies a voltage to the word lines (e.g., WL1, WL2) to apply a gate voltage to the transistors of the NOR flash memory cells.

[0073] The memory cell array 113 is connected so that the currents generated by the memory cells in response to the voltages applied by the voltage driver 115 are summed for the columns of memory cells in the array 113 (eg, as shown in FIG. 1 ). Figure 2 and the summed current is digitized to produce the sum of the bitwise multiplication. The inference logic circuit 123 can be configured to instruct the voltage driver 115 to apply a read voltage according to the column of the input, and perform shifting and summing to produce a column of weights or a matrix multiplied by the column of the input and the accumulated result.

[0074] In one embodiment, sensing circuitry 150 is coupled to the memory cells in tiles 141, 142. Sensing circuitry 150 is used to sense one or more characteristics of the memory cells. In one embodiment, sensing circuitry 150 includes circuitry to precharge the bit lines of tiles 141, 142. Sensing circuitry 150 is configured to receive signals from controller 124 and / or read register 160 to determine which bit lines are to be disabled. In one embodiment, sensing circuitry 150 includes an ADC or other digitizer to convert the sum of the output currents from the memory cells accumulated on enabled access lines (e.g., accumulated on enabled bit lines) to provide a digital result (e.g., an accumulated result).

[0075] The inference logic circuit 123 may be further configured to perform inference calculations (e.g., calculations of an artificial neural network) based on the weights stored in the memory cell array 113 and the inputs derived from the image data generated by the image sensing pixel array 111. Optionally, the inference logic circuit 123 may include a programmable processor that can execute a set of instructions to control the inference calculations. Alternatively, the inference calculations are configured for a specific artificial neural network having certain aspects that can be adjusted via the weights stored in the memory cell array 113. Optionally, the inference logic circuit 123 is implemented via the core of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a programmable microprocessor.

[0076] In one embodiment, the inference logic circuit 123 includes a controller 124. In one example, the controller 124 manages communications with the host system via the interface 125. In one example, the controller 124 performs a signed or unsigned multiplication using the memory cell array 113. In one embodiment, the controller 124 selects either a signed or unsigned multiplication to be performed based on the data type to be used as an input to the multiplication. In one example, the controller 124 selects a signed multiplication in response to determining that the input to the multiplication is signed.

[0077] exist Figure 1, the integrated circuit die 105 having the memory cell array 113 has a bottom surface 133; and the integrated circuit die 109 having the inference logic circuit 123 has a portion of the top surface 134. The two surfaces 133 and 134 can be connected via bonding (e.g., using hybrid bonding) to provide a portion of the interconnect 107 between the metal portions on the surfaces 133 and 134.

[0078] Similarly, the integrated circuit die 103 having the image sensing pixel array 111 has a bottom surface 131, and the integrated circuit die 109 having the inference logic circuit 123 has another portion of its top surface 132. The two surfaces 131 and 132 may be connected via bonding (e.g., using hybrid bonding) to provide a portion of the interconnect 107 between the metal portions on the surfaces 131 and 132.

[0079] The array of image sensing pixels in array 111 may include photosensitive elements configured to generate signals in response to the intensity of light received in the element. For example, image sensing pixels implemented using complementary metal oxide semiconductor (CMOS) technology or charge coupled device (CCD) technology may be used.

[0080] In some implementations, image processing logic 121 is configured to pre-process images from image sensing pixel array 111 to provide processed images as input to inference calculations controlled by inference logic 123. Optionally, image processing logic 121 may also use multiplication and accumulation functions provided via memory cell array 113.

[0081] In some implementations, interconnect 107 includes wires for writing image data from image sensing pixel array 111 to a portion of memory cell array 113 for further processing by image processing logic circuit 121 or inference logic circuit 123 or for retrieval via interface 125. Inference logic circuit 123 may buffer results of inference calculations in a portion of memory cell array 113.

[0082] The interface 125 of the integrated circuit device 101 may be configured to support the memory access protocol or the storage access protocol or any combination thereof. Thus, an external device (eg, a processor, a central processing unit) may send commands to the interface 125 to access the storage capacity provided by the memory cell array 113 .

[0083] For example, the interface 125 may be configured to support connections and communication protocols on a computer bus, such as a Peripheral Component Interconnect Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Universal Serial Bus (USB) bus, a Compute Express link, etc. In some embodiments, the interface 125 may be configured to include an interface for a solid state drive (SSD), such as a ball grid array (BGA) SSD. In some embodiments, the interface 125 may be configured to include an interface for a memory module, such as a double data rate (DDR) memory module, a dual in-line memory module, etc. The interface 125 may be configured to support communication protocols, such as protocols according to the Non-Volatile Memory Express (NVMe), the Non-Volatile Memory Host Controller Interface Specification (NVMHCIS), etc.

[0084] From the perspective of a device communicating with the interface 125, the integrated circuit device 101 may appear as a memory subsystem. Through the interface 125, an external device (e.g., a processor, a central processing unit) may access the storage capacity of the memory cell array 113. For example, the external device may store and update weight matrices and instructions for the inference logic circuit 123, retrieve images generated by the image sensing pixel array 111 and processed by the image processing logic circuit 121, and retrieve results of inference calculations controlled by the inference logic circuit 123.

[0085] Integrated circuit die 105 includes registers 160. Integrated circuit die 109 includes memory 170 including registers 174. In one embodiment, configuration data from a host is received via interface 125. In one example, the configuration data is data used to set registers 174 and / or 160. The configuration data corresponds to processing steps performed on the neural network. The processing includes MVM calculations mapped to tiles 141, 142.

[0086] exist Figure 1 In the embodiment of the present invention, the interface 125 is positioned at, for example, the bottom side of the integrated circuit device 101, while the image sensor chip is positioned at the top side of the integrated circuit device 101 to receive incident light to generate an image.

[0087] Controllable Figure 1 The voltage driver 115 in the array 113 is used to apply a voltage to program the threshold voltage of the memory cells in the array 113. The data stored in the memory cell can be represented by the level of the programmed threshold voltage of the memory cell.

[0088] In one example, the interface 125 may be operable for the host system to write data into the memory cell array 113 and read data from the memory cell array 113. For example, the host system may send commands to the interface 125 for writing a weight matrix of an artificial neural network into the memory cell array 113 and reading an output of the artificial neural network, raw image data from the image sensing pixel array 111, or processed image data from the image processing logic circuit 121, or any combination thereof.

[0089] The reasoning logic circuit 123 may be programmable and include a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), or any combination thereof. Instructions for implementing the calculations of the artificial neural network may also be written into the memory cell array 113 via the interface 125 for execution by the reasoning logic circuit 123.

[0090] Figure 2 A calculation is shown in which a column of weight bits is multiplied by a column of input bits to provide an accumulated result according to one embodiment. Figure 2 , 227 (eg, in the memory cell array 113 of the integrated circuit device 101) may be programmed to have threshold voltages at levels representing a weight of storing one bit per memory cell.

[0091] , 223 (eg, in voltage driver 115 of integrated circuit device 101 ) are configured to apply voltages 205 , 215 , . . . , 225 to memory cells 207 , 217 , . . . , 227 according to their received input bits 201 , 211 , . . . , 221 , respectively.

[0092] For example, when the input bit 201 has a value of one, the voltage driver 203 applies a predetermined read voltage as the voltage 205, causing the memory cell 207 to output a predetermined amount of current as its output current 209 to represent a stored weight of one when the memory cell 207 has a threshold voltage programmed at a lower level (which is lower than the predetermined read voltage), or to output a negligible amount of current as its output current 209 to represent a stored weight of zero when the memory cell 207 has a threshold voltage programmed at a higher level (which is higher than the predetermined read voltage).

[0093] However, when the input bit 201 has a value of zero, the voltage driver 203 applies a voltage (e.g., zero) lower than the threshold voltage of the lower level as the voltage 205 (e.g., does not apply the predetermined read voltage), thereby causing the memory cell 207 to output a negligible amount of current as its output current 209, regardless of the weight stored in the memory cell 207. Therefore, the output current 209, which is a multiple of the predetermined amount of current, represents the result of multiplying the weight bit stored in the memory cell 207 by the input bit 201.

[0094] Similarly, current 219 passing through memory cell 217 as a multiple of a predetermined current amount represents the result of multiplying the weight bits stored in memory cell 217 by input bit 211; and current 229 passing through memory cell 227 as a multiple of a predetermined current amount represents the result of multiplying the weight bits stored in memory cell 227 by input bit 221.

[0095] The output currents 209, 219, ..., 229 of the memory cells 207, 217, ..., 227 are connected to a common line 241 (e.g., a bit line or source line in the tile 141) for summing. In one example, the common line 241 is a bit line. When summing the output currents, a constant voltage (e.g., ground or -1V) is maintained on the bit line.

[0096] The digitizer 233 of the analog-to-digital converter 245 compares the summed current 231 with a unit current 232 equal to a predetermined current amount to determine a digital result 237 of multiplying the columns of weight bits stored in the memory cells 207, 217, ..., 227, respectively, by the columns of input bits 201, 211, ..., 221, respectively, and the sum of the multiplication results.

[0097] The sum of the negligible amounts of current from the memory cells connected to line 241 is smaller than the unit current 232 (e.g., the predetermined amount of current). Therefore, the presence of the negligible amounts of current from the memory cells does not change the result 237 and is negligible in the operation of the analog-to-digital converter 245.

[0098] exist Figure 2 , voltages 205, 215, ..., 225 applied to memory cells 207, 217, ..., 227 represent digitized input bits 201, 211, ..., 221; memory cells 207, 217, ..., 227 are programmed to store digitized weight bits; and currents 209, 219, ..., 229 represent digitized results.

[0099] The result 237 is an integer not greater than the count of memory cells 207, 217, ..., 227 connected to line 241. The digitized form of the output currents 209, 219, ..., 229 can improve the accuracy and reliability of calculations performed using the memory cells 207, 217, ..., 227.

[0100] In general, the weights involved in the multiplication and accumulation operations may be more than one bit. Memory cells may be used to store different significant bits of the weights (e.g., Figure 6 ) to perform multiplication and accumulation operations. Figure 2 The circuit illustrated in can be viewed as a multiplier-accumulator unit configured to operate on columns of 1-bit weights and columns of 1-bit inputs. Multiple such circuits can be connected in parallel to implement a multiplier-accumulator unit to operate on columns of multi-bit weights and columns of 1-bit inputs.

[0101] Figure 2 The circuits described in can also be used to read data stored in memory cells 207, 217, ..., 227. For example, the sensing circuit system 150 can be used to sense the current associated with the memory cell. For example, in order to read the data or weight stored in the memory cell 207, the input bit 211, ..., 221 can be set to zero to cause the memory cell 217, ..., 227 to output a negligible amount of current to the line 241 (e.g., as a bit line). The input bit 201 is set to one to cause the voltage driver 203 to apply a predetermined read voltage. Therefore, the result 237 from the digitizer 233 provides the data or weight stored in the memory cell 207. Similarly, the data or weight stored in the memory cell 217 can be read by applying one as the input bit 211 and applying zero as the remaining input bits in the column; and the data or weight stored in the memory cell 227 can be read by applying one as the input bit 221 and applying zero as the other input bits in the column.

[0102] Generally speaking, Figure 2 The circuits illustrated in can be used to select any of the memory cells 207, 217, ..., 227 for reading or writing. A voltage driver (e.g., 203) can apply a programming voltage pulse (e.g., one or more pulses or other waveforms, as appropriate for the memory cell type) to adjust the threshold voltage of the corresponding memory cell (e.g., 207) to erase data, store data or weight, etc.

[0103] In general, the inputs involved in multiplication and accumulation operations can be more than 1 bit. For example, columns of input bits can be applied one column at a time to weights stored in a memory cell array to obtain the result of multiplying the column of weights by the column of inputs and accumulating the results.

[0104] Figure 2The multiplier-accumulator unit described in Figure 1 The integrated circuit device 101 is implemented in the embodiment of the present invention.

[0105] In one implementation, a memory chip (e.g., integrated circuit die 105) includes circuits of voltage drivers, digitizers, shifters, and adders to perform multiplication and accumulation operations. The memory chip may further include circuits configured to control the operations of the drivers, digitizers, shifters, and adders to perform operations such as Figure 2 The control logic of the operations in .

[0106] The inference logic circuit 123 may be configured to use the computing power of the memory chip (e.g., the integrated circuit die 105) to perform inference calculations of an application, such as inference calculations of an artificial neural network. The inference results may be stored in a portion of the memory cell array 113 for retrieval by an external device via the interface 125 of the integrated circuit device 101.

[0107] Optionally, the voltage drivers, digitizers, shifters, adders, and at least a portion of the control logic may be configured in the integrated circuit die 109 of the logic chip.

[0108] Memory cells (e.g., memory cells of array 113) may include volatile memory, nonvolatile memory, or both. Examples of nonvolatile memory include flash memory, memory cells formed based on NAND logic gates, NOR logic gates, phase change memory (PCM), magnetic memory (MRAM), resistive random access memory, cross-point storage, and memory devices. Cross-point memory devices may use transistor-free memory elements, each of which has memory cells and selectors stacked together in columns. The columns of memory elements are connected via two layers of wires extending in a vertical direction, wherein the wires of one layer extend in one direction in a layer located above the columns of memory elements, and the wires of the other layer extend in another direction in a layer located below the columns of memory elements. Each memory element may be individually selected at the intersection of a wire on each of the two layers. Cross-point memory devices are fast and nonvolatile and may be used as a unified memory pool for processing and storage. Further examples of non-volatile memory include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM) memory, etc. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0109] Integrated circuit die 105 and integrated circuit die 109 may include circuits to address memory cells in memory cell array 113, such as row decoders and column decoders to convert physical addresses into control signals to select a portion of memory cells for reading and writing. Thus, an external device may send commands to interface 125 to write weights into memory cell array 113 and read results from memory cell array 113.

[0110] In some implementations, image processing logic circuit 121 may also send commands to interface 125 to write an image into memory cell array 113 for processing.

[0111] Figure 3 A method for calculation in an integrated circuit device based on summing output currents from memory cells according to one embodiment is presented. For example, Figure 3 The method can be used Figure 2 or 4 multiplication and accumulation techniques in Figure 1 is executed in the integrated circuit device 101.

[0112] Figure 3 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 3 The method is at least partially performed by one or more processing devices (e.g., Figure 1 The inference logic circuit 123 may be executed by the controller 124 or the local controller (not shown) of the integrated circuit die 105.

[0113] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0114] At block 301, a memory cell (or a group of memory cells storing bits of a signed weight, such as a group of 4 cells) is programmed to a target weight for performing a multiplication. In one example, the memory cells of the memory cell array 113 are programmed. In one example, the memory cells 207, 206, 208 are programmed to store weights of different bit significance. The weights correspond to multi-bit weights (e.g., Figure 6 Weight1).

[0115] At block 303, a voltage is applied to the memory cell. The voltage represents an input bit to be multiplied by the weight stored by the memory cell. In one example, a voltage driver applies the input voltage 205, 215, 225.

[0116] At block 305, the output currents from the memory cells resulting from the applied voltages are summed. In one example, using Figure 2 Line 241 in collects and sums the output currents.

[0117] At block 307, a digital result based on the summed output current is provided. In one example, the summed output current is used to generate Figure 2 The result is X 237.

[0118] In one embodiment, some memory cells have a first threshold voltage programmed to represent a value of one, and the applied voltage is less than the first threshold voltage.

[0119] In one embodiment, the applied voltage is at least 0.5 volts less than the first threshold voltage.

[0120] In one embodiment, the device further includes an interface (eg, 125) operable for a host system to write data into and read data from the memory cell array.

[0121] In one embodiment, the memory cell includes a first and a second memory cell; the corresponding weight stored by the first memory cell is the most significant bit (MSB) of the multi-bit weight; and the corresponding weight stored by the second memory cell is the least significant bit (LSB) of the multi-bit weight.

[0122] In one embodiment, the digitizer is configured in an analog-to-digital converter.

[0123] Figure 4 An analog weight fixed architecture for matrix vector multiplication (MVM) is shown according to one embodiment. Because the computational burden when executing a neural network is primarily on the MVM operation, an analog weight fixed architecture focused on the MVM operation is used. Other computations / logic required can typically be implemented in the digital and / or analog space as they have relatively little impact on performance and energy efficiency.

[0124] In a weight-fixed architecture, computations are performed where the weights are stored (e.g., in a NAND or NOR flash memory device where the weights are stored). This eliminates or reduces the performance bottleneck and power inefficiency of moving weights out of memory for computation. MVM computations are performed in the analog domain. This often results in some computational errors that are not present in the digital domain.

[0125] The weights are stored in a memory cell 405 (e.g., a memory cell) within a memory device (e.g., 101). The input is sent to an electrode 408 of the memory cell, resulting in a multiplication of the input and the weight (based on the conductance of the memory cell storing the weight) (e.g., weight g12 multiplied by input Vin1). Digital-to-analog converters (DACs) 402, 404 convert the digital input into a magnitude of an analog voltage used to drive an electrode 408 (e.g., an access line, such as a select gate drain line).

[0126] The result is summed to another electrode (e.g., 406) within the memory array (e.g., Figure 2 41) and detected by ADCs 420, 422. For example, integrators 410, 412 accumulate currents I1, I2 from memory cell 405 determined by the conductance of the cell and provide the accumulated current as input to the ADCs 420, 422.

[0127] In one embodiment, a memory device performs MVM on weights stored in a three-dimensional (3D) array of memory cells. The weights are stored in the memory cells. The memory cells extend vertically upward from a semiconductor substrate (not shown). The memory cells are arranged as vertical pillars of the cell.

[0128] The threshold voltage (VT) of the memory cell is set (programmed) based on the expected weight. When the cell is read using a fixed word line voltage, the cell will sink some current that varies depending on the weight stored within the cell (based on the cell IV characteristic).

[0129] In one embodiment, the three-dimensional memory cell array has a NOR configuration in which the memory cells are connected in parallel. Figure 1 An example of a memory cell array 113.

[0130] The array includes memory cells arranged into various vertical pillars, where each cell in a pillar is connected to a vertical local digit line. The array is located above a semiconductor substrate (not shown). The memory cells are also arranged into horizontal tiers. The tiers are vertically stacked.

[0131] Each of the cells is connected to a horizontally extending word line. Each memory cell is biased by applying a voltage to one of the word lines and one of the local digit lines to which the cell is connected. When performing multiplication, a memory cell in one or more of the levels is selected by applying a voltage to the word line.

[0132] Each local digit line of the pillar is connected to a global digit line using a select transistor. When performing a multiplication, the output currents from the selected memory cells of the level(s) are accumulated on the global digit line. In some embodiments of the resistive array, multiple levels can be selected simultaneously for calculation.

[0133] In one embodiment, each of the memory cells is programmed to store a weight bit for performing multiplication. For a selected level of memory cells to be used for multiplication, a voltage is applied on the word line of each cell so that each memory cell can contribute a certain level of output current depending on the programming state of the memory cell.

[0134] When performing a multiplication, a voltage is applied to the memory cell, such as discussed above. The applied voltage represents the input bit to be multiplied by the weight bit stored by the memory cell. The voltage is applied to the gate of the select transistor using a select line (e.g., SL-, SL+). The output currents from the memory cells are then summed on a global digital line and a digital result is provided, such as discussed above.

[0135] Figure 5 A three-dimensional memory cell array having floating gate memory cells in a NOR configuration is shown according to one embodiment. The memory cells are connected in parallel. Figure 5 The memory cell array illustrated in is an example of the memory cell array 113 .

[0136] Similar to the above discussion, the memory cells can be arranged in horizontal levels. One or more of the levels are selected for performing multiplication. For example, memory cells 506, 507, 508, 509 are selected by applying a gate voltage to each cell. The voltage is applied using word lines 512, 513, 514, 515.

[0137] In one embodiment, word lines 512 and 514 are connected as a single line. Word lines 513 and 515 are also connected as a single line.

[0138] The memory cells of the array are arranged to each have a pillar of vertical local digit lines 502, 504. Each local digit line is coupled to a global digit line 516,518 through a select transistor 520,522.

[0139] In one embodiment, each of the memory cells is programmed to store a weight bit for performing multiplication. For a selected level of memory cells to be used for multiplication, a voltage is applied on the word line so that each memory cell can contribute a certain level of output current depending on the programming state of the memory cell.

[0140] When performing a multiplication, a voltage is applied to the memory cell, such as discussed above. The applied voltage represents the input bit to be multiplied by the weight bit stored by the memory cell. The voltage is applied to the gates of the select transistors 520, 522 using a select line (SL). The output currents from the memory cells are then summed and provided as a digital result on the global digital lines 516, 518, such as discussed above.

[0141] Various memory cell implementations can be used to perform signed multiplication. In one embodiment, signed multiplication is performed in a so-called four-quadrant system, where each of the inputs and weights to be multiplied can have a positive or negative sign. For example, some neural network models use matrix-vector multiplication, where the weights of the model are signed. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0142] In one embodiment, matrix-vector multiplication is performed using stored weights. The input signal is multiplied by the weights to provide a result. In one example, the weights are determined by training a neural network model. The model uses both positive and negative values ​​for the weights. In one example, the weights are stored in Figure 1 In a memory cell of the memory cell array 113 of . In one example, the model is trained using image data, and the trained model provides inference results based on input from the image sensor.

[0143] In one embodiment, the multiplier accumulator unit uses signed multiplication. The weight can be represented by a multi-bit value (e.g., 8 to 64 bits). The extra bit is used to represent the sign of the weight value. For example, the system can use an 8-bit signed weight, where the value of the weight is represented by seven bits, and the eighth bit is used to represent the sign. For signed inputs, the extra bit can be used in a similar manner.

[0144] In one embodiment, a signed 1-bit number (e.g., input and / or weight) has one of three possible values: -1, 0, 1. For example, a signed weight may be represented by a 2-bit number, where a 2-bit value of 01 represents a signed 1-bit value of -1; a 2-bit value of 00 represents a signed 1-bit value of 0; and a 2-bit value of 10 represents a signed 1-bit value of +1. A 2-bit value of 11 is not used. In other examples, various combinations of 2 bits may represent different signed values, as may be desired for a given implementation.

[0145] In one example, a controller that controls multiplication manages two-bit values ​​by keeping track of the meaning (e.g., sign or magnitude) represented by each bit. In one example, the controller is Figure 1 Part of the inference logic circuit 123.

[0146] A 1-bit by 1-bit multiplication of a two-bit number representing a signed 1-bit input and a signed 1-bit weight can be configured to produce a signed 1-bit to 1-bit multiplication result. Figure 1 The interface 125 determines the result in response to a request from the host system. In one example, the signed input used to generate the result is based on the signed input of Figure 1 The image sensing pixel array 111 collects data.

[0147] In one embodiment, a two-cell implementation is used for signed 1-bit to 1-bit multiplication. Two memory cells in a group are used to store two bits of a signed 1-bit weight in a two-bit representation.

[0148] The two input lines are used to apply two bits of a signed 1-bit input (two-bit representation) (sometimes referred to herein as the "positive version") at a first moment (e.g., the first clock cycle T0), and then apply a negative version of the input at a second moment (e.g., the second clock cycle T1).

[0149] In one embodiment, a four-cell implementation is used for signed 1-bit to 1-bit multiplication. Four memory cells in a group are used to store two bits of a signed 1-bit weight in a two-bit representation (sometimes referred to herein as a "positive version") and a negative version of the two-bit representation. Two input lines are used to apply two bits of a signed 1-bit input (two-bit representation).

[0150] In one example, the input line provides a voltage to a group of memory cells. The group has four memory cells. In one example, the input line can be a word line, a bit line, or a select gate line (SL or SGD), depending on the type of memory cells and the specific group configuration (e.g., memory cells arranged in series for NAND flash memory versus memory cells arranged in parallel for RRAM or NOR).

[0151] The first pair of memory cells multiplies the signed input and sums the output current on the first line. The second pair of memory cells also multiplies the signed input and sums the output current on the second line.

[0152] The first line of bit results (e.g., 0 or 1) provides the first bit of a signed 1-bit to 1-bit multiplication (two-bit representation). The second line of bit results (e.g., 0 or 1) provides the second bit of a signed 1-bit to 1-bit multiplication (two-bit representation). In one example, these first and second bit results provide a 1-bit signed result.

[0153] In one example, an image is provided as an input to a neural network. The neural network includes convolutional layers. Each layer is of a different size. For example, each layer has a different number of features and neurons. For example, one layer uses a smaller number of filters than another layer. The neural network provides a final result. In one example, the final result is a classification of an object represented by the image.

[0154] When performing calculations, matrix-vector multiplication operations are mapped to tiles in a memory cell array (e.g., 113). For example, such mapping involves identifying portions of the memory cell array to be used during calculations for a particular layer. Such mapping typically changes as calculations progress from one layer to another.

[0155] In one example, the image is data obtained from the image sensing pixel array 111. In one example, the weights of the neural network have been programmed into the memory cells of the tiles 141, 142. In one example, as the computation progresses from one layer to another, a different memory array configuration is used for each layer.

[0156] In one example, tiles of a memory device are configured to be partially filled for performing multiplication or other operations for a neural network. The tiles are in an array of memory cells (e.g., 113). In one example, the array includes about 1,500 NAND or NOR tiles. The tiles are filled (programmed) with weights for neurons to be used (e.g., for at least one layer). The specific weights effective for a given MVM calculation will vary, as discussed above.

[0157] In one embodiment, the NAND or NOR memory device has registers exposed to the host interface. The host can set the registers to configure the NAND or NOR device (e.g., the parameters can be defined by the host). For example, the NAND or NOR device can provide fixed options of certain predefined neuron sizes to the host. The host can select one of the predefined neuron sizes that is closest to the current computation size. The NAND or NOR device uses logic circuitry to set the configuration based on the definition of the predefined neuron sizes by the host.

[0158] In one embodiment, the host or local controller communicates the neuron size in a register. In one embodiment, the NAND or NOR device selects one of the above predefined neuron sizes based on the neuron size stored in the register.

[0159] In one embodiment, the memory device uses an array of memory cells organized into groups of memory cells. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0160] Each group can be programmed to store a multi-bit signed weight. After being programmed, a voltage driver applies a voltage to the memory cells in each group. The voltage represents the multi-bit signed input to be multiplied by the multi-bit signed weight.

[0161] One or more common lines are coupled to each group. The lines receive one or more output currents from the memory cells in each group (eg, similar to that discussed above for groups of two or four cells). Each common line accumulates the currents to sum the output currents from the group.

[0162] In one example, the line(s) are bit lines that extend vertically above the semiconductor substrate. As an example, 512 groups of memory cells are coupled to the line(s). Input is provided using 512 pairs of select lines (e.g., SL+, SL-), with one pair used for each group. The output current from each of the 512 groups is collected on the line(s), and then one or more total current magnitudes are digitized to provide first and second digital values.

[0163] In one example, the memory device includes one or more digitizers. The digitizer(s) provide a signed result based on summing the output current from each of the 512 sets on the first and second digit lines (eg, as described above).

[0164] A first digital value (e.g., an integer) representing a current on a first digit line is determined as a multiple of a predetermined current (e.g., as described above) representing 1. A second digital value representing a current on a second digit line is determined as a multiple of the predetermined current. The first and second digital values ​​are, for example, outputs from a digitizer(s).

[0165] In one embodiment, the memory device includes a memory cell array (e.g., using memory cell array 113) having groups of NOR flash memory cells. Each group is programmable to store a multi-bit signed weight. A voltage driver applies a voltage to each group. The voltage corresponds to a multi-bit signed input that is multiplied by the multi-bit signed weight of each group. Two common lines are coupled to each group. Each common line sums the corresponding output currents from each group. The digitizer on each common line provides a signed result based on the summation of the output currents from the group. Each signed result corresponds to the bit significance of the input and the bit significance of the weight, for example as described above. The signed results are added together taking into account the corresponding bit significance to provide first and second digital values ​​representing the signed accumulation results from the multi-bit to multi-bit multiplication.

[0166] In one embodiment, a signed input is applied to a group of memory cells on two conductors (e.g., two select lines), each conductor carrying a signal. Whether the input is positive or negative depends on where the magnitude of the signal is provided. In other words, the sign depends on which conductor carries the signal. The other conductor carries a signal of a constant value (e.g., a constant voltage corresponding to zero).

[0167] Each signed input applied to the group is considered to have a positive magnitude. One of the two wires is always biased to zero (more generally to a constant signal). The other wire carries the magnitude of the input pattern.

[0168] In one embodiment, a multi-bit input is represented as a serial or time-sliced ​​input provided on two wires. For example, an input pattern is a number of bits (e.g., 1101011) for which a corresponding voltage is applied serially to the wires, one bit per time slice. In one example, the input bits are applied serially one at a time.

[0169] In one embodiment, the contribution of the output current from each of the memory cells to the common line varies corresponding to the MSB, MID, or LSB significance of the bit stored by the memory cell (e.g., for the 3 bits stored in the group of 3 memory cells described above). The contribution of the highest significance (e.g., 100 nA) is twice the MID significance (e.g., 50 nA). The contribution of the MID significance is twice the LSB significance (e.g., 25 nA).

[0170] When the output current contribution takes into account the bit significance, then no left shift is required when adding the signed results (e.g., the first, second, third, and fourth signed results) to obtain the signed accumulation result. Alternatively, the signed results can be added directly without left shift.

[0171] In one embodiment, a memory device performs an analog summation of 1-bit result currents with different bit significances implemented via different bias voltage levels. A memory cell (e.g., an RRAM cell or a NOR flash memory cell) can be programmed to have a current that increases exponentially (e.g., increases by powers of 2) for different bias voltage levels.

[0172] In one embodiment, a memory cell may be programmed to have a threshold with a current that increases exponentially for higher bias / applied voltages. A first voltage may be applied to the memory cell to allow a predetermined amount of current (indicated as 1X) to pass to represent a bit value of 1 for the least significant bit.

[0173] To represent a bit value of 1 for the second least significant bit, a second voltage may be applied to the memory cell to allow twice (indicated as 2X) the predetermined amount of current to pass, which is equal to the predetermined amount of current multiplied by the bit significance of the second least significant bit.

[0174] When the bit value is 1, the memory cell may similarly be biased to have a higher current amount equal to a predetermined current amount multiplied by the bit significance of the bit.

[0175] When different voltages are applied to memory cells that each represent a bit in a number so that the respective bit significance of each cell is built into the output current as described above, the results of multiplications involving the memory cells can be summed by connecting them to lines without having to individually convert the currents for the bits for summation.

[0176] For example, a 3-bit resolution weight can be implemented using three memory cells. Each memory cell stores 1 bit of the 3-bit weight. Each memory cell is biased at a separate voltage level so that if it is programmed in a state representing 1, the current through the cell is the base unit multiplied by the bit significance of the cell. For example, the current through the cell storing the least significant bit (LSB) is 25nA of the base unit, the current through the cell storing the middle bit (MID) is 2 times (2x) of the base unit (50nA), and the current through the cell storing the most significant bit (MSB) is 4 times (4x) of the base unit (100nA).

[0177] In one embodiment, a solid state drive (SSD) or other storage device uses a memory cell array having memory cells. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0178] In one embodiment, each memory cell can be programmed to store one bit of a multi-bit weight. After being programmed, a voltage driver applies different voltages to bias the memory cell for performing multiplication. The input to be multiplied by the multi-bit weight can be represented by a corresponding input pattern applied to a select gate coupled to a select transistor of the memory cell (e.g., as described above), or by varying different voltages between a fixed voltage state representing an input bit 1 and a zero state representing an input bit 0.

[0179] One or more common lines are coupled to the memory cells. The lines receive one or more output currents from the memory cells (eg, as described above). Each common line (eg, a digit line or a bit line) is used to accumulate the currents to sum the output currents.

[0180] In one embodiment, three memory cells store a three-bit value representing a stored weight. One bit is used for the MSB, one bit is used for a bit of medium significance (sometimes indicated herein as "MID"), and one bit is used for the LSB. This provides a multi-bit representation of the stored weight.

[0181] Figure 6 An architecture with resistive random access memory (RRAM) or NOR memory cells arranged in a parallel configuration in a memory cell array 602 for performing multiplication (e.g., MVM) according to one embodiment is shown. For example, memory cells 630, 631, 632 store bits of respective significance for a multi-bit weight (indicated as Weight1). A simple 3-bit weight is illustrated, but a larger number of bits may be stored for each weight. When performing multiplication, each of the memory cells 630, 631, 632 may be accessed in parallel. In one example, the memory cell array 602 includes a plurality of memory cells 630, 631, 632, each of which may be accessed in parallel. Fig. 9 Memory cells arranged as described in .

[0182] Each memory cell provides an output current corresponding to the validity of the bit stored by the memory cell.Memory cells 630, 631, 632 are connected to a common line 610 for accumulating the output currents.In one example, line 610 is a bit line.

[0183] Different voltages V1, V2, V3 are applied to memory cells 630, 631, 632 using word lines 620, 621, 622. The voltages are selected so that the output current varies by a power of 2 based on the bit significance, such as described above.

[0184] In one embodiment, input signal I1 is applied to the gate of select transistor 640. Select transistor 640 is coupled to common line 610. The output of select transistor 640 provides the sum of output currents. In one embodiment, when the input signal is applied to the gate of select transistor 640, different voltages V1, V2, V3 are maintained at a constant voltage level.

[0185] In an alternative embodiment, similar to what is described above, by varying different voltages V1, V2, V3 between a fixed voltage and a zero voltage, an input pattern for multiplying Weight1 may be applied to word lines 620, 621, 622 to represent input bits 1 or 0, respectively.

[0186] The memory cell array 602 is formed over a semiconductor substrate 604. In one embodiment, the memory cell array 602 and the semiconductor substrate 604 are on different chips or wafers (eg, joined by bonding) before being assembled.

[0187] Similarly, as described above for Weight1, multi-bit weights Weight2 and Weight3 can be stored in other memory cells of the memory cell array 602, and the output currents are accumulated on common lines 611, 612, as illustrated. These other memory cells can be accessed using word lines 620, 621, 622. Common lines 611, 612 are coupled to select transistors 641, 642, which each provide the sum of the output currents as output. Input patterns I2, I3 can be applied to the gates of the select transistors. Additional weights can be stored in the memory cell array 602.

[0188] The output currents from the common lines 610, 611, 612 are accumulated by accumulation circuitry 650. In one embodiment, accumulation circuitry 650 is formed in semiconductor substrate 604 (eg, at the top surface).

[0189] In one embodiment, voltage driver 606 and bias circuitry 605 are formed in semiconductor substrate 604. Logic circuitry (not shown) formed in semiconductor substrate 604 is used to implement controller 603. Controller 603 controls voltage driver 606 and bias circuitry 605.

[0190] In one embodiment, voltage driver 606 provides different voltages V1, V2, and V3. Bias circuitry 605 applies inputs I1, I2, I3.

[0191] Figure 7 Memory cells 702, 703, 704 are shown arranged in an electrically parallel configuration with current terminals connected to a common global digit line (GDL) 710 through a select transistor 706 according to one embodiment. The memory cells 702, 703, 704 are stacked vertically above a substrate (not shown) (e.g., see Figure 8 As a structural example). Each memory cell is biased by a word line (e.g., WL1, WL2). In one example, memory cells 702, 703, 704 are flash memory cells configured in memory cell array 113. In some embodiments, the current terminal of select transistor 706 is electrically connected to global digit line 710 using a via.

[0192] A local digit line (LDL) 708 electrically connects one current terminal of each memory cell to a global digit line 710 using a select transistor 706. The select transistor 706 is controlled (eg, turned on or off) by a select line (eg, WLS).

[0193] The other current terminal of each memory cell is connected to a local digit line (LDL') 712. In some embodiments, each memory cell is connected to a different local digit line 712. In other embodiments, each memory cell is connected to a common local digit line 712 (sometimes referred to as a common plate (PL)). The local digit lines 712 are connected to a bias circuit via an interconnect 714 (e.g., a via).

[0194] In some embodiments, several LDL's (PL) can be shorted together. In some embodiments, the connections to the LDL' can run along the bottom of the memory array, similar to how the GDL runs along the top of the memory array.

[0195] In one embodiment, logic circuitry (not shown) is located below the memory cells (eg, in a logic chiplet). The logic circuitry drives the voltages on global digit line 710, local digit line 712, word lines WL1, WL2, WL3, and select line WLS.

[0196] The output currents from one or more selected memory cells are accumulated by local digit line 708. In one embodiment, memory cells 702, 703, 704 are organized into vertical pillars. The output currents from the memory cells of a plurality of such pillars (not shown) are accumulated by global digit line 710, which is connected to the local digit line (not shown) of each pillar. Global digit line 710 is also connected to accumulation circuitry (not shown).

[0197] In one embodiment, each memory cell represents bits of equal bit significance (e.g., all bits have the least significant bit (LSB)). In one embodiment, two or more memory cells may be used together to represent a single bit of higher significance. For example, the word lines WL2, WL3 of the memory cells 703, 704 may be electrically shorted together so that the output current from the memory cells 703, 704 corresponds to a multiplication of a single bit using the most significant bit (MSB).

[0198] In one embodiment, the input pattern to be multiplied by the weights stored in the memory cells 702, 703, and / or 704 is applied by changing the voltage on the select line WLS. In one embodiment, the input pattern to be multiplied by the weights stored in the memory cells 702, 703, and / or 704 is applied by changing the voltage on the word line of the selected memory cell. In one embodiment, the word line voltage is changed in the time domain (e.g., the memory device implements time-sliced ​​unsigned multi-bit to multi-bit multiplication).

[0199] In one embodiment, each memory cell stores a single bit (binary single level cell (SLC)). In one embodiment, each memory cell stores multiple bits (eg, MLC, TLC).

[0200] Figure 8 Yes Fig. 9 0 (indicated by "XX") and shows a memory device according to one embodiment having NOR flash memory cells (e.g., 50 to 200 transistors) stacked vertically in pillars above a semiconductor substrate (not shown).

[0201] Each memory cell is implemented by one of a plurality of transistors stacked vertically into pillars above the substrate. Each transistor has a semiconductor layer 820 (e.g., silicon, polysilicon, oxide semiconductor) to provide a channel. The channel is horizontally (e.g., in Figure 8 Each semiconductor layer 820 also provides a source and a drain for each transistor.

[0202] Each transistor also has a gate stack layer 818 (e.g., an oxide-nitride-oxide (ONO) stack, ANO, ONOA, etc.) surrounding the periphery of the semiconductor layer 820. The memory storage element 824 of each transistor is provided by a portion of the gate stack layer 818 that is aligned with a corresponding portion of the word line 816 (e.g., WL1, WL2) of the transistor. The word line is connected in and out of the Figure 8 In some embodiments, the word line (WL) metal may be on only two sides (top and bottom) and not on the sidewalls. In one embodiment, the WL has a step and the contact is at the end of the WL. For example, the word line (WL) contacts the step of the contact at the edge of the memory array.

[0203] In one embodiment, the peripheral CMOS circuitry may be located either below or above the array.

[0204] In one embodiment, the vertical spacing between memory cells can be varied. In one embodiment, the WLs of some vertical cells can be shorted together and the isolation eliminated, effectively connecting the memory cells in parallel with improved density.

[0205] The word lines are used to apply gate voltages to the transistors. A portion of each word line surrounds the periphery of the gate layer of each transistor. An isolation layer 828 (eg, oxide) electrically separates the word lines of each transistor in the pillar.

[0206] A local digit line 826 (eg, LDL1) is connected to a first terminal of each transistor. A local digit line 822 (eg, LDL1') is connected to a second terminal of each transistor. Local digit lines 826 and 822 each extend vertically above the substrate.

[0207] The select transistor is located above the memory cell of the pillar, as illustrated. A semiconductor layer 812 (e.g., silicon) provides a channel for the select transistor. The select transistor electrically connects the local digit line 826 to the global digit line 804. The select transistor is controlled by a select line (WLS) 808. An insulating layer 810 electrically separates the select line 808 and the semiconductor layer 812. In one embodiment, the global digit line (GDL) 804 extends in a horizontal direction relative to the substrate.

[0208] The dielectric layer 802 (eg, oxide) and isolation layers 806, 814 (eg, oxide or nitride) provide electrical insulation for the various components, as illustrated.

[0209] Global digit line 804 is electrically connected to accumulation circuitry (not shown) that accumulates output currents from selected ones of the transistors using global digit line 804 and other global digit lines (not shown) when performing multiplication operations.

[0210] Fig. 9 906, 908 (eg, oxide or nitride) according to one embodiment. Figure 8 For example, local digit line 826 is isolated from local digit line 902 by dielectric material 906. Local digit line 822 is isolated from local digit line 904 by dielectric material 906.

[0211] Semiconductor layer 820 corresponds to a first memory cell. Semiconductor layer 910 corresponds to a second memory cell. The first and second memory cells are electrically isolated by dielectric material 906. Each memory cell has a gate controlled by a common word line (not shown). In one example, this common word line controls 300 to 1,000 memory cells. A portion of the word line surrounds the gate layer of the transistor of each memory cell (e.g., see Fig.16 word line 1610 in).

[0212] Each memory cell has a current terminal connected to a different local digit line. For example, semiconductor layer 910 provides a channel electrically connected to local digit lines 902, 904. This is electrically isolated from semiconductor layer 820, which provides a channel electrically connected to different local digit lines 822, 826.

[0213] In one embodiment, each storage transistor uses silicon to provide a horizontal channel. Due to being arranged in a NOR configuration, each storage transistor is bit-level addressable. Each storage transistor has direct access lines for its source and drain. The storage element is in the gate stack of each transistor. In one example, a gate stack is used in layer 818 to provide an ONO or TANOS cell. In one example, a charge trapping stack is used. In operation, the trapped charge in the storage element modulates the threshold voltage of the transistor, which changes its read current when multiplication is performed.

[0214] Fig.10 An example matrix of memory cells according to one embodiment is shown, wherein each matrix has a plurality of tiles 1002, 1004, and each tile has a plurality of pillars of memory cells. In one example, each pillar has Figure 8 A memory cell configured as described in .

[0215] The memory cells of each pillar are connected to a global digital line 1030 through select transistors 1010, 1012. The global digital line 1030 is connected to conversion circuitry 1040 (e.g., an analog-to-digital converter). The output currents from the memory cells are accumulated on the global digital line 1030. The conversion circuitry 1040 provides a digital result based on the magnitude of the total accumulated current.

[0216] In one example, each matrix has 48 tiles. Each pillar is associated with a local digital line (eg, 826). There are 21 synapses per local digital line.

[0217] For example, for three bits of resolution, three vertical memory cells are used per synapse. Each of the memory cells is on a different horizontal level of the memory array.

[0218] In an alternative embodiment, decoding of the selected transistor may be implemented using two levels of decoding. The first level corresponds to select transistor 1022, and the second level corresponds to select transistor 1020. The output currents from the memory cells of tiles 1006, 1008 are accumulated on a global digit line (e.g., 1032). A digital result is produced by conversion circuitry (e.g., 1042) connected to the global digit line. Two levels of decoding may reduce capacitive loading on the global digit lines and / or local digit lines (e.g., by isolating the capacitance of unused lower level select transistors).

[0219] In one example, the controller 124 uses select transistors 1010, 1012 and / or 1022, 1020 to configure the memory array for multiplication by turning on or off specific tiles of the memory array. The number of tiles used for a given multiplication will vary depending on the specific neural network being supported (e.g., depending on the size of the layer of the neural network currently being used).

[0220] Fig.11 Demonstrating an embodiment Fig.10 1004 in an example matrix. For example, as illustrated, tiles 1002, 1004 are arranged in parallel as thin rectangular strips. Global digit lines (e.g., 1030) run in a direction perpendicular to the parallel arranged tile strips. Each global digit line accumulates the output currents from selected memory cells of tiles 1002, 1004.

[0221] Fig.12 A memory device according to one embodiment is shown having global digit lines 1204 connecting memory cells of different tiles 1202 in an array of memory cells to accumulation circuitry 1230. Accumulation circuitry 1230 uses the output current accumulated by global digit lines 1204 as input(s) and produces digital output(s) as a result of a multiplication operation.

[0222] The global digit line 1204 is connected to the local digit line 1214 through the select transistor 1206. The select transistor 1206 is controlled by the voltage WLS applied to the select line 1218.

[0223] A local digit line 1214 is connected to a first current terminal of each memory cell 1208. A local digit line 1216 is connected to a second current terminal of each memory cell 1208. In one example, local digit lines 1216 are connected to a common plate.

[0224] Bias voltage is applied to each memory cell 1208 to vary the output current using word lines 1210, 1212. Word lines 1210, 1212 run in the same direction as select line 1218. Word line 1210 is used to select a first level of the memory array. Word line 1212 is used to select a second level of the memory array.

[0225] Fig.13 Demonstrating an embodiment Fig.12 A top view of a memory device of FIG. 1204. A global digit line 1204 runs perpendicular to a select line 1218. A word line 1210 runs parallel to the select line 1218. A driver 1302 (eg, a voltage driver 115) applies a voltage to the select line 1218 and / or the word line 1210.

[0226] The memory cells are arranged as vertical pillars 1304, 1306. In one example, each pillar 1304, 1306 has Figure 8 A structure similar to the memory cell structure described in .

[0227] Fig.14 is a top view of a memory device according to one embodiment, the memory device having Fig. 9 Similar structure, except that each of the memory cells in each pillar has one of its two current terminals connected to a common local digit line 1402 (LDL'). In one example, the common local digit line 1402 is a common plate. Using a common plate requires the use of bulk erase for the memory cells.

[0228] In an alternative embodiment, only a portion of the memory cells are shorted to the common plate. Other memory cells may have individual local digit lines 822.

[0229] Fig.15 is a cross-sectional view of a memory device according to one embodiment, the memory device having Figure 8 Similar structure, except that a portion of the memory cell in the pillar has its word line electrically shorted together so the memory cell is turned on and off as a unit. For example, silicon layers 1502, 1504 provide a channel for two memory cells located in two different levels 1500 vertically relative to each other. Word line portions 1506, 1508, 1510 are electrically shorted together. Therefore, the word line signal input is the same for each memory cell. Moreover, each memory cell stores the same weight value.

[0230] No dielectric isolation is required between word line portions that are electrically shorted in this way. This reduces the size requirements of the structure. Two memory cells together represent, for example, the most significant bit (MSB) and are switched on or off together.

[0231] Figures 16 to 18 Example structures for configuring local digit lines and memory cells of memory devices according to various embodiments are shown (using simplified block form for illustration purposes only). The simplified blocks in these figures are not drawn to scale and merely illustrate three-dimensional spatial relationships.

[0232] Fig.16 A local digit line 1606 is shown connecting the current terminal of each memory cell to the global digit line 1602 using a select transistor 1605 and a via (or other interconnect) 1603. The other current terminal of each memory cell is connected to a local digit line 1608 (or common plate). The select transistor 1605 is controlled by the select line 1604.

[0233] Each memory cell is controlled or switched by a word line 1610, 1612. Word line 1610 controls memory cells in a first level. Word line 1612 controls memory cells in a different lower level. Each word line surrounds the periphery of a gate layer / semiconductor layer 1614.

[0234] Fig.17 A first pillar of memory cells controlled using word line 1610 and a second pillar of memory cells controlled using word line 1700 are shown. The first pillar uses local digit lines 1702, 1704. The second pillar uses different local digit lines 1706, 1708.

[0235] Fig.18 A first pillar of memory cells controlled using word line 1610 and a second pillar of memory cells controlled using word line 1700 are shown. The first pillar uses local digit lines 1702, 1802. The memory cells of the second pillar share local digit line 1802 for one current terminal of each cell, but use a different local digit line 1708 for the other current terminal of each cell. In this embodiment, it should be noted that the respective gate stack layers of each device are isolated from one device to the next, but each word line 1610, 1700 is continuous across the devices.

[0236] Fig.19 A global digit line 1902 is shown that sums the output currents from selected memory cells of a tile 1912 in a memory array according to one embodiment. Memory cells are selected by applying voltages to select lines 1906 and / or word lines 1909. An accumulator 1904 generates a digital output based on the summed current. The global digit line 1902 is connected to the local digit lines of the memory cells 1910 in each pillar through select transistors 1908.

[0237] In one embodiment (referred to herein as "Case 1"), select lines are used to encode input patterns. Word lines are used to select a particular level. Select lines and global digit lines create a crosspoint array for any level (or group of levels, if required for synaptic resolution). The levels are statically selected. In one example, the physical array is roughly square. Accumulator 1904 sums the current from each pillar of the same level.

[0238] In one embodiment (referred to herein as "Case 2"), select lines are used to select a subset of the memory array. Word lines are used to encode input patterns. The input patterns are applied at the word lines. In this case, the hierarchy can be dynamically selected / deselected to map to the input patterns. The select lines define the size of the physical memory array. For example, for the same size electrical array, the memory array is more compact.

[0239] The accumulator 1904 sums the current from multiple legs and multiple levels. Multiple arrays can be supported by the same set of accumulators (eg, 1904).

[0240] Figures 20 to 21 Demonstrating various embodiments Fig.19 A top view of the memory array. Fig. 20 In , driver 2002 applies a voltage to select line 2004 to select pillar 2006. Fig.21 , driver 2102 applies a voltage to word line 2104 to select a level of memory cells in pillar 2006.

[0241] Fig. 22 A method for performing multiplication using memory cells located in selected portions of one or more tiles according to one embodiment is shown. For example, when performing multiplication, Figure 1 The integrated circuit device 101 performs Fig. 22 method (e.g., as described in the various embodiments above).

[0242] Fig. 22 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Fig. 22 The method is at least partially performed by one or more processing devices (e.g., Figure 1 Controller 124) to execute.

[0243] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0244] At block 2201, memory cells of one or more tiles in a memory array are programmed to store weights of a neural network. In one example, the memory cells are in memory cell array 113.

[0245] At block 2203, a portion (or all) of the tile is selected for multiplication. In one example, a portion of the tile 1202, 1912 is selected.

[0246] At block 2205, an input pattern is encoded for multiplication by a stored weight. In one example, the input pattern is time sliced. In one example, the input pattern is applied to a select line 808. In one example, the input pattern is applied to a word line 816.

[0247] At block 2207, weight multiplication by the input pattern is performed to provide one or more results. Each result is based on summing the output currents from the selected memory cells. In one example, the results are provided by accumulation circuitry (eg, 1230).

[0248] In one embodiment, a device includes: a memory cell array (e.g., 113) having vertically stacked memory cells, each memory cell being configured to store a weight used in a multiplication; a local digit line (e.g., 826) connected to a terminal of the memory cell, the local digit line extending vertically; a selection transistor (e.g., a transistor having a silicon layer 812) connected to the local digit line; a selection line (e.g., 808) configured to control the selection transistor and encode an input pattern to multiply the stored weight (e.g., Case 1 described above); and an accumulation circuit system (e.g., 1230) configured to accumulate output currents from the memory cells to determine a result of the multiplication.

[0249] In one embodiment, the device further includes a global digit line (eg, 804, 1204) extending horizontally in a direction orthogonal to the select line. The select transistor connects the global digit line to the local digit line, and the global digit line is used to accumulate the output current.

[0250] In one embodiment, the device further includes a word line (eg, 816) connected to the gates of the memory cells. The word line is configured to select at least a portion of the array for use in the multiplication.

[0251] In one embodiment, the word lines extend horizontally in a direction parallel to the select lines.

[0252] In one embodiment, the memory cells of the array are arranged in vertically stacked horizontal levels, and the word lines are further configured to select at least one level for use in the multiplication.

[0253] In one embodiment, the memory cells are arranged in vertical pillars, and each select transistor is located above the memory cell of a respective pillar.

[0254] In one embodiment, the local digit line is a first local digit line, the terminal is a first terminal, and the select transistor is a first select transistor. The device further includes: a second local digit line (e.g., 822) connected to a second terminal of the memory cell, the second local digit line extending vertically; and second select transistors connected to the second local digit line, wherein each second select transistor is located below the memory cell of a corresponding column.

[0255] In one embodiment, each memory cell is configured to store multiple bits (eg, three-level cell (TLC)).

[0256] In one embodiment, a device includes: a memory cell array having vertically stacked memory cells, each memory cell being configured to store a weight used in a multiplication, and each memory cell having a current channel extending in a horizontal direction (e.g., a channel provided by semiconductor layer 820); a word line connected to a gate of the memory cell, wherein the word line is configured to encode an input pattern to be multiplied by the stored weight (e.g., Case 2 described above); and an accumulation circuit system configured to accumulate output currents from the memory cells to determine a result of the multiplication.

[0257] In one embodiment, the apparatus further includes: local digit lines connected to terminals of the memory cells, the local digit lines (e.g., 708, 826, 1214) extending vertically; select transistors (e.g., 1206) connected to the local digit lines; and select lines (e.g., 1218) configured to control the select transistors to select a subset of the array for use in the multiplication (e.g., a controller uses the select lines to define the size of the physical array to use for any given multiplication).

[0258] In one embodiment, the apparatus further includes a controller (eg, 124) configured to dynamically select or deselect levels of the array to map to the input mode.

[0259] In one embodiment, the memory cells of the array are arranged in vertically stacked levels, and the output current is accumulated from multiple levels of the array.

[0260] In one embodiment, a first memory cell in a first pillar is used to represent a least significant bit (LSB) and at least two second memory cells of the first pillar are used to represent a most significant bit (MSB) (eg, 1500).

[0261] In one embodiment, the combined output current of the second memory cell is an integer multiple of the output current of the first memory cell (eg, the combined output current from two cells representing the MSB is twice the output current from a single cell representing the LSB).

[0262] In one embodiment, a device includes: a semiconductor substrate; a plurality of transistors stacked vertically into pillars above the substrate, each transistor including a semiconductor layer for providing a channel and a gate layer (e.g., gate stack layer 818) (e.g., ONO stack) surrounding at least half of the circumference of the semiconductor layer; and word lines (e.g., 816) (e.g., WL1, WL2) configured to apply a gate voltage to the transistors, wherein a portion of each word line surrounds at least half of the circumference of the gate layer of the corresponding transistor.

[0263] In one embodiment, the device further includes an isolation layer (eg, 828) electrically separating the word lines of each transistor in the pillar.

[0264] In one embodiment, the channel extends in a horizontal direction relative to the substrate.

[0265] In one embodiment, the apparatus further comprises: first local digit lines, wherein the first terminal of each transistor is connected to a corresponding first local digit line (eg, Fig. 9 and a second local digital line, wherein the second terminal of each transistor is connected to a corresponding second digital line (eg, Fig. 9 of LDL1', LDL2').

[0266] In one embodiment, the device further includes: local digital lines extending vertically above the substrate, wherein the first terminal of each transistor is connected to a corresponding local digital line (e.g., LDL1, LDL2); and selection transistors, wherein the corresponding selection transistor of each pillar (e.g., 1304, 1306) is located above the memory cell of the pillar, and each selection transistor is electrically connected to a corresponding local digital line.

[0267] In one embodiment, the device further includes: global digit lines (e.g., 1602) (e.g., GDL), wherein each global digit line is electrically connected to a corresponding local digit line (e.g., 1606), and wherein each global digit line extends in a horizontal direction relative to the substrate; and accumulation circuitry configured to accumulate output currents from selected ones of the transistors using the global digit lines when performing a multiplication operation.

[0268] In one embodiment, the device further includes local digit lines, wherein a first terminal of each transistor is connected to a respective local digit line (eg, LDL1, LDL2), and a common plate, wherein a second terminal of each transistor is connected to the common plate.

[0269] In one embodiment, word lines of a first memory cell are shorted together and the first memory cell is configured to represent a most significant bit (MSB) of a weight for a matrix-vector multiplication.

[0270] In one embodiment, the device further includes: a first local digital line extending vertically above the substrate, wherein the first terminal of each transistor in the first pillar is connected to a corresponding first local digital line (e.g., LDL1, LDL2); a second local digital line extending vertically above the substrate, wherein the second terminal of each transistor in the first pillar is connected to a corresponding second digital line (e.g., LDL1', LDL2'); and a third local digital line extending vertically above the substrate, wherein the first terminal of each transistor in the second pillar is connected to a corresponding third local digital line, and wherein the second terminal of each transistor in the second pillar is connected to one of the second local digital lines.

[0271] Integrated circuit device 101 (e.g., Figure 1 ) can be configured as a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0272] Integrated circuit device 101 (e.g., Figure 1 The image sensor (in the embodiment of the present invention) can be installed in a computing system as a memory subsystem with embedded image sensors and inference computing capabilities. Such a computing system can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a part of a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0273] Generally speaking, a computing system may include a memory system coupled to one or more memory subsystems (e.g., Figure 1In one example, the host system is coupled to a memory subsystem.

[0274] As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0275] For example, the host system may include a processor chipset (e.g., a processing device) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system uses a memory subsystem to write data to the memory subsystem and read data from the memory subsystem.

[0276] The host system may be coupled to the memory subsystem via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS) interface, a double data rate (DDR) memory bus interface, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM slot interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR) interface, a low power double data rate (LPDDR) interface, a compute express link (CXL) interface, or any other interface. The physical host interface may be used to transfer data between the host system and the memory subsystem. When the memory subsystem is coupled to the host system through a PCIe interface, the host system may further utilize an NVM express (NVMe) interface to access components (e.g., memory devices). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem and the host system. In general, a host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, or a combination of communication connections.

[0277] The processing device of the host system may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller may be referred to as a memory controller, a memory management unit, or an initiator. In one example, the controller controls communications on a bus coupled between the host system and the memory subsystem. Generally speaking, the controller may send commands or requests for desired access to the memory device to the memory subsystem. The controller may further include an interface circuit system for communicating with the memory subsystem. The interface circuit system may convert responses received from the memory subsystem into information for the host system.

[0278] The controller of the host system can communicate with the controller of the memory subsystem to perform operations such as reading data, writing data, or erasing data at the memory device and other such operations. In some examples, the controller is integrated into the same package of the processing device. In other examples, the controller is separated from the package of the processing device. The controller or processing device may include hardware, such as one or more integrated circuits (ICs), discrete components, buffer memory or cache memory, or a combination thereof. The controller or processing device may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0279] A memory device may include any combination of non-volatile memory components of different types and volatile memory components. A volatile memory device may be, but is not limited to, a random access memory (RAM) such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM).

[0280] Some examples of non-volatile memory components include NAND (or NOT AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0281] Each of the memory devices may include one or more arrays of memory cells. One type of memory cell (e.g., a single level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, PLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell, or any combination thereof. The memory cells of a memory device may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0282] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of non-volatile memory such as read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0283] A memory subsystem controller (or simply referred to as a controller) can communicate with a memory device to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device (e.g., in response to commands dispatched by the controller on a command bus). The controller may include hardware, such as one or more integrated circuits (ICs), discrete components, or buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0284] The controller may include a processing device (processor) configured to execute instructions stored in a local memory. In the illustrated example, the local memory of the controller includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem, including handling communications between the memory subsystem and the host system.

[0285] In some embodiments, the local memory may include memory registers that store memory pointers, fetched data, etc. The local memory may also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem includes a controller, in another embodiment of the present disclosure, the memory subsystem does not include a controller, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0286] In general, the controller may receive commands or operations from the host system and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device. The controller may be responsible for other operations associated with the memory device, such as wear leveling operations, obsolete item collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses). The controller may further include a host interface circuit system for communicating with the host system via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device, and convert responses associated with the memory device into information for the host system.

[0287] The memory subsystem may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from a controller and decode the addresses to access a memory device.

[0288] In some embodiments, a memory device includes a local media controller that operates in conjunction with a memory subsystem controller to perform operations on one or more memory cells of the memory device. An external controller (e.g., a memory subsystem controller) can manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local media controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0289] The controller or memory device may include a storage manager configured to implement the storage functions discussed above. In some embodiments, the controller in the memory subsystem includes at least a portion of the storage manager. In other embodiments or combinations, the controller or processing device in the host system includes at least a portion of the storage manager. For example, the controller or processing device may include logic circuitry that implements the storage manager. For example, the controller or processing device (processor) of the host system may be configured to execute instructions stored in the memory for performing the operations of the storage manager described herein. In some embodiments, the storage manager is implemented in an integrated circuit chip disposed in the memory subsystem. In other embodiments, the storage manager may be part of the firmware of the memory subsystem, the operating system of the host system, a device driver or application, or any combination thereof.

[0290] In one embodiment, an example machine of a computer system may execute within the machine a set of instructions for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system may correspond to a host system that includes, is coupled to, or utilizes a memory subsystem or can be used to perform the operations described above. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet, or any combination thereof. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0291] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a network attached storage facility, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0292] An example computer system includes a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory (SRAM), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0293] The processing device may be one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a processor implementing a combination of instruction sets. The processing device may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating over a network.

[0294] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The instructions may also reside completely or at least partially within the main memory and the processing device during execution by the computer system, the main memory and the processing device also constituting machine-readable storage media. The machine-readable medium, data storage system, or main memory may correspond to a memory subsystem.

[0295] In one embodiment, the instructions include instructions to implement functionality corresponding to the operations described above. Although the machine-readable medium is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0296] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Mainly for common purposes, it sometimes proves convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0297] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0298] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0299] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0300] In one embodiment, the memory device includes a voltage driver (e.g., Figure 2 203, 213, 223) and / or other components. The controller is instructed by firmware or other software. The software may be stored as instructions on a machine-readable medium, which may be used to program the controller. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0301] In this description, various functions and operations may be described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the meaning of such statements is that the functions are caused by one or more controllers or processors (such as microprocessors) executing computer instructions. Alternatively or in combination, the functions and operations may be implemented using dedicated circuit systems (such as using application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs)) with or without software instructions. Embodiments may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the technology is neither limited to any specific combination of hardware circuit systems and software, nor to any specific source of instructions executed by the data processing system.

[0302] Unless specifically stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" should be understood in the context as generally used to present items, terms, etc., to mean either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require the presence of at least one of X, at least one of Y, or at least one of Z, respectively.

[0303] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A device comprising: a memory cell array having stacked memory cells, each memory cell being configured to store a weight; and A select line is configured to control a select transistor and encode an input pattern to be multiplied by the stored weights.

2. The device according to claim 1, further comprising: a local digit line connected to a terminal of the memory cell, the local digit line extending vertically; and A global digit line extends horizontally in a direction orthogonal to the select line, wherein the select transistor connects the global digit line to the local digit line, and the global digit line is used to accumulate output currents from the memory cells.

3. The device of claim 1 , further comprising a word line connected to a gate of the memory cell, wherein: The word line is configured to select at least a portion of the array for use in multiplication; The word line extends horizontally in a direction parallel to the selection line; The memory cells of the array are arranged in vertically stacked horizontal levels; and The word line is further configured to select at least one level for use in the multiplication.

4. The device of claim 1 , wherein the memory cells are arranged in vertical pillars, and each select transistor is located above the memory cell of a respective pillar, and the select transistor is a first select transistor, the device further comprising: a first local digit line connected to a first terminal of the memory cell, the first local digit line extending vertically; a second local digit line connected to a second terminal of the memory cell, the second local digit line extending vertically; and Second selection transistors are connected to the second local digit line, wherein each second selection transistor is located under the memory cell of a corresponding pillar.

5. A device comprising: a memory cell array having vertically arranged memory cells, each memory cell being configured to store a weight, and each memory cell having a current channel extending in a horizontal direction; and A word line is connected to the gate of the memory cell, wherein the word line is configured to encode an input to be multiplied by the stored weight.

6. The apparatus according to claim 5, further comprising: a local digit line connected to a terminal of the memory cell, the local digit line extending vertically; a select transistor connected to the local digit line; and A select line is configured to control the select transistor to select a subset of the array for use in the multiplication.

7. The apparatus of claim 5, further comprising a controller configured to dynamically select or deselect a level of the array to map to the input, wherein: The memory cells of the array are arranged in vertically stacked levels, and output currents from the memory cells are accumulated from multiple levels of the array; A first memory cell in a first pillar is used to represent a least significant bit (LSB), and at least two second memory cells of said first pillar are used to represent a most significant bit (MSB); and The combined output current of the second memory cells is an integer multiple of the output current of the first memory cells.

8. An apparatus comprising: A plurality of transistors, each transistor comprising a semiconductor layer for providing a channel and a gate layer surrounding the semiconductor layer; and A word line is configured to apply a gate voltage to the transistor, wherein a portion of each word line surrounds the gate layer of a corresponding transistor.

9. The device of claim 8, wherein the transistor is configured above a semiconductor substrate and the channel extends in a horizontal direction relative to the substrate, the device further comprising an isolation layer electrically separating a word line of each transistor in a pillar.

10. The device of claim 8, wherein the transistors are arranged as pillars, the device further comprising: local digit lines extending vertically above the semiconductor substrate, wherein a first terminal of each transistor is connected to a respective local digit line; and Select transistors, wherein a respective select transistor for each pillar is located above the transistor of the pillar, and each select transistor is electrically connected to a respective local digit line.

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