Distributed power supply switching circuit for eFuse memory

Abstract

The invention provides a distributed power supply switching circuit for an eFuse memory. A global internal and external power supply conversion module comprises an external power supply VDD and an external power supply VQPS; the global internal and external power supply conversion module is connected with a signal PD and a signal PS; the distributed power domain switching module comprises an internal power supply VDDI, an internal power supply VQR, a first PMOS and a second PMOS; wherein the source electrode of the first PMOS is connected with an internal power supply VDDI, and the grid electrode of the first PMOS is connected with an internal power supply VQR; the source electrode of the second PMOS is connected with the internal power supply VQR, and the grid electrode of the second PMOS is connected with the internal power supply VDDI; the base electrodes and the drain electrodes of the first PMOS and the second PMOS are jointly connected with a node VLS; and the distributed power domain switching module supplies power to the word line or bit line control module through the node VLS. The possibility that an internal power supply supplies power to the node VLS at the same time does not occur in the power-off process of the circuit, and the risk of short circuit of the two power supplies is avoided. In addition, no extra signal is needed to control power supply switching, so that the risk of short circuit of two power supplies caused by delay of an original power supply switching control signal is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a distributed power supply switching circuit for an eFuse memory. Background Art

[0002] In different working modes, the eFuse memory will switch the power supply path as needed to ensure the normal function. In the read mode, the control signals of the word line and the bit line need to be powered by the lower potential core voltage V(core); in the programming mode, the control signals of the word line and the bit line need to be powered by the higher potential programming voltage V(prog).

[0003] The commonly used technologies in the industry are Figure 1 In the circuit shown, VDDI and VQR are two internal power supplies. VDDI is fed with V(core) potential by external power supply VDD, and VQR is fed with V(prog) potential by external power supply VQPS. They are respectively fed with VLS power supply to the local word line or bit line control module through two PMOS tubes. The gate of the PMOS tube is respectively controlled by two signals LG / HG, which are generated by PD and PS signals in the control module of the memory. For specific control logic and corresponding potentials, see Figure 2 In order to balance the VLS potential and enhance the power supply capability of adjacent modules, the distributed VLS are interconnected into a global power supply through metal wires.

[0004] However, the PMOS tubes connected to LG / HG are all large in size. When the memory capacity is large, a large number of power switching modules will be called. The gate capacitance of the LG / HG load is huge, and the driver of LG / HG controlled by PS must also be large. In addition, there is a large delay in the potential reversal of LG / HG at the near and far ends, especially when PS switches from 0 to 1, LG rises from 0 to a higher V(prog) slowly, while HG drops from a lower V(core) to 0 quickly. The two PMOS tubes are turned on at the same time, resulting in a short circuit between the VDDI and VQR power supplies. If the internal and external power switching modules operate at an intermediate voltage and continue to pass a large current, there may be a risk of IP failure or even chip burning. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a distributed power switching circuit for an eFuse memory, which is used to solve the problem in the prior art that when two PMOS tubes of the eFuse power switching control circuit are turned on at the same time, the two power supplies will be short-circuited.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a distributed power supply switching circuit for an eFuse memory, comprising at least:

[0007] A global internal and external power conversion module, including: an external power supply VDD and an external power supply VQPS; the global internal and external power conversion module is connected to a signal PD and a signal PS;

[0008] A distributed power domain switching module, comprising: an internal power supply VDDI and an internal power supply VQR, a first PMOS and a second PMOS; wherein the source of the first PMOS is connected to the internal power supply VDDI, and the gate thereof is connected to the internal power supply VQR; the source of the second PMOS is connected to the internal power supply VQR, and the gate thereof is connected to the internal power supply VDDI; the base and drain of the first PMOS and the second PMOS are commonly connected to a node VLS;

[0009] The word line or bit line control module, the distributed power domain switching module supplies power to the word line or bit line control module through the node VLS.

[0010] Preferably, the nodes VLS in the distributed power supply switching module are interconnected by metal wires to form a global internal power supply.

[0011] Preferably, when the signal PD is at a low level, the internal power supply VDDI is grounded, and the internal power supply VQR is grounded; when the signal PD is at a high level and the signal PS is at a low level, the potential of the internal power supply VDDI is V(core), and the internal power supply VQR is grounded; when the signal PD is at a high level and the signal PS is at a high level, the potential of the internal power supply VDDI is V(core), and the potential of the internal power supply VQR is V(prog), wherein V(core) is the core voltage and V(prog) is the programming voltage.

[0012] Preferably, the power supply mode of the global internal and external power conversion module to the internal power supply VDDI and the internal power supply VQR is: when the signal PD is at a high level, the external power supply to the internal power supply is cut off, and the internal power supply VDDI and the internal power supply VQR are both grounded; when the signal PD is at a low level and the signal PS is at a low level, the external power supply VDD supplies power to the internal power supply VDDI, and the internal power supply VQR is grounded; when the signal PD is at a low level and the signal PS is at a high level, the external power supply VDD supplies power to the internal power supply VDDI, and the external power supply VQPS supplies power to the internal power supply VQR.

[0013] Preferably, when the external power supply VDD and the external power supply VQPS are both powered on and stable normally, the signal PD is switched from a high level to a low level, and the signal PS is a low level. At this time, the external power supply VDD powers up the internal power supply VDDI to V(core), and the internal power supply VQR is still grounded. The first PMOS is turned on, and the second PMOS is turned off. At this time, the node VLS is maintained at the potential of V(core), and the eFuse memory operates in a read mode.

[0014] Preferably, when the signal PS is switched to a high level, the external power supply VQPS powers on the internal power supply VQR, and after the potential of the internal power supply VQR rises to be greater than V(core)-|Vth|, the first PMOS is turned off, and as the potential of the internal power supply VQR rises to be greater than V(core)+Vth, the P-well at the source of the second PMOS and the N-well of the substrate form a PN junction and are turned on, until the internal power supply VQR powers on the node VLS to V(prog)-Vth, the second PMOS is in an on state, and finally the potential of the node VLS rises and is maintained at V(prog), and the eFuse memory operates in a burning mode, where Vth is the threshold voltage of the PN junction.

[0015] Preferably, after the burning is completed, the signal PS is switched back from a high level to a low level, the external power supply VQPS turns off the power supply to the internal power supply VQR, and powers down the internal power supply VQR to a low level through the NMOS tube to the ground. After the potential of the internal power supply VQR drops to less than V(core)+|Vth|, the second PMOS is turned off, and after continuing to drop to V(core)-|Vth|, the first PMOS is turned on, the potential of the node VLS drops to V(core), and the eFuse memory operates in read mode.

[0016] Preferably, the distributed power supply switching circuit is used in a single-channel eFuse memory layout.

[0017] Preferably, the distributed power supply switching circuit is used in a multi-channel eFuse memory layout.

[0018] As described above, the distributed power switching circuit for eFuse memory of the present invention has the following beneficial effects: the present invention simplifies the control signal of the power switching module in the prior art, and controls the power selection of each other through the potential of the two internal power supplies VDDI and VQR. When the potential of the internal power supply VQR increases from 0 to V(prog), the node VLS can be switched to the internal power supply VQR for power supply, and the voltage is also increased to V(prog) at the same time; when the potential of VQR decreases from V(prog) to 0, VLS can be switched to VDDI for power supply, and the voltage is also reduced to V(core) at the same time. During the power-on and power-off process, the possibility of the internal power supplies VQR and VDDI supplying power to the node VLS at the same time will not occur, thus avoiding the risk of short circuit of the two power supplies. In addition, since there is no need to control the power switching by an additional signal, the risk of short circuit of the two power supplies caused by the delay of the original power switching control signal is avoided, and the generation logic and lines of the control signal are simplified, and the layout area is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a schematic diagram of an eFuse power switching control circuit in the prior art;

[0020] Figure 2 Display as Figure 1 The control logic of the circuit and the corresponding potential;

[0021] Figure 3 Shown is a circuit structure schematic diagram of a distributed power supply switching circuit for an eFuse memory of the present invention;

[0022] Figure 4 It is a schematic diagram showing a potential waveform when the distributed power supply switching circuit for eFuse memory of the present invention is boosted;

[0023] Figure 5 It is a schematic diagram showing a potential waveform when the distributed power supply switching circuit for the eFuse memory of the present invention is reduced in voltage. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] See also Figures 3 to 5It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0026] The present invention provides a distributed power supply switching circuit for an eFuse memory, such as Figure 3 As shown, including at least:

[0027] A global internal and external power conversion module (Power Switch), including: an external power supply VDD and an external power supply VQPS; the global internal and external power conversion module is connected to a signal PD and a signal PS;

[0028] A distributed power domain switching module, comprising: an internal power supply VDDI and an internal power supply VQR, a first PMOS (PM1) and a second PMOS (PM2); wherein the source of the first PMOS (PM1) is connected to the internal power supply VDDI, and the gate thereof is connected to the internal power supply VQR; the source of the second PMOS (PM2) is connected to the internal power supply VQR, and the gate thereof is connected to the internal power supply VDDI; the base and drain of the first PMOS (PM1) and the second PMOS (PM2) are commonly connected to a node VLS;

[0029] A word line or bit line control module (WL_DR / BL_DR), the distributed power domain switching module supplies power to the word line or bit line control module through a node VLS.

[0030] Furthermore, in the present invention, the nodes VLS in the distributed power supply switching module of this embodiment are interconnected by metal wires to form a global internal power supply.

[0031] The present invention further, in this embodiment, when the signal PD is at a low level (PD=0), the internal power supply VDDI is grounded (VDDI=0), and the internal power supply VQR is grounded (VQR=0); when the signal PD is at a high level (PD=1) and the signal PS is at a low level (PS=0), the potential of the internal power supply VDDI is V(core), and the internal power supply VQR is grounded (VQR=0); when the signal PD is at a high level (PD=1) and the signal PS is at a high level (PS=1), the potential of the internal power supply VDDI is V(core), and the potential of the internal power supply VQR is V(prog), wherein V(core) is the core voltage and V(prog) is the programming voltage.

[0032] The internal power supply VDDI controls the gate of the first PMOS (PM1) that switches on the internal power supply VQR access node VLS, and the internal power supply VQR controls the gate of the second PMOS (PM2) that switches on the internal power supply VDDI access node VLS.

[0033] The present invention further provides that the global internal and external power conversion module of this embodiment provides power to the internal power VDDI and the internal power VQR in the following power supply mode: when the signal PD is at a high level (PD=1), the external power supply to the internal power is cut off, and the internal power VDDI and the internal power VQR are both grounded (i.e., VDDI=0, VQR=0); when the signal PD is at a low level (PD=0) and the signal PS is at a low level (PS=0), the external power VDD supplies power to the internal power VDDI, and the internal power VQR is grounded (VQR=0); when the signal PD is at a low level (PD=0) and the signal PS is at a high level (PS=1), the external power VDD supplies power to the internal power VDDI, and the external power VQPS supplies power to the internal power VQR.

[0034] Power switching state: When the external power supply VDD and the external power supply VQPS are both powered on and stable normally, the signal PD is switched from a high level to a low level (i.e., PD=1 to PD=0), and the signal PS is a low level (PS=0). At this time, the external power supply VDD powers up the internal power supply VDDI to V(core), and the internal power supply VQR is still grounded (VQR=0). The first PMOS (PM1) is turned on, and the second PMOS (PM2) is turned off. At this time, the node VLS is maintained at the potential of V(core), and the eFuse memory operates in read mode.

[0035] The present invention further provides that, in this embodiment, when the signal PS is switched to a high level (PS=1), the external power supply VQPS powers on the internal power supply VQR, and the potential of the internal power supply VQR rises to a level greater than V(core)-|Vth| ( Figure 4 The first PMOS (PM1) is turned off, and as the potential of the internal power supply VQR rises to a value greater than V(core)+Vth ( Figure 4 b), the P well of the source of the second PMOS (PM2) forms a PN junction with the N well of the substrate and is turned on until the internal power supply VQR powers up the node VLS to V(prog)-Vth ( Figure 4Point c), since the programming voltage is often above 1.8V, V(prog)-Vth(PN junction)>V(core)+|Vth(PMOS)|, at this time |V(GS)|>|Vth|, so the second PMOS (PM2) is in the on state, and finally the potential of the node VLS rises and maintains to V(prog), and the eFuse memory works in the programming mode, where Vth is the threshold voltage of the PN junction, as shown in FIG. Figure 4 shown.

[0036] The present invention further, after the burning of the embodiment is completed, the signal PS is switched back from a high level to a low level (i.e., PS=1 to PS=0), the external power supply VQPS turns off the power supply to the internal power supply VQR, and the internal power supply VQR is powered down to a low level through the NMOS tube to the ground, and the potential of the internal power supply VQR drops to less than V(core)+|Vth| ( Figure 5 Point a), the second PMOS is turned off, and the voltage continues to drop to V(core)-|Vth| ( Figure 5 b), the first PMOS is turned on, the potential of the node VLS is reduced to V(core), and the eFuse memory works in the read mode, such as Figure 5 shown.

[0037] In the present invention, the distributed power switching circuit of this embodiment is used in a single-channel eFuse memory layout. In other embodiments, the distributed power switching circuit can also be used in a multi-channel eFuse memory layout.

[0038] Since this method of controlling power switching does not require the generation of LG / HG signals in the control module, a lot of area can be saved and used to strengthen other power or signal lines. In addition, since VDDI and VQR themselves have a strong enough power network throughout the entire memory, the potential of the near end and the far end is stable, which can effectively avoid the risk of short circuit caused by the simultaneous conduction of two power supplies when switching power.

[0039] In summary, the present invention simplifies the control signal of the power switching module in the prior art, and controls the power selection of each other through the potential of the two internal power supplies VDDI and VQR. When the potential of the internal power supply VQR increases from 0 to V(prog), the node VLS can be switched to the internal power supply VQR for power supply, and the voltage is also increased to V(prog) at the same time; when the potential of VQR decreases from V(prog) to 0, VLS can be switched to VDDI for power supply, and the voltage is also reduced to V(core) at the same time. During the power-on and power-off process, the possibility of the internal power supplies VQR and VDDI supplying power to the node VLS at the same time will not occur, thus avoiding the risk of short circuit of the two power supplies. In addition, since there is no need for an additional signal to control the power switching, the risk of short circuit of the two power supplies caused by the delay of the original power switching control signal is avoided, and the control signal generation logic and lines are simplified, and the layout area is reduced. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A distributed power switching circuit for an eFuse memory, characterized in that: At least: A global internal and external power conversion module, including: an external power supply VDD and an external power supply VQPS; the global internal and external power conversion module is connected to a signal PD and a signal PS; A distributed power domain switching module, comprising: an internal power supply VDDI and an internal power supply VQR, a first PMOS and a second PMOS; wherein the source of the first PMOS is connected to the internal power supply VDDI, and the gate thereof is connected to the internal power supply VQR; the source of the second PMOS is connected to the internal power supply VQR, and the gate thereof is connected to the internal power supply VDDI; the base and drain of the first PMOS and the second PMOS are commonly connected to a node VLS; The word line or bit line control module, the distributed power domain switching module supplies power to the word line or bit line control module through the node VLS.

2. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: The nodes VLS in the distributed power supply switching module are interconnected through metal wires to form a global internal power supply.

3. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: When the signal PD is at a low level, the internal power supply VDDI is grounded, and the internal power supply VQR is grounded; when the signal PD is at a high level and the signal PS is at a low level, the potential of the internal power supply VDDI is V(core), and the internal power supply VQR is grounded; when the signal PD is at a high level and the signal PS is at a high level, the potential of the internal power supply VDDI is V(core), and the potential of the internal power supply VQR is V(prog), wherein V(core) is the core voltage and V(prog) is the programming voltage.

4. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: The power supply mode of the global internal and external power conversion module to the internal power supply VDDI and the internal power supply VQR is: when the signal PD is at a high level, the external power supply to the internal power supply is cut off, and the internal power supply VDDI and the internal power supply VQR are both grounded; when the signal PD is at a low level and the signal PS is at a low level, the external power supply VDD supplies power to the internal power supply VDDI, and the internal power supply VQR is grounded; when the signal PD is at a low level and the signal PS is at a high level, the external power supply VDD supplies power to the internal power supply VDDI, and the external power supply VQPS supplies power to the internal power supply VQR.

5. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: When the external power supply VDD and the external power supply VQPS are both powered on and stable normally, the signal PD is switched from a high level to a low level, and the signal PS is a low level. At this time, the external power supply VDD powers up the internal power supply VDDI to V(core), and the internal power supply VQR is still grounded. The first PMOS is turned on, and the second PMOS is turned off. At this time, the node VLS is maintained at the potential of V(core), and the eFuse memory operates in a read mode.

6. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: When the signal PS is switched to a high level, the external power supply VQPS powers on the internal power supply VQR. After the potential of the internal power supply VQR rises to a value greater than V(core)-|Vth|, the first PMOS is turned off. As the potential of the internal power supply VQR rises to a value greater than V(core)+Vth, the P-well at the source of the second PMOS and the N-well of the substrate form a PN junction and are turned on until the internal power supply VQR powers on the node VLS to V(prog)-Vth. The second PMOS is in an on state. Finally, the potential of the node VLS rises and is maintained at V(prog). The eFuse memory operates in a burning mode, where Vth is the threshold voltage of the PN junction.

7. The distributed power switching circuit for eFuse memory according to claim 6, characterized in that: After the burning is completed, the signal PS switches back from a high level to a low level, the external power supply VQPS turns off the power supply to the internal power supply VQR, and powers down the internal power supply VQR to a low level through the NMOS tube to the ground. After the potential of the internal power supply VQR drops to less than V(core)+|Vth|, the second PMOS is turned off, and after continuing to drop to V(core)-|Vth|, the first PMOS is turned on, the potential of the node VLS drops to V(core), and the eFuse memory works in a read mode.

8. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: The distributed power supply switching circuit is used in a single-channel eFuse memory layout.

9. The distributed power switching circuit for eFuse memory according to claim 1, characterized in that: The distributed power supply switching circuit is used in a multi-channel eFuse memory layout.

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