Method for testing data retention characteristic of flash memory

Abstract

The invention provides a method for testing data retention characteristics of a flash memory. Reading operation is carried out before baking, and firstly, memory units which are unqualified in erasing and programming are screened and eliminated according to a first current boundary; on the basis that the storage units with unqualified data retention characteristics are screened and eliminated according to a second current boundary through reading operation after baking for a preset time, the storage units which are not eliminated through large screening before and after baking are divided into different current triggering gear intervals according to the current magnitude; calculating a difference value of the triggering gears before and after baking of the same storage unit, and if the difference value is greater than or equal to a preset gear offset, judging that the data retention characteristic is unqualified; and if the difference value is smaller than the preset gear offset, judging that the gear is qualified. And the test is more accurate by combining large screening of boundaries before and after baking with current triggering gear interval division. And under the condition of ensuring that the yield is not lost, chips with relatively poor data retention characteristics are more effectively screened out in a wafer test stage, and the quality of flash memory products is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for testing flash memory data retention characteristics. Background Art

[0002] With the development of the electronic product market, flash memory has been widely used as the main storage in mobile phones, digital cameras and other products, and the market size is constantly expanding. An important design indicator for measuring the quality of flash memory is the data retention characteristic, that is, the stored data must be able to be stored for more than 10 years. Flash memory stores data based on the principle of charge storage. The stored charge will gradually be lost after a long time, resulting in data errors. In certain cases, the data cannot be stored for more than 10 years. The data retention characteristics of flash memory are generally measured by high-temperature accelerated tests to accelerate the loss rate of stored charge. When the amount of charge loss exceeds a certain range, the stored data will change from 0 to 1. By detecting whether the stored data has changed, it is deduced whether the data can be stored for more than 10 years.

[0003] A method for screening flash memory data retention characteristics, the screening conditions are relatively rough, and can roughly screen out chips that are prone to aging, but are not precise enough, and some flash memory units with poor data retention characteristics cannot be screened out. Summary of the invention

[0004] The purpose of the present invention is to provide a method for testing the data retention characteristics of flash memory, which makes the test more accurate by combining the large boundary screening before and after baking with the current trigger gear interval division, and more effectively screens out chips that are prone to aging. While ensuring that the yield is not lost, it is more effective to screen out chips with relatively poor data retention characteristics during the wafer testing stage, thereby improving the quality of flash memory products.

[0005] The present invention provides a method for testing the data retention characteristics of a flash memory, comprising:

[0006] S1. performing a read operation on all memory cells to be tested in the flash memory at a first temperature to obtain first read currents corresponding to all memory cells to be tested;

[0007] S2, the memory cells whose first read current triggering gear is less than the first current boundary are judged as unqualified and eliminated, and the memory cells that fail to be erased and programmed are eliminated; the memory cells whose first read current is greater than or equal to the first current boundary are not eliminated, and are divided into several different current gear intervals according to the current size;

[0008] S3, baking the flash memory at the second temperature for a preset time, then cooling it to a third temperature, and performing a read operation on all the memory cells to be tested at the third temperature to obtain a second read current trigger position corresponding to each of the memory cells to be tested;

[0009] S4, the storage unit whose second read current triggering gear is less than the second current boundary is judged as having unqualified data retention characteristics and eliminated; the storage unit whose second read current triggering gear is greater than or equal to the second current boundary is not eliminated, and is divided into a number of different current triggering gear intervals according to the current triggering gear size;

[0010] S5. Calculate the difference between the first read current trigger level and the second read current trigger level of the same storage unit in different current trigger level intervals; if the difference is ≥ a preset level offset, determine that the data retention characteristic of the storage unit is unqualified; if the difference is < the preset level offset, determine that the data retention characteristic of the storage unit is qualified.

[0011] Furthermore, the first temperature has a value range of 10°C to 150°C.

[0012] Furthermore, the second temperature has a value range of 200°C to 500°C, the preset time has a value range of 48 hours to 240 hours, and the third temperature has a value range of 10°C to 150°C.

[0013] Furthermore, the first current boundary is a first preset percentage of a reference current Iref of a standard memory cell, and the second current boundary is smaller than the first current boundary.

[0014] Furthermore, the value range of the first preset percentage is 55% to 75%.

[0015] Furthermore, the second current boundary is a second preset percentage of the reference current Iref of the standard storage unit, and the value range of the second preset percentage is 50% to 70%.

[0016] Furthermore, the preset gear offset has a value range of: Iref*2% to Iref*10%.

[0017] Furthermore, in step S2, the range from the maximum value Iref*100% to the first current boundary is divided into a number of different current ranges according to the current trigger range size.

[0018] Furthermore, in step S2, the storage units whose first read current triggering gear is greater than or equal to the first current boundary are not eliminated, and are divided into several different current gear intervals according to the current triggering gear size, specifically including:

[0019] Raise the current boundary trigger gear. If the first read current trigger gear of the same storage unit is ≥ the first current boundary trigger gear after the increase, it will not be eliminated. Continue to raise the current boundary trigger gear until the first read current trigger gear of the same storage unit is < the latest current boundary trigger gear. Then the gear of the same storage unit is determined, and the gear upper limit is the latest current boundary, and the gear lower limit is the difference between the latest current boundary and the preset gear offset.

[0020] The current-triggered gear division method in step S4 is the same as that in step S2.

[0021] Furthermore, the read current obtained by the read operation is the drain current when the gate-source voltage Vgs of the memory cell is a predetermined voltage.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention provides a method for testing the data retention characteristics of a flash memory. The present invention firstly screens the first read current trigger gear before baking according to the first current boundary, eliminates the storage units that fail to be erased and programmed, and then divides the storage units that are not eliminated by the large screening into several different current gear intervals according to the size of the current trigger gear. The second read current trigger gear after baking is firstly screened according to the second current boundary, eliminates the storage units that fail to be eliminated by the large screening, and then divides the storage units that are not eliminated by the large screening into several different current gear intervals according to the size of the current trigger gear. The difference between the first read current trigger gear and the second read current trigger gear of the same storage unit in different current gear intervals is calculated. If the difference is ≥ the preset gear offset, it is judged that the data retention characteristics of the storage unit are unqualified; if the difference is < the preset gear offset, it is judged that the data retention characteristics of the storage unit are qualified.

[0024] The present invention is based on the first read current trigger gear being screened according to the first current boundary before baking, and the second read current trigger gear being screened according to the second current boundary after baking. In addition, the storage units that are not eliminated by the large screening before and after baking are divided into several different current gear intervals according to the current size, and the difference of the read current trigger gear before and after baking of the same storage unit in different current gear intervals is calculated. The test is more accurate and more effective in screening chips that are prone to aging through the current gear interval division. While ensuring that the yield is not lost, it is more effective to screen out chips with relatively poor data retention characteristics in the wafer testing stage. Under the demand for zero defects in automotive electronic products, the quality of flash memory products is better improved and the product competitiveness is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1The figure is a flow chart of a method for testing the data retention characteristics of a flash memory according to an embodiment of the present invention.

[0026] Figure 2 The figure is a schematic diagram of the principle of a read operation in a method for testing the data retention characteristics of a flash memory according to an embodiment of the present invention.

[0027] Figure 3 It is a schematic diagram of comparison of read current before and after baking in a method for testing data retention characteristics of a flash memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background technology, a method for screening the data retention characteristics of a flash memory has relatively rough screening conditions, which can roughly screen out chips that are prone to aging, but is not accurate enough, and some flash memory cells with poor data retention characteristics cannot be screened out. Specifically, it includes: before baking, a read operation is performed on all the memory cells to be tested in the flash memory to obtain the corresponding pre-baking read currents of all the memory cells to be tested. The reference current Iref of the standard memory cell is used as a reference, and the memory cells with a pre-baking read current <Iref*55% are judged as unqualified; the memory cells with a pre-baking read current ≥Iref*55% are judged as qualified. After baking, a read operation is performed on all the memory cells to be tested in the flash memory to obtain the corresponding post-baking read currents of all the memory cells to be tested. The memory cells with a post-baking read current <Iref*50% are judged as unqualified; the memory cells with a post-baking read current ≥Iref*50% are judged as qualified. Before and after baking, the percentage boundary of the reference current is reduced from Iref*55% to Iref*50%, and the reduced Iref*5% is used as the threshold value of the read current change caused by baking. This screening method is not accurate enough. For example, a memory cell has a read current of Iref*85% before baking and a read current of Iref*65% after baking. According to the existing judgment standard, both before and after baking are qualified, but the actual change in the read current caused by baking has reached Iref*20%, which is seriously exceeded. The flash memory cell with poor data retention characteristics is not screened out. Therefore, the one-size-fits-all method that only relies on the percentage boundary of the reference current set before and after baking cannot accurately test the data retention characteristics of the flash memory.

[0029] In view of the above problems, the present invention provides a method for testing the data retention characteristics of a flash memory. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0031] The embodiment of the present invention provides a method for testing the data retention characteristics of a flash memory, such as Figure 1 As shown, including:

[0032] S1. Performing a read operation on all memory cells to be tested in the flash memory at a first temperature to obtain first read current trigger positions corresponding to all memory cells to be tested;

[0033] S2, judging the memory cells whose first read current trigger level is less than the first current boundary as unqualified and eliminating them, and eliminating the memory cells that fail to be erased and programmed; not eliminating the memory cells whose first read current trigger level is greater than or equal to the first current boundary, and dividing them into several different current trigger level intervals according to the current trigger level size;

[0034] S3, baking the flash memory at the second temperature for a preset time, then cooling it to a third temperature, and performing a read operation on all the memory cells to be tested at the third temperature to obtain the second read current trigger gear corresponding to each of the memory cells to be tested;

[0035] S4, the memory cells whose second read current triggering gear is less than the second current boundary are judged as having unqualified data retention characteristics and are eliminated; the memory cells whose second read current triggering gear is greater than or equal to the second current boundary are not eliminated, and are divided into several different current triggering gear intervals according to the current triggering gear size;

[0036] S5. Calculate the difference between the first read current trigger level and the second read current trigger level of the same storage unit in different current trigger level intervals. If the difference is ≥ the preset level offset, the data retention characteristic of the storage unit is judged to be unqualified; if the difference is < the preset level offset, it is judged to be qualified.

[0037] The memory cell of the flash memory is, for example, a MOS transistor with a floating gate structure. The working principle is to store or release data by injecting or releasing charges into the floating gate to change the threshold voltage of the memory cell. The erasing process is to apply a reverse voltage to the control gate and the substrate to pull the charge out of the floating gate through the tunnel effect. Programming "0" is to inject charges into the floating gate through the channel effect by applying a voltage to the control gate and the bit line.

[0038] The data retention of the flash memory cell itself will be affected by the following aspects: First, as the programming / erase cycles increase, the tunneling oxide layer will cause trapped charges to be generated. These charges affect the threshold voltage of the storage cell and become unstable. When trapped charges appear, the threshold voltage will drift. Second, as time goes by, the charges in the floating gate will leak through the tunneling oxide layer, gate sidewalls and other pathways, causing the threshold voltage to shift and eventually causing the "1" or "0" cell to reverse. Third, the tunneling oxide layer will cause TDDB (time-dependent dielectric breakdown) or dielectric aging under the action of voltage and electric field, resulting in bit data errors.

[0039] Specifically, in steps S1 and S3, a read operation is performed on all memory cells to be tested. The read operation method is the same, except that step S1 is a read operation before the flash memory is baked, and step S3 is a read operation after the flash memory is baked. The read operation obtains the read current I corresponding to each of the memory cells to be tested. The read current I can be understood as the drain current when the gate-source voltage Vgs of the memory cell is a predetermined voltage. Figure 2 As shown, the read operation can use a flash memory read circuit to apply a certain read voltage V to the memory cell M0 of the flash memory, compare the read current I of the memory cell M0 with the reference current Iref through the sense amplifier, and then output the comparison result at the output terminal Do. By testing all the memory cells in the entire memory array, the data retention characteristics of the entire memory chip can be obtained.

[0040] Step S1, at a first temperature, read all the memory cells to be tested in the flash memory to obtain the first read current trigger gear corresponding to each of the memory cells to be tested. The reference current of the standard memory cell is used as a reference, and the first read current trigger gear corresponding to each of the memory cells to be tested has certain differences or fluctuations. The first temperature value range is optional: 10℃~150℃; the first temperature can be set according to actual needs without limitation.

[0041] Step S2, all the memory cells to be tested are screened according to the first current boundary, and the memory cells whose first read current trigger level is less than the first current boundary are judged as unqualified and eliminated, so as to eliminate the memory cells that fail to be erased and programmed; the memory cells whose first read current trigger level is greater than or equal to the first current boundary are not eliminated, and are divided into several different current trigger level intervals according to the current trigger level size. The reference current Iref of the standard memory cell is used as a reference. The first current boundary is the first preset percentage of the reference current Iref, and the first preset percentage is selected according to actual needs. The value range of the first preset percentage can be selected from 55% to 75%. The larger the first current boundary, the more stringent the screening; in this example, the first current boundary is, for example, Iref*55%.

[0042] Exemplarily, a memory cell with a first read current trigger level < Iref*55% is judged as unqualified and eliminated; a memory cell with a first read current trigger level ≥ Iref*55% is not eliminated and is divided into respective corresponding current trigger level intervals according to the current trigger level. From the maximum value Iref*100% to the first current boundary, the current level is divided into several different current trigger level intervals according to the current level.

[0043] Different current trigger gear intervals include, for example: [Iref*95%~Iref*100%], [Iref*90%~Iref*95%), [Iref*85%~Iref*90%), [Iref*80%~Iref*85%), [Iref*75%~Iref*80%), [Iref*70%~Iref*75%), [Iref*65%~Iref*70%), [Iref*60%~Iref*65%), [Iref*55%~Iref*60%). The preset gear offset value range is: Iref*2%~Iref*10%. The preset gear offset is the difference between the maximum value and the minimum value of each current trigger gear interval. In this example, the preset gear offset is based on Iref*5% as one gear; in other examples, it can be set according to actual needs without limitation.

[0044] In step S2, the storage units that are not eliminated after large screening are divided into respective corresponding current triggering gear intervals according to the current triggering gear size. Specifically, it includes:

[0045] Increase the current boundary trigger gear. If the first read current trigger gear of the same storage unit is ≥ the increased first current boundary trigger gear, it will not be eliminated. Continue to increase the current boundary trigger gear until the first read current trigger gear of the same storage unit is < the latest current boundary trigger gear. Then the gear of the same storage unit is determined, and the gear upper limit is the latest current boundary, and the gear lower limit is the difference between the latest current boundary and the preset gear offset.

[0046] Exemplarily, a storage unit is not eliminated when it enters the relatively loose screening conditions (for example, the first read current trigger level of the storage unit is ≥Iref*55%); then, the conditions are tightened to increase the current boundary trigger level, for example, the first current boundary trigger level after being increased is changed to Iref*60%; if the first read current trigger level of the storage unit is still ≥Iref*60%, the conditions are further tightened to increase the current boundary trigger level, for example, the second current boundary trigger level after being increased is changed to Iref*65%, for example, the third current boundary trigger level after being increased is changed to Iref*70%, until the first read current trigger level of the same storage unit is less than the latest current boundary trigger level, then the level of the storage unit is determined, and the upper limit of the level is the latest current boundary trigger level, and the lower limit of the level is the difference between the latest current boundary trigger level and the preset level offset.

[0047] Increase the current boundary. If the first read current trigger level of the same storage unit is less than the first current boundary trigger level after the increase, the level of the storage unit is determined, and the upper limit of the level is the first current boundary trigger level after the increase, and the lower limit of the level is the first current boundary. Exemplarily, if the first read current trigger level of the storage unit is less than Iref*60%, the level of the storage unit is determined and is within the level of [Iref*55%~Iref*60%).

[0048] There are many chips on a flash memory wafer, and each chip has tens of thousands of storage cells. Therefore, it is a huge workload to perform a read operation on all the storage cells to be tested in the flash memory and obtain the first read current corresponding to each of the storage cells to be tested. In steps S1 and S2, the first read current obtained at the moment of the read operation is compared with the first current boundary, and the current is divided into several different current ranges according to the current size, and the storage cells in the same current range can be distinguished by the same color mark; in steps S1 and S2, there is no need to store or display the specific value of the first read current for a long time. In actual work, the first read current is obtained instantly through the read operation, and the storage cells in different current ranges can be quickly classified.

[0049] S3. After baking the flash memory at the second temperature for a preset time, cool it down to the third temperature, and perform a read operation on all the memory cells to be tested at the third temperature to obtain the second read current corresponding to all the memory cells to be tested. The second temperature value range is optional: 200℃~500℃; the preset time value range is optional: 48 hours~240 hours; in one example, baking at 250℃ for 72 hours. The second temperature and preset time can be set according to actual needs without limitation. The third temperature value range is: 10℃~150℃.

[0050] The high temperature test of baking is used to accelerate the loss rate of the stored charge of the memory cell. The memory cell with poor data retention characteristics loses a large amount of stored charge, resulting in a significant decrease in the read current compared to before baking. The memory cell with good data retention characteristics basically does not lose the stored charge, and the read current does not change significantly.

[0051] S4, the storage unit whose second read current trigger gear is less than the second current boundary is judged as having unqualified data retention characteristics and eliminated; the storage unit whose second read current trigger gear is greater than or equal to the second current boundary is not eliminated, and is divided into several different current trigger gear intervals according to the current trigger gear size. In steps S3 and S4, there is no need to store or display the second read current value for a long time. In actual work, the second read current trigger gear is obtained instantly through the read operation, and the storage units in different current gear intervals can be quickly classified. The second current boundary is less than the first current boundary. The second current boundary is the second preset percentage of the reference current Iref. The second preset percentage is selected according to actual needs. The value range of the second preset percentage can be selected: 50% to 70%. The larger the second current boundary, the more stringent the screening; in this example, the second current boundary is, for example, Iref*50%.

[0052] Exemplarily, the memory cells whose second read current triggering gear is less than Iref*50% are judged as unqualified and eliminated; the memory cells whose second read current triggering gear is greater than or equal to Iref*50% are not eliminated, and are divided into respective corresponding current triggering gear intervals according to the current triggering gear size, with the reference current Iref of the standard memory cell as the reference. The current gear interval division in step S4 can be performed with reference to step S2.

[0053] Different current triggering gear intervals include, for example: [Iref*90%~Iref*95%), [Iref*85%~Iref*90%), [Iref*80%~Iref*85%), [Iref*75%~Iref*80%), [Iref*70%~Iref*75%), [Iref*65%~Iref*70%), [Iref*60%~Iref*65%), [Iref*55%~Iref*60%), [Iref*50%~Iref*55%). In this example, Iref*5% is one gear. In other examples, it can be set according to actual needs without limitation.

[0054] S5. Calculate the difference between the first read current trigger level and the second read current trigger level of the same storage unit in different current trigger level intervals. If the difference is ≥ the preset level offset, the data retention characteristic of the storage unit is judged to be unqualified; if the difference is < the preset level offset, the data retention characteristic of the storage unit is judged to be qualified. The preset level offset value range is optional: Iref*2%~Iref*10%. The preset level offset can be set according to actual needs without restriction. Figure 3 As shown, several memory cells are tested. The first read current of the same memory cell before baking is 43.68μA (marked in yellow), and the second read current after baking is 27.97μA (marked in yellow), which is greater than Iref*50%. It cannot be eliminated in step S4, but the difference between the first read current and the second read current in step S5 is ≥ the preset gear offset, so the data retention characteristic of the memory cell is judged to be unqualified; It can be seen that Figure 3 If the reading current of other memory cells before and after baking has no obvious change, and the difference of the reading current of other memory cells before and after baking is less than the preset gear offset, it is judged that the data retention characteristics of other memory cells are qualified.

[0055] In summary, the present invention provides a method for testing the data retention characteristics of a flash memory. The present invention firstly screens the first read current trigger gear before baking according to the first current boundary, eliminates the storage cells that fail to be erased and programmed, and then divides the storage cells that are not eliminated by the large screening into several different current gear intervals according to the size of the current trigger gear. The second read current trigger gear after baking is firstly screened according to the second current boundary, eliminates the storage cells that fail to meet the data retention characteristics, and then divides the storage cells that are not eliminated by the large screening into several different current gear intervals according to the size of the current trigger gear. The difference between the first read current trigger gear and the second read current trigger gear of the same storage cell in different current gear intervals is calculated. If the difference is ≥ the preset gear offset, it is judged that the data retention characteristics of the storage cell are unqualified; if the difference is < the preset gear offset, it is judged that the data retention characteristics of the storage cell are qualified.

[0056] The present invention is based on the first read current trigger gear being screened according to the first current boundary before baking, and the second read current trigger gear being screened according to the second current boundary after baking. In addition, the storage units that are not eliminated by the large screening before and after baking are divided into several different current gear intervals according to the current size, and the difference of the read current trigger gear before and after baking of the same storage unit in different current gear intervals is calculated. The test is more accurate and more effective in screening chips that are prone to aging through the current gear interval division. While ensuring that the yield is not lost, it is more effective to screen out chips with relatively poor data retention characteristics in the wafer testing stage. Under the demand for zero defects in automotive electronic products, the quality of flash memory products is better improved and the product competitiveness is enhanced.

[0057] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0058] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for testing the data retention characteristics of a flash memory, characterized in that: include: S1. Performing a read operation on all memory cells to be tested in the flash memory at a first temperature to obtain first read current trigger positions corresponding to all memory cells to be tested; S2, the memory cells whose first read current trigger level is less than the first current boundary are judged as unqualified and eliminated, so as to eliminate the memory cells that fail to be erased and programmed; the memory cells whose first read current trigger level is greater than or equal to the first current boundary are not eliminated, and are divided into several different current trigger level intervals according to the current trigger level; S3, baking the flash memory at the second temperature for a preset time, then cooling it to a third temperature, and performing a read operation on all the memory cells to be tested at the third temperature to obtain a second read current trigger position corresponding to each of the memory cells to be tested; S4, the storage unit whose second read current triggering gear is less than the second current boundary is judged as having unqualified data retention characteristics and eliminated; the storage unit whose second read current triggering gear is greater than or equal to the second current boundary is not eliminated, and is divided into a number of different current triggering gear intervals according to the current triggering gear size; S5. Calculate the difference between the first read current trigger level and the second read current trigger level of the same storage unit in different current trigger level intervals; if the difference is ≥ a preset level offset, determine that the data retention characteristic of the storage unit is unqualified; if the difference is < the preset level offset, determine that the data retention characteristic of the storage unit is qualified.

2. The method for testing the data retention characteristics of a flash memory as claimed in claim 1, wherein: The first temperature has a value range of 10°C to 150°C.

3. The method for testing the data retention characteristics of a flash memory as claimed in claim 1, characterized in that: The second temperature has a value range of 200°C to 500°C, the preset time has a value range of 48 hours to 240 hours; the third temperature has a value range of 10°C to 150°C.

4. The method for testing the data retention characteristics of a flash memory as claimed in claim 1, wherein: The first current boundary is a first preset percentage of a reference current Iref of a standard memory cell, and the second current boundary is smaller than the first current boundary.

5. The method for testing the data retention characteristics of a flash memory as claimed in claim 4, characterized in that: The value range of the first preset percentage is 55% to 75%.

6. The method for testing the data retention characteristics of a flash memory as claimed in claim 5, characterized in that: The second current boundary is a second preset percentage of the reference current Iref of the standard storage unit, and the value range of the second preset percentage is 50% to 70%.

7. The method for testing the data retention characteristics of a flash memory as claimed in claim 4, characterized in that: The preset gear offset value range is: Iref*2% to Iref*10%.

8. The method for testing the data retention characteristics of a flash memory as claimed in claim 4, characterized in that: In step S2, the range from the maximum value Iref*100% to the first current boundary is divided into a number of different current ranges according to the current trigger range size.

9. The method for testing the data retention characteristics of a flash memory as claimed in claim 1, characterized in that: In step S2, the storage units whose first read current triggering gear is greater than or equal to the first current boundary are not eliminated, and are divided into a number of different current gear intervals according to the current triggering gear size, specifically including: Raise the current boundary trigger gear. If the first read current trigger gear of the same storage unit is ≥ the first current boundary trigger gear after the increase, it will not be eliminated. Continue to raise the current boundary trigger gear until the first read current trigger gear of the same storage unit is < the latest current boundary trigger gear. Then the gear of the same storage unit is determined, and the gear upper limit is the latest current boundary trigger gear, and the gear lower limit is the difference between the latest current boundary trigger gear and the preset gear offset. The current-triggered gear division method in step S4 is the same as that in step S2.

10. The method for testing the data retention characteristics of a flash memory according to claim 1, wherein: The read current obtained by the read operation is the drain current of the memory cell when the gate-source voltage Vgs is a predetermined voltage.

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