Method for evaluating metal pollution in wafer process and test structure

Abstract

The invention relates to a method for evaluating wafer process metal pollution and a test structure, and the method comprises the steps: obtaining a test structure which comprises an N-type region and a P-type region which extend from a first main surface of a semiconductor substrate to the interior of the semiconductor substrate; performing a to-be-evaluated process on the test structure; heat treatment is carried out on the test structure after the to-be-evaluated process, and when heat treatment starts, the concentration of majority carriers of a first region, exposed out of the first main face, of the P-type region is larger than that of majority carriers of a second region, exposed out of the first main face, of the N-type region; cleaning the test structure by using an acidic cleaning solution after the heat treatment; the metal defects of the cleaned test structure are detected through defect detection equipment, and the more the detected metal defects are, the more serious the metal pollution is. Compared with a traditional ICP-MS testing method, the method has the advantages of being more direct in result and more representative.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for evaluating metal contamination in a wafer process, and also to a test structure. Background Art

[0002] As the critical dimensions of semiconductor manufacturing processes become smaller and smaller, environmental trace element pollution control has become an important issue for semiconductor chip manufacturing plants (Fabs). Different metal contaminations can lead to defects for different reasons, so the metal impurity content in wafer manufacturing must be strictly analyzed and controlled.

[0003] However, the traditional inductively coupled plasma mass spectrometry (ICP-MS) offline testing method for testing metal contamination has the problems of long response time and low efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a method to evaluate metal contamination in wafer processes.

[0005] A method for evaluating metal contamination in a wafer process comprises: obtaining a test structure, the test structure comprising an N-type region extending from a first main surface of a semiconductor substrate into the semiconductor substrate and a P-type region extending from the first main surface of the semiconductor substrate into the semiconductor substrate; performing a process to be evaluated on the test structure; performing a heat treatment on the test structure after the process to be evaluated, wherein at the beginning of the heat treatment, the concentration of majority carriers in a first region of the P-type region exposed on the first main surface is greater than the concentration of majority carriers in a second region of the N-type region exposed on the first main surface; cleaning the test structure with an acidic cleaning solution after the heat treatment; and detecting metal defects in the cleaned test structure by a defect detection device, wherein a greater number of metal defects detected indicates more serious metal contamination.

[0006] The above-mentioned method for evaluating metal contamination in wafer processes is to perform the process to be evaluated on the test structure. If the process to be evaluated brings about metal contamination, the metal elements introduced by the contamination will react with the semiconductor substrate during heat treatment to form alloy defects. That is, the metal elements introduced by the contamination will be adsorbed on the surface of the semiconductor substrate, and they will exchange electrons with the semiconductor elements in the semiconductor substrate during the thermal process, and then react electrochemically with the cleaning solution. Specifically, the electrons in the N-type region will migrate and gather in the P-type region. After obtaining the electrons, the metal ions will precipitate in the P-type doped region and form metal defects with the metal element as the core and containing the semiconductor element and O. And the doping of the P-type doped region can accelerate the diffusion of the contaminated metal and help form the metal precipitation defect. Then, the metal contamination can be quantitatively analyzed and evaluated through the defect detection equipment.

[0007] In one embodiment, the semiconductor substrate is a silicon substrate.

[0008] In one embodiment, the N-type region includes an N-well, the P-type region includes a P-well, and after the process to be evaluated and before the heat treatment, it also includes: doping P-type ions in the P-well to form a P-type doped region, the doping concentration of the P-type doped region is greater than the doping concentration of the P-well, and the first region includes the P-type doped region.

[0009] In one of the embodiments, an N-type doping region is formed in the N-well before the heat treatment step, and the doping concentration of the N-type doping region is greater than the doping concentration of the N-well.

[0010] In one embodiment, the N-type doped region is formed by doping N-type ions after the process to be evaluated and before the heat treatment.

[0011] In one embodiment, the test structure further includes a first isolation structure located between the N-well and the P-well.

[0012] In one embodiment, the first isolation structure is a shallow trench isolation structure.

[0013] In one embodiment, the step of obtaining the test structure includes forming a shallow trench isolation structure, and forming the N-well and the P-well; the step of forming the shallow trench isolation structure includes: forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; photolithography and etching to form a trench; filling the trench with insulating material; performing a planarization process; and removing the silicon nitride layer.

[0014] In one embodiment, for the process equipment used in the process of forming the shallow trench isolation structure, before the process starts, each process chamber has less than 20 attached particles with a size not less than 0.2 microns and less than 10 particles with a size not less than 1 micron.

[0015] In one embodiment, the first isolation structure forms a closed structure on a plane, and the inner side of the closed structure is the P-well; the test structure also includes a second isolation structure surrounding the first isolation structure, and the second isolation structure forms a closed structure on a plane, and the N-well is between the first isolation structure and the second isolation structure.

[0016] In one embodiment, the step of doping P-type ions includes implanting boron ions using an ion implantation process.

[0017] In one embodiment, the acidic cleaning solution includes hydrofluoric acid.

[0018] In one embodiment, the step of forming the N-well and the P-well comprises: implanting phosphorus ions with an implantation energy of 130 KeV to 180 KeV and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2 ; implant boron ions, the implant energy is 130Kev to 180Kev, the implant dose is 1E12 / cm 2 To 2E13 / cm 2 .

[0019] In one of the embodiments, the step of obtaining a test structure further comprises heat treating the test structure after removing the silicon nitride layer.

[0020] It is also necessary to provide a test structure.

[0021] A test structure comprises an N-type region extending from a first main surface of a semiconductor substrate into the semiconductor substrate and a P-type region extending from the first main surface of the semiconductor substrate into the semiconductor substrate, wherein the test structure evaluates metal contamination of a wafer process by the following steps: performing a process to be evaluated on the test structure; performing a heat treatment on the test structure after the process to be evaluated, wherein at the beginning of the heat treatment, the concentration of majority carriers in a first region of the P-type region exposed on the first main surface is greater than the concentration of majority carriers in a second region of the N-type region exposed on the first main surface; cleaning the test structure with an acidic cleaning solution after the heat treatment; and detecting metal defects in the cleaned test structure by a defect detection device, wherein a greater number of metal defects detected indicates more serious metal contamination.

[0022] In one embodiment, the semiconductor substrate is a silicon substrate.

[0023] In one embodiment, the N-type region includes an N-well, the P-type region includes a P-well, and after the process to be evaluated and before the heat treatment, it also includes: doping P-type ions in the P-well to form a P-type doped region, the doping concentration of the P-type doped region is greater than the doping concentration of the P-well, and the first region includes the P-type doped region.

[0024] In one of the embodiments, an N-type doping region is formed in the N-well before the heat treatment step, and the doping concentration of the N-type doping region is greater than the doping concentration of the N-well.

[0025] In one embodiment, the N-type doped region is formed by doping N-type ions after the process to be evaluated and before the heat treatment.

[0026] In one embodiment, the test structure further includes a first isolation structure located between the N-well and the P-well.

[0027] In one embodiment, the first isolation structure is a shallow trench isolation structure.

[0028] In one embodiment, the first isolation structure forms a closed structure on a plane, and the inner side of the closed structure is the P-well; the test structure also includes a second isolation structure surrounding the first isolation structure, and the second isolation structure forms a closed structure on a plane, and the N-well is between the first isolation structure and the second isolation structure.

[0029] In one embodiment, the step of doping P-type ions includes implanting boron ions using an ion implantation process.

[0030] In one embodiment, the acidic cleaning solution includes hydrofluoric acid.

[0031] In one embodiment, the step of forming the N-well and the P-well comprises: implanting phosphorus ions with an implantation energy of 130 KeV to 180 KeV and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2 ; implant boron ions, the implant energy is 130Kev to 180Kev, the implant dose is 1E12 / cm 2 To 2E13 / cm 2 .

[0032] In one of the embodiments, the step of obtaining a test structure further comprises heat treating the test structure after removing the silicon nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0034] Figure 1 is a flow chart of a method for evaluating metal contamination in a wafer process in one embodiment of the present application;

[0035] Figure 2 is a cross-sectional schematic diagram of a test structure in an embodiment of the present application;

[0036] Figure 3 is a relationship diagram between the contaminated metal ppb measured by ICP-MS and the number of metal defects measured by the first embodiment of the method for evaluating metal contamination in a wafer process of the present application;

[0037] Figure 4 is a cross-sectional schematic diagram of a test structure after forming a P-type doping region and an N-type doping region in one embodiment of the present application;

[0038] Figure 5 is a flow chart of forming STI in one embodiment of the present application;

[0039] Figure 6 is a top view of a test structure in one embodiment of the present application;

[0040] Figure 7 is a cross-sectional schematic diagram of the test structure after step S150 is completed in one embodiment of the present application;

[0041] Figure 8 It is a schematic diagram of the distribution of metal defects 7 on the surface of the test structure. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0045] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0048] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0049] This paper designs a new process test structure that can evaluate in real time the actual impact of metal contamination on the device during the process. Figure 1 1 is a flow chart of a method for evaluating metal contamination in a wafer process according to an embodiment of the present application, comprising the following steps:

[0050] S110, obtaining a test structure.

[0051] The test structure includes an N-type region and a P-type region formed and extending from the first main surface of the semiconductor substrate 2 into the semiconductor substrate 2. In one embodiment of the present application, the N-type region includes an N-well 4, and the P-type region includes a P-well 3. The material of the semiconductor substrate 2 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. In one embodiment of the present application, the semiconductor substrate 2 is a silicon substrate. Refer to Figure 2 In one embodiment of the present application, the test structure further includes a first isolation structure 1 located between the N-well 4 and the P-well 3. The first isolation structure 1 is used to perform insulation isolation between the N-well 4 and the P-well 3.

[0052] S120, performing an evaluation process on the test structure.

[0053] The test structure obtained in step S110 is placed in a process equipment of the process to be evaluated, and the process to be evaluated is performed.

[0054] S130, doping P-type ions in the P-well to form a P-type doped region.

[0055] In one embodiment of the present application, a P-type doping region 6 is formed in the P-well 3 by an ion implantation process. The P-type doping region 6 is equivalent to a P-type source region or a P-type drain region (ie, PSD) in the device.

[0056] S140, performing heat treatment on the test structure.

[0057] The test structure is annealed. When the heat treatment starts, the majority carrier concentration of the first region of the P-type region exposed at the first main surface of the semiconductor substrate 2 is greater than the majority carrier concentration of the second region of the N-type region exposed at the first main surface of the semiconductor substrate 2 .

[0058] In one embodiment of the present application, between steps S120 and S140, there is also included a step of doping P-type ions in the P-well to form a P-type doped region. Specifically, a P-type doped region 6 is formed in the P-well 3 by an ion implantation process. The P-type doped region 6 is equivalent to a P-type source region or a P-type drain region (i.e., PSD) in the device. In other embodiments, when forming the P-well 3 and the N-well 4, the P-well 3 is relatively concentrated and the N-well 4 is relatively dilute, so that the concentration of the majority carriers on the upper surface of the P-well 3 is greater than the concentration of the majority carriers on the upper surface of the N-well 4, and there is no need to set the P-type doped region 6. S150, use an acidic cleaning solution to clean the test structure.

[0059] The cleaning step needs to remove the natural oxide layer, so the cleaning liquid can be a cleaning liquid used to remove the oxide layer, such as hydrofluoric acid.

[0060] If step S120 brings about metal contamination, the metal elements introduced by the contamination will react with the semiconductor substrate 2 during the heat treatment to form alloy defects. That is, the metal elements introduced by the contamination will be adsorbed on the surface of the semiconductor substrate 2, and they will exchange electrons with the semiconductor elements in the semiconductor substrate during the thermal process (for example, for a silicon substrate, it will exchange electrons with silicon), and then react electrochemically with the cleaning solution in step S150. Specifically, the electrons in the N-type region will migrate and gather in the P-type region, and after obtaining the electrons, the metal ions will precipitate in the P-type doped region 6 and form metal defects containing the substrate semiconductor elements and O with the metal element as the core. Taking the metal contamination introduced in step S120 as copper, the cleaning solution as hydrofluoric acid, and the semiconductor substrate 2 as a silicon substrate as an example, the chemical formula involved in the above electrochemical reaction is as follows:

[0061] Si+6HF→H 2 SiF 6 +4H + +4e -

[0062] 2H + +2e - →H 2

[0063] Cu 2+ +2e - →Cu

[0064] Furthermore, the doping of the P-type doping region 6 in step S130 can accelerate the diffusion of the contaminated metal and help form the metal precipitation defect.

[0065] S160, detecting metal defects of the test structure by using a defect detection device.

[0066] The aforementioned precipitated metal defects can be detected through an online defect detection machine, that is, a defect scanning machine used by the online defect monitoring station (Inline Defect Monitor Step). The more metal defects detected, the more serious the metal contamination. The first isolation structure 1 can help improve the accuracy of metal contamination identification. Because if a large number of metal defects also appear on the surface of the first isolation structure 1, the metal defects may be caused by other problems rather than metal contamination. That is, the first isolation structure 1 can be used as a reference mark. By respectively using the traditional ICP-MS offline testing method and the method for evaluating wafer process metal contamination of the present application, the following can be obtained. Figure 3 The relationship diagram of the concentration of the parts per billion (ppb) of the contaminated metal measured by ICP-MS and the number of metal defects is shown. Each hollow dot is a set of data on the number of metal defects and the ppb of the contaminated metal (the ordinate of the hollow dot is the number of defects, and the abscissa is the ppb of the contaminated metal), and the oblique line segment is a relationship curve between the number of defects and ppb obtained by polynomial fitting of these hollow dots. That is, the number of defects is approximately proportional to the ppb of the offline ICP-MS, so the method for evaluating the metal contamination of the wafer process of the present application can provide a reference for the process tolerance of the device. The number of defects measured by the method for evaluating the metal contamination of the wafer process of the present application can well characterize the characterization of heavy metal pollution (such as copper) in the process to be evaluated on the product. Compared with the traditional ICP-MS test results, the present application has the advantages of more direct and more representative results.

[0067] In one embodiment of the present application, before step S140, an N-type doping region 5 is formed in the N-well 4 of the test structure, referring to Figure 4 The doping concentration of the N-type doping region 5 is greater than the doping concentration of the N-well 4. The N-type doping region 5 is equivalent to the N-type source region or the N-type drain region (i.e., NSD) in the device. In one embodiment of the present application, the N-type doping region 5 is formed by doping N-type ions after step S120 and before step S140, and specifically, N-type ions are injected into the N-well 4 by an ion implantation process to form the N-type doping region 5 in the N-well 4.

[0068] In one embodiment of the present application, the first isolation structure 1 is a shallow trench isolation (STI) structure. The STI may be formed first, and then the N well 4 and the P well 3 are formed. The method for forming the STI may adopt a STI formation method known in the art. Figure 5 In one embodiment of the present application, STI is formed by the following steps:

[0069] S101, forming a pad oxide layer on a semiconductor substrate.

[0070] In one embodiment of the present application, the pad oxide layer is formed by a deposition process. In other embodiments of the present application, the pad oxide layer may be formed by other methods known in the art for forming an oxide layer, such as thermal oxidation. The material of the pad oxide layer may be silicon dioxide.

[0071] S102, forming a silicon nitride layer on the pad oxide layer.

[0072] In one embodiment of the present application, the silicon nitride layer is formed by a deposition process.

[0073] S103, photolithography and etching to form a groove.

[0074] In one embodiment of the present application, a photoresist is coated on the silicon nitride layer, and then a photomask having a pattern corresponding to the STI to be formed is used for exposure, and after development, the photoresist is dissolved at the position where the STI is to be formed. Then, the remaining photoresist layer after development is used as an etching barrier layer, and the silicon nitride layer at the position where the photoresist is exposed is etched, and then the pad oxide layer and the semiconductor substrate 2 are etched to form a groove.

[0075] S104, filling the trench with insulating material.

[0076] In one embodiment of the present application, silicon dioxide may be deposited in the trench to form the STI.

[0077] S105, planarization process.

[0078] The excess insulating material outside the trench is removed by chemical mechanical planarization (CMP).

[0079] S106, removing the silicon nitride layer.

[0080] In one embodiment of the present application, the silicon nitride layer may be removed by wet etching.

[0081] We hope to avoid introducing contaminant particles as much as possible during the process of forming STI. Therefore, for the process machine used in steps S101 to S104, the cleanliness of the chamber must be guaranteed before the process starts. In one embodiment of the present application, each process chamber has less than 20 particles with a size ≥ 0.2 microns and less than 10 particles with a size ≥ 1 micron before the process starts.

[0082] In one embodiment of the present application, the first isolation structure 1 is a local oxidation isolation of silicon (LOCOS).

[0083] In one embodiment of the present application, the step of forming the N well 4 is to implant phosphorus ions by an ion implantation process, with an implantation energy of 130Kev to 180Kev and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2 .

[0084] In one embodiment of the present application, the step of forming the P well 3 is to implant boron ions by an ion implantation process, with an implantation energy of 130 KeV to 180 KeV and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2 .

[0085] In one embodiment of the present application, after step S106 and before step S120, a step of heat treating the test structure is further included. Specifically, annealing at 1020 to 1030 degrees Celsius for 5 to 10 minutes may be performed in a nitrogen atmosphere. In one embodiment of the present application, the annealing in step S140 is annealing at 1020 to 1030 degrees Celsius for 5 to 10 minutes in a nitrogen atmosphere.

[0086] In one embodiment of the present application, the first isolation structure 1 forms a closed structure on a plane, see Figure 6 On the plane, the inner side of the closed structure 1 is a P well 3. Figure 6 In the illustrated embodiment, the test structure further includes a second isolation structure 11 surrounding the first isolation structure 1. The second isolation structure 11 forms a closed structure on a plane. On a plane, an N well 4 is between the first isolation structure 1 and the second isolation structure 11. A graphic boundary can be defined by the second isolation structure 11. The second isolation structure 11 can be an STI. In one embodiment of the present application, more than one isolation structure can be formed around the second isolation structure 11, that is, the test structure includes a ring-shaped isolation structure.

[0087] Figure 7 is a schematic cross-sectional view of the test structure after step S150 is completed, and the metal defect 7 is precipitated on the surface of the P-type doped region 6 . Figure 8 is a schematic diagram of the distribution of metal defects 7 on the surface of the test structure. Figure 8 The P-type doping region 6 and the N-type doping region 5 are not shown.

[0088] In one embodiment of the present application, the P-type ions doped in step S130 are boron ions. Boron ions have a small atomic weight and diffuse faster, so they have a better effect of accelerating the diffusion of contaminated metals. In one embodiment of the present application, the injection energy of the boron ions injected in step S130 is 2Kev to 8Kev, and the injection dose is 8E14 / cm 2 To 2E16 / cm 2 .

[0089] In one embodiment of the present application, the acid cleaning solution used in step S150 is a buffered oxide etchant (BOE).

[0090] The present application accordingly provides a test structure.

[0091] A test structure includes an N-well and a P-well formed in a semiconductor substrate, wherein the test structure evaluates metal contamination in a wafer process by the following steps: performing a process to be evaluated on the test structure; doping P-type ions in the P-well to form a P-type doping region, wherein the doping concentration of the P-type doping region is greater than the doping concentration of the P-well; performing a heat treatment on the test structure formed with the P-type doping region; cleaning the test structure with an acidic cleaning solution after the heat treatment; and detecting metal defects in the cleaned test structure by a defect detection device, wherein a greater number of metal defects detected indicates more serious metal contamination.

[0092] In one of the embodiments, an N-type doping region is formed in the N-well before the heat treatment step, and the doping concentration of the N-type doping region is greater than the doping concentration of the N-well.

[0093] In one embodiment, the N-type doped region is formed by doping N-type ions after the process to be evaluated and before the heat treatment.

[0094] In one embodiment, the test structure further includes a first isolation structure located between the N-well and the P-well.

[0095] In one embodiment, the first isolation structure is a shallow trench isolation structure.

[0096] In one embodiment, the first isolation structure forms a closed structure on a plane, and the inner side of the closed structure is the P-well; the test structure also includes a second isolation structure surrounding the first isolation structure, and the second isolation structure forms a closed structure on a plane, and the N-well is between the first isolation structure and the second isolation structure.

[0097] In one embodiment, the step of doping P-type ions includes implanting boron ions using an ion implantation process.

[0098] In one embodiment, the acidic cleaning solution includes hydrofluoric acid.

[0099] In one embodiment, the step of forming the N-well and the P-well comprises: implanting phosphorus ions with an implantation energy of 130 KeV to 180 KeV and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2; implant boron ions, the implant energy is 130Kev to 180Kev, the implant dose is 1E12 / cm 2 To 2E13 / cm 2 .

[0100] In one of the embodiments, the step of obtaining a test structure further comprises heat treating the test structure after removing the silicon nitride layer.

[0101] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0102] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0103] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for evaluating metal contamination in a wafer process, comprising: Acquire a test structure, the test structure comprising an N-type region extending from a first main surface of the semiconductor substrate into the semiconductor substrate and a P-type region extending from the first main surface of the semiconductor substrate into the semiconductor substrate; performing a process to be evaluated on the test structure; After the process to be evaluated, the test structure is subjected to a heat treatment, wherein when the heat treatment starts, a concentration of majority carriers in a first region of the P-type region exposed on the first main surface is greater than a concentration of majority carriers in a second region of the N-type region exposed on the first main surface; cleaning the test structure using an acidic cleaning solution after the heat treatment; The metal defects of the cleaned test structure are detected by defect detection equipment. The more metal defects are detected, the more serious the metal contamination is.

2. The method for evaluating metal contamination in a wafer process according to claim 1, characterized in that: The N-type region includes an N-well, and the P-type region includes a P-well. After the process to be evaluated and before the heat treatment, the method further includes: doping P-type ions in the P-well to form a P-type doped region, wherein the doping concentration of the P-type doped region is greater than the doping concentration of the P-well, and the first region includes the P-type doped region.

3. The method for evaluating metal contamination in a wafer process according to claim 1, characterized in that: An N-type doping region is formed in the N-well before the heat treatment step, and the doping concentration of the N-type doping region is greater than the doping concentration of the N-well.

4. The method for evaluating metal contamination in a wafer process according to claim 2, characterized in that: The test structure also includes a first isolation structure located between the N-well and the P-well.

5. The method for evaluating metal contamination in a wafer process according to claim 4, characterized in that: The first isolation structure is a shallow trench isolation structure.

6. The method for evaluating metal contamination in a wafer process according to claim 5, characterized in that: The step of obtaining the test structure includes forming a shallow trench isolation structure, and forming the N-well and the P-well; The step of forming the shallow trench isolation structure comprises: forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; Photolithography and etching to form grooves; filling the groove with an insulating material; performing a planarization process; The silicon nitride layer is removed.

7. The method for evaluating metal contamination in a wafer process according to claim 6, characterized in that: For the process equipment used in the process of forming the shallow trench isolation structure, before the process starts, each process chamber has less than 20 attached particles with a size not less than 0.2 microns and less than 10 particles with a size not less than 1 micron.

8. The method for evaluating metal contamination in a wafer process according to claim 4, characterized in that: The first isolation structure forms a closed structure on a plane, and the inner side of the closed structure is the P well; The test structure further includes a second isolation structure surrounding the first isolation structure, the second isolation structure forms a closed structure on a plane, and the N well is between the first isolation structure and the second isolation structure.

9. The method for evaluating metal contamination in a wafer process according to claim 1, characterized in that: The step of doping P-type ions comprises implanting boron ions using an ion implantation process; and / or The acidic cleaning solution includes hydrofluoric acid; and / or The semiconductor substrate is a silicon substrate.

10. The method for evaluating metal contamination in a wafer process according to claim 6, characterized in that: The steps of forming the N well and the P well include: implanting phosphorus ions with an implantation energy of 130 KeV to 180 KeV and an implantation dose of 1E12 / cm 2 To 2E13 / cm 2 ; implant boron ions, the implant energy is 130Kev to 180Kev, the implant dose is 1E12 / cm 2 To 2E13 / cm 2 ; and / or The step of obtaining a test structure further includes heat treating the test structure after removing the silicon nitride layer.

11. A test structure, characterized in that: The test structure includes an N-type region extending from a first main surface of the semiconductor substrate to the semiconductor substrate and a P-type region extending from the first main surface of the semiconductor substrate to the semiconductor substrate. The test structure evaluates metal contamination of a wafer process by the following steps: performing a process to be evaluated on the test structure; After the process to be evaluated, the test structure is subjected to a heat treatment, wherein at the beginning of the heat treatment, the concentration of majority carriers in a first region of the P-type region exposed on the first main surface is greater than the concentration of majority carriers in a second region of the N-type region exposed on the first main surface; after the heat treatment, the test structure is cleaned using an acidic cleaning solution; The metal defects of the cleaned test structure are detected by a defect detection device, and a greater number of metal defects detected indicates more serious metal contamination.

12. The test structure according to claim 11, characterized in that: The N-type region includes an N-well, and the P-type region includes a P-well. After the process to be evaluated and before the heat treatment, the method further includes: doping P-type ions in the P-well to form a P-type doped region, wherein the doping concentration of the P-type doped region is greater than the doping concentration of the P-well, and the first region includes the P-type doped region.

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