Method and device for manufacturing and effectively etching device structure

Abstract

The invention provides a manufacturing and effective etching method and device of a device structure, and relates to the technical field of semiconductor manufacturing processes. Comprising the following steps: respectively determining a first etching rate of a hydrofluoric acid reagent to a silicon oxide layer and an oxidation isolation structure and a second etching rate of the hydrofluoric acid reagent to a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent to the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent to a silicon nitride layer and a fifth etching rate of the phosphoric acid reagent to the silicon oxide layer and the oxidation isolation structure; according to the target loss amount of the oxidation isolation structure, the thickness of a part of silicon oxynitride needing to be etched by a hydrofluoric acid reagent and the thickness of a residual silicon oxynitride layer needing to be etched by a phosphoric acid reagent are calculated, and the total phosphoric acid etching time and the total hydrofluoric acid etching time meeting the required thickness of the oxidation isolation structure are obtained; and etching the wafer by using a phosphoric acid reagent and a hydrofluoric acid reagent according to the corresponding etching time. According to the invention, effective etching of the wafer can be realized under the condition that the thickness requirement of the oxidation isolation structure is met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing process technology, and in particular to a method and apparatus for manufacturing and effectively etching a device structure. Background Art

[0002] LOCOS (LOCal Oxidation of Silicon) is a commonly used device isolation technology in CMOS (Complementary Metal Oxide Semiconductor) silicon process. It realizes the selective oxidation of silicon by using silicon nitride as a mask. Specifically, in the process of local oxidation of silicon, the area to be isolated is opened by photolithography and etching, and the isolation area is oxidized by a thermal oxidation process to form an oxidation isolation structure. The structure is silicon oxide layer, silicon oxynitride layer, silicon nitride layer, pad oxide layer, and silicon substrate from top to bottom.

[0003] In the process of using an etchant to remove the above-mentioned film layer, the conventional practice is to use hydrofluoric acid to etch the upper silicon oxide layer of the structure, use hydrofluoric acid or hot phosphoric acid to etch the middle silicon oxynitride layer, and then use hot phosphoric acid to etch the silicon nitride layer below. Since during the etching process, hydrofluoric acid and phosphoric acid will also etch the silicon oxide on the oxidation isolation structure, making its thickness thinner and thinner, it is particularly important to choose which reagent to use to etch the silicon oxynitride layer or how to combine the etching ratio of hydrofluoric acid and hot phosphoric acid to the silicon oxynitride layer, while ensuring the etching efficiency and reducing the cost, to ensure that the remaining thickness of the oxidation isolation structure meets the device requirements, and to etch the silicon oxide layer, silicon oxynitride layer, and silicon nitride layer cleanly. Moreover, since the proportion of effective components of phosphoric acid changes during use, its etching rate for silicon oxynitride will change with use, which increases the difficulty of calculating the time required for the combination of hydrofluoric acid and hot phosphoric acid to etch silicon oxynitride.

[0004] In practice, excessive etching is often used. However, facts show that even if an excessive amount (50-100% overetching) of etchant is used for etching, unclean etching will still occur. Excessive etching can easily cause excessive loss of the oxide layer of the oxide isolation structure, and the remaining thickness after etching is ultimately not up to standard. Since the requirements for the thickness of the isolation oxide layer on different integrated circuits are different, the etching method of the prior art not only cannot meet the requirements of different integrated circuits for the thickness of the isolation oxide layer, but also cannot achieve free adjustment of the process according to different requirements to achieve different thicknesses of the residual oxide isolation structure oxide layer thickness. Summary of the invention

[0005] In view of this, the purpose of the present application is to at least provide a method and apparatus for manufacturing and effectively etching a device structure, which can calculate the thickness of the silicon oxynitride required to be etched by hydrofluoric acid and the thickness of the silicon oxynitride required to be etched by phosphoric acid within the upper limit of the thickness loss requirement of the oxide isolation structure. At the same time, the etching time of hydrofluoric acid and phosphoric acid can be calculated based on the current state of use of phosphoric acid, so that effective etching of the wafer can be achieved while meeting the thickness loss requirement of the oxide isolation structure.

[0006] This application mainly includes the following aspects:

[0007] In the first aspect, the present application provides a method for manufacturing and effectively etching a device structure, including: providing a wafer that has been subjected to local isolation oxidation treatment, wherein an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate are stacked in sequence from top to bottom in the wafer; measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the original thickness of the oxidation isolation structure; respectively determining a first etching rate of a hydrofluoric acid reagent on the silicon oxide layer and the oxidation isolation structure, a second etching rate of a hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of a phosphoric acid reagent on the silicon oxide layer and the oxidation isolation structure, wherein the third etching rate and the fifth etching rate vary with the workload of continuous phosphoric acid etching, and the workload of continuous phosphoric acid etching is the cumulative number of wafers etched starting from the time when new phosphoric acid is added and the time required for phosphoric acid to etch a single wafer. The product of ; according to the original thickness of the oxide isolation structure and the required thickness of the oxide isolation structure, determine the target loss amount of the thickness of the oxide isolation structure in the continuous etching process; according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate, respectively calculate the thickness and etching time of the part of the silicon oxynitride layer that needs to be etched by the hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched by the phosphoric acid reagent; according to the thickness and etching time of the part of the silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer, calculate the total hydrofluoric acid etching time for etching the silicon oxide layer and the silicon oxynitride layer in sequence using hydrofluoric acid and the total phosphoric acid etching time for etching the silicon oxynitride layer and the silicon nitride layer in sequence using phosphoric acid; use the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, and obtain the oxide isolation structure with the target thickness.

[0008] In a possible implementation, the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness of the oxidation isolation structure are determined by the following formula:

[0009] S=T(DHF3)×E a +T(HPO3)×f1(x)

[0010] In this formula, S represents the target loss amount of the oxide isolation structure after the wafer etching is completed, S=S1-S2, S1 represents the original thickness of the oxide isolation structure before the wafer etching is performed, S2 represents the required thickness of the oxide isolation structure after the etching is completed, T(DHF3) represents the total hydrofluoric acid etching time, Ea represents the first etching rate, T(HPO3) represents the total phosphoric acid etching time, f1(x) represents the fifth etching rate of the phosphoric acid new acid reagent on the oxide isolation structure under the phosphoric acid continuous etching workload x, and the fifth etching rate varies as a function of the phosphoric acid continuous etching workload x.

[0011] In a possible implementation, the total phosphoric acid etching time and the total hydrofluoric acid etching time are expressed by the following formula:

[0012]

[0013] In this formula, T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, T(DHF2) represents the etching time of the hydrofluoric acid reagent on part of the silicon oxynitride layer, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, and T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer.

[0014] In a possible implementation, the etching time of the silicon oxide layer by the hydrofluoric acid reagent is determined by the following formula:

[0015] T(DHF1)=(X / E a )

[0016] In the formula, X represents the thickness of the silicon oxide layer, and Ea represents the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer.

[0017] In a possible implementation manner, the etching time of the hydrofluoric acid reagent on the portion of the silicon oxynitride layer is determined by the following formula:

[0018] T(DHF2)=Z / E1

[0019] In the formula, Z represents the thickness of the portion of the silicon oxynitride layer etched using the hydrofluoric acid reagent, and E1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

[0020] In a possible implementation manner, the etching time of the silicon nitride layer by the phosphoric acid reagent is determined by the following formula:

[0021] T(HPO1)=(Y / E b )×n

[0022] In the formula, Y represents the thickness of the silicon nitride layer, Eb represents the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n represents a given excess etching coefficient.

[0023] In a possible implementation manner, the etching time of the remaining silicon oxynitride layer by the phosphoric acid reagent is determined by the following formula:

[0024] T(HPO2)=(MZ) / f2(x)

[0025] In the formula, M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous phosphoric acid etching workload x, Z represents the thickness of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and MZ represents the remaining thickness of the silicon oxynitride layer after etching with the hydrofluoric acid reagent, and the remaining silicon oxynitride layer is etched by the phosphoric acid reagent.

[0026] In a possible implementation, the fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x is determined by the following formula:

[0027] f1(x)=9×10 8 x 2 -0.0007x+1.5945.

[0028] In a possible implementation, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the phosphoric acid continuous etching workload x is determined by the following formula:

[0029] f2(x)=10 7 x 2 -0.0013x+2.983.

[0030] In a second aspect, an embodiment of the present application also provides a device structure manufacturing and effective etching device, the device comprising: a providing module for providing a wafer after local isolation oxidation treatment, wherein an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked from top to bottom are formed in the wafer; a measuring module for measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the original thickness of the oxidation isolation structure; an etching rate determination module for respectively determining a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxidation isolation structure, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxidation isolation structure, wherein the third etching rate and the fifth etching rate vary with the continuous phosphoric acid etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of wafers etched starting from the phosphoric acid new acid and the time required for phosphoric acid to etch a single wafer; a loss amount A determination module is used to determine the target thickness loss amount of the oxide isolation structure during the continuous etching process according to the original thickness of the oxide isolation structure and the required thickness of the oxide isolation structure; a first etching time determination module is used to calculate the thickness and etching time of the part of the silicon oxynitride layer that needs to be etched by the hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched by the phosphoric acid reagent according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate; a second etching time determination module is used to calculate the total hydrofluoric acid etching time for etching the silicon oxide layer and the silicon oxynitride layer in sequence using hydrofluoric acid and the total phosphoric acid etching time for etching the silicon oxynitride layer and the silicon nitride layer in sequence using phosphoric acid according to the thickness and etching time of the part of the silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer; an etching module is used to use the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, and obtain an oxide isolation structure with a target thickness.

[0031] The embodiments of the present application provide a method and apparatus for manufacturing and effectively etching a device structure, including: respectively determining a first etching rate of a hydrofluoric acid reagent on a silicon oxide layer, a second etching rate of a hydrofluoric acid reagent on a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on a silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on a silicon nitride layer, and a fifth etching rate of a phosphoric acid reagent on an oxidation isolation structure; according to a target thickness loss value of the oxidation isolation structure during continuous etching, determining by calculation the thickness of part of the silicon oxynitride that needs to be etched by hydrofluoric acid and the remaining silicon oxynitride that needs to be etched by phosphoric acid, thereby obtaining the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness of the oxidation isolation structure; using phosphoric acid reagent and hydrofluoric acid reagent to complete the etching of the wafer according to the corresponding etching time. The method for manufacturing and effectively etching a device structure provided in the present application achieves effective etching of the wafer while meeting the required thickness requirements of the isolation structure.

[0032] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of a silicon local oxidation process provided by an embodiment of the present application is shown;

[0035] Figure 2 A schematic diagram of a silicon nitride removal process provided in an embodiment of the present application is shown;

[0036] Figure 3 A schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application is shown;

[0037] Figure 4 A flow chart showing a method for manufacturing and effectively etching a device structure provided in an embodiment of the present application is shown;

[0038] Figure 5 A graph showing a variation trend of the etching rate of silicon oxide by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid multiplied by the time required for phosphoric acid to etch a single wafer);

[0039] Figure 6A trend chart showing the change in etching rate of silicon oxynitride by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid multiplied by the time required for phosphoric acid to etch a single wafer);

[0040] Figure 7 A wafer etching effect diagram of removing a silicon nitride layer of a wafer using a conventional etching method is shown;

[0041] Figure 8 A wafer etching effect diagram after removing the silicon nitride layer of the wafer by the method provided by the present application is shown in an embodiment of the present application;

[0042] Fig. 9 A device structure slicing effect diagram after a silicon nitride layer of a wafer is removed by a method provided by the present application is shown in an embodiment of the present application;

[0043] Fig.10 A functional module diagram of a device structure manufacturing and effective etching device provided in an embodiment of the present application is shown;

[0044] Fig.11 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown.

[0045] Explanation of symbols in the figure: 101 is an oxide isolation structure; 102 is a silicon oxide layer; 103 is a silicon oxynitride layer; 104 is a silicon nitride layer; 105 is a pad oxide layer; and 106 is a silicon substrate. DETAILED DESCRIPTION

[0046] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0047] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0048] Silicon local oxidation is a commonly used device isolation technology in CMOS silicon process. It realizes the selective oxidation of silicon by using silicon nitride as a mask. Figure 1 , Figure 1 A schematic diagram of a silicon local oxidation process provided by an embodiment of the present application is shown. As shown in B1, a pad oxide layer 105 and a silicon nitride layer 104 are first grown on a silicon substrate 106, and as shown in B2, the region to be isolated is opened by photolithography and etching, and the region to be isolated is oxidized by a thermal oxidation process to form an oxidized isolation structure 101, the component of the oxidized isolation structure 101 is silicon oxide, and then high-temperature phosphoric acid is used as an etchant to remove the silicon nitride layer 104, and a device structure with an isolation function as shown in B4 is obtained.

[0049] Hydrofluoric acid is a conventional reagent for etching silicon oxide, and phosphoric acid is a conventional reagent for etching silicon nitride. Both hydrofluoric acid and phosphoric acid can etch silicon oxynitride.

[0050] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a silicon nitride removal process provided in an embodiment of the present application. Figure 1 and Figure 2 As shown, in the process of removing the silicon nitride layer 104 shown in B3 to B4, the conventional method of removing the silicon nitride layer 104 is to first use hydrofluoric acid to remove the silicon oxide layer 102 formed on the surface of the silicon nitride layer, then rinse off the hydrofluoric acid with water, and then use phosphoric acid to remove the silicon nitride layer 104, and finally rinse off the phosphoric acid with water.

[0051] In the process of using phosphoric acid to etch away the silicon nitride layer 104, the conventional practice is to use excessive phosphoric acid to clean the silicon nitride layer 104. However, facts show that even if excessive (50-100% over-etching) phosphoric acid is used to clean the silicon nitride layer 104, the etching may still not be clean during the actual etching process.

[0052] See also Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application. Figure 1and Figure 3 As shown, in the process of forming the oxidation isolation structure 101 shown in B2 to B3, in the process of oxidizing the isolation area through a thermal oxidation process, the silicon nitride layer 104 is affected by the thermal oxidation process, and a silicon oxide layer 102 is formed on the upper surface of the silicon nitride layer 104. A very thin silicon oxynitride layer 103 is formed between the silicon oxide layer 102 and the silicon nitride layer 104. Due to the existence of the silicon oxynitride layer 103, hydrofluoric acid or phosphoric acid can be selected to etch it, but the etching rates of the two are inconsistent, which will result in different etching times.

[0053] In addition, since the oxide isolation structure 101 is composed of silicon oxide, during the etching process of the silicon oxide layer 102, the silicon oxynitride layer 103 and the silicon nitride layer 104, both hydrofluoric acid and phosphoric acid will etch the oxide isolation structure 101. Since the integrated circuit has certain requirements on the thickness of the oxide isolation structure 101 corresponding to the wafer, the etching method of the prior art is not only unable to effectively remove silicon nitride, but also unable to meet the control of the thickness of the oxide isolation structure, which ultimately causes device structure abnormalities.

[0054] Based on this, the embodiments of the present application provide a method, apparatus and electronic device for manufacturing and effectively etching a device structure, which can achieve effective etching of a wafer while meeting the thickness loss requirements of the isolation structure, as follows:

[0055] See also Figure 4 , Figure 4 The flowchart of the method for manufacturing and effectively etching a device structure provided by the embodiment of the present application is shown. Figure 4 and Figure 3 As shown, the method provided in the embodiment of the present application comprises the following steps:

[0056] S100, providing a wafer that has been subjected to local isolation oxidation treatment.

[0057] An oxidation isolation structure and a silicon oxide layer 102 , a silicon oxynitride layer 103 , a silicon nitride layer 104 , a pad oxide layer 105 and a silicon substrate 106 stacked in sequence from top to bottom are formed in the wafer.

[0058] S200, measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the original thickness of the oxide isolation structure.

[0059] The thickness of the silicon oxide layer is the thickness corresponding to the silicon oxide layer 102 , and the thickness of the silicon nitride layer is the thickness corresponding to the silicon nitride layer 104 .

[0060] S300, respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxide isolation structure, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxide isolation structure.

[0061] The third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer.

[0062] S400, determining a target thickness loss amount of the oxidation isolation structure during continuous etching according to an original thickness of the oxidation isolation structure and a required thickness of the oxidation isolation structure.

[0063] S500, according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate, respectively calculate the thickness and etching time of the part of the silicon oxynitride layer that needs to be etched with the hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched with the phosphoric acid reagent.

[0064] The etching rates include a first etching rate, a second etching rate, a third etching rate, a fourth etching rate and a fifth etching rate.

[0065] S600, according to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer, obtain the total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and the total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid.

[0066] S700, using a phosphoric acid reagent and a hydrofluoric acid reagent, the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer are etched according to the total etching time of the hydrofluoric acid and the total etching time of the phosphoric acid, and an oxide isolation structure with a target thickness is obtained.

[0067] In step S500, the thickness and etching time of the portion of the silicon oxynitride layer 103 that needs to be etched with hydrofluoric acid are calculated based on the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, the thickness of the silicon oxynitride layer 103, the original thickness S1 of the oxidation isolation structure, the target required thickness S2 of the oxidation isolation structure, the first etching rate, the second etching rate, the third etching rate, the fourth etching rate and the fifth etching rate. The thickness and etching time of the remaining silicon oxynitride layer that needs to be etched with phosphoric acid are then calculated, and the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness S2 of the oxidation isolation structure are determined.

[0068] In the local isolation oxidation technology, the silicon nitride layer on the wafer undergoes the following reactions during the thermal oxidation process:

[0069] Si3 N4(s)+3 / 2O2(g)→3SiO(g)+2N2(g)------A.1

[0070] Si3 N4(s)+3O2(g)→3SiO2(g)+2N2(g)------A.2

[0071] Si3 N4(s)+5O2(g)→3SiO2(g)+4NO(g)------A.3

[0072] 4Si3 N4(s)+3O2(g)→6Si2N2O(g)+2N2(g)------A.4

[0073] It can be seen from chemical equations A.1 to A.3 that during the process of forming an oxidation isolation structure by the thermal oxidation process of the silicon nitride layer, the surface of the silicon nitride layer 104 is affected by the thermal oxidation process of silicon oxide, and a silicon oxide layer 102 is formed on the surface of the silicon nitride layer 104. It can be seen from chemical equation A.4 that under certain temperature conditions (for example, a temperature between 700°C and 1180°C) on the surface of the silicon nitride layer 104 that is thermally oxidized by oxygen O2 or hydrogen H2, an interface layer, namely a silicon oxynitride layer 103, can be formed between the silicon oxide layer 102 and the silicon nitride layer 104. The silicon oxynitride layer 103 is a conversion layer of the interface of silicon nitride during the oxidation process. In the prior art, phosphoric acid is reused, and its effective components gradually change with use. Therefore, the etching rate of the film layer also changes with use.

[0074] In the process of removing the silicon nitride layer 104, hydrofluoric acid is first used to remove the silicon oxide layer 102, and then phosphoric acid is used to remove the silicon nitride layer 104. Considering the silicon oxynitride layer 103 formed between the silicon nitride layer 104 and the silicon oxide layer 102 and the repeated use of phosphoric acid, when the hydrofluoric acid used is not sufficient to etch the silicon oxynitride layer 103, the silicon oxynitride layer 103 will be affected by the newness of the subsequent phosphoric acid reagent, which directly leads to the inability to effectively remove the silicon nitride.

[0075] Based on this, in steps S100 to S700 provided in the present application, in the process of removing the silicon nitride layer 104, the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104 and the given required thickness of the oxidation isolation structure are used to calculate the time for etching the silicon oxide layer 102 with hydrofluoric acid, the thickness and etching time of the part of the silicon oxynitride layer that needs to be etched away with hydrofluoric acid, the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched away with phosphoric acid, and the etching time of etching the silicon nitride layer 104 with phosphoric acid, and then the total etching time of hydrofluoric acid and the total etching time of phosphoric acid are further calculated, and the total etching time of phosphoric acid is calculated. Acid reagent and hydrofluoric acid reagent, according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, sequentially remove the silicon oxide layer 102, the silicon oxynitride layer 103 and the silicon nitride layer 104 to complete the etching of the wafer. In this process, the corresponding ratio of the total phosphoric acid etching time and the total hydrofluoric acid etching time is constrained by the required thickness of the oxidation isolation structure, so that when the final total phosphoric acid etching time and the total hydrofluoric acid etching time are used to remove silicon oxide, silicon oxynitride and silicon nitride, not only can the silicon nitride layer be effectively removed in the end, but the required thickness of the oxidation isolation structure can also be further accurately controlled to meet the different requirements of different integrated devices for the thickness of the oxidation isolation structure.

[0076] like Figure 3 As shown, after the thermal oxidation process, the wafer is formed with an oxidation isolation structure 101, a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105 and a silicon substrate 106. In step S200, the silicon nitride layer 104 and the silicon oxide layer 102 are measured to obtain the silicon oxide layer thickness X, the silicon nitride layer thickness Y and the silicon oxynitride layer thickness M. Since the silicon oxynitride layer 103 is thin, it is difficult to measure. According to experience, the silicon oxynitride layer thickness M generally corresponds to a range of ( represents the unit of length, angstrom).

[0077] In addition, the thickness of the oxide isolation structure needs to be measured to obtain the original thickness S1 of the oxide isolation structure before the oxide isolation structure is etched.

[0078] In step S300, the analysis of the use of phosphoric acid reagent and hydrofluoric acid reagent shows that the first etching rate Ea of the hydrofluoric acid reagent on the silicon oxide layer 102, the fourth etching rate Eb of the phosphoric acid reagent on the silicon nitride layer 104, and the second etching rate E1 of the hydrofluoric acid reagent on the silicon oxynitride layer 103 are generally conventional and stable, and can be obtained in advance through testing. Generally, the second etching rate (angstroms / minute).

[0079] Specifically, before executing step S500, it is necessary to pre-set a given excess etching coefficient n and determine the phosphoric acid continuous etching workload x corresponding to the new phosphoric acid reagent. The phosphoric acid continuous etching workload x is the product of the cumulative number of etched wafers calculated from the beginning of the new phosphoric acid and the time required for phosphoric acid to etch a single wafer. Among them, the given excess etching coefficient n is usually 1.2 to 2, which can be set according to actual needs. The phosphoric acid continuous etching workload x reflects the newness of the phosphoric acid. The phosphoric acid continuous etching workload x = phosphoric acid etching time for a single wafer × the cumulative number of wafers etched, and the phosphoric acid etching time for a single wafer corresponds to minutes min.

[0080] In step S400, the required thickness S2 of the oxide isolation structure is also determined, and the target thickness loss S=S1-S2 of the oxide isolation structure during the continuous etching process is calculated based on the required thickness S2 of the oxide isolation structure and the original thickness S1 of the oxide isolation structure.

[0081] In a preferred embodiment, in step S400, the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness of the oxidation isolation structure are determined by the following formula:

[0082] S=T(DHF3)×E a +T(HPO3)×f1(x) (1)

[0083] In formula (1), S represents the target loss amount of the oxide isolation structure after the wafer etching is completed, S=S1-S2, S1 represents the original thickness of the oxide isolation structure before the wafer etching is performed, S2 represents the required thickness of the oxide isolation structure after the etching is completed, T(DHF3) represents the total hydrofluoric acid etching time, Ea represents the first etching rate, T(HPO3) represents the total phosphoric acid etching time, f1(x) represents the fifth etching rate of the phosphoric acid new acid reagent on the oxide isolation structure under the phosphoric acid continuous etching workload x, and the fifth etching rate varies as a function of the phosphoric acid continuous etching workload x.

[0084] Among them, the first etching rate Ea is given in advance. In the present application, since the oxidation isolation structure is formed by the pad oxide layer 105, the first variation data of the etching rate of the phosphoric acid reagent on silicon oxide with the phosphoric acid continuous etching workload is collected in advance. According to the first variation data, the first curve of the etching rate of the phosphoric acid reagent on silicon oxide with the phosphoric acid continuous etching workload is drawn, and the first function expression for determining the fifth etching rate is created according to the first curve, wherein:

[0085] f1(x)=9×10 8 x 2 -0.0007x+1.5945 (2)

[0086] See also Figure 5, Figure 5 The graph shows the change trend of the etching rate of silicon oxide by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid and the time required for phosphoric acid to etch a single wafer). Figure 5 As shown, the horizontal axis is the continuous phosphoric acid etching workload x, that is, the product of the cumulative number of wafers etched from the beginning of phosphoric acid etching and the time required for phosphoric acid etching a single wafer, and the vertical axis represents the etching rate of phosphoric acid reagent on silicon oxide, and the unit of etching rate is (angstroms / minute), L1 represents the first curve of the etching rate of phosphoric acid reagent on silicon oxide as the amount of phosphoric acid continuous etching changes. The corresponding function expression of f1(x) created by the first curve L1 is:

[0087] f1(x)=9×10 8 x 2 -0.0007x+1.5945

[0088] Since the oxide isolation structure is composed of silicon oxide, the phosphoric acid continuous etching workload x is substituted into f1(x)=9×10 8 x 2 -0.0007x+1.5945, the fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x can be obtained.

[0089] In a preferred embodiment, the total phosphoric acid etching time is expressed by the following formula:

[0090] T(DHF3)=T(DHF1)+T(DHF2) (3)

[0091] In formula (3), T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102, T(DHF2) represents the etching time of the hydrofluoric acid reagent on a portion of the silicon oxynitride layer, and the total hydrofluoric acid etching time is the sum of the etching time T(DHF1) of the hydrofluoric acid reagent on the silicon oxide layer 102 and the etching time T(DHF2) of the hydrofluoric acid reagent on a portion of the silicon oxynitride layer.

[0092] In a specific embodiment, the etching time T(DHF1) of the hydrofluoric acid reagent on the silicon oxide layer 102 is determined by the following formula:

[0093] T(DHF1)=(X / E a ) (4)

[0094] In formula (4), X represents the thickness of the silicon oxide layer 102, and Ea represents the first etching rate of the silicon oxide layer 102 by the hydrofluoric acid reagent.

[0095] In a specific embodiment, the first etching rate Ea is predetermined.

[0096] In another preferred embodiment, the etching time T(DHF2) of the hydrofluoric acid reagent on the portion of the silicon oxynitride layer is determined by the following formula:

[0097] T(DHF2)=Z / E1 (5)

[0098] In formula (5), Z represents the thickness of the portion of the silicon oxynitride layer etched using the hydrofluoric acid reagent, and E1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

[0099] Generally, the second etching rate is stable at

[0100] In a preferred embodiment, the total phosphoric acid etching time T(HPO3) is expressed by the following formula:

[0101] T(HPO3)=T(HPO1)+T(HPO2) (6)

[0102] In formula (6), T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer 104, T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer, and the total phosphoric acid etching time T(HPO3) is the sum of the etching time T(HPO1) of the phosphoric acid reagent on the silicon nitride layer and the etching time T(HPO2) of the phosphoric acid reagent on the remaining silicon oxynitride layer.

[0103] In a preferred embodiment, the etching time T(HPO1) of the phosphoric acid reagent on the silicon nitride layer is determined by the following formula:

[0104] T(HPO1)=(Y / E b )×n (7)

[0105] In formula (7), Y represents the thickness of the silicon nitride layer 104, Eb represents the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n represents a given excess etching coefficient.

[0106] Specifically, the fourth etching rate Eb can be determined in advance according to actual conditions. The given excess etching coefficient n is given in advance, and n is usually taken between 1.2 and 2.

[0107] In another preferred embodiment, the etching time T(HPO2) of the phosphoric acid reagent on the remaining silicon oxynitride layer is determined by the following formula:

[0108] T(HPO2)=(MZ) / f2(x) (8)

[0109] In formula (8), M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous phosphoric acid etching workload x, Z represents the thickness of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and MZ represents the remaining thickness of the silicon oxynitride layer after etching with the hydrofluoric acid reagent. The remaining silicon oxynitride layer is etched by the phosphoric acid reagent.

[0110] In a specific embodiment, second variation data of the etching rate of the phosphoric acid reagent on silicon oxynitride as a function of the phosphoric acid continuous etching workload x is collected in advance, and a second curve of the etching rate of the phosphoric acid reagent on silicon oxynitride as a function of the phosphoric acid continuous etching workload is drawn according to the second variation data, and a function expression corresponding to the third etching rate f2(x) is created according to the second curve, wherein:

[0111] f2(x)=10 7 x 2 -0.0013x+2.983 (9)

[0112] See also Figure 6 , Figure 6 The trend diagram of the change of the etching rate of silicon oxynitride by a phosphoric acid reagent provided in an embodiment of the present application with the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched from the beginning of phosphoric acid and the time required for phosphoric acid to etch a single wafer) is shown. Figure 6 As shown, the horizontal axis is the phosphoric acid continuous etching workload x, the time unit is min (minutes), and the vertical axis represents the phosphoric acid reagent on the silicon oxynitride etching rate, the etching rate unit is L2 represents the second curve of the third etching rate as the phosphoric acid continuous etching workload changes x. The function expression f2(x)=10 is created from the second curve L2. 7 x 2 -0.0013x+2.983, substituting the phosphoric acid continuous etching workload x into formula (9), the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer 103 under the phosphoric acid continuous etching workload x can be obtained.

[0113] In a preferred embodiment, formula (1) and formula (3) to formula (8) are combined to obtain:

[0114]

[0115] Among them, the phosphoric acid continuous etching workload x is first determined, and the phosphoric acid continuous etching workload x is respectively substituted into formula (2) and formula (9) to determine the fifth etching rate f1(x) of the phosphoric acid reagent on the oxidation isolation structure 101 and the silicon oxide layer 102 and the third etching rate f2(x) of the phosphoric acid reagent on the silicon oxynitride layer 103 under the phosphoric acid continuous etching workload x.

[0116] Substitute the thickness X of the silicon oxide layer 102, the first etching rate Ea of hydrofluoric acid on the silicon oxide layer, the second etching rate E1 of the hydrofluoric acid reagent on the silicon oxynitride layer 103, the thickness Y of the silicon nitride layer 104, the fourth etching rate Eb of the phosphoric acid reagent on the silicon nitride layer 104, a given excess etching coefficient n, the thickness M of the silicon oxynitride layer 103, the fifth etching rate f1(x) corresponding to the phosphoric acid reagent under the phosphoric acid continuous etching workload x, the third etching rate f2(x) corresponding to the phosphoric acid continuous etching workload x, and the target loss amount S corresponding to the oxide isolation structure 101 after the wafer etching is completed into formula (10) for solution, and the silicon oxynitride layer thickness Z and etching time required to be etched by the hydrofluoric acid reagent in the silicon oxynitride layer 103, and the remaining silicon oxynitride thickness MZ and etching time required to be etched by the phosphoric acid reagent can be obtained.

[0117] After determining the thickness Z of the silicon oxynitride layer etched by the hydrofluoric acid reagent, formula (3) to formula (5) are combined to obtain:

[0118] T(DHF3)=(X / E a )+Z / E1 (11)

[0119] Substituting the silicon oxide layer thickness X, the first etching rate Ea, the thickness Z of the portion of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and the second etching rate E1 of the hydrofluoric acid reagent on the silicon oxynitride layer 103 into formula (11), the total hydrofluoric acid etching time can be obtained.

[0120] Combining formula (6) to formula (8), we get:

[0121] T(HPO3)=(Y / E b )×n+(MZ) / f2(x) (12)

[0122] Substitute the thickness Y of the silicon nitride layer 104, the fourth etching rate Eb of the phosphoric acid reagent on the silicon nitride layer 104, the given excess etching coefficient n, the thickness M of the silicon oxynitride layer 103, the thickness Z of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and the third etching rate f2(x) under the continuous phosphoric acid etching workload x into formula (12) to solve it, and the total phosphoric acid etching time can be obtained.

[0123] In step S700, the etching of the wafer is completed by:

[0124] First, use hydrofluoric acid reagent to etch the silicon oxide layer 102 on the surface of the wafer and part of the silicon oxynitride layer of Z thickness. The etching time corresponding to the hydrofluoric acid reagent is the calculated total hydrofluoric acid etching time. Then rinse off the hydrofluoric acid reagent remaining on the surface of the wafer with water. Then, use phosphoric acid reagent to etch the silicon oxynitride layer and silicon nitride layer 104 of MZ thickness on the surface of the wafer. The etching time corresponding to the phosphoric acid reagent is the calculated total phosphoric acid etching time. Finally, rinse off the phosphoric acid reagent remaining on the surface of the wafer with water to complete the etching of the wafer.

[0125] In a specific embodiment, it is assumed that the original thickness of the oxide isolation structure 101 grown after the wafer undergoes local isolation oxidation treatment is The thickness of the silicon nitride layer 104 is measured. The thickness of the silicon nitride layer 104 after being oxidized to silicon oxide (i.e. the thickness corresponding to the silicon oxide layer 102) Among them, the thickness required for the oxide isolation structure is That is, the target loss amount of the oxide isolation structure after the wafer etching or the silicon nitride layer removal is required to be (The actual loss amount may fluctuate up or down The excess etching coefficient n=1.3 is given, and the thickness M of the silicon oxynitride layer 103 is set to be ( Indicated in angstroms).

[0126] In addition, given: the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer 102 The fourth etching rate of phosphoric acid reagent on the silicon nitride layer 104 is The second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer 103 The phosphoric acid continuous etching workload x corresponding to the phosphoric acid reagent is 2500 min.

[0127] In the traditional removal process of silicon nitride layer:

[0128] Sure:

[0129] T(DHF)_nor=X / E a =70 / 26min=2.69min

[0130] T(HPO)_nor=(Y / E b )×n=1500 / 50min×1.3=39min

[0131] Wherein, T(DHF)_nor represents the etching time corresponding to the hydrofluoric acid reagent calculated in the conventional silicon nitride layer removal method, and T(HPO)_nor represents the etching time corresponding to the phosphoric acid reagent calculated in the conventional silicon nitride layer removal method. Figure 7 , Figure 7 FIG. 1 shows a wafer etching effect diagram of removing a silicon nitride layer of a wafer using a conventional etching method. Figure 7 As shown, a large amount of residue still exists in the silicon nitride layer using the conventional etching method, and the silicon nitride layer is not effectively removed.

[0132] For this application, the calculation yields:

[0133] T(DHF1)=(X / E a )=70 / 26min=2.69min

[0134] T(DHF2)=(Z / E1)=Z / 1.26min

[0135] T(HPO1)=(Y / E b )×n=(1500 / 50)×1.3min=39min

[0136] f2(x=2500)=10 7 ×2500 2 -0.0013×2500+1.5945=0.4min

[0137] T(HPO2)=((MZ) / f2(x=2500))=(13-Z / 0.4)min

[0138] From T(DHF1) and T(DHF2) we get:

[0139] T(DHF3)=T(DHF1)+T(DHF2)=(2.69+Z / 0.4)min

[0140] T(HPO3)=T(HPO1)+T(HPO2)=39+(13-Z / 0.4)min

[0141] For T(DHF3) and T(HPO3), the following conditions must be met:

[0142] S=T(DHF3)×E a +T(HPO3)×f1(x=2500)

[0143] in:

[0144]

[0145]

[0146] That is, we get:

[0147]

[0148] Finally available That is, the target loss amount of silicon oxide in the oxide isolation structure is Under the requirement, the thickness of silicon oxynitride removed by hydrofluoric acid is approximately equal to 0, that is, in this case, the silicon oxynitride needs to be completely removed by phosphoric acid to meet the requirement of silicon oxide loss of the oxidation isolation structure, that is, T(DHF3)=2.69min, T(HPO3)=71.5min.

[0149] See also Figure 8 , Figure 8 The figure shows the etching effect of a wafer after the silicon nitride layer of the wafer is removed by the method provided by the present application. Figure 8 As shown, etching the wafer using the phosphoric acid etching time and the hydrofluoric acid etching time determined in the present application can effectively remove the silicon nitride layer, and the method of the present application also achieves precise control of the required thickness of the isolation layer, and effectively removes the silicon nitride layer while meeting the required thickness of the isolation layer.

[0150] Based on the same application concept, the embodiments of the present application also provide a device structure manufacturing and effective etching device corresponding to the device structure manufacturing and effective etching method provided in the above embodiments. Since the principle of solving the problem by the device in the embodiments of the present application is similar to the device structure manufacturing and effective etching method in the above embodiments of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0151] See also Fig. 9 , Fig. 9 The device structure slicing effect diagram after removing the silicon nitride layer of the wafer by the method provided by the present application is shown in the embodiment of the present application. Fig. 9 As shown, combined with the target loss amount of the oxidation isolation structure given in the specific embodiment of step S700 (The actual loss amount may fluctuate up and down ), the original thickness of the oxide isolation structure The target required thickness is (The target loss amount fluctuates up and down That is, after the process is completed, the actual remaining thickness of the oxide isolation structure is and The process requirements are met), and the wafer is etched using T(DHF3)=2.69min, T(HPO3)=71.5min obtained by the method of this application, and the final measurement is Fig.11 The thickness of the isolation oxide layers on the left and right sides is 295.3 nm (i.e. ) and 295.61nm (approx. ), the thickness of the isolation oxide layer on the left and right sides is between and The corresponding actual loss amount meets the thickness requirement of the oxide isolation structure of the present application. It can be seen that the method of the present application can achieve precise control of the thickness of the oxide isolation structure so that the oxide isolation structure is not over-etched.

[0152] See also Fig.10 , Fig.10 The functional module diagram of a device structure manufacturing and effective etching device provided by an embodiment of the present application is shown. Fig.10 As shown, the device comprises:

[0153] A module 800 is provided for providing a wafer after local isolation oxidation treatment, wherein an oxidation isolation structure and a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105 and a silicon substrate 106 are stacked in sequence from top to bottom are formed in the wafer.

[0154] The measurement module 810 is used to measure the wafer to determine the thickness of the silicon oxide layer 102 , the thickness of the silicon nitride layer 104 , and the original thickness S1 of the oxide isolation structure.

[0155] The etching rate determination module 820 is used to respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer 102 and the oxidation isolation structure 101, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer 103, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer 103, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer 104, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer 102 and the oxidation isolation structure 101, wherein the third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer.

[0156] The loss amount determination module 830 is used to determine the target loss amount of the thickness of the oxidation isolation structure during the continuous etching process according to the original thickness of the oxidation isolation structure and the required thickness of the oxidation isolation structure.

[0157] The first etching time determination module 840 is used to calculate the thickness and etching time of the part of the silicon oxynitride layer that needs to be etched with a hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched with a phosphoric acid reagent, based on the target loss amount, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness and etching rate.

[0158] The second etching time determination module 850 is used to obtain the total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and the total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid based on the thickness and etching time of a portion of the silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer.

[0159] The etching module 860 is used to use phosphoric acid reagent and hydrofluoric acid reagent to complete the etching of the silicon oxide layer, silicon oxynitride layer and silicon nitride layer of the wafer according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, and obtain an oxide isolation structure with a target thickness.

[0160] Based on the same application idea, please refer to Fig.11 , Fig.11 FIG. 1 is a schematic diagram showing the structure of an electronic device provided by an embodiment of the present application. Fig.11 As shown, the electronic device 900 includes: a processor 910, a memory 920 and a bus 930. The memory 920 stores machine-readable instructions executable by the processor 910. When the electronic device 900 is running, the processor 910 and the memory 920 communicate through the bus 930. The machine-readable instructions are executed by the processor 910 when it is running, such as the steps of the device structure manufacturing and effective etching method provided in any of the above embodiments.

[0161] Based on the same application concept, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the device structure manufacturing and effective etching method provided in the above embodiment are executed.

[0162] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0163] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0164] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0165] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0166] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for manufacturing and effectively etching a device structure, characterized in that: The method comprises: Providing a wafer after local isolation oxidation treatment, wherein the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; Measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the original thickness of the oxide isolation structure; Determine respectively a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxide isolation structure, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxide isolation structure, wherein the third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; Determining a target thickness loss amount of the oxide isolation structure during continuous etching according to an original thickness of the oxide isolation structure and a required thickness of the oxide isolation structure; According to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate, respectively calculating the thickness and etching time of the portion of the silicon oxynitride layer that needs to be etched using a hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched using a phosphoric acid reagent; According to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer, a total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and a total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid are obtained; Phosphoric acid reagent and hydrofluoric acid reagent are used to complete the etching of the silicon oxide layer, silicon oxynitride layer and silicon nitride layer of the wafer according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, and obtain an oxide isolation structure with a target thickness.

2. The method according to claim 1, characterized in that The total phosphoric acid etching time and the total hydrofluoric acid etching time to meet the required thickness of the oxide isolation structure are determined by the following formula: S=T(DHF3)×E a +T(HPO3)×f1(x) In this formula, S represents the target loss amount of the oxide isolation structure after the wafer etching is completed, S=S1-S2, S1 represents the original thickness of the oxide isolation structure before the wafer etching is performed, and S2 represents the required thickness of the oxide isolation structure after the etching is completed. T(DHF3) represents the total hydrofluoric acid etching time, E a represents the first etching rate, T(HPO3) represents the total phosphoric acid etching time, f1(x) represents the fifth etching rate of the phosphoric acid new acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x, and the fifth etching rate varies as a function of the phosphoric acid continuous etching workload x.

3. The method according to claim 2, characterized in that The total phosphoric acid etching time and the total hydrofluoric acid etching time are expressed by the following formula: In this formula, T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, T(DHF2) represents the etching time of the hydrofluoric acid reagent on part of the silicon oxynitride layer, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, and T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer.

4. The method according to claim 3, characterized in that: The etching time of the silicon oxide layer with hydrofluoric acid is determined by the following formula: T(DHF1)=(X / E a ) In this formula, X represents the thickness of the silicon oxide layer, E a It represents the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer.

5. The method according to claim 3, characterized in that: The etching time of the hydrofluoric acid reagent on the silicon oxynitride layer is determined by the following formula: T(DHF2)=Z / E1 In the formula, Z represents the thickness of the portion of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and E1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

6. The method according to claim 3, characterized in that The etching time of the silicon nitride layer with phosphoric acid reagent is determined by the following formula: T(HPO1)=(Y / E b ) × n In this formula, Y represents the thickness of the silicon nitride layer, E b It represents the fourth etching rate of phosphoric acid reagent on silicon nitride layer, and n represents a given excess etching coefficient.

7. The method according to claim 3, characterized in that The etching time of the remaining silicon oxynitride layer by phosphoric acid reagent is determined by the following formula: T(HPO2)=(MZ) / f2(x) In this formula, M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous phosphoric acid etching workload x, Z represents the thickness of the partial silicon oxynitride layer etched by the hydrofluoric acid reagent, and MZ represents the thickness of the remaining silicon oxynitride layer after etching with the hydrofluoric acid reagent, and the remaining silicon oxynitride layer is etched by the phosphoric acid reagent.

8. The method according to claim 2, characterized in that: The fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x is determined by the following formula: f1(x)=9×10 8 x 2 -0.0007x+1.5945。 9. The method according to claim 7, characterized in that: The third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the phosphoric acid continuous etching workload x is determined by the following formula: f2(x)=10 7 x 2 -0.0013x+2.983 In the formula, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous phosphoric acid etching workload x.

10. A device structure manufacturing and effective etching device, characterized in that: The device comprises: A module is provided, for providing a wafer after local isolation oxidation treatment, wherein the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; A measurement module, used to measure the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the original thickness of the oxide isolation structure; An etching rate determination module is used to respectively determine a first etching rate of a hydrofluoric acid reagent on a silicon oxide layer and an oxidation isolation structure, a second etching rate of a hydrofluoric acid reagent on a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on a silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on a silicon nitride layer, and a fifth etching rate of a phosphoric acid reagent on a silicon oxide layer and an oxidation isolation structure, wherein the third etching rate and the fifth etching rate vary with a phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of wafers etched from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; A loss amount determination module is used to determine a target loss amount of thickness of the oxide isolation structure during continuous etching according to an original thickness of the oxide isolation structure and a required thickness of the oxide isolation structure; A first etching time determination module is used to calculate the thickness and etching time of a portion of the silicon oxynitride layer that needs to be etched using a hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched using a phosphoric acid reagent, respectively, according to the target loss amount, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness and the etching rate; A second etching time determination module is used to obtain a total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and a total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid according to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer; The etching module is used to use phosphoric acid reagent and hydrofluoric acid reagent to etch the silicon oxide layer, silicon oxynitride layer and silicon nitride layer of the wafer according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, and obtain an oxide isolation structure with a target thickness.

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