Preparation method of trench isolation structure and semiconductor structure
By utilizing trench isolation structures and step filleting in the semiconductor manufacturing process, the problems of traditional corner rounding that are difficult and unsatisfactory have been solved, achieving a more precise and high-quality rounding effect, and improving the performance of semiconductor devices. electrical performance and reliability.
Patent Information
- Application Number
- CN202411178319.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-01-21
AI Technical Summary
The traditional top corner smoothing process is difficult to perform and the smoothing effect is not ideal. Especially when the gate oxide layer is thick, it affects the electrical performance and reliability of semiconductor devices.
By forming a grooved structure on the substrate, round -pointed treatment is used by the steps to form a more accurate and high -quality side wall top angle appearance, thereby improving the electrical performance and reliability of semiconductor devices.
It achieves a more accurate and high-quality smooth effect, improves the production yield of the semiconductor process and the reliability of the semiconductor device, and avoids process incompatibility or processing difficulty caused by the unsatisfactory sidewall apex angle morphology in subsequent processes. Added problem.
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Figure CN119340270A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a trench isolation structure and a semiconductor structure. Background Art
[0002] In the semiconductor manufacturing process, in order to avoid the electric field concentration effect caused by sharp corners, the corners of the active area can be rounded. The rounding process can not only reduce the electric field concentration, but also improve the increase of parasitic capacitance and parasitic resistance, avoid affecting the switching speed and energy consumption performance of semiconductor devices, and thus improve the electrical performance of semiconductor devices.
[0003] However, the traditional top corner rounding process is difficult to perform, the rounding effect is not ideal and has limitations. For example, when the gate oxide layer (Gate Oxide) is relatively thick, the difficulty of top corner rounding is further increased, thereby affecting the electrical performance and reliability of semiconductor devices.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention
[0005] Based on this, the embodiments of the present application provide a method for preparing a trench isolation structure and a semiconductor structure, which can achieve a more precise and higher-quality rounding effect, and help improve the production yield of the semiconductor process and the reliability of semiconductor devices.
[0006] According to some embodiments, the present application provides a method for preparing a trench isolation structure, comprising the following steps:
[0007] Providing a substrate, and sequentially forming a first mask material layer and a first patterned photoresist layer on one side of the substrate in a direction away from the substrate; the first patterned photoresist layer has a first opening pattern;
[0008] According to the first opening pattern, an initial opening is etched in the first mask material layer, and an isolation trench is etched in the substrate based on the initial opening, and the first mask material layer is retained as a patterned mask layer;
[0009] forming a second patterned photoresist layer above the patterned mask layer, wherein the second patterned photoresist layer has a second opening pattern;
[0010] According to the second opening pattern, etching the patterned mask layer and the top corners of the side walls of the isolation trench in a direction of expanding the initial opening, so as to etch a step at the top corners of the side walls of the isolation trench;
[0011] The step is rounded, and an isolation dielectric layer is formed in the isolation trench after the rounding.
[0012] In some embodiments, before forming the second patterned photoresist layer on the patterned mask layer, the preparation method further includes the following steps:
[0013] forming a filling dielectric material layer, wherein the filling dielectric material layer fills the isolation trench and covers the patterned mask layer;
[0014] forming a second mask material layer on a side of the filling dielectric material layer away from the patterned mask layer;
[0015] The step of forming a second patterned photoresist layer on the patterned mask layer comprises the following steps:
[0016] The second patterned photoresist layer is formed on a side of the second mask material layer away from the filling dielectric material layer.
[0017] In some embodiments, after etching the step at the top corner of the sidewall of the isolation trench, the preparation method further includes the following steps:
[0018] The remaining second mask material layer and the filling dielectric material layer are removed.
[0019] In some embodiments, the material forming the filling dielectric material layer includes an organic filling material.
[0020] In some embodiments, a gate dielectric layer is further formed between the patterned mask layer and the substrate.
[0021] In some embodiments, the rounding of the step comprises the following steps:
[0022] A passivation layer is formed on the inner wall of the isolation trench, and the passivation layer also covers the step.
[0023] In some embodiments, the passivation layer and the isolation dielectric layer have the same constituent material.
[0024] In some embodiments, the step of forming a passivation layer on the inner wall of the isolation trench comprises the following steps:
[0025] A furnace tube process is adopted to form a liner oxide layer on the inner wall of the isolation trench, and the liner oxide layer is used as the passivation layer.
[0026] In some embodiments, the first mask material layer includes a nitride material layer.
[0027] According to some embodiments, the present application further provides a semiconductor structure on the other hand, wherein the semiconductor structure has a trench isolation structure, and the trench isolation structure is prepared by the method for preparing the trench isolation structure provided in the aforementioned embodiment.
[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.
[0029] The embodiments of the present application may or at least have the following advantages:
[0030] In an embodiment of the present application, an initial opening is first etched in the first mask material layer based on the first opening pattern in the first patterned photoresist layer, and an isolation groove is etched in the substrate based on the initial opening; then, the sidewall top angles of the patterned mask layer and the isolation groove are etched in the direction of expanding the initial opening based on the second opening pattern in the second patterned photoresist layer, so as to etch a step at the sidewall top angle of the isolation groove. In the embodiment of the present application, the sidewall top angle of the isolation groove is rounded by a step. Compared with the traditional rounding process, the rounding process based on the step makes the roundness of the sidewall top angle of the isolation groove controllable, which is conducive to achieving more accurate and higher quality sidewall top angle morphology, thereby improving the production yield of the semiconductor process and the reliability of the use of semiconductor devices. In addition, by controlling the roundness of the sidewall top angle of the isolation groove, it is possible to avoid problems such as process incompatibility or increased processing difficulty due to the sidewall top angle morphology not meeting the requirements in the subsequent process. Therefore, the embodiment of the present application can ensure the performance and reliability of the semiconductor device while also helping to optimize the semiconductor process.
[0031] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.
[0033] Figure 1 A schematic diagram of a process for preparing a trench isolation structure provided in some embodiments of the present application;
[0034] Figure 2 A schematic diagram of the process of preparing a trench isolation structure provided in some embodiments of the present application before forming a second patterned photoresist layer;
[0035] Figure 3A schematic cross-sectional view of a structure obtained after forming a first patterned photoresist layer in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0036] Figure 4 A schematic diagram of the cross-sectional structure of a structure obtained after etching an isolation trench in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0037] Figure 5 A schematic diagram of a cross-sectional structure of a structure obtained after a filling dielectric material layer is formed in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0038] Figure 6 A schematic cross-sectional view of a structure obtained after forming a second mask material layer in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0039] Figure 7 A schematic cross-sectional view of a structure obtained after forming a second patterned photoresist layer in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0040] Figure 8 A schematic diagram of a cross-sectional structure of a structure obtained after etching a step in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0041] Fig. 9 A schematic diagram of a cross-sectional structure of a structure obtained after rounding a step in a method for preparing a trench isolation structure provided in some embodiments of the present application;
[0042] Fig.10 A schematic cross-sectional view of a structure obtained after forming an isolation dielectric layer in a method for preparing a trench isolation structure provided in some embodiments of the present application.
[0043] Description of reference numerals:
[0044] 11. substrate; 12. first mask material layer; 13. gate dielectric material layer; 14. advanced graphic thin film; 15. dielectric anti-reflection layer; 16. first graphic photoresist layer; 21. graphic mask layer; 22. gate dielectric layer; 31', filling dielectric material layer; 32. second mask material layer; 33. second graphic photoresist layer; 51. isolation dielectric layer; 52. passivation layer;
[0045] t, initial opening; T, isolation trench; S, step. DETAILED DESCRIPTION
[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0048] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.
[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0051] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.
[0052] In the semiconductor manufacturing process, in order to avoid the electric field concentration effect caused by sharp corners, the corners of the active area can be rounded. The rounding process can not only reduce the electric field concentration, but also improve the increase of parasitic capacitance and parasitic resistance, avoid affecting the switching speed and energy consumption performance of semiconductor devices, and thus improve the electrical performance of semiconductor devices.
[0053] However, the traditional top corner rounding process is difficult to perform, the rounding effect is not ideal and has limitations. For example, when the gate oxide layer (Gate Oxide) is relatively thick, the difficulty of top corner rounding is further increased, thereby affecting the electrical performance and reliability of semiconductor devices.
[0054] In view of the shortcomings of the related art, the present application provides a method for preparing a trench isolation structure and a semiconductor structure, which can achieve a more precise and better rounding effect, and help improve the production yield of semiconductor processes and the reliability of semiconductor devices. The details will be described in the subsequent embodiments.
[0055] See also Figure 1 The present application provides a method for preparing a trench isolation structure. The preparation method may specifically include the following steps S100 to S500:
[0056] S100: providing a substrate, and sequentially forming a first mask material layer and a first patterned photoresist layer on one side of the substrate in a direction away from the substrate; the first patterned photoresist layer has a first opening pattern.
[0057] S200: etching an initial opening in a first mask material layer according to a first opening pattern, and etching an isolation trench in a substrate based on the initial opening, and retaining the first mask material layer as a patterned mask layer.
[0058] S300: forming a second patterned photoresist layer on the patterned mask layer, wherein the second patterned photoresist layer has a second opening pattern.
[0059] S400: etching the patterned mask layer and the top corners of the side walls of the isolation trenches in a direction of expanding the initial opening according to the second opening pattern, so as to etch a step at the top corners of the side walls of the isolation trenches.
[0060] S500: performing a rounding process on the step, and forming an isolation dielectric layer in the rounded isolation trench.
[0061] In the above preparation method, an initial opening is first etched in the first mask material layer based on the first opening pattern in the first patterned photoresist layer, and an isolation groove is etched in the substrate based on the initial opening; then, based on the second opening pattern in the second patterned photoresist layer, the side wall corners of the patterned mask layer and the isolation groove are etched in the direction of expanding the initial opening, thereby etching a step at the side wall corner of the isolation groove.
[0062] The above-mentioned preparation method utilizes steps to round the top corners of the side walls of the isolation trench. Compared with the traditional rounding process, the step-based rounding method makes the smoothness of the top corners of the side walls of the isolation trench controllable, which is conducive to achieving more precise and higher-quality side wall top corner morphology, thereby improving the production yield of the semiconductor process and the reliability of semiconductor devices.
[0063] In addition, the above-mentioned preparation method can control the smoothness of the top angle of the isolation trench side wall, and can also avoid problems such as process incompatibility or increased processing difficulty caused by the side wall top angle morphology not meeting the requirements in subsequent processes. Therefore, the embodiments of the present application can ensure the performance and reliability of semiconductor devices while helping to optimize the semiconductor process.
[0064] See also Figure 2 In some embodiments, before forming a second patterned photoresist layer on the patterned mask layer, the preparation method may further include the following steps S210 to S220:
[0065] S210: forming a filling dielectric material layer, wherein the filling dielectric material layer fills the isolation trench and covers the patterned mask layer.
[0066] S220: forming a second mask material layer on a side of the filling dielectric material layer away from the patterned mask layer.
[0067] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 3 to 10 Understand some embodiments of the present application.
[0068] In step S100, refer to Figure 3 , providing a substrate 11, and sequentially forming a first mask material layer 12 and a first patterned photoresist layer 16 on one side of the substrate 11 in a direction away from the substrate 11; the first patterned photoresist layer 16 has a first opening pattern.
[0069] For example, the substrate 11 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 11 can be a single-layer structure or a multi-layer structure. For example, the substrate 11 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 11 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.
[0070] The present embodiment of the application does not specifically limit the constituent material of the first mask material layer 12 formed in step S100. In some embodiments, the first mask material layer 12 may include but is not limited to a nitride material layer. Nitride materials have high corrosion resistance and stability, and can provide a good masking effect in the subsequent etching process, ensuring high processing accuracy in the formation of the initial opening and the step, thereby ensuring the accuracy and production yield of the trench isolation structure.
[0071] Exemplarily, the nitride material layer may include but is not limited to a silicon nitride (SiN) layer.
[0072] In step S200, refer to Figure 4 According to the first opening pattern, an initial opening t is etched in the first mask material layer 12 , and based on the initial opening t, an isolation trench T is etched in the substrate 11 , and the retained first mask material layer 12 is used as a patterned mask layer 21 .
[0073] In some embodiments, in step S200, an initial opening t is etched in the mask material layer 12, which can be specifically performed as follows:
[0074] First, if Figure 3 As shown, an advanced pattern film 14 (APF) and a dielectric anti-reflective layer 15 are sequentially formed on the side of the mask material layer 12 away from the substrate 11 as a hard mask, and a patterned photoresist (PR) layer 16 is formed on the side of the dielectric anti-reflective layer 15 away from the advanced pattern film 14.
[0075] The first opening pattern in the first patterned photoresist layer 16 can be used to define the shape, size and distribution of the isolation trench T. The advanced pattern film 14 can be used to improve the accuracy of transferring the first opening pattern in the first patterned photoresist layer 16 to the mask material layer 12. The dielectric anti-reflection layer 15 can be used to absorb the light irradiated thereon, thereby improving the pattern transferred to the advanced pattern film 14. The constituent material of the dielectric anti-reflection layer 15 may include but is not limited to silicon oxynitride (SiON).
[0076] After forming the first patterned photoresist layer 16, the dielectric anti-reflection layer 15 and the advanced patterned film 14 are sequentially etched using the first patterned photoresist layer 16 as a mask, so as to transfer the first opening pattern in the first patterned photoresist layer 16 to the first mask material layer 12. Figure 4 As shown, an initial opening t is etched.
[0077] In some embodiments, please refer to Figure 4 A gate dielectric layer 22 may be formed between the patterned mask layer 21 and the substrate 11. The gate dielectric layer 22 may include, for example, a gate oxide layer (Gate Oxide, GOX for short).
[0078] In the above embodiment, if Figure 3 As shown, a gate dielectric material layer 13, a first mask material layer 12, an advanced graphic thin film 14 and a dielectric anti-reflection layer 15 can be sequentially formed on one side of the substrate 11 as a hard mask. Afterwards, the dielectric anti-reflection layer 15 and the advanced graphic thin film 14 are sequentially etched using the first patterned photoresist layer 16 as a mask to transfer the pattern in the first patterned photoresist layer 16 to the first mask material layer 12 and the gate dielectric material layer 13, and an initial opening t is etched. At this point, the remaining gate dielectric material layer 13 serves as the gate dielectric layer 22.
[0079] In some embodiments, please combine Figures 5 and 6 It is understood that the preparation method may further include the following steps S210 to S220.
[0080] In step S210, Figure 5 As shown, a filling dielectric material layer 31 ′ is formed, and the filling dielectric material layer 31 ′ fills the isolation trench T and covers the patterned mask layer 21 .
[0081] In step S220, Figure 6 As shown, a second mask material layer 32 is formed on a side of the filling dielectric material layer 31 ′ away from the patterned mask layer 21 .
[0082] In step S300, refer to Figure 7, a second patterned photoresist layer 33 is formed on the patterned mask layer 21, and the second patterned photoresist layer 33 has a second opening pattern.
[0083] In some embodiments, the second patterned photoresist layer 33 may be formed on a side of the second mask material layer 32 away from the filling dielectric material layer 31 ′.
[0084] In the above embodiment, by forming a filling dielectric material layer 31', filling the isolation trench T and covering the patterned mask layer 21, the isolation trench T can be protected by the filling dielectric material layer 31' in the subsequent etching process, so that the morphology of the isolation trench T will not be damaged in the subsequent etching process.
[0085] The present application embodiment does not specifically limit the constituent material of the filling dielectric material layer 31' formed in the above step S210. In some embodiments, the constituent material of the filling dielectric material layer 31' may include an organic filling material. The organic filling material may be, for example, a bottom anti-reflective coating (BARC) material or a spin-on carbon (SOC) material, but is not limited thereto; the organic filling material may be spin-coated in the isolation trench T and on the surface of the patterned mask layer 21 using a spin coating process as the filling dielectric material layer 31'.
[0086] As an example, on the basis of the above steps, a chemical mechanical planarization (CMP) process or other planarization processes can be used to planarize the top surface of the filling dielectric material layer 31' to achieve precise flatness and uniformity, thereby ensuring that subsequent etching process steps can be performed on a flat surface, improving the processing accuracy of subsequent etching steps, and reducing the generation of defects, which is conducive to more accurately defining the morphology of the steps.
[0087] The present embodiment of the present application does not specifically limit the constituent material of the second mask material layer 32. As an example, the constituent material of the second mask material layer 32 may include an oxide material, such as an oxide (SiO x ) materials or doped oxide materials, etc., but not limited to them.
[0088] In step S400, refer to Figure 8 According to the second opening pattern, the patterned mask layer 21 and the top corners of the side walls of the isolation trench T are etched along the direction of expanding the initial opening t, so as to etch a step S at the top corners of the side walls of the isolation trench T.
[0089] It can be understood that the second opening pattern in the second patterned photoresist layer 33 can be used to define the size of the step S. Specifically, the orthographic projection of the second opening pattern in the second patterned photoresist layer 33 falling on the surface of the substrate 11 should be able to include the orthographic projection of the first opening pattern in the first patterned photoresist layer 16 falling on the surface of the substrate 11. In this way, the initial opening t can be enlarged during the execution of the above step S400.
[0090] Specifically, in the above step S400 , the second patterned photoresist layer 33 is used as a mask to sequentially etch the patterned mask layer 21 and the top corners of the sidewalls of the isolation trenches T, so as to etch out the steps S at the top corners of the sidewalls of the isolation trenches T.
[0091] It should be noted that, in some embodiments, the patterned mask layer 21 and the gate dielectric layer 22 may be etched simultaneously, so that the side walls of the patterned mask layer 21 and the gate dielectric layer 22 simultaneously retreat in the direction of expanding the initial opening t1, thereby etching a step S at the top corner of the side wall of the isolation trench T.
[0092] In some embodiments, after performing step S400 to etch the step S at the top corner of the sidewall of the isolation trench T, the remaining second mask material layer 32 and the filling dielectric material layer 31 ′ may be removed.
[0093] In step S500, refer to Fig. 9 , the step S is rounded, and an isolation dielectric layer 51 is formed in the isolation trench T after the rounding process. Fig.10 shown.
[0094] In some embodiments, Fig. 9 As shown, the process of rounding the step S may include the following steps:
[0095] A passivation layer 52 is formed on the inner wall of the isolation trench T, and the passivation layer 52 also covers the step S.
[0096] The present application embodiment does not specifically limit the constituent material of the passivation layer 52 formed in the above steps. In some embodiments, the passivation layer 52 and the isolation dielectric layer 51 may have the same constituent material. That is, the isolation dielectric layer 51 may be formed using the same constituent material as the passivation layer 52. Using the same constituent material as the passivation layer 52 as the isolation dielectric material can ensure that in the subsequent heat treatment and use process, there will be no inconsistency in stress or interface effects due to differences in constituent materials, thereby improving the production yield and use reliability of the trench isolation structure.
[0097] Similarly, the passivation layer 52 may be formed of the same material as the gate dielectric layer 22. For example, the gate dielectric layer 22, the passivation layer 52 and the isolation dielectric layer 51 may have the same material to further improve the production yield and reliability of the trench isolation structure.
[0098] The present embodiment of the application does not specifically limit the material of the isolation dielectric layer 51. As an example, the constituent material of the isolation dielectric layer 51 may include but is not limited to oxide materials (eg, silicon dioxide).
[0099] In some embodiments, a furnace tube process may be used to form a liner oxide layer on the inner wall of the isolation trench T, and the liner oxide layer is used as the passivation layer 52. The difference in consumption of substrate materials by the furnace tube process makes the top angle of the side wall of the isolation trench T smoother under the action of the step and can extend downward to a certain extent, so that the top angle of the side wall of the isolation trench T has better smoothness, further reduces electric field concentration, and improves the increase of parasitic capacitance and parasitic resistance.
[0100] Based on the same inventive concept, the embodiment of the present application also provides a semiconductor structure on the other hand. The semiconductor structure has a trench isolation structure, and the trench isolation structure is prepared by the preparation method of the trench isolation structure provided in the above embodiment. Therefore, the technical effects that can be achieved by the preparation method of the above trench isolation structure can also be achieved by the semiconductor structure, which will not be repeated here.
[0101] It can be understood that the specific definition of the semiconductor structure can refer to the definition of the preparation method of the trench isolation structure above, and the technical features between the method embodiment and the structural embodiment can also be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of this application. No further details will be given here.
[0102] In addition, those skilled in the art will understand that Fig.10 The structure shown is merely a schematic diagram of some layers and / or parts related to the scheme of the present application, and does not constitute a limitation of the scheme of the present application. The specific semiconductor structure may include more layers and / or parts than those shown in the figure, or combine certain layers and / or parts, or have a different arrangement.
[0103] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0104] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a trench isolation structure, characterized in that: The steps include: Providing a substrate, and sequentially forming a first mask material layer and a first patterned photoresist layer on one side of the substrate in a direction away from the substrate; the first patterned photoresist layer has a first opening pattern; According to the first opening pattern, an initial opening is etched in the first mask material layer, and an isolation trench is etched in the substrate based on the initial opening, and the first mask material layer is retained as a patterned mask layer; forming a second patterned photoresist layer above the patterned mask layer, wherein the second patterned photoresist layer has a second opening pattern; According to the second opening pattern, etching the patterned mask layer and the top corners of the side walls of the isolation trench in a direction of expanding the initial opening, so as to etch a step at the top corners of the side walls of the isolation trench; The step is rounded, and an isolation dielectric layer is formed in the isolation trench after the rounding.
2. The method for preparing a trench isolation structure according to claim 1, characterized in that: Before forming the second patterned photoresist layer on the patterned mask layer, the preparation method further includes the following steps: forming a filling dielectric material layer, wherein the filling dielectric material layer fills the isolation trench and covers the patterned mask layer; forming a second mask material layer on a side of the filling dielectric material layer away from the patterned mask layer; The step of forming a second patterned photoresist layer on the patterned mask layer comprises the following steps: The second patterned photoresist layer is formed on a side of the second mask material layer away from the filling dielectric material layer.
3. The method for preparing a trench isolation structure according to claim 2, characterized in that: After etching the step at the top corner of the sidewall of the isolation trench, the preparation method further comprises the following steps: The remaining second mask material layer and the filling dielectric material layer are removed.
4. The method for preparing a trench isolation structure according to claim 2, characterized in that: The constituent material of the filling medium material layer includes an organic filling material.
5. The method for preparing a trench isolation structure according to claim 1, characterized in that: A gate dielectric layer is also formed between the patterned mask layer and the substrate.
6. The method for preparing a trench isolation structure according to claim 1, characterized in that: The step of rounding the steps comprises the following steps: A passivation layer is formed on the inner wall of the isolation trench, and the passivation layer also covers the step.
7. The method for preparing a trench isolation structure according to claim 6, characterized in that: The passivation layer and the isolation dielectric layer have the same constituent material.
8. The method for preparing a trench isolation structure according to claim 6, characterized in that: The step of forming a passivation layer on the inner wall of the isolation trench comprises the following steps: A furnace tube process is adopted to form a liner oxide layer on the inner wall of the isolation trench, and the liner oxide layer is used as the passivation layer.
9. The method for preparing a trench isolation structure according to claim 1, characterized in that: The first mask material layer includes a nitride material layer.
10. A semiconductor structure, characterized in that: The semiconductor structure has a trench isolation structure, and the trench isolation structure is prepared by the method for preparing a trench isolation structure according to any one of claims 1 to 9.