Semiconductor device and semiconductor module

Abstract

The invention provides a semiconductor device and a semiconductor module for reducing inductance. This semiconductor module is provided with: a semiconductor chip having an output electrode and an input electrode; a negative electrode terminal which is in contact with the negative electrode conductive layer of the wiring terminal and is electrically connected to the output electrode of the semiconductor chip; and a positive electrode terminal that is separated from the negative electrode terminal, is parallel to the negative electrode terminal, is in electrical contact with the positive electrode conductive layer of the wiring terminal, and is electrically connected to the input electrode of the semiconductor chip. The semiconductor module is further provided with a package in which the positive electrode terminal and the negative electrode terminal extend from a long side surface facing the wiring terminal to the outside in the same direction from the long side surface, the package affixes the semiconductor chip to the positive electrode terminal and the negative electrode terminal, and the package has a housing groove between the positive electrode terminal and the negative electrode terminal on the long side surface. The insulating end edge of the insulating layer of the wiring terminal is inserted into the accommodating groove.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a semiconductor module. Background Art

[0002] A semiconductor device includes a semiconductor module and a capacitor (condenser or capacitor) connected to the semiconductor module (for example, see Patent Document 1). The semiconductor module includes a semiconductor chip, a positive terminal, a negative terminal, and a packaging component that packages the semiconductor chip, and the positive terminal and the negative terminal extend outward from one surface of the packaging component (for example, see Patent Documents 2, 3, and 4). In addition, a method that does not rely on bolt fastening when connecting a bus bar to a semiconductor module has been proposed (for example, see Patent Document 5).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141729

[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-117944

[0007] Patent Document 3: International Publication No. 2017 / 119226

[0008] Patent Document 4: International Publication No. 2014 / 002442

[0009] Patent Document 5: International Publication No. 2015 / 162712 Summary of the invention

[0010] Technical issues

[0011] An object of the present invention is to provide a semiconductor device and a semiconductor module with reduced inductance.

[0012] Technical Solution

[0013] According to one aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising a wiring terminal and a semiconductor module, the wiring terminal comprising an insulating layer, a first conductive layer provided on one main surface of the insulating layer, and a second conductive layer provided on the other main surface of the insulating layer, the insulating end edge of the insulating layer extending to a position further outward than the conductive end edges of each of the first conductive layer and the second conductive layer, the semiconductor module comprising: a semiconductor chip having a first electrode and a second electrode; a first terminal comprising a first end portion and electrically connected to the first electrode of the semiconductor chip, the first end portion having a first contact surface in contact with the first conductive layer of the wiring terminal; A second terminal, comprising a second end portion electrically connected to the second electrode of the semiconductor chip, the second end portion being separated from the first end portion and having a second contact surface parallel to the first contact surface and electrically in contact with the second conductive layer of the wiring terminal; and a fixing portion, the first end portion and the second end portion extending in the same direction from a base surface of the fixing portion opposite to the wiring terminal to a position further outward than the base surface, the fixing portion fixing the semiconductor chip, the first terminal and the second terminal, and having a recess between the first end portion and the second end portion of the base surface, the insulating end edge of the insulating layer of the wiring terminal being inserted into the recess.

[0014] In addition, the fixing portion may be a packaging component.

[0015] In addition, the first end portion and the second end portion may be flat-plate-shaped, and the first end portion and the second end portion may be arranged on the base surface in such a manner that a first width direction of the first end portion is parallel to a second width direction of the second end portion when viewed from above, and the recess may be parallel to the first width direction and the second width direction when viewed from above.

[0016] Furthermore, the recess may be formed across the base surface in parallel with the first width direction and the second width direction.

[0017] Furthermore, the first end portion and the second end portion may be provided on the base surface at positions offset in the first width direction and the second width direction, respectively, in a plan view.

[0018] Furthermore, the conductive end sides of the first conductive layer and the second conductive layer of the wiring terminal may be in contact with the base surface of the semiconductor module.

[0019] Furthermore, the semiconductor device may further include a capacitor including the wiring terminal.

[0020] In addition, according to one aspect of the present invention, a semiconductor module is provided, which has: a first semiconductor chip having a first electrode and a second electrode; a second semiconductor chip having a third electrode and a fourth electrode electrically connected to the first electrode of the first semiconductor chip; a first terminal including a first end electrically connected to the first electrode of the first semiconductor chip, the first end having a first contact surface; a second terminal including a second end electrically connected to the fourth electrode of the second semiconductor chip, the second end being separated from the first end and having a second contact surface parallel to the first contact surface; and a fixing portion, the first end and the second end extending from a base surface of the fixing portion in the same direction to a position further outside than the base surface, the fixing portion fixing the first semiconductor chip, the second semiconductor chip, the first terminal and the second terminal, and having a recess between the first end and the second end of the base surface.

[0021] It should be noted that the above invention summary does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions.

[0022] Technical Effects

[0023] According to the disclosed technology, the inductance is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a top view of the semiconductor device according to the embodiment.

[0025] Figure 2 It is a side view (XZ plane) of the semiconductor device according to the embodiment.

[0026] Figure 3 It is a perspective view of a semiconductor module included in the semiconductor device according to the embodiment.

[0027] Figure 4 It is a side view (XZ plane) of a semiconductor module included in the semiconductor device according to the embodiment.

[0028] Figure 5 It is a side view (ZY plane) of a semiconductor module included in the semiconductor device according to the embodiment.

[0029] Figure 6 This is a back view of a semiconductor module included in the semiconductor device according to the embodiment.

[0030] Figure 7 It is a plan view of a semiconductor unit included in the semiconductor module according to the embodiment.

[0031] Figure 8It is a cross-sectional view of a semiconductor unit included in the semiconductor module according to the embodiment.

[0032] Fig. 9 It is a side view (ZY plane) of a semiconductor unit included in the semiconductor module according to the embodiment.

[0033] Fig.10 It is a plan view of an insulating circuit substrate included in the semiconductor module according to the embodiment.

[0034] Fig.11 This is a perspective view of a capacitor included in the semiconductor device according to the embodiment.

[0035] Fig.12 It is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment.

[0036] Fig.13 It is a side view (XZ plane) of the semiconductor device of the reference example.

[0037] Fig.14 It is a side view (ZY plane) of a semiconductor module included in the semiconductor device according to the embodiment (Variation 1).

[0038] Fig.15 It is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (variation 1).

[0039] Fig.16 It is a side view (ZY plane) of a semiconductor module included in the semiconductor device according to the embodiment (Variation 2).

[0040] Fig.17 It is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (variation 2).

[0041] Explanation of symbols

[0042] 1Semiconductor device

[0043] 2. 2a, 2b, 2c semiconductor modules

[0044] 3 Semiconductor unit

[0045] 5. Capacitor

[0046] 10 Package

[0047] 10a, 10c long side

[0048] 10b, 10d short side

[0049] 10e upper surface

[0050] 10f Bottom

[0051] 10g storage slot (recessed)

[0052] 20 Insulated circuit board

[0053] 21 Insulation layer

[0054] 21a, 21c long side

[0055] 21b, 21d short side

[0056] 22a Positive circuit pattern layer

[0057] 22a1 Terminal area

[0058] 22a2, 22a3 chip area

[0059] 22b Negative circuit pattern layer

[0060] 22b1 terminal area

[0061] 22b2, 22b3 wiring area

[0062] 22c output circuit pattern layer

[0063] 22c1 terminal area

[0064] 22c2, 22c3 wiring area

[0065] 22c4, 22c5 chip area

[0066] 22d, 22f control circuit pattern layer

[0067] 22e, 22g sensing circuit pattern layer

[0068] 23 Metal Layer

[0069] 30 Semiconductor Chip

[0070] 31 Control electrode

[0071] 35 Joint parts

[0072] 36 Control Line

[0073] 37 Sensing line

[0074] 38 Main current line

[0075] 40 Positive terminal

[0076] 40a Positive electrode junction area

[0077] 40c1 contact surface

[0078] 40d Fastening hole

[0079] 41 Negative terminal

[0080] 41a Negative electrode junction area

[0081] 41b Connection area

[0082] 41c wiring area

[0083] 41c1 contact surface

[0084] 41d Fastening hole

[0085] 42 Output terminals

[0086] 42a Output junction area

[0087] 43a, 43b control terminals

[0088] Ta, Tb, Tc configuration area

[0089] 50 Shell

[0090] 50a, 50c long side

[0091] 50b, 50d short sides

[0092] 50e upper surface

[0093] 50f bottom

[0094] 51 Wiring terminal

[0095] 52 Insulation layer

[0096] 53 positive electrode conductive layer

[0097] 53a Positive fastening hole

[0098] 53b Negative electrode opening

[0099] 54 negative electrode conductive layer

[0100] 54a Negative electrode fastening hole

[0101] 54b Positive electrode opening

[0102] 54d floating wiring

[0103] 54e Floating fastening hole

[0104] 55a Bolt

[0105] 55b Nut

[0106] 55c, 55d, 55e insulation parts DETAILED DESCRIPTION

[0107] Hereinafter, the embodiments will be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "upper surface" represent the XY plane facing the upper side (+Z direction) in the semiconductor device 1 of the accompanying drawings. Similarly, "up" represents the direction of the upper side (+Z direction) in the semiconductor device 1 of the figure. "Back" and "lower surface" represent the XY plane facing the lower side (-Z direction) in the semiconductor device 1 of the figure. Similarly, "lower" represents the direction of the lower side (-Z direction) in the semiconductor device 1 of the accompanying drawings. As required, the same directionality as above is also meant in other drawings. "High position" refers to the position indicating the upper side (+Z direction) in the semiconductor device 1 of the accompanying drawings. Similarly, "lower position" refers to the position indicating the lower side (-Z direction) in the semiconductor device 1 of the accompanying drawings. "Front", "upper surface", "upper" and "back", "lower surface", "lower" and "side" are merely expressions for the convenience of determining the relative positional relationship, and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily mean the vertical direction relative to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. In addition, in the following description, "main component" means the case where it contains 80% by volume or more. In addition, "substantially the same" can be within the range of ±10%. In addition, "vertical", "orthogonal" and "parallel" can be within the range of ±10°.

[0108] [Implementation Method]

[0109] use Figure 1 and Figure 2 A semiconductor device according to an embodiment will be described. Figure 1 is a top view of a semiconductor device according to an embodiment, Figure 2 1 is a side view (XZ plane) of a semiconductor device according to an embodiment. Figure 2 Observe in the +Y direction Figure 1 FIG. 1 is a side view of the semiconductor device 1 .

[0110] The semiconductor device 1 includes three semiconductor modules 2a to 2c and a capacitor 5. The semiconductor modules 2a to 2c all have the same configuration and the same function. Hereinafter, when the semiconductor modules 2a to 2c are not distinguished, they are referred to as the semiconductor module 2.

[0111] The semiconductor module 2 is connected to the capacitor 5 by clamping the front side and the back side of the wiring terminal 51 described later included in the capacitor 5 through the positive terminal 40 and the negative terminal 41 included in the semiconductor module 2. The positive terminal 40 and the negative terminal 41 of the semiconductor module 2 are connected to the wiring terminal 51 of the capacitor 5 by nuts and bolts, respectively. The details of this connection will be described later.

[0112] Next, use Figure 3 to Figure 6The appearance of the semiconductor module 2 according to the embodiment will be described. Figure 3 It is a perspective view of a semiconductor module included in the semiconductor device according to the embodiment. Figure 4 It is a side view (XZ plane) of a semiconductor module included in the semiconductor device according to the embodiment. Figure 5 It is a side view (ZY plane) of a semiconductor module included in the semiconductor device according to the embodiment. Figure 6 This is a back view of a semiconductor module included in the semiconductor device according to the embodiment.

[0113] It should be explained that Figure 4 Observe in the -Y direction Figure 3 A side view of a semiconductor module 2 is shown. Figure 5 Observe in the +X direction Figure 3 A side view of a semiconductor module 2 is shown. Figure 6 Observe in the +Z direction Figure 3 A back view of the semiconductor module 2 is shown. Figure 5 The side view of the semiconductor module 2 viewed in the -Y direction can be referred to as Figure 4 Although omitted, Figure 3 In the side view of the semiconductor module 2 viewed in the −X direction, only the output terminal 42 extends from the long side surface 10 c.

[0114] The semiconductor module 2 includes a semiconductor unit 3 ( Figure 7 to Figure 10 ) and a package 10 that packages the semiconductor unit 3. The package 10 is an example of a fixing portion, and fixes the semiconductor chip 30, the positive terminal 40, and the negative terminal 41 included in the semiconductor unit 3. The package 10 is a cube, including an upper surface 10e that is rectangular in a plan view and a bottom surface 10f opposite to the upper surface 10e. The package 10 also includes a long side 10a, a short side 10b, a long side 10c, and a short side 10d that sequentially surround the upper surface 10e and the bottom surface 10f.

[0115] The upper surface 10e and the bottom surface 10f are of substantially the same shape and of substantially the same size. The upper surface 10e and the bottom surface 10f are substantially smooth as a whole. The upper surface 10e and the bottom surface 10f are also substantially parallel. The control terminals 43a and 43b included in the semiconductor unit 3 each extend vertically upward (in the +Z direction) from the upper surface 10e. The back surface of the metal layer 23 of the insulating circuit substrate 20 described later included in the semiconductor unit 3 is exposed from the bottom surface 10f. The metal layer 23 is substantially flush with the bottom surface 10f.

[0116] The long side surfaces 10a and 10c respectively connect the long sides of the upper surface 10e and the bottom surface 10f. The connection portion is approximately at a right angle. The connection portion is not limited to a right angle, and may also be R-chamfered or C-chamfered. The long side surface 10a is a base surface, and the positive terminal 40 and the negative terminal 41 included in the semiconductor unit 3 each extend in the vertical direction (-X direction). It should be noted that when viewed from the side (viewed in the +X direction), the negative terminal 41 is located on the side of the upper surface 10e, and the positive terminal 40 is located on the side of the bottom surface 10f.

[0117] In addition, when the long side surface 10a is viewed from the side (viewed in the +X direction), a recess, namely a storage groove 10g, is formed between the positive terminal 40 and the negative terminal 41 (the upper surface 10e and the bottom surface 10f). The storage groove 10g is formed on the long side surface 10a in a manner that crosses the width of the long side surface 10a in the ±Y direction. In addition, the storage groove 10g is formed to be parallel to the width directions of the positive terminal 40 and the negative terminal 41 respectively when viewed from above. The depth (in the +X direction) and the width (in the ±Z direction) of the storage groove 10g can be a size that the front end of the insulating layer 52 described later can fully enter, and the insulating layer 52 protrudes from the positive conductive layer 53 and the negative conductive layer 54 of the wiring terminal 51 of the capacitor 5. It should be noted that the depth (in the +X direction) of the storage groove 10g can also be a depth that does not reach the connection area 41b of the negative terminal 41 in the package 10 (refer to Figure 8 ) depth. In order to maintain the insulation of the connection area 41b of the negative terminal 41, the distance (in the ±X direction) between the bottom of the storage groove 10g and the connection area 41b of the negative terminal 41 in the package 10 can be about 1 mm. It should be noted that the opening of the storage groove 10g can also be R-chamfered or C-chamfered.

[0118] The output terminal 42 included in the semiconductor unit 3 extends in the vertical direction (+X direction) at the center of the long side surface 10 c. The output terminal 42 may be located at substantially the same height as the positive electrode terminal 40 .

[0119] The short side surfaces 10b and 10d connect the short sides of the upper surface 10e and the bottom surface 10f, respectively. Moreover, the short side surfaces 10b and 10d (along the circumference of the package body 10) connect the two sides of the long side surfaces 10a and 10c, respectively. Each connection part is substantially at a right angle. The connection part is not limited to a right angle, and can also be R-chamfered or C-chamfered.

[0120] Such a package 10 is composed of a thermosetting resin as a main component. Examples of the thermosetting resin include epoxy resin, phenolic resin, and maleimide resin. In addition, the thermosetting resin may contain a filler. Examples of the filler include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride.

[0121] Next, use Figure 7 to Figure 10The semiconductor unit 3 will be described. Figure 7 is a top view of a semiconductor unit included in a semiconductor module according to an embodiment, Figure 8 It is a cross-sectional view of a semiconductor unit included in the semiconductor module according to the embodiment. Fig. 9 It is a side view (ZY plane) of a semiconductor unit included in the semiconductor module according to the embodiment. Fig.10 1 is a top view of an insulating circuit substrate included in a semiconductor module according to an embodiment. Figure 8 yes Figure 7 Cross-sectional view at the single-dot chain line YY. Fig. 9 Observe in the +X direction Figure 7 A side view of the semiconductor unit 3 is shown. Figure 8 and Fig. 9 Illustration of the control terminals 43a and 43b and various wires is omitted.

[0122] The semiconductor unit 3 includes an insulating circuit substrate 20 , a semiconductor chip 30 , a control line 36 , a sensing line 37 , a main current line 38 , a positive electrode terminal 40 , a negative electrode terminal 41 , an output terminal 42 , and control terminals 43 a and 43 b .

[0123] The insulating circuit substrate 20 is rectangular in shape when viewed from above. The insulating circuit substrate 20 has an insulating layer 21, a plurality of circuit pattern layers formed on the front side of the insulating layer 21, and a metal layer 23 formed on the back side of the insulating layer 21. It should be noted that the plurality of circuit pattern layers include a positive circuit pattern layer 22a, a negative circuit pattern layer 22b, an output circuit pattern layer 22c, a control circuit pattern layer 22d, 22f, and a sensing circuit pattern layer 22e, 22g. Hereinafter, they are referred to as circuit pattern layers without particularly distinguishing them. The outer shapes of the plurality of circuit pattern layers and the metal layer 23 are smaller than the outer shapes of the insulating layer 21 when viewed from above, and are formed on the inner side of the insulating layer 21. It should be noted that the shape, number, and size of the plurality of circuit pattern layers are an example.

[0124] The insulating layer 21 is rectangular in plan view. In addition, the corners of the insulating layer 21 may be chamfered. For example, C chamfering or R chamfering may be performed. The insulating layer 21 is surrounded by a long side surface 21a, a short side surface 21b, a long side surface 21c, and a short side surface 21d as the outer periphery. Such an insulating layer 21 is made of ceramics with excellent thermal conductivity. For example, the ceramics are made of a material having aluminum oxide, aluminum nitride, or silicon nitride as a main component.

[0125] The metal layer 23 is rectangular in shape when viewed from above. In addition, the corners may be, for example, C-chamfered or R-chamfered. The size of the metal layer 23 is smaller than that of the insulating layer 21, and is formed on the entire back side of the insulating layer 21 except for the edge portion. The metal layer 23 is composed of a metal with excellent thermal conductivity as a main component. The metal is, for example, copper, aluminum, or an alloy containing at least one of them. In order to improve the corrosion resistance of the metal plate, a plating treatment may also be performed. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0126] As described above, the plurality of circuit pattern layers include a positive circuit pattern layer 22a, a negative circuit pattern layer 22b, an output circuit pattern layer 22c, control circuit pattern layers 22d, 22f, and sensing circuit pattern layers 22e, 22g. The plurality of circuit pattern layers are formed on the entire surface of the insulating layer 21 except for the edge portion. Preferably, when viewed from above, the ends of the plurality of circuit pattern layers facing the periphery of the insulating layer 21 overlap with the ends of the metal layer 23 on the periphery side of the insulating layer 21.

[0127] The plurality of circuit pattern layers are made of metals with excellent electrical conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of them. In addition, in order to improve corrosion resistance, the surfaces of the plurality of circuit pattern layers may be plated. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0128] The positive circuit pattern layer 22a included in the plurality of circuit pattern layers is F-shaped in a plan view and is formed facing the long side surface 21a of the insulating layer 21. The positive circuit pattern layer 22a includes a terminal region 22a1 and chip regions 22a2 and 22a3.

[0129] The terminal area 22a1 is rectangular in shape when viewed from above. The terminal area 22a1 is formed on the front side of the insulating layer 21 in a manner extending parallel to the long side 21a (long side direction). The end of the terminal area 22a1 in the -Y direction and the center line C of the front side of the insulating layer 21 are separated by a predetermined distance toward the short side 21b. It should be noted that the center line C passes through the center of the long sides 21a and 21c and is parallel to the short sides 21b and 21d. A gap is left between the end of the terminal area 22a1 in the +Y direction and the short side 21b. The terminal area 22a1 faces the long side 21a. The dotted area (configuration area Ta) shown in the terminal area 22a1 is the bonding portion of the positive terminal 40.

[0130] The chip area 22a2 is rectangular in a plan view. The chip area 22a2 extends from the end of the terminal area 22a1 in the +Y direction toward the long side 21c in a manner parallel to the short side surfaces 21b and 21d (short side direction). A gap is left between the end of the chip area 22a2 in the +X direction and the long side surface 21c. The end of the chip area 22a2 in the +Y direction is in the same plane as the end of the terminal area 22a1 in the +Y direction. The two dotted line areas shown in the chip area 22a2 are the bonding parts of the semiconductor chip 30.

[0131] The chip area 22a3 is rectangular in shape when viewed from above. The chip area 22a3 is connected to a position separated by a predetermined distance in the +Y direction from the end of the terminal area 22a1 in the -Y direction, and extends toward the long side 21c in a manner parallel to the short side surfaces 21b and 21d. There is a gap between the end of the chip area 22a3 in the +X direction and the long side surface 21c. The ends of the chip areas 22a2 and 22a3 in the +X direction are in the same plane. In addition, there is a gap between the end of the chip area 22a3 in the -Y direction and the center line C. There is a gap between the end of the chip area 22a2 in the -Y direction and the end of the chip area 22a3 in the +Y direction. The two dotted line areas shown in the chip area 22a3 are the bonding parts of the semiconductor chip 30. It should be noted that the width of the chip area 22a3 in the ±Y direction is approximately equal to the width of the chip area 22a2 in the ±Y direction.

[0132] The negative circuit pattern layer 22b included in the plurality of circuit pattern layers is J-shaped in a plan view and is formed facing the long side surface 21a of the insulating layer 21. The negative circuit pattern layer 22b includes a terminal region 22b1 and wiring regions 22b2 and 22b3.

[0133] The terminal area 22b1 is rectangular in shape when viewed from above. The terminal area 22b1 is formed on the front side of the insulating layer 21 in a manner extending parallel to the long side 21a (long side direction). The end of the terminal area 22b1 in the +Y direction is separated from the center line C of the front side of the insulating layer 21 by a predetermined distance toward the short side 21d. In addition, the end of the terminal area 22b1 in the +Y direction and the end of the terminal area 22a1 in the -Y direction are line symmetrical with respect to the center line C. The terminal area 22b1 faces the long side 21a. The dotted area (configuration area Tb) shown in the terminal area 22b1 is the bonding portion of the negative terminal 41.

[0134] The wiring area 22b2 is rectangular in a plan view. The wiring area 22b2 extends from the end of the terminal area 22b1 in the +Y direction toward the long side 21c in a manner parallel to the short side surfaces 21b and 21d (short side direction). A gap is left between the end of the wiring area 22b2 in the +X direction and the long side surface 21c. The end of the wiring area 22b2 in the +Y direction is in the same plane as the end of the terminal area 22b1 in the +Y direction.

[0135] The wiring area 22b3 is rectangular in shape when viewed from above. The wiring area 22b3 extends from the end of the terminal area 22b1 in the -Y direction toward the long side 21c in a manner parallel to the short side faces 21b and 21d (short side direction). The end of the wiring area 22b3 in the +X direction is formed by leaving the edge of the long side face 21c empty. Moreover, the end of the wiring area 22b3 in the -Y direction faces the short side face 21d. The end of the wiring area 22b3 in the -Y direction is in the same plane as the end of the terminal area 22b1 in the -Y direction. It should be noted that the width of the wiring area 22b3 in the ±Y direction is approximately equal to the width of the wiring area 22b2 in this direction.

[0136] The output circuit pattern layer 22c included in the plurality of circuit pattern layers has a comb-teeth shape in a plan view and is formed facing the long side surface 21c of the insulating layer 21. The output circuit pattern layer 22c includes a terminal region 22c1, wiring regions 22c2 and 22c3, and chip regions 22c4 and 22c5.

[0137] The terminal area 22c1 is rectangular in shape when viewed from above. The terminal area 22c1 is formed to extend in parallel with the long side 21c (long side direction) on the front side of the insulating layer 21. The end of the terminal area 22c1 in the +Y direction faces the short side 21b on the front side of the insulating layer 21. In addition, the end of the terminal area 22c1 in the -Y direction is formed with a gap between the short side 21d. The terminal area 22c1 also faces the long side 21c. The dotted area (configuration area Tc) shown in the terminal area 22c1 is the bonding portion of the output terminal 42.

[0138] The wiring area 22c2 is rectangular in a plan view. The wiring area 22c2 extends from the end of the terminal area 22c1 in the +Y direction toward the long side 21a in a manner parallel to the short side 21b, 21d (short side direction). The end of the wiring area 22c2 in the -X direction faces the long side 21a. The end of the wiring area 22c2 in the +Y direction is in the same plane as the end of the terminal area 22c1 in the +Y direction.

[0139] The wiring area 22c3 is rectangular in a plan view. The wiring area 22c3 extends from the terminal area 22c1 between the chip area 22a3 and the wiring area 22b2 toward the long side 21a in a manner parallel to the short side 21b, 21d (short side direction). The end of the wiring area 22c3 in the -X direction faces the terminal area 22a1. The width of the wiring area 22c3 in the ±Y direction corresponds to the interval between the chip area 22a3 and the wiring area 22b2, and is approximately equal to the width of the wiring area 22c2 in the ±Y direction.

[0140] The chip area 22c4 is rectangular in a plan view. The chip area 22c4 extends from the terminal area 22c1 between the wiring area 22b2 and the control circuit pattern layer 22f described later in a manner parallel to the short side surfaces 21b and 21d (short side direction) toward the long side surface 21a. The end of the chip area 22c4 in the -X direction faces the terminal area 22b1. The two dotted line areas shown in the chip area 22c4 are the bonding parts of the semiconductor chip 30.

[0141] The chip area 22c5 is rectangular in shape when viewed from above. The chip area 22c5 extends from the end of the terminal area 22c1 in the -Y direction between the wiring area 22b3 and the sensing circuit pattern layer 22g described later toward the long side 21a in a manner parallel to the short sides 21b, 21d (short side direction). The end of the chip area 22c5 in the -X direction faces the terminal area 22b1. The chip areas 22c4, 22c5 and the ends of the wiring area 22c3 in the -X direction are in the same plane. In addition, the end of the chip area 22c5 in the -Y direction is in the same plane as the end of the terminal area 22c1 in the -Y direction. The two dotted line areas shown in the chip area 22c5 are the bonding parts of the semiconductor chip 30. It should be noted that the width of the chip area 22c5 in the ±Y direction is approximately equal to the width of the chip area 22c4 in the ±Y direction. In addition, the width of the gap between the end of the chip region 22c5 in the +Y direction and the end of the chip region 22c4 in the -Y direction is substantially equal to the widths of the chip regions 22c4 and 22c5 in the ±Y directions.

[0142] The control circuit pattern layer 22d and the sensing circuit pattern layer 22e included in the plurality of circuit pattern layers are rectangular in shape when viewed from above, and are formed in a region surrounded by the terminal region 22c1 of the positive circuit pattern layer 22a and the output circuit pattern layer 22c in parallel with the short side surfaces 21b and 21d (short side direction). The widths of the control circuit pattern layer 22d and the sensing circuit pattern layer 22e in the ±Y direction are smaller than the widths of the wiring region 22c2 in the ±Y direction.

[0143] The control circuit pattern layer 22f and the sensing circuit pattern layer 22g included in the plurality of circuit pattern layers are rectangular in plan view and are formed in a region surrounded by the terminal region 22b1 of the negative circuit pattern layer 22b, the terminal region 22c1 of the output circuit pattern layer 22c, and the chip regions 22c4 and 22c5 in parallel with the short side faces 21b and 21d (short side direction). The widths of the control circuit pattern layer 22f and the sensing circuit pattern layer 22g in the ±Y direction are smaller than the widths of the wiring region 22c2 in the ±Y direction.

[0144] As the insulating circuit substrate 20 having such a structure, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. The insulating circuit substrate 20 conducts the heat generated by the semiconductor chip 30 to the back side of the insulating circuit substrate 20 via the positive circuit pattern layer 22a, the negative circuit pattern layer 22b, the insulating layer 21, and the metal layer 23 to dissipate the heat.

[0145] The semiconductor chip 30 is a power device made of silicon carbide. As an example of the power device, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be cited. In the power MOSFET, the body diode functions as a FWD (Free Wheeling Diode). The semiconductor chip 30 has a drain electrode as an input electrode on the back side, a gate electrode as a control electrode 31 on the front side, and a source electrode as an output electrode.

[0146] In addition, the semiconductor chip 30 may also be a power device made of silicon. The power device in this case is, for example, an RC (Reverse Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a circuit formed by connecting an IGBT as a switching element and a FWD as a diode element in reverse parallel in one chip. The semiconductor chip 30, for example, has a collector as an input electrode on the back, a gate electrode as a control electrode on the front, and an emitter as an output electrode.

[0147] It should be noted that, in the present embodiment, a plurality of semiconductor chips 30 are respectively arranged in the positive circuit pattern layer 22a and the output circuit pattern layer 22c via the above-mentioned bonding member 35. In the present embodiment, an example is given in which two semiconductor chips 30 are arranged in the chip regions 22a2 and 22a3 of the positive circuit pattern layer 22a and the chip regions 22c4 and 22c5 of the output circuit pattern layer 22c along the short side surfaces 21b and 21d. In addition, in the present embodiment, the two semiconductor chips 30 respectively arranged in the chip regions 22a2 and 22a3 of the positive circuit pattern layer 22a and the chip regions 22c4 and 22c5 of the output circuit pattern layer 22c are arranged so that the control electrodes 31 of each other are opposite.

[0148] The positive terminal 40, the negative terminal 41, the output terminal 42, and the control terminals 43a and 43b are made of metals with excellent conductivity. Such metals are, for example, copper, copper alloys, aluminum, and aluminum alloys. In order to improve the corrosion resistance of the metal plates of the positive terminal 40, the negative terminal 41, the output terminal 42, and the control terminals 43a and 43b, plating treatment may also be performed. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0149] The positive terminal 40 is in the shape of a flat plate. The positive electrode bonding area 40a, which is the inner end of the positive terminal 40, is bonded to the configuration area Ta of the terminal area 22a1 of the positive circuit pattern layer 22a via the bonding component 35. That is, the positive terminal 40 is electrically connected to the input electrode on the back side of the semiconductor chip 30. The outer end (first end) of the positive terminal 40 extends in the vertical direction (-X direction) from the terminal area 22a1 of the positive circuit pattern layer 22a. The corners of the outer end of the positive terminal 40 can be R-chamfered or C-chamfered. The contact surface 40c1 on the front side of the outer end of the positive terminal 40 contacts the positive conductive layer 53 included in the wiring terminal 51 of the capacitor 5 described later. In addition, a through fastening hole 40d can also be formed at the outer end of the positive terminal 40. Such a fastening hole 40d can be used to install the busbar. The positive terminal 40 as a whole has a substantially uniform thickness and a uniform ( Figure 7 The thickness of the positive terminal 40 is, for example, greater than 0.4 mm and less than 0.6 mm. In addition, the length of the positive terminal 40 extending from the long side surface 10a of the package 10 in the -X direction is, for example, greater than 20 mm and less than 30 mm.

[0150] The negative terminal 41 includes a negative electrode bonding region 41a, a connection region 41b, and a wiring region 41c. The negative electrode bonding region 41a, the connection region 41b, and the wiring region 41c are all in the form of a flat plate. The negative terminal 41 has a substantially uniform thickness and uniform ( Figure 7The negative terminal 41 is formed so that its width direction (±Y direction) is parallel to the width direction (±Y direction) of the positive terminal 40 when viewed from above. Therefore, the width directions of the negative terminal 41 and the positive terminal 40 are respectively formed to be parallel to the long side surface 10a of the package 10. In addition, the negative terminal 41 is offset in position relative to the positive terminal 40 in the width direction (±Y direction). The inner end of the negative terminal 41, i.e., the negative electrode bonding area 41a, is bonded to the configuration area Tb of the terminal area 22b1 of the negative circuit pattern layer 22b via the bonding component 35. The connection area 41b and the negative electrode bonding area 41a are ( Figure 7 The wiring area 41c is connected to the connection area 41b and extends in the vertical direction (-X direction) from the terminal area 22b1 of the negative circuit pattern layer 22b. Therefore, the wiring area 41c of the negative terminal 41 is separated from the front of the insulating circuit substrate 20 in the +Z direction by an amount corresponding to the height of the connection area 41b. In addition, the corner of the outer end of the wiring area 41c of the negative terminal 41 can be R-chamfered or C-chamfered. The contact surface 41c1 on the back side of the outer end of the negative terminal 41 (wiring area 41c) contacts the negative conductive layer 54 included in the wiring terminal 51 of the capacitor 5 described later. The contact surface 41c1 of the negative terminal 41 is formed to be parallel to the contact surface 40c1 of the positive terminal 40 when viewed from the side. A through fastening hole 41d can be formed at the outer end of the negative terminal 41. Such a fastening hole 41d can be used to attach a wiring terminal 51 of the capacitor 5 described later. The thickness of the negative terminal 41 is, for example, 0.4 mm to 0.6 mm. In addition, the length of the negative terminal 41 extending from the long side surface 10a of the package 10 in the -X direction is, for example, 20 mm to 30 mm.

[0151] The output terminal 42 is in the shape of a plate. The output bonding area 42a, which is the inner end of the output terminal 42, is bonded to the configuration area Tc of the terminal area 22c1 of the output circuit pattern layer 22c via the bonding component 35. The outer end of the output terminal 42 extends in the vertical direction (+X direction) from the terminal area 22c1 of the output circuit pattern layer 22c. It should be noted that the corners of the outer end of the output terminal 42 can also be R-chamfered or C-chamfered. In addition, a through hole can also be formed in the outer end of the output terminal 42. Such a through hole can be used to install a bus bar. In addition, the output terminal 42 as a whole has a substantially uniform thickness and a uniform ( Figure 7 (in the ±Y direction) width.

[0152] The control terminals 43a and 43b are columnar. The cross-section of the columnar shape can be polygonal, circular, or elliptical. The lower end of the control terminal 43a is respectively joined to the ends of the long side 21a of the control circuit pattern layer 22d and the sensing circuit pattern layer 22e through a joining component 35 (not shown). The upper end of the control terminal 43a extends vertically upward (+Z direction) from the control circuit pattern layer 22d and the sensing circuit pattern layer 22e. The lower end of the control terminal 43b is respectively joined to the ends of the long side 21a of the control circuit pattern layer 22f and the sensing circuit pattern layer 22g through a joining component 35 (not shown). The upper end of the control terminal 43b extends vertically upward (+Z direction) from the control circuit pattern layer 22f and the sensing circuit pattern layer 22g.

[0153] The control line 36, the sensing line 37, and the main current line 38 are mainly composed of a material with excellent conductivity. Such a material is composed of, for example, gold, copper, aluminum, or an alloy containing at least one of them. In addition, the diameter of the control line 36 and the sensing line 37 can be smaller than the diameter of the main current line 38.

[0154] Control line 36( Figure 7 The control line 36 ( Figure 7 The control electrodes 31 of each semiconductor chip 30 are directly connected to the control circuit pattern layer 22f.

[0155] Sensing line 37 ( Figure 7 The output electrodes of each semiconductor chip 30 are directly connected to the sensing circuit pattern layer 22e. Figure 7 The output electrodes of each semiconductor chip 30 are directly connected to the sensing circuit pattern layer 22g.

[0156] Main current line 38 ( Figure 7 The output electrodes of each semiconductor chip 30 are directly connected to the wiring areas 22c2 and 22c3 of the output circuit pattern layer 22c. The main current line 38 ( Figure 7 The output electrodes of the semiconductor chips 30 are directly connected to the wiring regions 22b2 and 22b3 of the negative circuit pattern layer 22b (-Y direction side). The main current lines 38 are wired in parallel with the long side surfaces 21a and 21c.

[0157] Next, use Fig.11 The capacitor 5 will be described. Fig.11 1 is a perspective view of a capacitor included in the semiconductor device according to the embodiment. Capacitor 5 includes case 50 and wiring terminals 51 .

[0158] The housing 50 is the main body of the capacitor. The housing 50 includes an upper surface 50e, a bottom surface 50f, a long side 50a, a short side 50b, a long side 50c and a short side 50d. The upper surface 50e and the bottom surface 50f are equal in shape and size and are rectangular in shape when viewed from above. The long side 50a, the short side 50b, the long side 50c and the short side 50d surround the four sides of the upper surface 50e and the bottom surface 50f in sequence. The long sides 50a and 50c correspond to the long sides of the upper surface 50e and the bottom surface 50f. The short sides 50b and 50d correspond to the short sides of the upper surface 50e and the bottom surface 50f. The material of the housing 50 is, for example, epoxy resin. A plurality of capacitor components with N poles and P poles, which are omitted from the figure, are accommodated in the housing 50.

[0159] The wiring terminal 51 includes an insulating layer 52, a positive electrode conductive layer 53 and a negative electrode conductive layer 54. The insulating layer 52 is made of an insulating material having insulating properties. Such insulating materials are composed of, for example, insulating paper based on a wholly aromatic polyamide polymer, fluorine-based, and polyimide-based resin materials as main components. In addition, the insulating layer 52 is formed into a sheet shape from such insulating materials. The insulating layer 52 extends outward from the long side 50a of the housing 50. The insulating layer 52 is sandwiched by the positive electrode conductive layer 53 and the negative electrode conductive layer 54 as described later, and maintains the insulation of the positive electrode conductive layer 53 and the negative electrode conductive layer 54. In addition, the insulating layer 52 also maintains the insulation between the positive electrode conductive layer 53 and the negative electrode conductive layer 54 in the housing 50. The insulating layer 52 is formed with holes at positions opposite to the positive electrode fastening hole 53a, the negative electrode opening hole 53b, the negative electrode fastening hole 54a, and the positive electrode opening hole 54b described later.

[0160] The positive electrode conductive layer 53 is electrically connected to the P poles of the plurality of capacitor components in the housing 50 and extends outward from the long side surface 50a of the housing 50. The portion of the positive electrode conductive layer 53 extending outward is in the shape of a flat plate and is disposed on the back of the insulating layer 52. The positive electrode conductive layer 53 is formed with a positive electrode fastening hole 53a and a negative electrode opening hole 53b (see Fig.12 ). The positive electrode fastening hole 53a and the negative electrode opening hole 53b are set as a group, corresponding to the number of semiconductor modules 2 mounted on the wiring terminal 51. The positive electrode fastening hole 53a fastens the positive terminal 40 of the semiconductor module 2 by a bolt. The diameter of the negative electrode opening hole 53b is much larger than the diameter of the positive electrode fastening hole 53a. The negative electrode opening hole 53b is inserted without contacting the bolt, and the bolt fastens the negative terminal 41 of the semiconductor module 2.

[0161] The negative electrode conductive layer 54 is electrically connected to the N poles of the plurality of capacitor components in the housing 50, and extends outward from the long side surface 50a of the housing 50. The portion of the negative electrode conductive layer 54 extending outward is in the shape of a flat plate and is provided on the front side of the insulating layer 52. The shape and size of the portion of the negative electrode conductive layer 54 extending outward are the same as the shape and size of the portion of the positive electrode conductive layer 53 extending outward. The negative electrode conductive layer 54 is formed with a negative electrode fastening hole 54a and a positive electrode opening hole 54b (see Fig.12 ). The negative electrode fastening hole 54a and the positive electrode opening hole 54b are set as a group, corresponding to the number of semiconductor modules 2 mounted on the wiring terminal 51. The negative electrode fastening hole 54a fastens the negative terminal 41 of the semiconductor module 2 by a bolt. The diameter of the positive electrode opening hole 54b is much larger than the diameter of the negative electrode fastening hole 54a. The positive electrode opening hole 54b is inserted without contacting the bolt, and the bolt fastens the positive terminal 40 of the semiconductor module 2.

[0162] In such a wiring terminal 51, when viewed from above, the positive electrode fastening hole 53a corresponds to the positive electrode opening hole 54b, and the negative electrode fastening hole 54a corresponds to the negative electrode opening hole 53b. For the insulating layer 52, the size of at least the portion on the outside of the long side 50a of the shell 50 is larger than the size of the positive conductive layer 53 and the negative conductive layer 54. Therefore, the outer edge (end side) of the insulating layer 52 clamped by the positive conductive layer 53 and the negative conductive layer 54 protrudes from the outer edge (end side) of the positive conductive layer 53 and the negative conductive layer 54, respectively. The protruding length of the insulating layer 52 is, for example, greater than 1.0 mm and less than 1.4 mm. Therefore, the insulation distance between the positive conductive layer 53 and the negative conductive layer 54 is maintained, and the insulation of the positive conductive layer 53 and the negative conductive layer 54 is maintained.

[0163] Next, use Figure 1 , Figure 2 and Fig.12 The connection between the semiconductor module 2 and the capacitor 5 will be described. Fig.12 1 is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment. Fig.12 It is aimed at Figure 1 and Figure 2 5 and 6. A cross-sectional view taken along a dashed line XX in the case where the bolt 55a and the nut 55b are connected. In addition, the bolt 55a and the nut 55b are made of, for example, a conductive metal.

[0164] The long side surfaces 10a of a plurality of (for example, three here) semiconductor modules 2 are respectively placed opposite to the long side surfaces 50a of the capacitor 5, and the plurality of semiconductor modules 2 are respectively moved toward the capacitor 5. Figure 1 and Figure 2As shown, the wiring terminal 51 of the capacitor 5 is clamped by the positive terminal 40 and the negative terminal 41 of the plurality of semiconductor modules 2. That is, the positive terminal 40 of the plurality of semiconductor modules 2 is in contact with the back surface of the positive conductive layer 53 of the wiring terminal 51. At this time, the front end of the positive conductive layer 53 of the wiring terminal 51 is in contact with the long side 10a of the semiconductor module 2. The negative terminal 41 of the plurality of semiconductor modules 2 is in contact with the front surface of the negative conductive layer 54 of the wiring terminal 51. At this time, the front end of the negative conductive layer 54 of the wiring terminal 51 is in contact with the long side 10a of the semiconductor module 2. Moreover, the front end of the insulating layer 52 enters (is stored in) the storage groove 10g of the long side 10a of the semiconductor module 2.

[0165] After the wiring terminal 51 of the capacitor 5 is mounted between the positive terminal 40 and the negative terminal 41 of the semiconductor module 2, as shown in FIG. Fig.12 As shown, the bolt 55a is inserted from the front side of the negative terminal 41 into the fastening hole 41d of the negative terminal 41 and the negative fastening hole 54a of the negative conductive layer 54. The lower end of the bolt 55a is exposed from the negative opening hole 53b of the positive conductive layer 53, and the nut 55b is fastened at the lower end in the negative opening hole 53b of the positive conductive layer 53. At this time, the diameter of the negative opening hole 53b of the positive conductive layer 53 is much larger than the diameter of the nut 55b, so the bolt 55a and the nut 55b do not contact the positive conductive layer 53, and the insulation is maintained. That is, the negative terminal 41 and the positive conductive layer 53 are maintained in insulation.

[0166] Similarly, the bolt 55a is passed through the positive electrode fastening hole 53a of the positive electrode conductive layer 53 and the fastening hole 40d of the positive electrode terminal 40 from the positive electrode opening hole 54b of the negative electrode conductive layer 54. The lower end of the bolt 55a is exposed from the fastening hole 40d of the positive electrode terminal 40, and the nut 55b is fastened to the lower end. At this time, the diameter of the positive electrode opening hole 54b of the negative electrode conductive layer 54 is much larger than the diameter of the bolt 55a, so the bolt 55a does not contact the negative electrode conductive layer 54, and the insulation is maintained. That is, the positive terminal 40 and the negative electrode conductive layer 54 are maintained in insulation.

[0167] As described above, the plurality of semiconductor modules 2 and the capacitor 5 are mechanically and electrically connected to form the semiconductor device 1 .

[0168] Here, a reference example of the semiconductor device 1 of the embodiment will be described. The semiconductor module included in the semiconductor device of the reference example does not have a housing groove 10g for the semiconductor module 2. Fig.13 A semiconductor device according to such a reference example will be described. Fig.13 1 is a side view (XZ plane) of a semiconductor device of a reference example. It should be noted that in the semiconductor device 100 of the reference example, Fig.13 and Figure 2 correspond.

[0169] The semiconductor device 100 includes a plurality of semiconductor modules 200 and a capacitor 5. The capacitor 5 is the same as the capacitor 5 of the embodiment. The semiconductor module 200 does not form the storage groove 10g on the long side surface 10a included in the semiconductor module 2 of the embodiment, and the entire long side surface 10a is flat. The semiconductor module 200 has the same structure as the semiconductor module 2 except for the long side surface 10a.

[0170] like Fig.13 As shown in FIG. 1 , the wiring terminal 51 of the capacitor 5, the positive electrode terminal 40 and the negative electrode terminal 41 of the plurality of semiconductor modules 200 are mounted (see also FIG. 1 ). Figure 1 In this case, the front end (in the +X direction) of the wiring terminal 51 (insulating layer 52) abuts against the long side surface 10a of the semiconductor module 200. In addition, a gap G is left between the front end (in the +X direction) of the positive electrode conductive layer 53 and the negative electrode conductive layer 54 and the long side surface 10a of the semiconductor module 200.

[0171] The inductance component of the semiconductor device 100 depends on the length of the wiring terminal 51 of the capacitor 5 and the positive terminal 40 and the negative terminal 41 of the semiconductor module 200. The wiring terminal 51 of the capacitor 5 has an insulating layer 52 sandwiched between the positive conductive layer 53 and the negative conductive layer 54 (laminated) to reduce the inductance. In addition, it is desirable to laminate the positive terminal 40 and the negative terminal 41 of the semiconductor module 200 by such a wiring terminal 51. As a result, the wiring terminal 51 and the positive terminal 40 and the negative terminal 41 are in a configuration relationship in which the currents that reciprocate in accordance with the switch overlap. As a result, the magnetic field is offset and the inductance can be suppressed.

[0172] However, in the semiconductor module 200 , the wiring terminal 51 cannot completely overlap with the positive electrode terminal 40 and the negative electrode terminal 41 in the gap G. Therefore, in the gap G, the inductance cannot be reduced.

[0173] On the other hand, the semiconductor device 1 of the embodiment includes a semiconductor module 2 and a capacitor 5. The capacitor 5 has a wiring terminal 51, which includes an insulating layer 52, a positive conductive layer 53 provided on one main surface of the insulating layer 52, and a negative conductive layer 54 provided on the other main surface of the insulating layer 52, and the insulating end side of the insulating layer 52 extends to a position further outward than the conductive end sides of the positive conductive layer 53 and the negative conductive layer 54.

[0174] The semiconductor module 2 comprises: a semiconductor chip 30 having an output electrode and an input electrode; a negative terminal 41 including a contact surface 41c1 in contact with the negative conductive layer 54 of the wiring terminal 51 and electrically connected to the output electrode of the semiconductor chip 30; and a positive terminal 40, which is separated from the negative terminal 41 and includes a contact surface 40c1 parallel to the negative terminal 41 and electrically in contact with the positive conductive layer 53 of the wiring terminal 51, and electrically connected to the input electrode of the semiconductor chip 30. The semiconductor module 2 further includes a package 10, wherein a positive terminal 40 and a negative terminal 41 extend from a long side surface 10a of the package 10 opposite to the wiring terminal 51 in the same direction from the long side surface 10a to the outside, the package 10 fixes the semiconductor chip 30 to the positive terminal 40 and the negative terminal 41, and has a storage groove 10g between the positive terminal 40 and the negative terminal 41 of the long side surface 10a, and the front end of the insulating layer 52 of the wiring terminal 51 is inserted into the storage groove 10g. In the semiconductor device 1, by making the front end of the insulating layer 52 of the wiring terminal 51 of the capacitor 5 enter the storage groove 10g of the long side surface 10a of the semiconductor module 2, the portion where the positive terminal 40 and the negative terminal 41 of the semiconductor module 2 overlap with the wiring terminal 51 of the capacitor 5 can be increased. Therefore, the inductance can be further reduced compared with the semiconductor device 100 of the reference example.

[0175] As the tip of the insulating layer 52 of the wiring terminal 51 goes deeper into the receiving groove 10g of the long side 10a of the semiconductor module 2, the gap G of the reference example becomes smaller, and the inductance can be reduced. That is, as long as the tip of the insulating layer 52 of the wiring terminal 51 slightly enters the receiving groove 10g of the long side 10a of the semiconductor module 2, the gap G can be reduced, and the inductance can be reduced. Therefore, the depth of the receiving groove 10g of the long side 10a of the semiconductor module 2 is preferably such a depth that the entire tip of the insulating layer 52 protruding from the positive conductive layer 53 and the negative conductive layer 54 of the wiring terminal 51 of the capacitor 5 enters so that the gap G disappears.

[0176] (Variant 1)

[0177] Next, a modification of the semiconductor device 1 is described. Fig.14 A semiconductor module 2 according to Modification 1 will be described. Fig.14 FIG. 1 is a side view (ZY plane) of a semiconductor module included in a semiconductor device according to an embodiment (variant 1). In the semiconductor module 2 according to variant 1, as shown in FIG. Fig.14 As shown, the positive terminal 40 extending from the long side surface 10a is disposed opposite to the negative terminal 41. In the package 10 of the semiconductor module 2, the shapes of the positive terminal 40 and the negative terminal 41 can be changed so that the positive terminal 40 and the negative terminal 41 are disposed in this way.

[0178] Next, use Fig.15 The connection between the semiconductor module 2 and the capacitor 5 will be described. Fig.15 1 is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (variant 1). Fig.15 Corresponding to the case where the semiconductor module 2 of the modification example 1 is connected to the capacitor 5 Figure 1 and Figure 2 The single-point dash line XX Fig.12 Cross-sectional view of .

[0179] The insulating layer 52 of the wiring terminal 51 included in the capacitor 5 of Modification 1 is also sandwiched by the positive conductive layer 53 and the negative conductive layer 54. The positive fastening hole 53a and the negative fastening hole 54a of the positive conductive layer 53 and the negative conductive layer 54 of Modification 1 are formed at positions corresponding to the positive fastening hole 53a and the negative fastening hole 54a of the positive conductive layer 53 and the negative conductive layer 54 of the embodiment, respectively. In addition, the negative opening hole 53b and the positive opening hole 54b are not formed in the positive conductive layer 53 and the negative conductive layer 54 of Modification 1.

[0180] The long side surfaces 10a of the plurality of (here, for example, three) semiconductor modules 2 are respectively opposed to the long side surfaces 50a of the capacitor 5, and the plurality of semiconductor modules 2 are moved toward the capacitor 5. The wiring terminal 51 of the capacitor 5 is clamped by the positive terminal 40 and the negative terminal 41 of the plurality of semiconductor modules 2. At this time, the front end of the insulating layer 52 enters (is accommodated in) the accommodation groove 10g of the long side surface 10a of the semiconductor module 2.

[0181] After the wiring terminal 51 of the capacitor 5 is mounted between the positive terminal 40 and the negative terminal 41 of the semiconductor module 2, as shown in FIG. Fig.15 As shown, the bolt 55a is inserted through the fastening hole 41d of the negative terminal 41, the negative fastening hole 54a of the negative conductive layer 54, the positive fastening hole 53a of the positive conductive layer 53, and the fastening hole 40d of the positive terminal 40. The lower end of the bolt 55a is exposed from the fastening hole 40d of the positive terminal 40, and the nut 55b is fastened to the lower end.

[0182] The semiconductor device 1 including the semiconductor module 2 and the capacitor 5 can also reduce the inductance as in the embodiment. It should be noted that in the modification 1, insulating members 55c, 55d, and 55e are provided between the bolt 55a and the negative terminal 41, between the nut 55b and the positive terminal 40, and in the fastening hole 41d, the negative fastening hole 54a, the positive fastening hole 53a, and the fastening hole 40d. Therefore, the insulation between the negative terminal 41 and the positive terminal 40 is maintained.

[0183] (Variant 2)

[0184] use Fig.16 A semiconductor module 2 according to a second modification will be described. Fig.16 FIG. 1 is a side view (ZY plane) of a semiconductor module included in a semiconductor device according to an embodiment (variant 2). In the semiconductor module 2 according to the variant 2, as shown in FIG. Fig.16 As shown, the positive terminal 40 and the negative terminal 41 extending from the long side surface 10a are in the same plane when viewed from the side. It should be noted that in the package 10 of the semiconductor module 2, the shapes of the positive terminal 40 and the negative terminal 41 can be changed so that the positive terminal 40 and the negative terminal 41 are arranged in this way.

[0185] Next, use Fig.17 The connection between the semiconductor module 2 and the capacitor 5 will be described. Fig.17 2 is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (variant 2). Fig.17 Corresponding to the case where the semiconductor module 2 of the second modification is connected to the capacitor 5 Fig.13 Cross-sectional view at the single-point dash line XX.

[0186] The insulating layer 52 of the wiring terminal 51 included in the capacitor 5 of the modification example 2 is also sandwiched by the positive conductive layer 53 and the negative conductive layer 54. The positive conductive layer 53 of the modification example 2 is the same as the positive conductive layer 53 of the embodiment. On the other hand, compared with the negative conductive layer 54 of the embodiment, the portion of the negative conductive layer 54 of the modification example 2 that contacts the positive terminal 40 is opened and provided with a floating wiring 54d. The floating wiring 54d is separated from the other portions of the negative conductive layer 54 and is electrically isolated. The thickness of the floating wiring 54d is the same thickness as that of the negative conductive layer 54. The floating wiring 54d is formed with a floating fastening hole 54e. The negative conductive layer 54 of the modification example 2 is not formed with a positive opening hole 54b.

[0187] In such wiring terminal 51, negative electrode fastening hole 54a of negative electrode conductive layer 54 corresponds to negative electrode opening hole 53b of positive electrode conductive layer 53. Also, floating fastening hole 54e of floating wiring 54d included in negative electrode conductive layer 54 corresponds to positive electrode fastening hole 53a of positive electrode conductive layer 53.

[0188] The long side surfaces 10a of the plurality of (here, for example, three) semiconductor modules 2 are respectively opposed to the long side surfaces 50a of the capacitor 5, and the plurality of semiconductor modules 2 are moved toward the capacitor 5. The positive terminals 40 and the negative terminals 41 of the plurality of semiconductor modules 2 are arranged from the front side at the wiring terminals 51 of the capacitor 5. At this time, the front end of the insulating layer 52 enters (is accommodated in) the accommodation groove 10g of the long side surface 10a of the semiconductor module 2.

[0189] After the wiring terminal 51 of the capacitor 5 is configured with the positive terminal 40 and the negative terminal 41 of the semiconductor module 2, as shown in FIG. Fig.17 As shown, the bolt 55a is inserted through the fastening hole 41d of the negative terminal 41 and the negative fastening hole 54a of the negative conductive layer 54. The lower end of the bolt 55a is exposed from the negative opening hole 53b of the positive conductive layer 53, and a nut 55b is fastened to the lower end.

[0190] The bolt 55a is inserted through the fastening hole 40d of the positive terminal 40, the floating fastening hole 54e of the floating wiring 54d, and the positive fastening hole 53a of the positive conductive layer 53. The lower end of the bolt 55a is exposed from the positive fastening hole 53a of the positive conductive layer 53, and a nut 55b is fastened to the lower end.

[0191] The semiconductor device 1 including the semiconductor module 2 and the capacitor 5 can also reduce the inductance similarly to the embodiment.

Claims

1. A semiconductor device, characterized in that: have: A wiring terminal comprising an insulating layer, a first conductive layer provided on one main surface of the insulating layer, and a second conductive layer provided on the other main surface of the insulating layer, wherein the insulating end edge of the insulating layer extends to a position further outward than the conductive end edges of the first conductive layer and the second conductive layer; as well as Semiconductor modules, The semiconductor module comprises: a semiconductor chip having a first electrode and a second electrode; a first terminal including a first end portion and electrically connected to the first electrode of the semiconductor chip, the first end portion having a first contact surface in contact with the first conductive layer of the wiring terminal; a second terminal including a second end portion and electrically connected to the second electrode of the semiconductor chip, the second end portion being separated from the first end portion and having a second contact surface that is parallel to the first contact surface and electrically in contact with the second conductive layer of the wiring terminal; as well as A fixing portion, wherein the first end portion and the second end portion extend from a base surface of the fixing portion opposite to the wiring terminal in the same direction to a position further outward than the base surface, the fixing portion fixes the semiconductor chip, the first terminal and the second terminal, and has a recess between the first end portion and the second end portion of the base surface, and the insulating end edge of the insulating layer of the wiring terminal is inserted into the recess.

2. The semiconductor device according to claim 1, wherein: The fixing portion is a packaging component.

3. The semiconductor device according to claim 2, wherein: The first end portion and the second end portion are in a flat plate shape, The first end portion and the second end portion are arranged on the base surface in such a manner that a first width direction of the first end portion is parallel to a second width direction of the second end portion in a plan view. The recess is parallel to the first width direction and the second width direction in a plan view.

4. The semiconductor device according to claim 3, wherein: The recess is formed across the base surface in parallel with the first width direction and the second width direction.

5. The semiconductor device according to claim 4, wherein: The first end portion and the second end portion are disposed on the base surface at positions offset in the first width direction and the second width direction, respectively, in a plan view.

6. The semiconductor device according to claim 1, wherein: The conductive end sides of each of the first conductive layer and the second conductive layer of the wiring terminal abut against the base surface of the semiconductor module.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a capacitor including the wiring terminal.

8. A semiconductor module, characterized in that: have: a first semiconductor chip having a first electrode and a second electrode; a second semiconductor chip having a third electrode and a fourth electrode electrically connected to the first electrode of the first semiconductor chip; A first terminal including a first end portion and electrically connected to the first electrode of the first semiconductor chip, wherein the first end portion has a first contact surface; a second terminal including a second end portion and electrically connected to the fourth electrode of the second semiconductor chip, the second end portion being spaced apart from the first end portion and having a second contact surface parallel to the first contact surface; and A fixing portion, wherein the first end portion and the second end portion extend from a base surface of the fixing portion in the same direction to a position further outward than the base surface, the fixing portion fixes the first semiconductor chip, the second semiconductor chip, the first terminal and the second terminal, and has a recess between the first end portion and the second end portion of the base surface.

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