Semiconductor etching method

Abstract

The invention provides a semiconductor etching method which comprises the following steps: providing a substrate structure which is made of a III-V group compound semiconductor material; spin-coating photoresist on the substrate structure to form a photoresist layer; preparing a photoetching pattern by utilizing a photoetching process; performing dry shallow etching on the substrate structure with the photoetching pattern; performing oxygen plasma treatment on the substrate structure after the dry shallow etching; and repeating the dry shallow etching and the oxygen plasma treatment until a vertical groove with a target depth is formed in the substrate structure. According to the semiconductor etching method provided by the invention, dry shallow etching is carried out on the III-V compound semiconductor substrate, so that by-products in the etching process are effectively reduced, and a small amount of by-products formed on the surface of the substrate and the groove in the dry shallow etching process are removed through oxygen plasma treatment, so that the yield of the semiconductor is improved. Through circular processing of dry shallow etching and oxygen plasma processing on the substrate, the perpendicularity of the groove after the III-V group semiconductor with the target depth is etched is effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor etching method. Background Art

[0002] In the preparation of high-power semiconductor laser chips, the transfer of photolithography patterns to semiconductor substrate structures containing epitaxial layers by dry etching technology is a widely used preparation method for laser chips. When III-V compound semiconductors such as GaAs, GaN and InP are dry-etched with photoresist patterns, the photoresist is prone to react in chlorine-based gases to generate by-products, especially for ridge grooves with large etching areas and small duty cycles. More by-products are generated and easily adhere to the side walls of the etched grooves, hindering the substrate grooves from approaching 90° vertical grooves, thereby affecting the performance of single-junction or multi-junction high-power single-mode laser chips.

[0003] At present, in order to improve the verticality of the grooves after etching of III-V compound semiconductors, the usual method is to transfer the photoresist pattern to a hard mask, such as a Cr metal layer or a dielectric film layer such as Al2O3, SiO2, and then remove the photoresist by stripping, and use the remaining hard mask layer to perform vertical dry etching of the III-V semiconductor substrate. However, this method is not suitable for some products with high Al component substrate structures. The remaining hard mask layer after dry etching needs to be removed using a wet corrosive liquid. The wet corrosive liquid will cause the substrate structure with a high Al component to degenerate, thereby rendering such devices ineffective. In addition, the introduction of the hard mask layer will also complicate the device preparation process, increase costs, and reduce product yield. Summary of the invention

[0004] The purpose of the present disclosure is to provide a semiconductor etching method that can solve one or more of the above-mentioned prior art problems.

[0005] According to one aspect of the present disclosure, a semiconductor etching method is provided, comprising the following steps: S11: providing a substrate structure, wherein the material of the substrate structure is a III-V group compound semiconductor material; S12: Spin-coating a photoresist on the substrate structure to form a photoresist layer; S13: preparing a photolithography pattern by using a photolithography process; S14: performing dry shallow etching on the substrate structure having the photolithography pattern; S15: performing oxygen plasma treatment on the substrate structure after the dry shallow etching; S16: Repeat S14 and S15 until a vertical groove of a target depth is formed in the substrate structure.

[0006] In some embodiments, in S14, the etching depth of the dry shallow etching is 1 nm-100 nm.

[0007] In some embodiments, in S15, the substrate structure after the dry shallow etching is subjected to oxygen plasma treatment, and the thickness of the byproducts of the dry shallow etching in S14 removed is 1 nm-100 nm.

[0008] In some embodiments, S14 and S15 are repeated 1 to 10,000 times.

[0009] In some embodiments, the dry shallow etching in S14 uses a chlorine-based gas as an etching gas.

[0010] In some embodiments, the etching gas used in the dry shallow etching in S14 is at least one of Cl2, BCl3, HCl, SiCl4 and CCl4.

[0011] In some embodiments, the process parameters of the dry shallow etching in S14 are: The RF power range is 20W-2000W, the temperature range is -20℃-80℃, the chamber pressure range is 1-200mT, and the etching time range is 1-600s.

[0012] In some embodiments, the gas used in the oxygen plasma treatment in S15 is oxygen or a mixed gas of oxygen and an inert gas.

[0013] In some embodiments, the duration of the oxygen plasma treatment in S15 is 1-300 s.

[0014] In some embodiments, both S14 and S15 are performed using plasma equipment, and S14 and S15 are performed in the same process chamber.

[0015] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: by performing dry shallow etching on the III-V compound semiconductor substrate, the by-products in the etching process are effectively reduced, and a small amount of by-products formed on the substrate surface and the groove during the dry shallow etching process are removed by oxygen plasma treatment. By performing a cyclic treatment of dry shallow etching and oxygen plasma treatment on the substrate, the verticality of the groove after etching the III-V semiconductor of the target depth is effectively improved, so that the inclination angle of the side wall of the groove reaches 90°.

[0016] In addition, in the technical solution disclosed in the present invention, unless otherwise specified, the technical solution can be implemented by adopting conventional means in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flowchart of a semiconductor etching method provided by one embodiment of the present disclosure.

[0019] Figure 2 This is a schematic diagram of the structure prepared in S13 in the semiconductor etching method provided in one embodiment of the present disclosure.

[0020] Figure 3 This is a schematic diagram of the structure prepared in S14 in the semiconductor etching method provided in one embodiment of the present disclosure.

[0021] Figure 4 This is a schematic diagram of the structure prepared in S15 in the semiconductor etching method provided in one embodiment of the present disclosure.

[0022] Figure 5 This is a schematic diagram of the structure prepared by S16 in the semiconductor etching method provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Example: Reference Manual Attached Figure 1-Figure 5 , showing a semiconductor etching method provided by an embodiment of the present disclosure, comprising the following steps: S11: providing a substrate structure 1, wherein the material of the substrate structure 1 is a III-V group compound semiconductor material; S12: Spin-coating a photoresist on the substrate structure 1 to form a photoresist layer 2; S13: preparing a photolithography pattern by using a photolithography process; S14: performing dry shallow etching on the substrate structure 1 having the photolithography pattern; S15: performing oxygen plasma treatment on the substrate structure 1 after the dry shallow etching; S16: S14 and S15 are repeated until a vertical groove with a target depth is formed in the substrate structure 1 .

[0025] The material of the substrate structure in S11 may be a single layer or multiple layers of GaAs, GaN, InP, and similar doped III-V group compound semiconductor materials.

[0026] Providing the substrate structure in S11 may include preparing and cleaning the substrate.

[0027] Reference Manual Attached Figure 2 As shown, a schematic diagram of the structure prepared in S13 is shown. At this time, the substrate structure 1 has not been etched, and a photolithography pattern is prepared on the photoresist layer 2.

[0028] In an optional embodiment, in S14, the etching depth of the dry shallow etching may be 1 nm-100 nm. Thus, the etching depth of each dry shallow etching is smaller, and the corresponding byproducts formed on the sidewall of the groove are less.

[0029] Specifically, the dry shallow etching in S14 uses a chlorine-based gas as an etching gas, and the etching gas may be at least one of Cl2, BCl3, HCl, SiCl4 and CCl4.

[0030] In an optional embodiment, the process parameters of the dry shallow etching in S14 may be: RF power range is 20W-2000W, temperature range is -20°C-80°C, chamber pressure range is 1-200mT, and etching time range is 1-600s.

[0031] Reference Manual Attached Figure 3 As shown, a schematic diagram of the structure prepared in S14 is shown, at which a by-product 3 is formed on the side wall of the groove after dry shallow etching.

[0032] In an optional embodiment, in S15, the substrate structure after the dry shallow etching is subjected to oxygen plasma treatment, and the thickness of the byproduct 3 of the dry shallow etching in S14 removed is 1 nm-100 nm.

[0033] The gas used in the oxygen plasma treatment in S15 is oxygen or a mixed gas of oxygen and an inert gas. The inert gas mixed with oxygen can be one or more of inert gases such as Ar, N2 and He.

[0034] In an optional embodiment, the duration of the oxygen plasma treatment in S15 is 1-300 s.

[0035] Reference Manual Attached Figure 4 As shown, a schematic diagram of the structure prepared in S15 is shown, at which time the by-product 3 on the side wall of the groove has been completely removed after oxygen plasma treatment.

[0036] In an optional embodiment, the number of times of repeating S14 and S15 is 1 time to 10000 times. Thus, the verticality of the groove after etching is effectively improved through the cyclic treatment of dry shallow etching and oxygen plasma.

[0037] The shallower the etching depth of the dry shallow etching in S14, the more cycles of S14 and S15, and the higher the verticality of the side wall of the groove after etching. In the production process, the depth of each dry shallow etching, the time of oxygen plasma treatment, and the number of cycles of S14 and S15 can be adjusted according to actual production conditions.

[0038] Reference Manual Attached Figure 5 As shown, a schematic diagram of the structure prepared by S16 is shown.

[0039] In an optional embodiment, both S14 and S15 are performed using plasma equipment, and S14 and S15 are performed in the same process chamber. Thus, the substrate structure does not need to be moved during the etching process, which simplifies the process flow, improves production efficiency, and reduces production costs.

[0040] The plasma equipment is a type of reactive ion etcher, inductively coupled plasma etcher and electron cyclotron resonance plasma etcher.

[0041] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: by performing dry shallow etching on a III-V compound semiconductor substrate, by-products in the etching process are effectively reduced; by-products formed on the substrate surface and in the grooves during the dry shallow etching process can be completely removed by oxygen plasma treatment; at the same time, the sidewall morphology of the photoresist layer can remain stable; by performing cyclic treatment of dry shallow etching and oxygen plasma treatment on the substrate, the verticality of the groove after etching of the target depth III-V semiconductor is effectively improved, so that the inclination angle of the sidewall of the groove reaches 90°, and the performance of the III-V semiconductor device is effectively improved; in the process of etching high verticality grooves, there is no need to deposit metal films or dielectric films, etc., and the process is simple, the cost is low, and the application range is wide.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor etching method, characterized in that: The following steps are involved: S11: providing a substrate structure, wherein the material of the substrate structure is a III-V group compound semiconductor material; S12: Spin-coating a photoresist on the substrate structure to form a photoresist layer; S13: preparing a photolithography pattern by using a photolithography process; S14: performing dry shallow etching on the substrate structure having the photolithography pattern; S15: performing oxygen plasma treatment on the substrate structure after the dry shallow etching; S16: Repeat S14 and S15 until a vertical groove of a target depth is formed in the substrate structure.

2. The semiconductor etching method according to claim 1, characterized in that: In S14, the etching depth of the dry shallow etching is 1 nm-100 nm.

3. The semiconductor etching method according to claim 1, characterized in that: In S15, the substrate structure after the dry shallow etching is treated with oxygen plasma, and the thickness of the byproducts of the dry shallow etching in S14 removed is 1 nm-100 nm.

4. The semiconductor etching method according to claim 1, characterized in that: The number of repetitions of S14 and S15 is 1 to 10,000.

5. The semiconductor etching method according to claim 1, characterized in that: In S14, the dry shallow etching uses chlorine-based gas as etching gas.

6. The semiconductor etching method according to claim 5, characterized in that: The etching gas used for the dry shallow etching in S14 is at least one of Cl2, BCl3, HCl, SiCl4 and CCl4.

7. The semiconductor etching method according to claim 1, characterized in that: The process parameters of dry shallow etching in S14 are: The RF power range is 20W-2000W, the temperature range is -20℃-80℃, the chamber pressure range is 1-200mT, and the etching time range is 1-600s.

8. The semiconductor etching method according to claim 1, characterized in that: The gas used in the oxygen plasma treatment in S15 is oxygen or a mixed gas of oxygen and an inert gas.

9. The semiconductor etching method according to claim 1, characterized in that: The time of oxygen plasma treatment in S15 is 1-300s.

10. The semiconductor etching method according to claim 1, characterized in that: S14 and S15 are both performed using plasma equipment, and S14 and S15 are performed in the same process chamber.

Images