H-bridge three-level control system and method and storage medium

Abstract

The invention provides an H-bridge three-level control system and method and a storage medium, and belongs to the field of power control, the H-bridge three-level control system comprises a processor, an H-bridge three-level circuit and a capacitor, and the H-bridge three-level circuit is connected with the processor, the two ends of the capacitor, a modulation wave input end and a modulation wave output end; the H-bridge three-level circuit is used for outputting an H-bridge three-level carrier group; and the processor is used for importing an initial sine wave, carrying out waveform comparison on the initial sine wave and the H-bridge three-level carrier wave group, and controlling the H-bridge three-level circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to a comparison result. According to the invention, the utilization rate of the system and the power of the H-bridge three-level circuit are improved, the service life of the system is prolonged, the problems of harmonic output and local heating are reduced, the generated waveforms are completely symmetrical, and even harmonics are reduced.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of power control, and in particular to an H-bridge three-level control system, method and storage medium. Background Art

[0002] The existing H-bridge three-level inverter uses 8 IGBTs to connect. The advantages of the three-level inverter are: it uses multiple levels to synthesize step waves to approach the sinusoidal output voltage. Since there is one more output level than the two-level inverter, the output PWM wave is closer to the sinusoidal waveform and has less ripple content. The voltage that the IGBT in the three-level inverter circuit bears at the beginning of conduction and the end of shutdown is half of the two-level voltage, which determines that the du / dt of the three-level IGBT is much smaller than the du / dt of the two-level IGBT.

[0003] The existing H-bridge three-level control methods are divided into unipolar modulation and bipolar modulation. Among them, the disadvantages of the unipolar modulation control method are as follows:

[0004] 1. The IGBTs are turned on inconsistently, resulting in inconsistent IGBT temperature rise. IGBT5, IGBT6, IGBT7, and IGBT8 only have on-state losses, and the temperature rise is relatively low. IGBT1 and 2 have two types of on-state and switching losses, and the power will be obviously inconsistent.

[0005] 2. Large harmonics at low frequencies. At low frequencies, the harmonic content of the output voltage of unipolar modulation is much larger than at high frequencies, which will lead to unsatisfactory output characteristics. Since the IGBT frequency used in the unit cannot be continuously increased, the harmonic characteristics of the unit itself are very poor.

[0006] 3. Since the IGBT has only two switching working states at any time, the device utilization rate is very low, only 25%, which wastes resources.

[0007] The disadvantages of the bipolar modulation control method are as follows:

[0008] 1. The output waveforms of the positive and negative half axes of bipolar modulation are not completely symmetrical, which will lead to the appearance of even harmonics and affect the output characteristics.

[0009] 2. The output harmonics are relatively large. Due to the asymmetric waveform, the output harmonics are large.

[0010] 3. The IGBT needs to be configured with a dead zone when outputting. In order to prevent the four IGBTs from being directly connected, a dead zone must be added. Small currents require 2us, while large currents may require more than 10us, which affects the integrity of the waveform. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide an H-bridge three-level control system, method and storage medium in view of the deficiencies in the prior art.

[0012] The technical solution of the present invention to solve the above technical problems is as follows: an H-bridge three-level control system, comprising a processor, an H-bridge three-level circuit and a capacitor,

[0013] The H-bridge three-level circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end;

[0014] The H-bridge three-level circuit is used to output an H-bridge three-level carrier group;

[0015] The processor is used to import an initial sine wave, compare the initial sine wave with the H-bridge three-level carrier group, and control the H-bridge three-level circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0016] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output end to output a target positive half-cycle waveform according to the analysis result;

[0017] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0018] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0019] Another technical solution of the present invention to solve the above technical problem is as follows: an H-bridge three-level control method comprises the following steps:

[0020] Outputting an H-bridge three-level carrier group from the H-bridge three-level circuit;

[0021] Importing an initial sine wave, performing waveform comparison between the initial sine wave and the H-bridge three-level carrier group, and controlling the H-bridge three-level circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to the comparison result;

[0022] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result;

[0023] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0024] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0025] The beneficial effects of the present invention are as follows: by comparing the waveforms of an initial sine wave with an H-bridge three-level carrier group, the H-bridge three-level circuit is controlled to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to the comparison result, the positive half-cycle waveform of the to-be-processed positive half-cycle waveform group is analyzed, and the modulation wave output end is controlled to output a target positive half-cycle waveform according to the analysis result, the negative half-cycle waveform of the to-be-processed negative half-cycle waveform group is analyzed, and the modulation wave input end is controlled to output a target negative half-cycle waveform according to the analysis result, and the target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform, thereby improving the utilization rate of the system and the power of the H-bridge three-level circuit, enhancing the service life of the system, reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 One of the structural block diagrams of an H-bridge three-level control system provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a target waveform of an H-bridge three-level control system provided by an embodiment of the present invention;

[0028] Figure 3 The second structural block diagram of an H-bridge three-level control system provided by an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of a phase-shifted carrier of an H-bridge three-level positive half-cycle carrier subset of an H-bridge three-level control system provided by an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a phase-shifted carrier of an H-bridge three-level negative half-cycle carrier subset of an H-bridge three-level control system provided by an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of a phase-shifted carrier of a first insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0032] Figure 7 A schematic diagram of a phase-shifted carrier of a second insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0033] Figure 8 A schematic diagram of a phase-shifted carrier of a seventh insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0034] Fig. 9 A schematic diagram of a phase-shifted carrier of an eighth insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0035] Fig.10A schematic diagram of a phase-shifted carrier of a third insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0036] Fig.11 A schematic diagram of a phase-shifted carrier of a fourth insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0037] Fig.12 A schematic diagram of a phase-shifted carrier of a fifth insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0038] Fig.13 A schematic diagram of a phase-shifted carrier of a sixth insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0039] Fig.14 A schematic diagram of a target positive half-cycle waveform of an H-bridge three-level control system provided by an embodiment of the present invention;

[0040] Fig.15 A schematic diagram of a target negative half-cycle waveform of an H-bridge three-level control system provided by an embodiment of the present invention;

[0041] Fig.16 A schematic diagram of waveforms of a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor of an H-bridge three-level control system provided by an embodiment of the present invention;

[0042] Fig.17 A schematic diagram of waveforms of a fifth insulated gate bipolar transistor, a sixth insulated gate bipolar transistor, a seventh insulated gate bipolar transistor, and an eighth insulated gate bipolar transistor of an H-bridge three-level control system provided in one embodiment of the present invention;

[0043] Fig.18 A schematic flow chart of an H-bridge three-level control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0045] Figure 1 A module block diagram of an H-bridge three-level control system provided by an embodiment of the present invention.

[0046] like Figure 1 and 2 As shown, an H-bridge three-level control system includes a processor, an H-bridge three-level circuit and a capacitor.

[0047] The H-bridge three-level circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end;

[0048] The H-bridge three-level circuit is used to output an H-bridge three-level carrier group;

[0049] The processor is used to import an initial sine wave, compare the initial sine wave with the H-bridge three-level carrier group, and control the H-bridge three-level circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0050] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output end to output a target positive half-cycle waveform according to the analysis result;

[0051] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0052] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0053] It should be understood that the H-bridge three-level circuit is respectively connected to the processor, the two ends of the capacitor C1, the modulation wave input terminal IN, and the modulation wave output terminal OUT.

[0054] It should be understood that a sine wave (ie, target waveform) is synthesized by subtracting the upper half waveform of the sine wave (ie, target positive half waveform) and the lower half waveform (ie, target negative half waveform) through time-sharing.

[0055] Specifically, Figure 2 As shown, the 8 waveforms of the IGBT are 600Hz PMW, and the total PWM wave generated is 24 PWM, which is achieved by turning on and off the IGBT at 600Hz, equivalent to a switching frequency of 2.4KHz.

[0056] In the above embodiment, by comparing the waveforms of the initial sine wave with the H-bridge three-level carrier group, the H-bridge three-level circuit is controlled to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result, the positive half-cycle waveform of the positive half-cycle waveform group to be processed is analyzed, and the modulation wave output end is controlled to output the target positive half-cycle waveform according to the analysis result, and the negative half-cycle waveform of the negative half-cycle waveform group to be processed is analyzed, and the modulation wave input end is controlled to output the target negative half-cycle waveform according to the analysis result, and the target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain the target waveform, thereby improving the utilization rate of the system and the power of the H-bridge three-level circuit, enhancing the service life of the system, reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics.

[0057] Optionally, as an embodiment of the present invention, Figures 1 to 3 As shown, the H-bridge three-level circuit includes a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor, a fifth insulated gate bipolar transistor, a sixth insulated gate bipolar transistor, a seventh insulated gate bipolar transistor, an eighth insulated gate bipolar transistor, a first diode, a second diode, a third diode and a fourth diode:

[0058] The gate of the first insulated gate bipolar transistor is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor is respectively connected to the collector of the fifth insulated gate bipolar transistor and one end of the capacitor, the emitter of the first insulated gate bipolar transistor is respectively connected to the collector of the second insulated gate bipolar transistor and the cathode of the first diode, the gate of the second insulated gate bipolar transistor is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor is respectively connected to the collector of the third insulated gate bipolar transistor and the modulation wave input end, the gate of the third insulated gate bipolar transistor is connected to the third port of the processor, the emitter of the third insulated gate bipolar transistor is respectively connected to the collector of the fourth insulated gate bipolar transistor and the anode of the second diode, the cathode of the second diode is respectively connected to the anode of the first diode, the cathode of the third diode and the anode of the fourth diode, and the fourth insulated gate bipolar transistor is respectively connected to the anode of the first diode, the cathode of the third diode and the anode of the fourth diode. The gate of the insulated gate bipolar transistor is connected to the fourth port of the processor, the emitter of the fourth insulated gate bipolar transistor is respectively connected to the other end of the capacitor and the emitter of the eighth insulated gate bipolar transistor, the gate of the eighth insulated gate bipolar transistor is connected to the fifth port of the processor, the collector of the eighth insulated gate bipolar transistor is respectively connected to the emitter of the seventh insulated gate bipolar transistor and the anode of the third diode, the gate of the seventh insulated gate bipolar transistor is connected to the sixth port of the processor, the collector of the seventh insulated gate bipolar transistor is respectively connected to the emitter of the sixth insulated gate bipolar transistor and the modulation wave output end, the gate of the sixth insulated gate bipolar transistor is connected to the seventh port of the processor, the collector of the sixth insulated gate bipolar transistor is respectively connected to the emitter of the fifth insulated gate bipolar transistor and the negative electrode of the fourth diode, and the gate of the fifth insulated gate bipolar transistor is connected to the eighth port of the processor.

[0059] Specifically, Figure 3As shown, the gate of the first insulated gate bipolar transistor I GBT1 is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor I GBT1 is respectively connected to the collector of the fifth insulated gate bipolar transistor I GBT5 and one end of the capacitor C1, the emitter of the first insulated gate bipolar transistor I GBT1 is respectively connected to the collector of the second insulated gate bipolar transistor I GBT2 and the cathode of the first diode D1, the gate of the second insulated gate bipolar transistor I GBT2 is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor I GBT2 is respectively connected to the collector of the third insulated gate bipolar transistor I GBT3 and the modulation wave input terminal IN, the gate of the third insulated gate bipolar transistor I GBT3 is connected to the third port of the processor, and the third insulated gate bipolar transistor I The emitter of IGBT3 is respectively connected to the collector of the fourth insulated gate bipolar transistor IGBT4 and the anode of the second diode D2, the cathode of the second diode D2 is respectively connected to the anode of the first diode D1, the cathode of the third diode D3 and the anode of the fourth diode D4, the gate of the fourth insulated gate bipolar transistor IGBT4 is connected to the fourth port of the processor, the emitter of the fourth insulated gate bipolar transistor IGBT4 is respectively connected to the other end of the capacitor C1 and the emitter of the eighth insulated gate bipolar transistor IGBT8, the gate of the eighth insulated gate bipolar transistor IGBT8 is connected to the fifth port of the processor, the collector of the eighth insulated gate bipolar transistor IGBT8 is respectively connected to the emitter of the seventh insulated gate bipolar transistor IGBT7 and the anode of the third diode D3, the gate of the seventh insulated gate bipolar transistor IGBT7 is connected to the sixth port of the processor, and the collector of the seventh insulated gate bipolar transistor IGBT7 is respectively connected to the emitter of the sixth insulated gate bipolar transistor IGBT8. The emitter of the sixth insulated gate bipolar transistor I GBT6 is connected to the modulation wave output terminal OUT, the gate of the sixth insulated gate bipolar transistor I GBT6 is connected to the seventh port of the processor, the collector of the sixth insulated gate bipolar transistor I GBT6 is respectively connected to the emitter of the fifth insulated gate bipolar transistor I GBT5 and the cathode of the fourth diode D4, and the gate of the fifth insulated gate bipolar transistor I GBT5 is connected to the eighth port of the processor.

[0060] In the above embodiments, the utilization rate of the system and the power of the H-bridge three-level circuit are improved by using the insulated gate bipolar transistors and diodes, the service life of the system is enhanced, and the occurrence of harmonic output and local heating problems is reduced.

[0061] Optionally, as an embodiment of the present invention, Figures 1 to 5As shown, in the processor, the process of performing waveform comparison between the initial sine wave and the H-bridge three-level carrier group, and controlling the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result includes:

[0062] Determine whether the first initial sine wave data point in the initial sine wave is greater than 0, if so, execute the first solution; if not, execute the second solution;

[0063] The initial sine wave includes an initial sine wave positive half cycle and an initial sine wave negative half cycle, and the H-bridge three-level carrier group includes an H-bridge three-level positive half cycle carrier subset and an H-bridge three-level negative half cycle carrier subset;

[0064] Among them, the first solution is:

[0065] Compare the waveforms of the positive half cycle of the initial sine wave with the positive half cycle carrier subset of the H-bridge three-level positive half cycle, and control the H-bridge circuit to output a positive half cycle waveform group to be processed according to a first comparison result;

[0066] Compare the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and control the H-bridge circuit to output a negative half cycle waveform group to be processed according to a second comparison result;

[0067] The second solution is:

[0068] Compare the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and control the H-bridge circuit to output a negative half cycle waveform group to be processed according to the second comparison result;

[0069] The positive half cycle of the initial sine wave is compared with the positive half cycle of the H-bridge three-level positive half cycle carrier subset, and the H-bridge circuit is controlled to output a positive half cycle waveform group to be processed according to a first comparison result.

[0070] In the above embodiment, the initial sine wave is compared with the H-bridge three-level carrier group in waveform, and the H-bridge circuit is controlled to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result, thereby enhancing the service life of the system and reducing the occurrence of harmonic output and local heating problems.

[0071] Optionally, as an embodiment of the present invention, Figures 1 to 9As shown, the H-bridge three-level positive half-cycle carrier subset includes a first insulated gate bipolar transistor carrier data point at multiple moments corresponding to the first insulated gate bipolar transistor, a second insulated gate bipolar transistor carrier data point at multiple moments corresponding to the second insulated gate bipolar transistor, a seventh insulated gate bipolar transistor carrier data point at multiple moments corresponding to the seventh insulated gate bipolar transistor, and an eighth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the eighth insulated gate bipolar transistor, and the initial sinusoidal wave positive half cycle includes a sinusoidal wave positive half cycle data point at multiple moments,

[0072] In the processor, a process of performing a waveform comparison of the positive half cycle of the initial sine wave with the positive half cycle carrier subset of the H-bridge three-level positive half cycle, and controlling the H-bridge circuit to output a positive half cycle waveform group to be processed according to a first comparison result includes:

[0073] At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the first insulated gate bipolar transistor; if so, control the first insulated gate bipolar transistor to output a first preset value; if not, control the first insulated gate bipolar transistor to output a second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first positive half-cycle waveform to be processed;

[0074] At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the second insulated gate bipolar transistor; if so, control the second insulated gate bipolar transistor to output the first preset value; if not, control the second insulated gate bipolar transistor to output the second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all the output results are plotted as the second positive half-cycle waveform to be processed;

[0075] For each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the seventh insulated gate bipolar transistor; if so, control the seventh insulated gate bipolar transistor to output the first preset value; if not, control the seventh insulated gate bipolar transistor to output the second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all the output results are plotted as the third positive half-cycle waveform to be processed;

[0076] For each moment, determine whether the sinusoidal wave positive half-cycle data point is greater than the eighth insulated gate bipolar transistor carrier data point. If so, control the eighth insulated gate bipolar transistor to output the first preset value; if not, control the eighth insulated gate bipolar transistor to output the second preset value, until all the sinusoidal wave positive half-cycle data points corresponding to all moments are compared, and all output results are plotted as a fourth positive half-cycle waveform to be processed, and the positive half-cycle waveform group to be processed includes the first positive half-cycle waveform to be processed, the second positive half-cycle waveform to be processed, the third positive half-cycle waveform to be processed, and the fourth positive half-cycle waveform to be processed.

[0077] Preferably, the first preset value is 1, and the second preset value is 0.

[0078] Specifically, Figure 4 , 6 As shown in , 7, 8 and 9, the 4 phase-shifted carriers of the first half cycle (i.e., the first IGBT carrier data point at multiple moments, the second IGBT carrier data point at multiple moments, the seventh IGBT carrier data point at multiple moments and the eighth IGBT carrier data point at multiple moments), a single carrier is a triangular wave for 25% of the cycle (0 to 1, 1 to 0), and the remaining 75% of the cycle is 0. The 4 carriers are shifted in sequence to fill the entire cycle. The 4 half-cycle carriers (i.e., the first IGBT carrier data point at multiple moments, the second IGBT carrier data point at multiple moments, the seventh IGBT carrier data point at multiple moments and the eighth IGBT carrier data point at multiple moments) are superimposed on the sine wave (i.e., the initial sine wave positive half cycle) to generate PWM (i.e., the first positive half cycle waveform to be processed, the second positive half cycle waveform to be processed, the third positive half cycle waveform to be processed and the fourth positive half cycle waveform to be processed) of IGBT1, IGBT2, IGBT7 and IGBT8.

[0079] It should be understood that Figure 6 As shown, the PWM generation method of IGBT1 (i.e., the first positive half-cycle waveform to be processed) is formed by comparing the sine wave (i.e., the initial sine wave positive half-cycle) and the carrier (25% triangle wave, 0-1) (i.e., the first insulated gate bipolar transistor carrier data points at multiple moments).

[0080] It should be understood that Figure 7 As shown, the PWM generation method of IGBT2 (i.e., the second positive half-cycle waveform to be processed) is formed by comparing the sine wave (i.e., the initial sine wave positive half-cycle) and the carrier (25% triangle wave, 0-1) (i.e., the second insulated gate bipolar transistor carrier data points at multiple moments).

[0081] Specifically, Figure 8As shown, the PWM generation method of IGBT7 (i.e., the seventh positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (0 to 1) (i.e., the seventh insulated gate bipolar transistor carrier data points at multiple moments).

[0082] Specifically, Fig. 9 As shown, the PWM generation method of IGBT8 (i.e., the eighth positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (0 to 1) (i.e., the eighth insulated gate bipolar transistor carrier data points at multiple moments).

[0083] In the above embodiment, the waveform of the positive half cycle of the initial sinusoidal wave is compared with the positive half cycle carrier subset of the H-bridge three-level positive half cycle, and the H-bridge circuit is controlled to output the positive half cycle waveform group to be processed according to the first comparison result, thereby improving the utilization rate of the system and the power of the H-bridge three-level circuit, enhancing the service life of the system, reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics.

[0084] Optionally, as an embodiment of the present invention, Figures 1 to 13 As shown, the H-bridge three-level negative half-cycle carrier subset includes a third insulated gate bipolar transistor carrier data point at multiple moments corresponding to the third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the fourth insulated gate bipolar transistor, a fifth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the fifth insulated gate bipolar transistor, and a sixth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the sixth insulated gate bipolar transistor, and the initial sinusoidal wave negative half cycle includes sinusoidal wave negative half cycle data points at multiple moments,

[0085] In the processor, the process of performing a waveform comparison of the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and controlling the H-bridge circuit to output a negative half cycle waveform group to be processed according to a second comparison result includes:

[0086] For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the third insulated gate bipolar transistor; if so, control the third insulated gate bipolar transistor to output the first preset value; if not, control the third insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first negative half-cycle waveform to be processed;

[0087] For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the fourth insulated gate bipolar transistor; if so, control the fourth insulated gate bipolar transistor to output the first preset value; if not, control the fourth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second negative half-cycle waveform to be processed;

[0088] For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the fifth insulated gate bipolar transistor; if so, control the fifth insulated gate bipolar transistor to output the first preset value; if not, control the fifth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the third negative half-cycle waveform to be processed;

[0089] For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the sixth insulated gate bipolar transistor. If so, control the sixth insulated gate bipolar transistor to output the first preset value; if not, control the sixth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as a fourth negative half-cycle waveform to be processed, and the negative half-cycle waveform group to be processed includes the first negative half-cycle waveform to be processed, the second negative half-cycle waveform to be processed, the third negative half-cycle waveform to be processed, and the fourth negative half-cycle waveform to be processed.

[0090] Preferably, the first preset value is 1, and the second preset value is 0.

[0091] Specifically, Figure 5 , 10As shown in Figures 11, 12 and 13, the 4 phase-shifted carriers in the second half of the cycle (i.e., the third insulated gate bipolar transistor carrier data points at multiple moments, the fourth insulated gate bipolar transistor carrier data points at multiple moments, the fifth insulated gate bipolar transistor carrier data points at multiple moments, and the sixth insulated gate bipolar transistor carrier data points at multiple moments) have a single carrier wave with 25% of the cycle (0 to 1, 1 to 0) being a triangular wave and the remaining 75% of the cycle being 0. The 4 carrier waves are offset in sequence to fill the entire cycle. These 4 half-cycle carriers (i.e., the third insulated gate bipolar transistor carrier data points at multiple moments, the fourth insulated gate bipolar transistor carrier data points at multiple moments, the fifth insulated gate bipolar transistor carrier data points at multiple moments, and the sixth insulated gate bipolar transistor carrier data points at multiple moments) and the sine wave (i.e., the negative half-cycle of the initial sine wave) are superimposed to generate PWM of IGBT3, IGBT4, IGBT5, and IGBT6 (i.e., the first negative half-cycle waveform to be processed, the second negative half-cycle waveform to be processed, the third negative half-cycle waveform to be processed, and the fourth negative half-cycle waveform to be processed).

[0092] It should be understood that if Fig.10 As shown, the PWM generation method of IGBT3 (i.e., the third positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (-1 to 0) (i.e., the third insulated gate bipolar transistor carrier data points at multiple moments).

[0093] It should be understood that if Fig.11 As shown, the PWM generation method of IGBT4 (i.e., the fourth positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (-1 to 0) (i.e., the fourth insulated gate bipolar transistor carrier data points at multiple moments).

[0094] Specifically, Fig.12 As shown, the PWM generation method of IGBT5 (i.e., the fifth positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (-1 to 0) (i.e., the fifth insulated gate bipolar transistor carrier data points at multiple moments).

[0095] Specifically, Fig.13 As shown, the PWM generation method of IGBT6 (i.e., the sixth positive half-cycle waveform to be processed) is formed by superimposing a sine wave (i.e., the initial sine wave positive half-cycle) and a carrier (-1 to 0) (i.e., the sixth insulated gate bipolar transistor carrier data points at multiple moments).

[0096] In the above embodiment, the negative half-cycle of the initial sinusoidal wave is compared with the negative half-cycle waveform of the H-bridge three-level negative half-cycle carrier subset, and the H-bridge circuit is controlled to output the negative half-cycle waveform group to be processed according to the second comparison result, thereby enhancing the service life of the system, reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics.

[0097] Optionally, as an embodiment of the present invention, Fig.14 As shown, the first to-be-processed positive half-cycle waveform includes the first to-be-processed positive half-cycle data points at multiple moments, the second to-be-processed positive half-cycle waveform includes the second to-be-processed positive half-cycle data points at multiple moments, the third to-be-processed positive half-cycle waveform includes the third to-be-processed positive half-cycle data points at multiple moments, and the fourth to-be-processed positive half-cycle waveform includes the fourth to-be-processed positive half-cycle data points at multiple moments.

[0098] In the processor, a process of performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result includes:

[0099] For each moment, determine whether the first to-be-processed positive half-cycle data point, the second to-be-processed positive half-cycle data point, the third to-be-processed positive half-cycle data point and the fourth to-be-processed positive half-cycle data point are all the first preset value. If so, control the modulated wave output end to output the first preset value; if not, control the modulated wave output end to output the second preset value, until all the first to-be-processed positive half-cycle data points corresponding to all moments are determined, and all output results are plotted as the target positive half-cycle waveform.

[0100] Preferably, the first preset value is 1, and the second preset value is 0.

[0101] Specifically, when the 4 PWM waves, I GBT1, I GBT2, I GBT7, and I GBT8 (i.e., the first positive half-cycle waveform to be processed, the second positive half-cycle waveform to be processed, the third positive half-cycle waveform to be processed, and the fourth positive half-cycle waveform to be processed) are all 1 in the positive half-cycle waveform output of the sine wave, 1 is output, and when not all are 1, 0 is output.

[0102] In the above embodiment, a positive half-cycle waveform analysis is performed on the positive half-cycle waveform group to be processed, and the modulated wave output end is controlled to output the target positive half-cycle waveform according to the analysis result, thereby reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics.

[0103] Optionally, as an embodiment of the present invention, Fig.15As shown, the first negative half-cycle waveform to be processed includes the first negative half-cycle data points to be processed at multiple moments, the second negative half-cycle waveform to be processed includes the second negative half-cycle data points to be processed at multiple moments, the third negative half-cycle waveform to be processed includes the third negative half-cycle data points to be processed at multiple moments, and the fourth negative half-cycle waveform to be processed includes the fourth negative half-cycle data points to be processed at multiple moments.

[0104] In the processor, a process of performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result includes:

[0105] For each moment, determine whether the first negative half-cycle data point to be processed, the second negative half-cycle data point to be processed, the third negative half-cycle data point to be processed, and the fourth negative half-cycle data point to be processed are all the first preset values. If so, control the modulation wave input end to output the first preset value; if not, control the modulation wave input end to output the second preset value, until the first negative half-cycle data points to be processed corresponding to all moments are determined, and all output results are plotted as the target negative half-cycle waveform.

[0106] Preferably, the first preset value is 1, and the second preset value is 0.

[0107] Specifically, when the 4-way PWM waves, IGBT3, IGBT4, IGBT5, and IGBT6 (i.e., the first negative half-cycle waveform to be processed, the second negative half-cycle waveform to be processed, the third negative half-cycle waveform to be processed, and the fourth negative half-cycle waveform to be processed) are all 1 in the positive half-cycle waveform output of the sine wave, 1 is output, and when not all are 1, 0 is output.

[0108] In the above embodiment, a negative half-cycle waveform analysis is performed on the negative half-cycle waveform group to be processed, and the modulation wave input end is controlled to output the target negative half-cycle waveform according to the analysis result, thereby reducing the occurrence of harmonic output and local heating problems, making the generated waveform completely symmetrical, and reducing the occurrence of even harmonics.

[0109] Optionally, as another embodiment of the present invention, the present invention implements a 4-fold frequency technology of a three-level H-bridge based on carrier phase shifting, and realizes 8 IGBTs controlling the positive and negative half-cycle output of a sine wave. The carrier is given to 8 IGBTs at the same time, and compared with the existing sine wave (modulation wave), and respective PWM waveforms are obtained. The carrier frequency is 600Hz, that is, each IGBT switching cycle is 600Hz, and the equivalent frequency of generating the final PWM is 2.4kHz, that is, 4 times the frequency. At the same time, due to the characteristics, no matter how the IGBT is turned on and off, there will be no direct pass, so there is no need to add a dead zone.

[0110] Optionally, as another embodiment of the present invention, the control strategy of the present invention is as follows: IGBT1, IGBT2, IGBT7, and IGBT8 work in the first half of the sine wave, and IGBT3, IGBT4, IGBT5, and IGBT6 work in the second half of the sine wave. Finally, they are combined into a sine wave (modulation wave).

[0111] Optionally, as another embodiment of the present invention, Fig.16 and 17 As shown, the IGBT1234 and IGBT5678 of the present invention cannot all be 1 at the same moment, so a direct pass to the capacitor cannot be formed, so there is no need to add a dead zone.

[0112] Optionally, as another embodiment of the present invention, the beneficial effects of the present invention are as follows:

[0113] 1. The 4-fold frequency effect is achieved by superimposing 4 low-frequency IGBTs;

[0114] 2. The upper and lower bridge walls cannot be directly connected permanently, and normal output can be guaranteed without adding dead zones;

[0115] 3. Each IGBT is turned on almost the same number of times, reducing the problem of local heating;

[0116] 4. Reduce IGBT control frequency, equivalent to 4 times IGBT switching frequency, and reduce voltage harmonic output;

[0117] 5. The output waveform is completely symmetrical, which can reduce harmonic output;

[0118] 6. Reduce the dv / dt of each IGBT and increase the life of IGBT;

[0119] 7. Improve IGBT utilization to a maximum of 50%, with 4 IGBTs turned on and off in any cycle.

[0120] Optionally, as another embodiment of the present invention, the present invention improves the utilization rate of IGBT to a maximum of 50%, and the purpose of bipolar continuous output can be achieved without adding a dead zone. The number of IGBT switches per cycle is the same, reducing local heating. The 4-fold frequency effect is generated by superposition of 4 IGBTs, improving the quality of the output voltage and reducing harmonic output, and the waveform is completely symmetrical. The dv / dt of the IGBT is reduced, and the life of the IGBT is increased.

[0121] Fig.18 A schematic flow chart of an H-bridge three-level control method provided by an embodiment of the present invention.

[0122] Optionally, as another embodiment of the present invention, Fig.18As shown, an H-bridge three-level control method comprises the following steps:

[0123] Outputting an H-bridge three-level carrier group from the H-bridge three-level circuit;

[0124] Importing an initial sine wave, performing waveform comparison between the initial sine wave and the H-bridge three-level carrier group, and controlling the H-bridge three-level circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to the comparison result;

[0125] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result;

[0126] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0127] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0128] Optionally, another embodiment of the present invention provides an H-bridge three-level control system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the H-bridge three-level control method as described above is implemented. The system may be a computer or other system.

[0129] Optionally, another embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the H-bridge three-level control method as described above is implemented.

[0130] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0131] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0133] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0134] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0135] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. For such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0136] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. An H-bridge three-level control system, characterized in that: include: Processor, H-bridge three-level circuit and capacitor, The H-bridge three-level circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end; The H-bridge three-level circuit is used to output an H-bridge three-level carrier group; The processor is used to import an initial sine wave, compare the initial sine wave with the H-bridge three-level carrier group, and control the H-bridge three-level circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result; Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result; Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result; The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

2. The H-bridge three-level control system according to claim 1, characterized in that: The H-bridge three-level circuit includes a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor, a fifth insulated gate bipolar transistor, a sixth insulated gate bipolar transistor, a seventh insulated gate bipolar transistor, an eighth insulated gate bipolar transistor, a first diode, a second diode, a third diode and a fourth diode: The gate of the first insulated gate bipolar transistor is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor is respectively connected to the collector of the fifth insulated gate bipolar transistor and one end of the capacitor, the emitter of the first insulated gate bipolar transistor is respectively connected to the collector of the second insulated gate bipolar transistor and the cathode of the first diode, the gate of the second insulated gate bipolar transistor is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor is respectively connected to the collector of the third insulated gate bipolar transistor and the modulation wave input end, the gate of the third insulated gate bipolar transistor is connected to the third port of the processor, the emitter of the third insulated gate bipolar transistor is respectively connected to the collector of the fourth insulated gate bipolar transistor and the anode of the second diode, the cathode of the second diode is respectively connected to the anode of the first diode, the cathode of the third diode and the anode of the fourth diode, and the fourth insulated gate bipolar transistor is respectively connected to the anode of the first diode, the cathode of the third diode and the anode of the fourth diode. The gate of the insulated gate bipolar transistor is connected to the fourth port of the processor, the emitter of the fourth insulated gate bipolar transistor is respectively connected to the other end of the capacitor and the emitter of the eighth insulated gate bipolar transistor, the gate of the eighth insulated gate bipolar transistor is connected to the fifth port of the processor, the collector of the eighth insulated gate bipolar transistor is respectively connected to the emitter of the seventh insulated gate bipolar transistor and the anode of the third diode, the gate of the seventh insulated gate bipolar transistor is connected to the sixth port of the processor, the collector of the seventh insulated gate bipolar transistor is respectively connected to the emitter of the sixth insulated gate bipolar transistor and the modulation wave output end, the gate of the sixth insulated gate bipolar transistor is connected to the seventh port of the processor, the collector of the sixth insulated gate bipolar transistor is respectively connected to the emitter of the fifth insulated gate bipolar transistor and the negative electrode of the fourth diode, and the gate of the fifth insulated gate bipolar transistor is connected to the eighth port of the processor.

3. The H-bridge three-level control system according to claim 2, characterized in that: In the processor, the process of performing waveform comparison between the initial sine wave and the H-bridge three-level carrier group, and controlling the H-bridge circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to the comparison result includes: Determine whether the first initial sine wave data point in the initial sine wave is greater than 0, if so, execute the first solution; if not, execute the second solution; The initial sine wave includes an initial sine wave positive half cycle and an initial sine wave negative half cycle, and the H-bridge three-level carrier group includes an H-bridge three-level positive half cycle carrier subset and an H-bridge three-level negative half cycle carrier subset; Among them, the first solution is: Compare the waveforms of the positive half cycle of the initial sine wave with the positive half cycle carrier subset of the H-bridge three-level positive half cycle, and control the H-bridge circuit to output a positive half cycle waveform group to be processed according to a first comparison result; Compare the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and control the H-bridge circuit to output a negative half cycle waveform group to be processed according to a second comparison result; The second solution is: Compare the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and control the H-bridge circuit to output a negative half cycle waveform group to be processed according to a second comparison result; The positive half cycle of the initial sine wave is compared with the positive half cycle of the H-bridge three-level positive half cycle carrier subset, and the H-bridge circuit is controlled to output a positive half cycle waveform group to be processed according to a first comparison result.

4. The H-bridge three-level control system according to claim 3, characterized in that: The H-bridge three-level positive half-cycle carrier subset includes a first insulated gate bipolar transistor carrier data point at multiple moments corresponding to the first insulated gate bipolar transistor, a second insulated gate bipolar transistor carrier data point at multiple moments corresponding to the second insulated gate bipolar transistor, a seventh insulated gate bipolar transistor carrier data point at multiple moments corresponding to the seventh insulated gate bipolar transistor, and an eighth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the eighth insulated gate bipolar transistor, and the initial sinusoidal wave positive half cycle includes a plurality of sinusoidal wave positive half cycle data points at multiple moments, In the processor, a process of performing a waveform comparison of the positive half cycle of the initial sine wave with the positive half cycle carrier subset of the H-bridge three-level positive half cycle, and controlling the H-bridge circuit to output a positive half cycle waveform group to be processed according to a first comparison result includes: At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the first insulated gate bipolar transistor; if so, control the first insulated gate bipolar transistor to output a first preset value; if not, control the first insulated gate bipolar transistor to output a second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first positive half-cycle waveform to be processed; At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the second insulated gate bipolar transistor; if so, control the second insulated gate bipolar transistor to output the first preset value; if not, control the second insulated gate bipolar transistor to output the second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all the output results are plotted as the second positive half-cycle waveform to be processed; For each moment, determine whether the positive half-cycle data point of the sine wave is greater than the carrier data point of the seventh insulated gate bipolar transistor; if so, control the seventh insulated gate bipolar transistor to output the first preset value; if not, control the seventh insulated gate bipolar transistor to output the second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all the output results are plotted as the third positive half-cycle waveform to be processed; For each moment, determine whether the sinusoidal wave positive half-cycle data point is greater than the eighth insulated gate bipolar transistor carrier data point. If so, control the eighth insulated gate bipolar transistor to output the first preset value; if not, control the eighth insulated gate bipolar transistor to output the second preset value, until all the sinusoidal wave positive half-cycle data points corresponding to all moments are compared, and all output results are plotted as a fourth positive half-cycle waveform to be processed, and the positive half-cycle waveform group to be processed includes the first positive half-cycle waveform to be processed, the second positive half-cycle waveform to be processed, the third positive half-cycle waveform to be processed, and the fourth positive half-cycle waveform to be processed.

5. The H-bridge three-level control system according to claim 4, characterized in that: The H-bridge three-level negative half-cycle carrier subset includes a third insulated gate bipolar transistor carrier data point at multiple moments corresponding to the third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the fourth insulated gate bipolar transistor, a fifth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the fifth insulated gate bipolar transistor, and a sixth insulated gate bipolar transistor carrier data point at multiple moments corresponding to the sixth insulated gate bipolar transistor, and the initial sinusoidal wave negative half cycle includes sinusoidal wave negative half cycle data points at multiple moments, In the processor, the process of performing a waveform comparison of the negative half cycle of the initial sine wave with the negative half cycle of the H-bridge three-level negative half cycle carrier subset, and controlling the H-bridge circuit to output a negative half cycle waveform group to be processed according to a second comparison result includes: For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the third insulated gate bipolar transistor; if so, control the third insulated gate bipolar transistor to output the first preset value; if not, control the third insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first negative half-cycle waveform to be processed; For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the fourth insulated gate bipolar transistor; if so, control the fourth insulated gate bipolar transistor to output the first preset value; if not, control the fourth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second negative half-cycle waveform to be processed; For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the fifth insulated gate bipolar transistor; if so, control the fifth insulated gate bipolar transistor to output the first preset value; if not, control the fifth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the third negative half-cycle waveform to be processed; For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the carrier data point of the sixth insulated gate bipolar transistor. If so, control the sixth insulated gate bipolar transistor to output the first preset value; if not, control the sixth insulated gate bipolar transistor to output the second preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as a fourth negative half-cycle waveform to be processed, and the negative half-cycle waveform group to be processed includes the first negative half-cycle waveform to be processed, the second negative half-cycle waveform to be processed, the third negative half-cycle waveform to be processed, and the fourth negative half-cycle waveform to be processed.

6. The H-bridge three-level control system according to claim 4, characterized in that: The first to-be-processed positive half-cycle waveform includes first to-be-processed positive half-cycle data points at multiple moments, the second to-be-processed positive half-cycle waveform includes second to-be-processed positive half-cycle data points at multiple moments, the third to-be-processed positive half-cycle waveform includes third to-be-processed positive half-cycle data points at multiple moments, and the fourth to-be-processed positive half-cycle waveform includes fourth to-be-processed positive half-cycle data points at multiple moments. In the processor, a process of performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result includes: For each moment, determine whether the first to-be-processed positive half-cycle data point, the second to-be-processed positive half-cycle data point, the third to-be-processed positive half-cycle data point and the fourth to-be-processed positive half-cycle data point are all the first preset value. If so, control the modulated wave output end to output the first preset value; if not, control the modulated wave output end to output the second preset value, until all the first to-be-processed positive half-cycle data points corresponding to all moments are determined, and all output results are plotted as the target positive half-cycle waveform.

7. The H-bridge three-level control system according to claim 5, characterized in that: The first negative half-cycle waveform to be processed includes first negative half-cycle data points to be processed at multiple moments, the second negative half-cycle waveform to be processed includes second negative half-cycle data points to be processed at multiple moments, the third negative half-cycle waveform to be processed includes third negative half-cycle data points to be processed at multiple moments, and the fourth negative half-cycle waveform to be processed includes fourth negative half-cycle data points to be processed at multiple moments. In the processor, a process of performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result includes: For each moment, determine whether the first negative half-cycle data point to be processed, the second negative half-cycle data point to be processed, the third negative half-cycle data point to be processed, and the fourth negative half-cycle data point to be processed are all the first preset values. If so, control the modulation wave input end to output the first preset value; if not, control the modulation wave input end to output the second preset value, until the first negative half-cycle data points to be processed corresponding to all moments are determined, and all output results are plotted as the target negative half-cycle waveform.

8. An H-bridge three-level control method, characterized in that: The steps include: Outputting an H-bridge three-level carrier group from the H-bridge three-level circuit; Importing an initial sine wave, performing waveform comparison between the initial sine wave and the H-bridge three-level carrier group, and controlling the H-bridge three-level circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to the comparison result; Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output terminal to output a target positive half-cycle waveform according to the analysis result; Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result; The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

9. An H-bridge three-level control system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the H-bridge three-level control method according to claim 8 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the H-bridge three-level control method as claimed in claim 8 is implemented.

Images