Oscillator

Abstract

The invention discloses an oscillator, which comprises a multi-pulse generation module, the input end of which is connected with a reference signal output end, and the output end of which is used for outputting a first pulse signal, a second pulse signal and a third pulse signal generated based on a received reference signal, the first pulse signal and the third pulse signal are two pulse signals with the same pulse period and different pulse widths, and the second pulse signal is logic negation of the first pulse signal; the differential delay modules are electrically connected end to end in sequence to form an annular oscillator body; injection modules corresponding to the differential delay modules, wherein the output end of each injection module is electrically connected with the output end of the corresponding differential delay module; any injection module serves as a target injection module, a first input port of the target injection module is used for receiving the first pulse signal, a second input port is used for receiving the second pulse signal, and a third input port is used for receiving the third pulse signal. The phase noise of the ring oscillator can be suppressed.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an oscillator. Background Art

[0002] High-frequency multi-phase clocks are widely used in wired and wireless transceiver communication systems. Multi-phase clock signals are used to control the transmitter to send data and to sample the signals received by the receiver at the appropriate time. The measurement indicators of multi-phase clock signals are phase noise and phase error of the multi-phase clock, which directly affect the bit error rate of the transceiver.

[0003] In a traditional injection-locked oscillator based on a ring oscillator, the injected signal introduced will periodically clear the intrinsic phase noise generated by the oscillator. However, the injected signal will destroy the symmetry between the differential delay modules of the ring oscillator, increase the phase error of the multi-phase clock, and thus cause the multi-phase clock signal to be generated inaccurately. At the same time, the ability to suppress the intrinsic phase noise of the oscillator is weak. Summary of the invention

[0004] In view of this, the present invention provides an oscillator, the main purpose of which is to solve the problem that the existing oscillator has weak intrinsic phase noise suppression capability.

[0005] In order to solve the above problems, the present application provides an oscillator, comprising:

[0006] A multi-pulse generating module, wherein the input end is connected to the reference signal output end, and the output end is used to output a first pulse signal, a second pulse signal and a third pulse signal generated based on the received reference signal, wherein the first pulse signal and the third pulse signal are two pulse signals with the same pulse period and different pulse widths, and the second pulse signal is the logical inversion of the first pulse signal;

[0007] A plurality of differential delay modules, each of which is electrically connected end to end in sequence to form a ring oscillator body;

[0008] An injection module corresponding to each differential delay module, the output end of each injection module is electrically connected to the output end of the corresponding differential delay module; wherein any injection module serves as a target injection module, the first input port, the second input port and the third input port of the target injection module are respectively electrically connected to the output end of the multi-pulse generation module in a one-to-one correspondence, for receiving a first pulse signal, a second pulse signal and a third pulse signal, so as to periodically clear the phase noise accumulated in the ring oscillator by injecting current into the ring oscillator body under the control of the first pulse signal, the second pulse signal and the third pulse signal; the first input port, the second input port and the third output port of each non-target injection module are grounded.

[0009] Optionally, the multi-pulse generating module includes:

[0010] A first delay gate, a second delay gate and a third delay gate connected in series in sequence; the input end of the first delay gate is used as the first input end of the multi-pulse generation module for receiving a reference signal; the second delay gate is a delay gate with a reverse function;

[0011] A first AND gate, wherein one input end of the first AND gate is electrically connected to the output end of the third delay gate, and the other input end of the first AND gate is used to receive a reference signal; the output end of the first AND gate is electrically connected to a first transmission gate and an inverter, respectively, for outputting a first pulse signal based on the transmission gate, and for outputting a second pulse signal based on the inverter;

[0012] A second AND gate, one input end of the second AND gate is electrically connected to the output end of the first delay gate, and the other input end of the second AND gate is electrically connected to the output end of the second delay gate; the output end of the second AND gate is electrically connected to the second transmission gate, which is used to output a third pulse signal based on the second transmission gate.

[0013] Optionally, each of the differential delay modules comprises: two inverters, two transmission gates and a load adjustment unit;

[0014] The input end of the first inverter and the input end of the first transmission gate serve as the first input end of the differential delay module;

[0015] The input end of the second inverter and the input end of the second transmission gate serve as the second input end of the differential delay module;

[0016] The output end of the first inverter is electrically connected to the output end of the second transmission gate to serve as the first output end of the differential delay module;

[0017] The output end of the second inverter is electrically connected to the output end of the first transmission gate to serve as the second output end of the differential delay gate;

[0018] The load adjustment unit is arranged in parallel between the first output end and the second output end, and is used to adjust the delay time of the differential delay module by adjusting the load size.

[0019] Optionally, the first inverter and the second inverter have the same circuit structure, and respectively include a first transistor and a second transistor; the gates of the first transistor and the second transistor are electrically connected to serve as the input end of the inverter, and the drain of the first transistor and the drain of the second transistor are electrically connected to serve as the output end of the inverter;

[0020] The circuit structure of the first transmission gate is the same as that of the second transmission gate, including: a plurality of third transistors and a plurality of fourth transistors, the drain of each of the third transistors and the drain of each of the fourth transistors are electrically connected to serve as the input end of the transmission gate, and the source of each of the third transistors and the source of each of the fourth transistors are electrically connected to serve as the output end of the transmission gate.

[0021] The load adjustment unit comprises: two voltage-controlled capacitors connected in series, and a voltage adjustment terminal for adjusting the load size is arranged between the two voltage-controlled capacitors.

[0022] Optionally, each of the injection modules includes: a first enabling inverter, a second enabling inverter connected in reverse parallel to the first enabling inverter, and an enabling transmission gate connected in parallel to the first enabling inverter;

[0023] Among them, the first enable end of the first enable inverter and the first enable end of the second enable inverter serve as the first input port of the injection module, for receiving the first pulse signal; the second enable end of the first enable inverter and the second enable end of the second enable inverter serve as the second input port of the injection module, for receiving the second pulse signal; the enable end of the enable transmission gate serves as the third input port of the injection module, for receiving the third pulse signal.

[0024] Optionally, the first enabling inverter has the same circuit structure as the second enabling inverter, and includes four transistors, wherein: the drains of the fifth transistor and the sixth transistor are electrically connected to serve as the first output terminal of the enabling inverter; the gate of the fifth transistor serves as the first enabling terminal of the inverter; and the gate of the sixth transistor serves as the second enabling terminal of the inverter;

[0025] The source of the fifth transistor is electrically connected to the drain of the seventh transistor, and the source of the sixth transistor is electrically connected to the drain of the eighth transistor;

[0026] The gate of the seventh transistor is electrically connected to the gate of the eighth transistor to serve as the second output terminal of the enabling inverter;

[0027] The enabling transmission gate includes: a ninth transistor and a tenth transistor;

[0028] The gates of the ninth transistor and the tenth transistor are electrically connected to serve as an enable terminal of an enable transmission gate;

[0029] The drain of the ninth transistor and the drain of the tenth transistor are electrically connected to serve as a first output terminal of the enable transmission gate;

[0030] The source of the ninth transistor and the source of the tenth transistor are electrically connected to serve as the second output terminal of the enable transmission gate.

[0031] The oscillator in the present application, the multi-phase clock generated by the multi-pulse generation module has a good ability to suppress the intrinsic phase noise of the oscillator, because the injection current controlled by the first pulse signal and the injection current controlled by the third pulse signal work together to remove the intrinsic phase noise of the oscillator. Therefore, compared with the injection-locked oscillator controlled by a single narrow pulse, the injection-locked oscillator based on multi-pulse control in the present application has a stronger ability to suppress the intrinsic phase noise of the oscillator, and solves the compromise problem between the multi-phase clock error and the ability to suppress the intrinsic phase noise of the oscillator in the traditional injection-locked oscillator controlled by a single injection pulse.

[0032] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0034] Figure 1 Schematic diagram of the connection relationship between the differential delay module and the injection module in the embodiment of the present application;

[0035] Figure 2 A circuit diagram of a multi-pulse generating module in an embodiment of the present application;

[0036] Figure 3 A waveform diagram of a pulse signal generated by a multi-pulse generation module in the implementation of this application;

[0037] Figure 4 A circuit diagram of a differential delay module in the implementation of this application;

[0038] Figure 5 A circuit diagram of an injection module in an embodiment of the present application;

[0039] Figure 6 is the oscillator's natural oscillation frequency vs. noise suppression bandwidth;

[0040] Figure 7 Oscillator intrinsic oscillation frequency vs phase error;

[0041] Figure 8 Output phase error for a conventional injection locked oscillator;

[0042] Fig. 9Eliminate output signal phase error for multi-pulse control injection;

[0043] Fig.10 Eliminate the intrinsic phase noise of the oscillator output signal for multi-pulse controlled injection;

[0044] Fig.11 is the oscillator's natural oscillation frequency vs. noise suppression bandwidth;

[0045] Fig.12 is the oscillator's natural oscillation frequency vs phase error. DETAILED DESCRIPTION

[0046] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0047] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0049] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0050] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0051] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0052] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0053] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0054] The embodiment of the present application provides an oscillator, including: a multi-pulse generating module, the input end of which is connected to the reference signal output end, and the output end is used to output a first pulse signal INJW, a second pulse signal INJW_B and a third pulse signal INJN generated based on the received reference signal, wherein the first pulse signal INJW and the third pulse signal INJN are two pulse signals with the same pulse period and different pulse widths, and the second pulse signal INJW_B is the logical inversion of the first pulse signal INJW; a plurality of differential delay modules, each of which is electrically connected head to tail in sequence to form a ring oscillator body; and injection modules corresponding to each differential delay module, the output end of each injection module being connected to the corresponding The output end of the differential delay module is electrically connected; wherein, any injection module serves as a target injection module, and the first input port INJW, the second input port INJW_B and the third input port INJN of the target injection module are respectively electrically connected to the output end of the multi-pulse generation module in a one-to-one correspondence, for receiving the first pulse signal, the second pulse signal and the third pulse signal, so as to periodically clear the phase noise accumulated in the ring oscillator by injecting current into the ring oscillator body under the control of the first pulse signal, the second pulse signal and the third pulse signal; the first input port INJW, the second input port INJW_B and the third output port INJN of each non-target injection module are grounded.

[0055] In the specific implementation process of this embodiment, there may be 4 differential delay modules and 4 injection modules. The electrical connection relationship between each differential delay module and the injection module may be as follows: Figure 1As shown. That is, the first differential delay module, the second differential delay module, the third differential delay module, and the fourth differential delay module are connected to form a four-stage ring oscillator. The two output terminals of the first injection module are connected to the output terminal of the first differential delay module, the two output terminals of the second injection module are connected to the output terminal of the second differential delay module, the two output terminals of the third injection module are connected to the two output terminals of the third injection module, and the two output terminals of the fourth injection module are connected to the output terminal of the fourth differential delay module. The first injection module serves as a target injection module. Under the control of the first pulse signal INJW and the third pulse signal INJN, the first injection module periodically clears the phase noise accumulated by the ring oscillator by injecting current into the ring oscillator. The INJW port and the INJN port of the second injection module, the third injection module, and the fourth injection module are all grounded as dummy duty modules to ensure the matching of the loads at the output terminals of the four differential delay modules, so that the signals output at the output terminals of the four differential delay modules, i.e., the 8-phase output of the multi-pulse locked oscillator, have a very small phase error. That is, only the INJW port of the first injection module is connected to the INJW signal output by the matching multi-pulse generation module / multi-pulse generation circuit, and the INJN port of the first injection module is connected to the INJN signal output by the matching multi-pulse generation module. The INJW_B port of the first injection module is connected to the INJW_B signal output by the matching multi-pulse generation module.

[0056] The oscillator in this embodiment, the multi-phase clock generated by the multi-pulse generation module has a good ability to suppress the intrinsic phase noise of the oscillator, because the injection current controlled by the first pulse signal and the injection current controlled by the third pulse signal work together to remove the intrinsic phase noise of the oscillator. Therefore, compared with the injection-locked oscillator controlled by a single narrow pulse, the injection-locked oscillator based on multi-pulse control in this application has a stronger ability to suppress the intrinsic phase noise of the oscillator, and solves the compromise problem between the multi-phase clock error and the ability to suppress the intrinsic phase noise of the oscillator in the traditional injection-locked oscillator controlled by a single injection pulse.

[0057] Based on the above embodiment, another embodiment of the present application provides an oscillator. The structure of the multi-pulse generating module in this embodiment can be as follows: Figure 2As shown, it includes: two delay gates G1 and G3 with a delay time of Δt, a delay gate G2 with a delay time of ΔT and an inverting function, two AND gates G4 and G5, two normally open transmission gates G6 and G8, and an inverter G7. The first delay gate G1, the second delay gate G2 and the third delay gate G3 are connected in series in sequence. The input end of the first delay gate G1 is used as the first input end of the multi-pulse generation module to receive the reference signal REF. One input end of the first AND gate G4 is electrically connected to the output end of the third delay gate G3, and the other input end of the first AND gate G4 is used to receive the reference signal REF. The output end of the first AND gate G4 is electrically connected to the first transmission gate G8 and the inverter G7, respectively, for outputting the first pulse signal INJW based on the transmission gate G8, and for outputting the second pulse signal INJW_B based on the inverter G7. One input end of the second AND gate G5 is electrically connected to the output end of the first delay gate G1, and the other input end of the second AND gate G5 is electrically connected to the output end of the second delay gate G2; the output end of the second AND gate G5 is electrically connected to the second transmission gate G6, which is used to output the third pulse signal INJN based on the second transmission gate G6.

[0058] This embodiment adopts the multi-pulse generation module of the above structure to generate Figure 3 The pulse signals shown, that is, the output signals are narrow pulses INJN, wide pulses INJW and the logical inverse INJW_B signal of INJW. In this embodiment, the third pulse signal INJN generated by the multi-pulse generation module is a narrow pulse signal, while the first INJW is a wide pulse signal. The pulse width of the third pulse signal INJN is less than half a period of the signal generated by the oscillator. The pulse width of the first pulse signal INJW is greater than half a period of the signal generated by the oscillator and less than one period of the signal generated by the oscillator. The periods of the above three pulse signals are consistent with the input signal REF of the multi-pulse generation module. The REF period is determined by the circuit design requirements and can be adjusted according to actual needs. In this embodiment, the frequency of the first pulse signal INJW is 2GHz, the pulse width is 81ps, and the frequency of the third pulse signal INJN is 2GHz, and the pulse width is 37.25ps. It should be noted that the use of this method is universal, not limited to the input reference signal of 2GHz, and can be applied to any input reference signal. It is not limited to the output signal of 8-phase 8GHz, and can be applied to any multi-phase and different frequency outputs. The output is not limited to the four-times frequency of the input, and can be applied to any ratio of output and input. The width of the injected narrow pulse INJN is not limited to 37.25ps and the width of the wide pulse INJW_P is 81ps, and can be applied to any injected pulse width.

[0059] Based on the above embodiment, another embodiment of the present application provides an oscillator. In this embodiment, each differential delay module structure can be as follows: Figure 4As shown, it includes: two inverters, two transmission gates and a load adjustment unit. Among them, the input end of the first inverter and the input end of the first transmission gate serve as the first input end INN of the differential delay module; the input end of the second inverter and the input end of the second transmission gate serve as the second input end INP of the differential delay module; the output end of the first inverter is electrically connected to the output end of the second transmission gate, serving as the first output end OUTP of the differential delay module; the output end of the second inverter is electrically connected to the output end of the first transmission gate, serving as the second output end OUTN of the differential delay gate; the load adjustment unit is arranged in parallel between the first output end and the second output end, and is used to adjust the delay time of the differential delay module by adjusting the load size.

[0060] The circuit structure of the first inverter is the same as that of the second inverter, and they respectively include a first transistor M1 and a second transistor M9 (a first transistor M8 and a second transistor M16); the gates G of the first transistor M1 and the second transistor M9 are electrically connected to serve as the input of the inverter, and the drain D of the first transistor M1 and the drain D of the second transistor M9 are electrically connected to serve as the output of the inverter. The source S of the first transistor M1 is connected to the power supply, and the source S of the second transistor M9 is grounded. Similarly, the gates G of the first transistor M8 and the second transistor M16 are electrically connected to serve as the input of the inverter, and the drain D of the first transistor M8 and the drain D of the second transistor M16 are electrically connected to serve as the output of the inverter. The source S of the first transistor M8 is connected to the power supply, and the source S of the second transistor M16 is grounded.

[0061] The circuit structure of the first transmission gate is the same as that of the second transmission gate, including: a plurality of third transistors and a plurality of fourth transistors, the drain D of each of the third transistors M2 / M3 / M4 and the drain D of each of the fourth transistors M10 / M11 / M12 are electrically connected (the drain D of each of the third transistors M5 / M6 / M7 and the drain D of each of the fourth transistors M13 / M14 / M15 are electrically connected), as the input end of the transmission gate, the source S of each of the third transistors and the source S of each of the fourth transistors are electrically connected, as the output end of the transmission gate. Among them, the gates G of the third transistors M2 and M5 are also connected to the digital adjustment signal S <2> The gates G of the third transistors M3 and M6 are connected to the digital adjustment signal S <1> The gates G of the third transistors M4 and M7 are connected to the digital adjustment signal S <0> The gates G of the fourth transistors M10 and M13 are connected to the digital adjustment signal S_B <2> The gates G of the fourth transistors M11 and M14 are connected to the digital adjustment signal S_B <1> The gates G of the fourth transistors M12 and M15 are connected to the digital adjustment signal S_B <0> S_B<2:0> is the logical inverse of S<2:0>.

[0062] The load adjustment unit includes: two voltage-controlled capacitors C1 and C2 connected in series, and a voltage adjustment terminal for adjusting the load size is arranged between the two voltage-controlled capacitors.

[0063] That is, the differential delay unit module in this embodiment is composed of NMOS tubes M9, M10, M11, M12, M13, M14, M15, M16 and PMOS tubes M1, M2, M3, M4, M5, M6, M7, M8, and two voltage-controlled capacitors C1 and C2. INN, INP, S<2:0>, S_B<2:0>, and VCTRL are the input terminals of the delay unit, and OUTP and OUTN are the output terminals of the delay unit. INN is respectively connected to the gates G of M1 and M9, and to the drains D of M2, M3, M4, M10, M11, and M12.

[0064] INP is connected to the gate G of M8 and M16, and the drain D of M5, M6, M7, M13, M14, and M15. OUTP is connected to the source S of M5, M6, M7, M13, M14, and M15, and the positive terminal of C1. OUTN is connected to the source S of M2, M3, M4, M10, M11, and M12, and the positive terminal of C2. VCTRL is connected to the negative terminals of C1 and C2. S <2> Connect the gates G of M2 and M5, S <1> Connect M3 and M6 gate G, S <0> Connect to M4 and M7 gate G. S_B <2> Connect the gates G of M10 and M13, S_B <1> Connect M11 and M14 gate G, S_B <0> Connect to the gate G of M12 and M15. S_B<2:0> is the logical inversion of S<2:0>. The ground potential is connected to M9 and M16, and the power supply is connected to the source S of M1 and M8.

[0065] The differential delay module in this embodiment selects the 12 MOS tubes M2, M3, M4, M5, M6, M7, M10, M11, M12, M13, M14, and M15 by adjusting the digital adjustment signal S<2:0> (when adjusting S, S_B is also adjusted). M2, M3, M4, M10, M11, and M12 constitute the feedforward path from INN to OUTN, and M5, M6, M7, M13, M14, and M15 constitute the feedforward path from INP to OUTP. The digital adjustment signal S<2:0> controls the conduction strength of the feedforward path to control the delay time of the differential delay unit. The adjustment voltage terminal can control the load capacitance of the output terminals OUTP and OUTN by accessing the adjustment voltage VCTRL, thereby adjusting the delay time of the differential delay unit.

[0066] On the basis of the above embodiments, the present application further provides an oscillator. In this embodiment, the structure of each injection module can be as follows: Figure 5As shown, it includes a first enabling inverter, a second enabling inverter connected in reverse parallel to the first enabling inverter, and an enabling transmission gate connected in parallel to the first enabling inverter. Among them, the first enabling terminal INJW of the first enabling inverter and the first enabling terminal INJW of the second enabling inverter serve as the first input port INJW port of the injection module, which is used to receive the first pulse signal; the second enabling terminal INJW_B of the first enabling inverter and the second enabling terminal INJW_B of the second enabling inverter serve as the second input port INJW_B of the injection module, which is used to receive the second pulse signal; the enabling terminal INJN of the enabling transmission gate serves as the third input port of the injection module, which is used to receive the third pulse signal INJN.

[0067] In the specific implementation process of this embodiment, the circuit structure of the first enabling inverter is the same as that of the second enabling inverter, including four transistors, wherein: the drain D of the fifth transistor Q1 and the drain D of the sixth transistor Q8 are electrically connected, serving as the first output terminal of the enabling inverter; the gate G of the fifth transistor Q1 serves as the first enabling terminal INJW of the inverter; the gate of the sixth transistor Q8 serves as the second enabling terminal INJW_B of the inverter. The source S of the fifth transistor Q1 is electrically connected to the drain D of the seventh transistor Q2, and the source S of the sixth transistor Q8 is electrically connected to the drain D of the eighth transistor Q7; wherein the source S of the seventh transistor Q2 is grounded. The source S of the eighth transistor Q7 is connected to the power supply. The gate G of the seventh transistor Q2 and the gate G of the eighth transistor Q7 are electrically connected, serving as the second output terminal of the enabling inverter.

[0068] The enable transmission gate includes: a ninth transistor Q5 and a tenth transistor Q6; a gate G of the ninth transistor Q5 and a gate G of the tenth transistor Q6 are electrically connected to serve as an enable terminal INJN of the enable transmission gate; a drain D of the ninth transistor Q5 and a drain D of the tenth transistor Q6 are electrically connected to serve as a first output terminal of the enable transmission gate; a source S of the ninth transistor Q5 and a source S of the tenth transistor Q6 are electrically connected to serve as a second output terminal of the enable transmission gate.

[0069] That is, each injection module in this embodiment is composed of NMOS tubes Q1, Q2, Q3, Q4, Q5 and PMOS tubes Q6, Q7, Q8, Q9, Q10. INJN, INJW_B, INJW are the input terminals of the injection module, and OUTP and OUTN are the output terminals of the injection module. INJW_B is the logical inversion of INJW. INJN is a narrow injection control signal, and INJW is a wide injection control signal. INJN is connected to the gates G of Q5 and Q6. INJW is connected to the gates G of Q1 and Q3. INJW_B is connected to the gates G of Q8 and Q10. OUTP is connected to the drains S of Q1, Q5, Q6, Q8, and to the gates G of Q4 and Q9. OUTN is connected to the drains D of Q3 and Q10, to the sources S of Q5 and Q6, and to the gates G of Q2 and Q7. The source S of Q7 is connected to the power supply, the drain D of Q7 is connected to the source S of Q8, the source S of Q2 is grounded, the drain D of Q2 is connected to the source S of Q1, the source S of Q9 is connected to the power supply, the drain D of Q9 is connected to the source S of Q10, the source S of Q4 is grounded, and the drain D of Q4 is connected to the source S of Q3.

[0070] In this embodiment, Q5 and Q6 constitute the injection part controlled by INJN (narrow pulse). Q1, Q2, Q3, Q4, Q7, Q8, Q9, and Q10 constitute the injection part controlled by INJW (wide pulse). When INJN is high, Q5 and Q6 are turned on, and the injection controlled by the narrow pulse begins to make the OUTP and OUTN potentials tend to be consistent. When INJW is high and INJW_B is low, Q1, Q4, Q8, and Q10 are turned on, and the inverter composed of Q2 and Q7 and the inverter composed of Q4 and Q9 start to work, and the injection controlled by the wide pulse begins to make the OUTP and OUTN potentials tend to be opposite.

[0071] For the oscillator in the present application, when in use, the INJW_P terminal of the first injection module can be connected to the ground potential, the INJN terminal can be connected to the ground potential, and the INJW_N terminal can be connected to the power supply potential. The injection locked oscillator has no pulse control injection. At this time, the oscillator can be regarded as an ordinary ring oscillator, and the output frequency of the oscillator is recorded as the intrinsic oscillation frequency of the oscillator, and the output signal phase noise is recorded as the intrinsic phase noise of the oscillator. The intrinsic oscillation frequency of the oscillator can be adjusted by adjusting the VCTRL port of the oscillator.

[0072] For the oscillator in the present application, when in use, the INJW_P terminal of the first injection module can be connected to the ground potential, the INJN terminal can be connected to the ground potential, the INJW_N terminal can be connected to the power supply potential, and VCTRL can be adjusted so that the intrinsic oscillation frequency is 8 GHz (setting in the embodiment). The INJN terminal of the multi-pulse generation module is connected to the INJN terminal of the first injection module. At this time, the injection-locked oscillator is a traditional single narrow pulse controlled injection-locked oscillator. Figure 6 and Figure 7 As shown, the size of the VCTRL signal is adjusted to obtain the phase noise of the output signal and the phase error of the 8-phase signal under different intrinsic oscillation frequencies of the oscillator. When the intrinsic oscillation frequency is 8GHz, only the INJN signal is connected to the first injection module. At this time, the intrinsic phase noise suppression bandwidth of the oscillator is 49MHz, and the output phase error is 2.477°. The greater the intrinsic phase noise suppression capability of the oscillator, the greater the corresponding intrinsic phase noise suppression bandwidth of the oscillator.

[0073] The oscillator in this application, when in use, adjusts VCTRL so that the oscillator's intrinsic oscillation frequency is 8 GHz, corresponding to Figure 8 The T0 is 62.5ps. Connect the INJN output of the multi-pulse generation module to the INJN port of the first injection module in the injection-locked oscillator, the INJW port of the first injection module is grounded, and the INJW_B port is connected to the power supply potential. At this time, the injection-locked oscillator corresponds to the traditional single narrow pulse controlled injection-locked oscillator. Fig. 9 The origin of the output phase error of the traditional injection-locked oscillator is explained. The injection of the INJN pulse control will affect the phase of the P0 and P180 signals. During the period from the rising edge of the INJN pulse to the subsequent output cross point, the impact of the injection on the output signal phase is T N_A During the high level period of INJN signal, from the time when the output cross point occurs to the time when INJN falls, the impact of injection on the output signal phase is T N_D . Figure 8 INJN causes the intersection of P0 and P180 to shift by T N_A .

[0074] When the oscillator in the present application is in use, the INJN output by the multi-pulse generation module is connected to the INJN port of the first injection module in the injection-locked oscillator, the INJW output by the multi-pulse generation module is connected to the INJW port of the first injection module in the injection-locked oscillator, and the INJW_B output by the multi-pulse generation module is connected to the INJW_B port of the first injection module in the injection-locked oscillator. At this time, the injection-locked oscillator is the multi-pulse controlled injection-locked oscillator proposed in the present application. Fig. 9 Explain the multi-pulse control injection to eliminate the phase error of the output signal. During the period from the rising edge of the INJN pulse to the subsequent output cross point, the impact of the INJN pulse control injection on the output signal phase is T N_A During the period from the rising edge of the INJW pulse to the subsequent output cross point, the effect of the injection of the INJW pulse control on the output signal phase is T W_D . T W_D and T N_A The signs of T N_AGreater than 0, indicating that the injection controlled by INJN will accelerate the arrival of the output signal crossing point. W_D Less than 0, indicating that the injection of INJW control will slow down the arrival of the output signal crossing point. W_D and T N_A They cancel each other out, thus eliminating the output signal phase error.

[0075] When the oscillator in the present application is in use, the INJN output by the multi-pulse generation module is connected to the INJN port of the first injection module in the injection-locked oscillator, the INJW output by the multi-pulse generation module is connected to the INJW port of the first injection module in the injection-locked oscillator, and the INJW_B output by the multi-pulse generation module is connected to the INJW_B port of the first injection module in the injection-locked oscillator. At this time, the injection-locked oscillator is the multi-pulse controlled injection-locked oscillator proposed in the present application. Fig.10 Explain why multi-pulse controlled injection has a stronger ability to suppress the intrinsic phase noise of the oscillator than traditional single narrow pulse controlled injection. When the noise disturbance causes the output signal crossover point to shift T PN The relative phase relationship between the output signal and the INJN signal and the INJW signal will also change. The INJN-controlled injection will correct the offset of the output signal intersection point, and the INJW-controlled injection will also correct the offset of the output signal intersection point. Therefore, compared with the single narrow pulse controlled injection, the multi-pulse controlled injection proposed in this application has a stronger ability to suppress the intrinsic phase noise of the oscillator.

[0076] For the injection locked oscillator in this application, when in use, the INJN output by the multi-pulse generation module is connected to the INJN port of the first injection module in the injection locked oscillator, the INJW output by the multi-pulse generation module is connected to the INJW port of the first injection module in the injection locked oscillator, and the INJW_B output by the multi-pulse generation module is connected to the INJW_B port of the first injection module in the injection locked oscillator. At this time, the injection locked oscillator is the multi-pulse controlled injection locked oscillator proposed in this application. Fig.11 and Fig.12 As shown, by adjusting the size of the VCTRL signal, the phase noise of the output signal and the phase error of the 8-phase signal are obtained at different intrinsic oscillation frequencies of the oscillator. When the intrinsic oscillation frequency is 8GHz, the intrinsic phase noise suppression bandwidth of the oscillator by injection is 80MHz, and the output phase error is 0.31°. The greater the intrinsic phase noise suppression capability of the oscillator by injection, the larger the corresponding intrinsic phase noise suppression bandwidth of the oscillator by injection. Compared with the injection situation of single narrow pulse control, the multi-pulse controlled injection-locked oscillator in the present application has a greater ability to suppress the intrinsic phase noise of the oscillator and a smaller phase error.

[0077] The above embodiments are only exemplary embodiments of the present application and are not intended to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present application within the essence and protection scope of the present application, and such modifications or equivalent substitutions shall also be deemed to fall within the protection scope of the present application.

Claims

1. An oscillator, characterized in that: include: A multi-pulse generating module, wherein the input end is connected to the reference signal output end, and the output end is used to output a first pulse signal, a second pulse signal and a third pulse signal generated based on the received reference signal, wherein the first pulse signal and the third pulse signal are two pulse signals with the same pulse period and different pulse widths, and the second pulse signal is the logical inversion of the first pulse signal; A plurality of differential delay modules, each of which is electrically connected end to end in sequence to form a ring oscillator body; An injection module corresponding to each differential delay module, the output end of each injection module is electrically connected to the output end of the corresponding differential delay module; wherein any injection module serves as a target injection module, the first input port, the second input port and the third input port of the target injection module are respectively electrically connected to the output end of the multi-pulse generation module in a one-to-one correspondence, for receiving a first pulse signal, a second pulse signal and a third pulse signal, so as to periodically clear the phase noise accumulated in the ring oscillator by injecting current into the ring oscillator body under the control of the first pulse signal, the second pulse signal and the third pulse signal; the first input port, the second input port and the third output port of each non-target injection module are grounded.

2. The oscillator according to claim 1, characterized in that The multi-pulse generating module comprises: A first delay gate, a second delay gate and a third delay gate connected in series in sequence; the input end of the first delay gate is used as the first input end of the multi-pulse generation module for receiving a reference signal; the second delay gate is a delay gate with a reverse function; A first AND gate, wherein one input end of the first AND gate is electrically connected to the output end of the third delay gate, and the other input end of the first AND gate is used to receive a reference signal; the output end of the first AND gate is electrically connected to a first transmission gate and an inverter, respectively, for outputting a first pulse signal based on the transmission gate, and for outputting a second pulse signal based on the inverter; A second AND gate, one input end of the second AND gate is electrically connected to the output end of the first delay gate, and the other input end of the second AND gate is electrically connected to the output end of the second delay gate; the output end of the second AND gate is electrically connected to the second transmission gate, which is used to output a third pulse signal based on the second transmission gate.

3. The oscillator according to claim 1, characterized in that Each of the differential delay modules comprises: two inverters, two transmission gates and a load adjustment unit; The input end of the first inverter and the input end of the first transmission gate serve as the first input end of the differential delay module; The input end of the second inverter and the input end of the second transmission gate serve as the second input end of the differential delay module; The output end of the first inverter is electrically connected to the output end of the second transmission gate to serve as the first output end of the differential delay module; The output end of the second inverter is electrically connected to the output end of the first transmission gate to serve as the second output end of the differential delay gate; The load adjustment unit is arranged in parallel between the first output end and the second output end, and is used to adjust the delay time of the differential delay module by adjusting the load size.

4. The oscillator according to claim 3, characterized in that The first inverter and the second inverter have the same circuit structure, and respectively include a first transistor and a second transistor; the gate of the first transistor and the second transistor are electrically connected to serve as the input end of the inverter, and the drain of the first transistor and the drain of the second transistor are electrically connected to serve as the output end of the inverter; The circuit structure of the first transmission gate is the same as that of the second transmission gate, including: a plurality of third transistors and a plurality of fourth transistors, the drain of each of the third transistors and the drain of each of the fourth transistors are electrically connected to serve as the input end of the transmission gate, and the source of each of the third transistors and the source of each of the fourth transistors are electrically connected to serve as the output end of the transmission gate. The load adjustment unit comprises: two voltage-controlled capacitors connected in series, and a voltage adjustment terminal for adjusting the load size is arranged between the two voltage-controlled capacitors.

5. The oscillator according to claim 1, characterized in that Each of the injection modules comprises: a first enabling inverter, a second enabling inverter connected in reverse parallel to the first enabling inverter, and an enabling transmission gate connected in parallel to the first enabling inverter; Among them, the first enable end of the first enable inverter and the first enable end of the second enable inverter serve as the first input port of the injection module, for receiving the first pulse signal; the second enable end of the first enable inverter and the second enable end of the second enable inverter serve as the second input port of the injection module, for receiving the second pulse signal; the enable end of the enable transmission gate serves as the third input port of the injection module, for receiving the third pulse signal.

6. The oscillator according to claim 5, characterized in that The first enabling inverter has the same circuit structure as the second enabling inverter, and includes four transistors, wherein: The drains of the fifth transistor and the sixth transistor are electrically connected to serve as the first output terminal of the inverter; the gate of the fifth transistor serves as the first enable terminal of the inverter; and the gate of the sixth transistor serves as the second enable terminal of the inverter; The source of the fifth transistor is electrically connected to the drain of the seventh transistor, and the source of the sixth transistor is electrically connected to the drain of the eighth transistor; The gate of the seventh transistor is electrically connected to the gate of the eighth transistor to serve as the second output terminal of the enabling inverter; The enabling transmission gate includes: a ninth transistor and a tenth transistor; The gates of the ninth transistor and the tenth transistor are electrically connected to serve as an enable terminal of an enable transmission gate; The drain of the ninth transistor and the drain of the tenth transistor are electrically connected to serve as a first output terminal of the enable transmission gate; The source of the ninth transistor and the source of the tenth transistor are electrically connected to serve as the second output terminal of the enable transmission gate.

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