Clock duty cycle adjustment circuit

Abstract

The present invention discloses a clock duty cycle adjustment circuit, which belongs to the field of integrated circuits. In order to solve the problems of limited adjustment range and poor linearity, the clock duty cycle adjustment circuit of the present invention includes several delay units, a first selection module, a second selection module and a phase interpolator; after the input clock passes through several delay units, multiple delayed clocks are generated; multiple delayed clocks are used as input signals of the first selection module to generate a first interpolation input signal; multiple delayed clocks are used as input signals of the second selection module to generate a second interpolation input signal; the first interpolation input signal and the second interpolation input signal are used as input signals of the phase interpolator, and the phase interpolator generates an output clock; and the rising edge of the first interpolation input signal and the rising edge of the second interpolation input signal are both aligned with the rising edge of one of the multiple delayed clocks. The clock duty cycle adjustment circuit of the present invention has a wider adjustment range and better linearity.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a clock duty cycle adjustment circuit. Background Art

[0002] The Register Clock Driver (RCD) is a core component for Registered Dual In-Line Memory Modules (RDIMMs), responsible for managing and optimizing the timing and clock signal transmission within the memory module. Its core responsibility is to relay instructions from the Central Processing Unit (CPU) and perform necessary processing before the information is passed to the memory module. As an intermediary between the CPU and RDIMM, the RCD performs functions such as timing adjustment, clock signal enhancement, delay control, and signal distribution, usually in conjunction with the Data Buffer (DB) to enhance the stability and operating efficiency of the memory. The internal structure of the RCD includes key components such as clock distribution logic, timing controller, clock amplifier, and delay circuit.

[0003] The clock duty cycle calibration (DCC) circuit is an important clock control circuit. Figure 1 It is a DCC circuit in the prior art, including Metal Oxide Semiconductor (MOS) tubes M0, M1, M2, M3, M4, M5, M6 and M7, an input clock CKIN, an intermediate clock CKMID and an output clock CKOUT.

[0004] The DCC circuit is designed to finely control the clock edge transition time (the slope of the rising and falling edges) of the intermediate clock CKMID and the output clock CKOUT by adjusting the current intensity of the MOS tubes M2, M3, M6 and M7, ensuring that the duty cycle of the final output clock CKOUT reaches a preset value, such as 50%. Its implementation involves changing the parallel number of M2 to M7 or adjusting its gate voltage, thereby achieving precise control of the pull-up and pull-down current differences, and then regulating the transition characteristics of the clock edge.

[0005] However, this solution faces the problems of limited adjustment range, poor linearity, and direct intervention in edge transition time makes the system more sensitive to power supply noise, especially when the edge transitions slowly. In addition, different adjustment settings may cause output phase shift, which is an unacceptable defect in applications that require strict delay control.

[0006] Based on this, a solution with a wider adjustment range, better linearity, and stronger resistance to power supply noise is urgently needed in this field. Summary of the invention

[0007] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0008] A clock duty cycle adjustment circuit receives an input clock and obtains an output clock, the clock duty cycle adjustment circuit includes a plurality of delay units, a first selection module, a second selection module and a phase interpolator; after the input clock passes through the plurality of delay units, a plurality of delayed clocks are generated; the plurality of delayed clocks are used as input signals of the first selection module to generate a first interpolation input signal; the plurality of delayed clocks are used as input signals of the second selection module to generate a second interpolation input signal; the first interpolation input signal and the second interpolation input signal are used as input signals of the phase interpolator, and the phase interpolator generates the output clock; in addition, the rising edge of the first interpolation input signal and the rising edge of the second interpolation input signal are both aligned with the rising edge of a delayed clock in the plurality of delayed clocks; in the first selection module and the second selection module, both include an OR gate and an AND gate, so that the falling edge of the generated first interpolation input signal and the falling edge of the first interpolation input signal can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval; and the second interpolation input signal used to form the first interval and the second interpolation input signal used to form the second interval are generated by the same generation method.

[0009] Furthermore, the multiple continuous intervals include a third interval, and the third interval is adjacent to the second interval; the first interpolation input signal used to form the second interval and the first interpolation input signal used to form the third interval are generated by the same generation method.

[0010] Furthermore, the method of generating the first interpolation input signal or the second interpolation input signal includes: directly using one of the multiple delayed clocks as the first interpolation input signal or the second interpolation input signal.

[0011] Furthermore, the phase interpolator includes a first group of tri-state gates and a second group of tri-state gates.

[0012] Furthermore, the control code is converted into a first thermometer code and a second thermometer code through a transcoding module; the first group of three-state gates is controlled by the first thermometer code, and the second group of three-state gates is controlled by the second thermometer code; and the second thermometer code is generated by inputting the first thermometer code into at least a first inverter.

[0013] Further, the first interpolation input signal is used as an input signal of the first group of tri-state gates, and the second interpolation input signal is used as an input signal of the second group of tri-state gates.

[0014] Furthermore, the output signal of the first group of tri-state gates and the output signal of the second group of tri-state gates are used as input signals of the second inverter, and the output signal of the second inverter is the output clock.

[0015] Furthermore, the clock duty cycle adjustment circuit is applied in a clock sampling scenario.

[0016] Furthermore, the clock duty cycle adjustment circuit is applied to a fifth generation double data rate synchronous dynamic random access memory protocol clock path.

[0017] Furthermore, the clock duty cycle adjustment circuit is applied to a register clock driver. The technical solution of the present invention has one or more of the following beneficial technical effects:

[0018] (1) Duty cycle adjustment is achieved through complementary metal oxide semiconductor (CMOS) logic gates rather than traditional analog current regulation methods. Therefore, it is more stable and reliable, has stronger resistance to capacitor noise, and has better power consumption.

[0019] (2) It is implemented using digital CMOS logic gates, with a simple and clear structure, and its adjustment range and linearity are superior to traditional existing technologies.

[0020] (3) The coarse adjustment interval is generated by the logic gates in the first selection module and the second selection module, and then the fine adjustment gear is generated by the phase interpolator, so that the control of the clock signal is more precise.

[0021] (4) The phase interpolator is controlled by thermometer code to ensure better linearity.

[0022] (5) The rising edge of the output clock DCC_OUT is not affected by the adjustment gear position and is suitable for other scenarios that require clock sampling, such as RCD.

[0023] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a DCC circuit diagram in the prior art;

[0025] Figure 2 is a delay line schematic;

[0026] Figure 3 It is a schematic diagram of the DCC circuit structure of the present invention;

[0027] Figure 4 It is a signal timing diagram of the present invention;

[0028] Figure 5 It is a schematic diagram of a thermometer code generation module of the present invention;

[0029] Figure 6 It is the circuit diagram of the phase interpolator of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0032] Figure 2 In the present invention, after the input clock DCC_IN passes through a plurality of delay units, a plurality of delayed clocks are generated.

[0033] For example, through 4 delay units, the delay time of each delay unit is the same, the input clock DCC_IN passes through the 4 delay units in sequence, and the delay line can lead to 5 delayed clocks with equal phase difference: DCC_DLY0, DCC_DLY1, DCC_DLY2, DCC_DLY3 or DCC_DLY4. Among them, DCC_DLY0 is a clock directly derived from the input clock DCC_IN without any delay unit. Among them, the input clock DCC_IN is a clock that requires the DCC circuit to adjust the duty, and its source can be a phase-locked loop or other clock path.

[0034] For example, the rising edge of DCC_DLY2 can be used as the rising edge of the final DCC circuit output clock DCC_OUT, and the falling edge of the DCC circuit output clock DCC_OUT is generated by the falling edges of two delayed clocks among DCC_DLY0, DCC_DLY1, DCC_DLY2, DCC_DLY3 and DCC_DLY4 and through a phase interpolator (PI).

[0035] Figure 3It is a schematic diagram of the DCC circuit structure of the present invention. The five delayed clocks DCC_DLY0, DCC_DLY1, DCC_DLY2, DCC_DLY3 and DCC_DLY4 are respectively sent to the first selection module and the second selection module as input signals to perform timing control, and the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y for falling edge interpolation are respectively obtained. The first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are used as inputs of the phase interpolator, and the output clock DCC_OUT of the DCC circuit is obtained through the phase interpolator. The output clock DCC_OUT is a clock after the duty cycle is adjusted.

[0036] Figure 4 The rising edge of the first interpolation input signal DCC_X and the rising edge of the second interpolation input signal DCC_Y are both aligned with the rising edge of one of the delayed clocks.

[0037] The falling edge of the output clock DCC_OUT falls in which interval (first interval, second interval, third interval or fourth interval) depends on the target duty cycle. The first interval, second interval, third interval and fourth interval here are divided by the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y output by the first selection module and the second selection module respectively.

[0038] For example, in the circuit numerical calculation logic, the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are generated through an OR gate and an AND gate:

[0039] First interval:

[0040] ;

[0041] Second interval:

[0042] ;

[0043] The third interval:

[0044] ;

[0045] Fourth interval:

[0046] ;

[0047] Among them, the symbol " "Represents logical and symbolic" " indicates logical OR. For ease of reading, Figure 4 DCC_X=0 2 is the above "DCC_X = DCC_DLY0 DCC_DLY2", DCC_X=2 is the abbreviation of the above "DCC_X=DCC_DLY2", and other abbreviations are similar.

[0048] It is not difficult to see that the first interpolation input signal DCC_X or the second interpolation input signal DCC_Y in adjacent intervals remains unchanged, which leads to the continuity of the intervals, increases the linearity when switching between intervals, and reduces the circuit complexity.

[0049] In other words, both the first selection module and the second selection module include an OR gate and an AND gate, so that the falling edge of the generated first interpolation input signal DCC_X and the falling edge of the first interpolation input signal DCC_X can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval.

[0050] Further, the second interpolation input signal DCC_Y used to form the first interval and the second interpolation input signal DCC_Y used to form the second interval are generated in the same manner.

[0051] The plurality of continuous intervals include a third interval, and the third interval is adjacent to the second interval; the first interpolation input signal DCC_X used to form the second interval and the first interpolation input signal DCC_X used to form the third interval are generated in the same manner.

[0052] For example, one of the delayed clocks may be directly used as the first interpolation input signal DCC_X or the second interpolation input signal DCC_Y.

[0053] Figure 5 Schematic diagram of the thermometer code generation module of the present invention. For example, the control code BIN<3:0> contains 4 bits, and after passing through the transcoding module, a 16-bit first thermometer code THM<15:0> is generated, and then after being inverted by at least a first inverter, a second thermometer code THM_B<15:0> is obtained. In other words, the first thermometer code and the second thermometer code are inverted signals to each other. The specific scheme for generating the thermometer code is well known to those skilled in the art and will not be repeated here.

[0054] Figure 6 : is a circuit diagram of a phase interpolator of the present invention. The phase interpolator circuit includes a first group of three-state gates and a second group of three-state gates. The first group of three-state gates is controlled by a first thermometer code THM<15:0>, and the second group of three-state gates is controlled by a second thermometer code THM_B<15:0>. By way of example, the first group of three-state gates and the second group of three-state gates each include a plurality of three-state gates, and by way of example, include 16 three-state gates. The present invention can control the number of interpolations through the thermometer code to ensure that the opening of the three-state gates used for interpolation is linear.

[0055] The first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are used as input signals of the phase interpolator, and are respectively subjected to weighted processing of the first thermometer code THM<15:0> and the second thermometer code THM_B<15:0>. Specifically, the first interpolation input signal DCC_X is used as the input signal of the first group of tri-state gates, and the second interpolation input signal DCC_Y is used as the input signal of the second group of tri-state gates. The output signal of the first group of tri-state gates and the output signal of the second group of tri-state gates are used as the input signal of the second inverter, and the output signal of the second inverter is the output clock DCC_OUT.

[0056] As the adjustment gear increases, the falling edge synthesized by the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y will move backward, and since the rising edges of the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are fixed, different adjustment gears are generated as the control code BIN<3:0> changes, and the falling edge of the output clock DCC_OUT also changes, but the rising edge of the output clock DCC_OUT remains unchanged, that is, the duty cycle of the output clock DCC_OUT can be adjusted by the control code BIN<3:0>.

[0057] The present invention proposes a DCC circuit applied to the protocol clock path of the fifth-generation double data rate synchronous dynamic random access memory (DDR SDRAM). With its high precision and high linearity characteristics, the design can effectively adjust and maintain the duty cycle of the clock path to ensure the high quality of the output clock signal.

[0058] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0059] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A clock duty cycle adjustment circuit receives an input clock and obtains an output clock, characterized in that: The clock duty cycle adjustment circuit includes a plurality of delay units, a first selection module, a second selection module and a phase interpolator; The input clock generates multiple delayed clocks after passing through a plurality of delay units; The plurality of delayed clocks are used as input signals of a first selection module to generate a first interpolation input signal; The multiple delayed clocks are used as input signals of a second selection module to generate a second interpolation input signal; The first interpolation input signal and the second interpolation input signal are used as input signals of a phase interpolator, and the phase interpolator generates the output clock; in addition, A rising edge of the first interpolation input signal and a rising edge of the second interpolation input signal are both aligned with a rising edge of a delayed clock among the plurality of delayed clocks; In the first selection module and the second selection module, both include an OR gate and an AND gate, so that the falling edge of the generated first interpolation input signal and the falling edge of the first interpolation input signal can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval; and, The second interpolation input signal used to form the first interval and the second interpolation input signal used to form the second interval are generated in the same manner.

2. The clock duty cycle adjustment circuit according to claim 1, characterized in that: The plurality of continuous intervals include a third interval, and the third interval is adjacent to the second interval; The first interpolation input signal used to form the second interval and the first interpolation input signal used to form the third interval are generated in the same manner.

3. The clock duty cycle adjustment circuit according to claim 2, characterized in that: The method of generating the first interpolation input signal or the second interpolation input signal includes: One of the delayed clocks is directly used as the first interpolation input signal or the second interpolation input signal.

4. The clock duty cycle adjustment circuit according to claim 3, characterized in that: The phase interpolator includes a first group of tri-state gates and a second group of tri-state gates.

5. The clock duty cycle adjustment circuit according to claim 4, characterized in that: The control code is converted into a first thermometer code and a second thermometer code by a transcoding module; Controlling a first group of three-state gates by a first thermometer code and controlling a second group of three-state gates by a second thermometer code; A second thermometer code is generated by inputting the first thermometer code to at least the first inverter.

6. The clock duty cycle adjustment circuit according to claim 5, characterized in that: The first interpolation input signal is used as an input signal of the first group of tri-state gates, and the second interpolation input signal is used as an input signal of the second group of tri-state gates.

7. The clock duty cycle adjustment circuit according to claim 6, characterized in that: The output signal of the first group of tri-state gates and the output signal of the second group of tri-state gates are used as input signals of the second inverter, and the output signal of the second inverter is the output clock.

8. The clock duty cycle adjustment circuit according to claim 7, characterized in that: The clock duty cycle adjustment circuit is applied in a clock sampling scenario.

9. The clock duty cycle adjustment circuit according to claim 7, characterized in that: The clock duty cycle adjustment circuit is applied to the fifth generation double data rate synchronous dynamic random access memory protocol clock path.

10. The clock duty cycle adjustment circuit according to claim 7, characterized in that: The clock duty cycle adjustment circuit is applied to a register clock driver.

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