DCC Circuit

Abstract

The present invention discloses a DCC circuit, which belongs to the field of integrated circuits. In order to improve the adjustment range, the DCC circuit of the present invention receives an input clock and obtains an output clock. The DCC circuit includes a plurality of DCDLs, a first selection module, a second selection module and a phase interpolator, and each DCDL includes n delay branches and a multiplexer; the input clock generates a plurality of delayed clocks after passing through a plurality of DCDLs; the plurality of delayed clocks are used as input signals of the first selection module and the second selection module, respectively generating a first interpolation input signal and a second interpolation input signal; the first interpolation input signal and the second interpolation input signal are used as input signals of the phase interpolator, and the phase interpolator generates the output clock; the n delay branches respectively include inverters of different numbers; according to the frequency of the input clock, one of the n delay branches is selected as the output path of the multiplexer. The adjustment range of the present invention is wider and the use frequency range is wider.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a DCC circuit. Background Art

[0002] The Register Clock Driver (RCD) is a key component of the Registered Dual In-Line Memory Module (RDIMM) and plays a core role in the timing and clock signal management and optimization within the memory module.

[0003] The main functions of RCD involve receiving instructions from the central processing unit and preprocessing them. As a bridge between the central processing unit and RDIMM, RCD performs tasks including timing correction, clock signal amplification, delay management and signal distribution. It usually cooperates with the data buffer (DB) to improve the stability and operating performance of the memory. The internal structure of RCD integrates key technical links such as clock distribution logic unit, timing control module, clock amplification component and delay line.

[0004] As an advanced clock management technology, the clock duty cycle calibration (DCC) circuit plays an important role. Figure 1 This is a DCC circuit diagram in the prior art. The DCC circuit covers Metal Oxide Semiconductor (MOS) tubes M0, M1, M2, M3, M4, M5, M6, M7, as well as input clock CKIN, intermediate clock CKMID and output clock CKOUT.

[0005] The fundamental goal of the DCC circuit design is to use the current intensity of MOS tubes M2, M3, M6 and M7 to fine-tune the clock edge conversion rate (i.e., the rising and falling slopes) of the intermediate clock CKMID and the output clock CKOUT to ensure that the duty cycle of the output clock CKOUT accurately reaches the expected value, typically 50%. This adjustment process is achieved by changing the parallel configuration of MOS tubes M2 to M7 or adjusting the gate voltage, thereby precisely controlling the balance of pull-up and pull-down currents and effectively managing the transition characteristics of the clock edge.

[0006] However, current solutions suffer from the challenges of limited regulation range, poor linear response, and direct intervention in the edge transition process makes the system more sensitive to power supply noise, especially during slow edge transitions.

[0007] Since the current solution is to adjust the duty cycle by directly adjusting the rising and falling edge climbing time, if a larger adjustment range is required, it is necessary to rely on a slower rising and falling edge climbing time. When the climbing time becomes longer, the impact of noise will also become greater, whether it is random jitter or deterministic jitter.

[0008] In addition, different adjustment configurations may lead to output phase deviation, which is a problem that cannot be ignored in high-precision delay control application scenarios.

[0009] Therefore, developing a solution with a wider adjustment range, better linearity, and stronger power supply noise suppression capability has become an urgent need in this field. Summary of the invention

[0010] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0011] A DCC circuit receives an input clock and obtains an output clock, the DCC circuit includes a plurality of DCDLs, a first selection module, a second selection module and a phase interpolator, each DCDL includes n delay branches and a multiplexer, n is a positive integer greater than 1; the input clock generates a plurality of delayed clocks after passing through a plurality of DCDLs; the plurality of delayed clocks serve as input signals of the first selection module and the second selection module, respectively generating a first interpolation input signal and a second interpolation input signal; the first interpolation input signal and the second interpolation input signal serve as input signals of a phase interpolator, and the phase interpolator generates the output clock; in addition, the n delay branches respectively include an unequal number of inverters; according to the frequency of the input clock, one of the n delay branches is selected as the output path of the multiplexer.

[0012] Furthermore, when the frequency of the input clock becomes higher, a delay branch with fewer inverters is selected as the output path of the multiplexer; when the frequency of the input clock becomes lower, a delay branch with more inverters is selected as the output path of the multiplexer.

[0013] Furthermore, the rising edge of the first interpolation input signal and the rising edge of the second interpolation input signal are both aligned with the rising edge of a delayed clock among the multiple delayed clocks; in the first selection module and the second selection module, both include an OR gate and an AND gate, so that the generated falling edge of the first interpolation input signal and the falling edge of the first interpolation input signal can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval; and the second interpolation input signal used to form the first interval and the second interpolation input signal used to form the second interval are generated by the same generation method; the plurality of continuous intervals include a third interval, and the third interval is adjacent to the second interval; the first interpolation input signal used to form the second interval and the first interpolation input signal used to form the third interval are generated by the same generation method.

[0014] Furthermore, the method of generating the first interpolation input signal or the second interpolation input signal includes: directly using one of the multiple delayed clocks as the first interpolation input signal or the second interpolation input signal.

[0015] Furthermore, the phase interpolator includes a first group of three-state gates and a second group of three-state gates; the control code is converted into a first thermometer code and a second thermometer code through a transcoding module; the first group of three-state gates is controlled by the first thermometer code, and the second group of three-state gates is controlled by the second thermometer code; and the second thermometer code is generated by inputting the first thermometer code into at least a first inverter.

[0016] Furthermore, the first interpolation input signal is used as the input signal of the first group of three-state gates, and the second interpolation input signal is used as the input signal of the second group of three-state gates; the output signal of the first group of three-state gates and the output signal of the second group of three-state gates are used as input signals of the second inverter, and the output signal of the second inverter is the output clock.

[0017] Furthermore, the DCC circuit is applied in a clock sampling scenario.

[0018] Furthermore, the DCC circuit is applied to a register clock driver.

[0019] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0020] (1) Within a wide frequency range, the input clock DCC_IN has a suitable and large duty cycle adjustment range.

[0021] (2) The applicable frequency range is wide and can be controlled through digital registers. The solution is reliable and effective.

[0022] (3) Duty cycle adjustment is achieved through logic gates rather than the traditional analog current adjustment method, so it is more stable and reliable, has stronger resistance to capacitor noise, and has better power consumption.

[0023] (4) It is implemented using digital CMOS logic gates, with a simple and clear structure, and its adjustment range and linearity are superior to traditional existing technologies.

[0024] (5) The phase interpolator is controlled by the thermometer code to ensure better linearity. The rising edge of the output clock DCC_OUT is not affected by the adjustment gear, which is suitable for other scenarios that require clock sampling, such as RCD. The coarse adjustment of the logic gate and the fine adjustment of the phase interpolator can control the clock signal more accurately.

[0025] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a DCC circuit diagram in the prior art;

[0027] Figure 2 It is a schematic diagram of the DCC circuit structure of the present invention;

[0028] Figure 3 It is a schematic diagram of the DCDL structure;

[0029] Figure 4 It is a signal timing diagram of the present invention;

[0030] Figure 5 Circuit diagram of the phase interpolator of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0033] Figure 2The DCC circuit structure diagram of the present invention includes the input clock DCC_IN of the DCC circuit and the output clock DCC_OUT of the DCC circuit. The DCC circuit includes a number of digitally controlled delay lines (DCDL), which are used to generate the same delay. The DCDL in the present invention can be used to expand the applicable clock frequency range of the DCC circuit.

[0034] After the input clock DCC_IN passes through multiple DCDLs, multiple delayed clocks are generated. For example, setting 4 DCDLs will generate 5 delayed clocks. These 5 delayed clocks DCC_DLY0, DCC_DLY1, DCC_DLY2, DCC_DLY3 and DCC_DLY4 are respectively sent to the first selection module and the second selection module as input signals to perform timing control, and respectively obtain the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y used for interpolating the falling edge of the output clock DCC_OUT.

[0035] The first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are used as inputs of the phase interpolator (PI), and the output clock DCC_OUT of the DCC circuit is obtained through the phase interpolator. In the phase interpolator, the falling edge of the output clock DCC_OUT is used for adjustment. The output clock DCC_OUT is the target clock after the duty cycle is adjusted. The rising edge of the first interpolation input signal DCC_X and the rising edge of the second interpolation input signal DCC_Y are aligned.

[0036] In addition, DCC_DLY0 is a clock directly derived from the input clock DCC_IN without any delay unit.

[0037] Furthermore, the input clock DCC_IN is a clock that requires the DCC circuit to adjust the duty cycle, and its source may be a phase-locked loop or other clock paths.

[0038] Figure 3 is a schematic diagram of the DCDL structure. For example, the DCDL includes n delay branches, wherein the first delay branch exemplarily includes 2 inverters, the second delay branch exemplarily includes 4 inverters, ..., the nth delay branch exemplarily includes 2n inverters, and n is a positive integer greater than 1. In other words, the n delay branches include unequal numbers of inverters to generate n different delays.

[0039] The n delay branches all receive the clock to be delayed CLK_IN, and the outputs of the n delay branches serve as the input of the multiplexer. The output path of the multiplexer is controlled by configuring the register, and one of the delay branches is selected to access the output end of DCDL to output the delayed clock CLK_OUT.

[0040] By controlling the output path of the multiplexer, when the frequency of the input clock DCC_IN is high, a delay branch with a smaller delay can be selected. Conversely, when the frequency of the input clock DCC_IN is low, a delay branch with a larger delay can be selected. The advantage of this technical means is that it can achieve a suitable and larger duty cycle adjustment range for the input clock DCC_IN within a wider frequency range.

[0041] Figure 4 The rising edge of the first interpolation input signal DCC_X and the rising edge of the second interpolation input signal DCC_Y are both aligned with the rising edge of one of the delayed clocks.

[0042] For example, the rising edge of DCC_DLY2 can be used as the rising edge of the final DCC circuit output clock DCC_OUT, and the falling edge of the DCC circuit output clock DCC_OUT is generated by the falling edges of two delayed clocks among DCC_DLY0, DCC_DLY1, DCC_DLY2, DCC_DLY3 and DCC_DLY4 through a phase interpolator.

[0043] Depending on the target duty cycle, the falling edge of the output clock DCC_OUT falls in the first interval, the second interval, the third interval or the fourth interval. The first interval, the second interval, the third interval and the fourth interval are divided by the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y output by the first selection module and the second selection module respectively.

[0044] For example, in the circuit numerical calculation logic, the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are generated through an OR gate and an AND gate:

[0045] First interval:

[0046] ;

[0047] Second interval:

[0048] ;

[0049] The third interval:

[0050] ;

[0051] Fourth interval:

[0052] ;

[0053] Among them, the symbol " "Represents logical and symbolic" " indicates logical OR. For ease of reading, Figure 4 DCC_X=0 2 is the above "DCC_X = DCC_DLY0 DCC_DLY2", DCC_X=2 is the abbreviation of the above "DCC_X=DCC_DLY2", and other abbreviations are similar.

[0054] It is not difficult to see that the first interpolation input signal DCC_X or the second interpolation input signal DCC_Y in adjacent intervals remains unchanged, which leads to the continuity of the intervals, increases the linearity when switching between intervals, and reduces the circuit complexity.

[0055] In other words, both the first selection module and the second selection module include an OR gate and an AND gate, so that the falling edge of the generated first interpolation input signal DCC_X and the falling edge of the first interpolation input signal DCC_X can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval.

[0056] Further, the second interpolation input signal DCC_Y used to form the first interval and the second interpolation input signal DCC_Y used to form the second interval are generated in the same manner.

[0057] The plurality of continuous intervals include a third interval, and the third interval is adjacent to the second interval; the first interpolation input signal DCC_X used to form the second interval and the first interpolation input signal DCC_X used to form the third interval are generated in the same manner.

[0058] For example, one of the delayed clocks may be directly used as the first interpolation input signal DCC_X or the second interpolation input signal DCC_Y.

[0059] Figure 5 : is a circuit diagram of a phase interpolator of the present invention. The phase interpolator circuit includes a first group of three-state gates and a second group of three-state gates. The first group of three-state gates is controlled by a first thermometer code THM<15:0>, and the second group of three-state gates is controlled by a second thermometer code THM_B<15:0>. By way of example, the first group of three-state gates and the second group of three-state gates each include a plurality of three-state gates, and by way of example, include 16 three-state gates. The present invention can control the number of interpolations through the thermometer code to ensure that the opening of the three-state gates used for interpolation is linear.

[0060] Furthermore, the first thermometer code THM<15:0> and the second thermometer code THM_B<15:0> are mutually inverted signals. As a conventional signal inversion technique in the art, the first thermometer code THM<15:0> can be input into at least the first inverter (in Figure 5 The second thermometer code THM_B<15:0> is generated by the second thermometer code THM_B<15:0>, and the second group of tri-state gates is controlled by the second thermometer code THM_B<15:0>.

[0061] The first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are used as input signals of the phase interpolator, and are respectively subjected to weighted processing of the first thermometer code THM<15:0> and the second thermometer code THM_B<15:0>. Specifically, the first interpolation input signal DCC_X is used as the input signal of the first group of tri-state gates, and the second interpolation input signal DCC_Y is used as the input signal of the second group of tri-state gates. The output signals of the first group of tri-state gates and the output signals of the second group of tri-state gates are used as the second inverter ( Figure 5 The input signal of the second inverter is the rightmost inverter in the figure, and the output signal of the second inverter is the output clock DCC_OUT.

[0062] As the adjustment gear increases, the falling edge synthesized by the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y will move backward, and since the rising edges of the first interpolation input signal DCC_X and the second interpolation input signal DCC_Y are fixed, the falling edge of the output clock DCC_OUT also changes as the adjustment gear changes, but the rising edge of the output clock DCC_OUT remains unchanged, that is, the duty cycle of the output clock DCC_OUT can be adjusted by the first thermometer code and the second thermometer code.

[0063] The present invention proposes a DCC circuit applied to the protocol clock path of the fifth-generation double data rate synchronous dynamic random access memory (DDR SDRAM). With its high precision and high linearity characteristics, the design can effectively adjust and maintain the duty cycle of the clock path to ensure the high quality of the output clock signal. In addition, the present invention can use a wider clock frequency range. Within the wider frequency range, the input clock DCC_IN has a suitable and large duty cycle adjustment range.

[0064] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0065] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A DCC circuit, receiving an input clock and obtaining an output clock, characterized in that: The DCC circuit includes a plurality of DCDLs, a first selection module, a second selection module and a phase interpolator, each DCDL includes n delay branches and a multiplexer, and n is a positive integer greater than 1; The input clock generates a plurality of delayed clocks after passing through a plurality of DCDLs; The multiple delayed clocks are used as input signals of the first selection module and the second selection module to generate a first interpolation input signal and a second interpolation input signal respectively; The first interpolation input signal and the second interpolation input signal are used as input signals of a phase interpolator, and the phase interpolator generates the output clock; in addition, The n delay branches respectively include inverters of different numbers; According to the frequency of the input clock, one of the n delay branches is selected as the output path of the multiplexer; A rising edge of the first interpolation input signal and a rising edge of the second interpolation input signal are both aligned with a rising edge of a delayed clock among the plurality of delayed clocks; In the first selection module and the second selection module, both include an OR gate and an AND gate, so that the falling edge of the generated first interpolation input signal and the falling edge of the first interpolation input signal can form a plurality of continuous intervals, wherein the plurality of continuous intervals include a first interval and a second interval adjacent to the first interval; and, The second interpolation input signal used to form the first interval and the second interpolation input signal used to form the second interval are generated by the same generation method; The plurality of continuous intervals include a third interval, and the third interval is adjacent to the second interval; The first interpolation input signal used to form the second interval and the first interpolation input signal used to form the third interval are generated in the same manner.

2. The DCC circuit according to claim 1, characterized in that: When the frequency of the input clock becomes higher, a delay branch line with a smaller number of inverters is selected as an output path of the multiplexer; When the frequency of the input clock becomes lower, the delay branch with a larger number of inverters is selected as the output path of the multiplexer.

3. The DCC circuit according to claim 2, characterized in that: The method of generating the first interpolation input signal or the second interpolation input signal includes: One of the delayed clocks is directly used as the first interpolation input signal or the second interpolation input signal.

4. The DCC circuit according to claim 3, characterized in that: The phase interpolator includes a first group of tri-state gates and a second group of tri-state gates; The control code is converted into a first thermometer code and a second thermometer code by a transcoding module; Controlling a first group of three-state gates by a first thermometer code and controlling a second group of three-state gates by a second thermometer code; A second thermometer code is generated by inputting the first thermometer code to at least the first inverter.

5. The DCC circuit according to claim 4, characterized in that: The first interpolation input signal is used as an input signal of the first group of tri-state gates, and the second interpolation input signal is used as an input signal of the second group of tri-state gates; The output signal of the first group of tri-state gates and the output signal of the second group of tri-state gates are used as input signals of the second inverter, and the output signal of the second inverter is the output clock.

6. The DCC circuit according to claim 5, characterized in that: The DCC circuit is applied in a clock sampling scenario.

7. The DCC circuit according to claim 6, characterized in that: The DCC circuit is applied in a register clock driver.

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