Signal offset calibration method, calibration device and high-speed DRAM interface

Abstract

The present application proposes a signal offset calibration method, a calibration device and a high-speed DRAM interface, which relates to the field of high-speed communication technology. The signal offset calibration method includes: obtaining an original signal and an error signal; adding the original signal and the error signal through a DFE adder, and outputting them to a sampler for sampling to output a corresponding sampling result; determining an offset adjustment direction corresponding to the sampling result through an offset control logic, and adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the output end of the DFE adder changes. The present application can better alleviate the deviation of the input buffer and reduce the distortion of the received signal.

Description

Technical Field

[0001] The present application relates to the field of high-speed communication technology, and in particular to a signal offset calibration method, a calibration device and a high-speed DRAM interface. Background Art

[0002] In the field of contemporary communication systems, especially in high-speed data transmission, the multipath effect and other interference factors of the signal often cause serious distortion of the signal, which in turn affects the accuracy of data recovery at the receiving end. The deviation of the receive buffer (RXbuffer) mainly comes from the mismatch of transistors, which is caused by the fluctuation of local threshold voltage. These fluctuations are affected by the well proximity effect (WPE) and shallow trench isolation (STI), which are common phenomena in advanced process technologies. Therefore, it is crucial to minimize the deviation of the input buffer.

[0003] In order to alleviate the deviation problem of the input buffer, various technical means are usually adopted, such as capacitor compensation and input transistor size control. However, these methods cannot completely eliminate the deviation on each sampling path. Summary of the invention

[0004] The main purpose of the present invention is to provide a signal offset calibration method, aiming to alleviate the deviation of the input buffer to reduce the distortion of the received signal.

[0005] To achieve the above object, the present invention provides a signal offset calibration method, which is applied to a high-speed DRAM interface, wherein the high-speed DRAM interface includes at least one signal processing path, and any signal processing path includes a DFE adder, a sampler, and an offset control logic device electrically connected to each other, and the signal offset calibration method includes:

[0006] Obtaining original signal and error signal;

[0007] The original signal and the error signal are added by a DFE adder, and output to the sampler for sampling to output a corresponding sampling result;

[0008] The offset adjustment direction corresponding to the sampling result is determined by the offset control logic, and the signal output by the DFE adder is adjusted according to the offset adjustment direction until the level state of the signal output by the sampler changes.

[0009] Optionally, the high-speed DRAM interface further comprises a variable gain amplifier, the input end of the variable gain amplifier is used to receive an input signal, and the output end of the variable gain amplifier is connected to the input end of the signal processing path;

[0010] The obtaining of the original signal and the error signal comprises:

[0011] Setting the voltage of the input signal as a reference voltage to obtain the original signal;

[0012] The input voltage at the signal input terminal is input to the variable gain amplifier for preprocessing to generate a corresponding error signal.

[0013] Optionally, the offset control logic includes a detection circuit and a counter;

[0014] The offset adjustment direction corresponding to the sampling result is determined by the offset control logic as follows:

[0015] The level state of the sampling result is detected by a detection circuit, and a corresponding control signal is output to the counter, so that the counter performs offset adjustment according to the control signal.

[0016] Optionally, detecting the level state of the sampling result through a detection circuit and outputting a corresponding control signal to the counter so that the counter performs offset adjustment according to the control signal includes:

[0017] If the output sampling result is a high level, a low level signal is output to the counter to control the offset adjustment to decrease;

[0018] If the output sampling result is a low level, a high level signal is output to the counter to control the offset adjustment to increase.

[0019] Optionally, if the output sampling result is a high level, outputting a low level signal to the counter to control the offset adjustment reduction includes:

[0020] If the sampling result output is a high level, the control signal outputs a low level to control the counter to decrease, so as to control the offset adjustment to decrease.

[0021] Optionally, if the output sampling result is a low level, outputting a high level signal to the counter to control the offset adjustment to increase comprises:

[0022] If the output sampling result is a low level, the control signal outputs a high level to control the counter to increment, so as to control the offset adjustment to increase.

[0023] Optionally, the adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the signal output by the sampler changes is specifically:

[0024] If the offset adjustment direction is offset adjustment increase, adjusting the negative signal path;

[0025] If the offset adjustment direction is offset adjustment reduction, adjusting the forward signal path;

[0026] The negative signal path and the positive signal path are repeatedly adjusted until the level state of the signal output by the sampler changes, and it is determined that the calibration is completed, and the sampler outputs a square wave of a preset frequency.

[0027] In addition, to achieve the above-mentioned purpose, the present invention also provides a calibration device, which includes: a memory, a processor, and a signal offset calibration program stored in the memory and executable on the processor, wherein the signal offset calibration program is configured to implement the signal offset calibration method as described above.

[0028] In addition, to achieve the above object, the present invention also provides a high-speed DRAM interface, including the calibration device as described above.

[0029] The embodiment of the present invention obtains an original signal and an error signal, adds the original signal and the error signal through a DFE adder, and then outputs the added signal to a sampler for sampling to output a corresponding sampling result. Finally, an offset adjustment direction corresponding to the sampling result is determined through an offset control logic, thereby adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the signal output by the sampler changes, thereby better alleviating the deviation of the input buffer and reducing the distortion of the received signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0032] Figure 1 A model diagram of a high-speed DRAM interface of the present invention;

[0033] Figure 2 A schematic diagram of a signal offset calibration method according to an embodiment of the present invention;

[0034] Figure 3 for Figure 2 A detailed method flow chart of step S100 in FIG.

[0035] Figure 4for Figure 2 A detailed method flow diagram of step S300 in FIG.

[0036] Figure 5 for Figure 4 A detailed method flow diagram of step S310 in FIG.

[0037] Figure 6 for Figure 5 A detailed method flow diagram of step S311 in FIG.

[0038] Figure 7 for Figure 5 A detailed method flow diagram of step S312 in FIG.

[0039] Figure 8 A schematic flow chart of a signal offset calibration method according to another embodiment of the present invention;

[0040] Fig. 9 This is the timing diagram during the offset calibration process.

[0041] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and the well-known modules, units and their connections, links, communications or operations are not shown or described in detail. In addition, the described features, architectures or functions can be combined in any way in one or more embodiments. It should be understood by those skilled in the art that the various embodiments described below are only for illustration and not for limiting the scope of protection of the present invention. It can also be easily understood that the modules or units or processing methods in the various embodiments described herein and shown in the drawings can be combined and designed according to various different configurations. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0043] The limitations of various nouns or methods in the following embodiments, except for those that are logically untenable, are generally based on the broad concepts that can be implemented under the premise of the contents disclosed in the embodiments. Under such understanding, the various specific subordinate specific limitations of the nouns or methods should be regarded as the inventive content of the present invention, and should not be understood narrowly or interpreted in a biased manner on the grounds that the specification does not disclose the specific limitations. Similarly, under the premise that it can be implemented logically, the order of the steps in the method is flexible and changeable, and the specific subordinate specific limitations in the broad concepts of various nouns or methods all fall within the scope of protection of the present invention.

[0044] The main solution of the embodiment of the present application is: by acquiring the original signal and the error signal, adding the original signal and the error signal through the DFE adder, and then outputting the added signal to the sampler for sampling to output the corresponding sampling result, and finally determining the offset adjustment direction corresponding to the sampling result through the offset control logic, thereby adjusting the signal output by the DFE adder according to the offset adjustment direction until the output end of the DFE adder reaches a balanced state.

[0045] In this embodiment, for the convenience of description, the following description is made with the calibration device as the execution subject.

[0046] In the field of contemporary communication systems, especially in high-speed data transmission, the multipath effect and other interference factors of the signal often cause serious distortion of the signal, which in turn affects the accuracy of data recovery at the receiving end. The deviation of the receive buffer (RXbuffer) mainly comes from the mismatch of transistors, which is caused by the fluctuation of local threshold voltage. These fluctuations are affected by the well proximity effect (WPE) and shallow trench isolation (STI), which are common phenomena in advanced process technologies. Therefore, it is crucial to minimize the deviation of the input buffer.

[0047] However, the existing technology cannot completely eliminate the deviation on each sampling path by adopting various technical means such as capacitor compensation and controlling the size of input transistors.

[0048] The present application provides a solution that can better alleviate the deviation of the input buffer and reduce the distortion of the received signal.

[0049] To this end, the present invention proposes a signal offset calibration method; it can be understood that a calibration device for storing and executing the following method is provided in the high-speed DRAM interface, and the calibration device can be implemented by a main controller, such as MCU (Micro controller Unit), DSP (Digital Signal Process), FPGA (Field Programmable Gate Array), SOC (System OnChip), etc.

[0050] It should be understood that the signal offset calibration method proposed in the present invention is applied to high-speed DRAM interface. Figure 1 As shown, the high-speed DRAM interface includes at least one signal processing path, and any signal processing path includes a DFE adder, a sampler, and an offset control logic that are electrically connected to each other.

[0051] Reference Figure 2 In one embodiment of the present invention, the signal offset calibration method includes steps S100-S300, wherein:

[0052] S100, obtaining an original signal and an error signal;

[0053] S200, adding the original signal and the error signal through the DFE adder, and outputting them to the sampler for sampling to output the corresponding sampling result;

[0054] S300, determining an offset adjustment direction corresponding to the sampling result through an offset control logic, and adjusting a signal output by a DFE adder according to the offset adjustment direction until a level state of a signal output by the sampler changes.

[0055] In this embodiment, the original signal includes an externally input DQS signal and a reference signal, wherein the DQS signal is a signal to be amplified, and the reference signal is used to provide a reference level. The function of the DFE adder is to combine the original signal with the error signal to reduce the distortion of the signal during transmission. The sampler is responsible for sampling the signal output by the adder to obtain an accurate sampling result. The offset control logic adjusts the output signal of the DFE adder according to the sampling result to ensure that the signal offset in the signal processing path is effectively calibrated. Through such a cyclic adjustment, the signal processing of the high-speed DRAM interface is finally optimized, thereby improving the accuracy and stability of data transmission.

[0056] In practical applications, such as Figure 1As shown, assuming that there are four signal processing paths, "IB path", "Q path", "QB path" and "I path", this division results in the formation of four different paths in the receiver (RX). The "I path" path includes a DFE adder, a sampler and offset control logic, and the other three paths also include a DFE adder, a sampler and offset control logic, and the three form a closed-loop path. In the offset calibration mode, the offset between the paths will be reflected in the OUT_I (output I) result, and the offset will be adjusted through the offset control logic. For example, if the result of OUT_I is '1', the upper / lower output will be '0', and the OUT_DFE_P path will be adjusted. On the contrary, if the result of OUT_I is '0', the upper / lower output will be '1', and the OUT_DFE_N path will be adjusted. Once the offset calibration is completed, OUT_I will switch between '1010' or '0101'. For example, if Fig. 9 As shown in the timing diagram, if the OUT_I result remains at '1', the output of the upper / lower will remain at '0' until OUT_I becomes '0'. After this transition, the offset calibration is considered complete, that is, the output of the DFE adder reaches a balanced state, and OUT_I will start toggling in a '0101' manner.

[0057] This embodiment obtains an original signal and an error signal, adds the original signal and the error signal through a DFE adder, and then outputs the added signal to a sampler for sampling to output a corresponding sampling result. Finally, an offset adjustment direction corresponding to the sampling result is determined through an offset control logic, thereby adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the signal output by the sampler changes, which can better alleviate the deviation of the input buffer and reduce the distortion of the received signal.

[0058] Please understand that Figure 1 As shown, the high-speed DRAM interface also includes a variable gain amplifier, the input end of the variable gain amplifier is used to access the input signal, and the output end of the variable gain amplifier is connected to the input end of the signal processing path;

[0059] Optionally, refer to Figure 3 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 2 In the embodiment shown, obtaining the original signal and the error signal includes steps S110-S120, wherein:

[0060] S110, setting the voltage of the input signal as a reference voltage to obtain an original signal;

[0061] S120 , inputting the input voltage of the signal input terminal to the variable gain amplifier for preprocessing to generate a corresponding error signal.

[0062] In this embodiment, the gain of the variable gain amplifier can be dynamically adjusted according to the strength of the input signal to ensure the stability and accuracy of the signal during transmission. In this way, the signal strength changes caused by line loss or signal attenuation can be compensated, thereby improving the performance of the overall signal processing.

[0063] Among them, the gain adjustment of the variable gain amplifier can be completed by the automatic gain control (AGC) circuit, which can automatically adjust the gain according to the real-time state of the signal to improve the adaptability and robustness of signal processing and ensure the stable performance of the high-speed DRAM interface under various working conditions.

[0064] Among them, in the offset calibration mode, the two input terminals of the variable gain amplifier (VGA) are set to the reference voltage VREF, one is the input terminal of the signal to be amplified, and the other is the input terminal of the reference voltage, both are set to the reference voltage VREF to provide the same input to the two paths. The signal from the VGA to the sampler runs in a differential manner, thereby achieving accurate comparison and calibration of the signal.

[0065] It should be understood that the offset control logic includes a detection circuit and a counter;

[0066] Optionally, refer to Figure 4 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 2 In the embodiment shown, determining the offset adjustment direction corresponding to the sampling result by the offset control logic is specifically step S310, wherein:

[0067] S310, detecting the level state of the sampling result through a detection circuit, and outputting a corresponding control signal to a counter, so that the counter performs offset adjustment according to the control signal.

[0068] In this embodiment, the detection circuit may be a comparator for comparing the sampling result with a preset threshold level. When the sampling result exceeds the threshold, the comparator outputs a high level signal; otherwise, it outputs a low level signal. The counter counts according to the output signal of the comparator to determine the direction in which the DFE adder output signal needs to be adjusted. Through the counting result of the counter, the DFE adder output signal can be gradually fine-tuned until the optimal offset calibration state is reached.

[0069] Among them, the counting direction and step size of the counter can be adjusted according to the actual application requirements to adapt to different signal processing environments and requirements. For example, if the counting direction of the counter is positive, it means that the level of the positive signal output by the DFE adder needs to be increased, and if the counting direction of the counter is negative, it means that the level of the negative signal output by the DFE adder needs to be reduced. In this way, the offset of the signal can be accurately controlled to ensure the accuracy and stability of the high-speed DRAM interface during data transmission.

[0070] Optionally, refer to Figure 5 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 4 In the embodiment shown, the detection circuit detects the level state of the sampling result and outputs a corresponding control signal to the counter, so that the counter performs offset adjustment according to the control signal, including steps S311-S312, wherein:

[0071] S311, if the output sampling result is a high level, output a low level signal to the counter to control the offset adjustment to decrease;

[0072] S312: If the output sampling result is a low level, a high level signal is output to the counter to control the offset adjustment to increase.

[0073] In this embodiment, the output signal of the detection circuit is opposite to the counting direction of the counter, which ensures that the offset of the signal can be effectively adjusted during the offset calibration process. For example, when the detection circuit detects that the sampling result is a high level, it means that the output signal of the DFE adder is too high and the offset needs to be reduced. Therefore, the counter will reduce the count after receiving a low level signal, and vice versa. In this way, the counter can dynamically adjust the output signal of the DFE adder according to the level state of the sampling result to achieve accurate offset calibration. Finally, when the sampling result stably switches between high and low levels, it indicates that the offset calibration has been completed, and the signal offset in the signal processing path of the high-speed DRAM interface has been effectively calibrated, thereby ensuring the accuracy and stability of data transmission.

[0074] Optionally, refer to Figure 6 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 5 In the embodiment shown, if the output sampling result is a high level, a low level signal is output to the counter to control the offset adjustment reduction, including step S3111, wherein:

[0075] S3111. If the output sampling result is a high level, the control signal outputs a low level to control the counter to decrease, so as to control the offset adjustment to decrease.

[0076] In this embodiment, the counter can be increased or decreased according to the level state of the sampling result to dynamically adjust the output signal of the DFE adder to achieve accurate offset calibration. Finally, when the sampling result stably switches between the high level and the low level, it indicates that the offset calibration has been completed, and the signal offset in the signal processing path of the high-speed DRAM interface has been effectively calibrated, thereby ensuring the accuracy and stability of data transmission.

[0077] Optionally, refer to Figure 7 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 5 In the embodiment shown, if the output sampling result is a low level, a high level signal is output to the counter to control the offset adjustment to increase the step S3121, wherein:

[0078] S3121. If the output sampling result is a low level, the control signal outputs a high level to control the counter to increase, so as to control the offset adjustment to increase.

[0079] In this embodiment, the counter can be increased or decreased according to the level state of the sampling result to dynamically adjust the output signal of the DFE adder to achieve accurate offset calibration. Finally, when the sampling result stably switches between the high level and the low level, it indicates that the offset calibration has been completed, and the signal offset in the signal processing path of the high-speed DRAM interface has been effectively calibrated, thereby ensuring the accuracy and stability of data transmission.

[0080] Optionally, refer to Figure 8 Another embodiment of the present invention provides a signal offset calibration method based on the above Figure 2 In the embodiment shown, adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the signal output by the sampler changes specifically includes steps S320-S340, wherein:

[0081] S320, if the offset adjustment direction is offset adjustment increase, adjust the negative signal path;

[0082] S330, if the offset adjustment direction is offset adjustment reduction, adjusting the forward signal path;

[0083] S340, repeatedly adjusting the negative signal path and the positive signal path until the level state of the signal output by the sampler changes, determining that the calibration is completed, and the sampler outputs a square wave of a preset frequency.

[0084] In this embodiment, by specifically controlling the offset adjustment direction, fine adjustment of the DFE adder output signal can be achieved. When the signal output by the sampler stably outputs '1010' or '0101' or switches between the two, it means that the signal offset calibration has achieved the expected effect, thereby ensuring the accuracy and stability of the high-speed DRAM interface during data transmission. In this way, the offset problem that may occur in the high-speed transmission process of the signal can be effectively solved, and the performance and reliability of the overall system can be improved.

[0085] The present invention also proposes a calibration device, which includes: the calibration device includes: a memory, a processor, and a signal offset calibration program stored in the memory and executable on the processor, the signal offset calibration program being configured to implement the above signal offset calibration method.

[0086] It is worth noting that since the calibration device of the present invention is based on the above-mentioned signal offset calibration method, the embodiments of the calibration device of the present invention include all technical solutions of all embodiments of the above-mentioned signal offset calibration method, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0087] The present invention also provides a high-speed DRAM interface, which includes the calibration device as described in the above embodiment.

[0088] It is worth noting that since the high-speed DRAM interface of the present invention is based on the above-mentioned calibration device, the embodiments of the high-speed DRAM interface of the present invention include all technical solutions of all embodiments of the above-mentioned calibration device, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0089] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0090] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, including a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0092] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A signal offset calibration method, applied to a high-speed DRAM interface, wherein the high-speed DRAM interface comprises at least one signal processing path, any signal processing path comprises a DFE adder, a sampler and an offset control logic electrically connected to each other, characterized in that: The signal offset calibration method comprises: Obtaining original signal and error signal; The original signal and the error signal are added by a DFE adder, and output to the sampler for sampling to output a corresponding sampling result; Determining an offset adjustment direction corresponding to the sampling result through an offset control logic, and adjusting a signal output by a DFE adder according to the offset adjustment direction until a level state of the signal output by the sampler changes; In the offset calibration mode, if the sampling result is '1', the output of the offset control logic is '0', and the OUT_DFE_P path of the DFE adder is adjusted; if the sampling result is '0', the output of the offset control logic is '1', and the OUT_DFE_N path of the DFE adder is adjusted; once the offset calibration is completed, the sampling result switches between '1010' or '0101'.

2. The signal offset calibration method according to claim 1, wherein: The high-speed DRAM interface further includes a variable gain amplifier, the input end of the variable gain amplifier is used to receive an input signal, and the output end of the variable gain amplifier is connected to the input end of the signal processing path; The obtaining of the original signal and the error signal comprises: Setting the voltage of the input signal as a reference voltage to obtain the original signal; The input voltage at the signal input terminal is input to the variable gain amplifier for preprocessing to generate a corresponding error signal.

3. The signal offset calibration method according to claim 1, wherein: The offset control logic includes a detection circuit and a counter; The offset adjustment direction corresponding to the sampling result is determined by the offset control logic as follows: The level state of the sampling result is detected by a detection circuit, and a corresponding control signal is output to the counter, so that the counter performs offset adjustment according to the control signal.

4. The signal offset calibration method according to claim 3, characterized in that: The detecting circuit detects the level state of the sampling result and outputs a corresponding control signal to the counter so that the counter performs offset adjustment according to the control signal, including: If the output sampling result is a high level, a low level signal is output to the counter to control the offset adjustment to decrease; If the output sampling result is a low level, a high level signal is output to the counter to control the offset adjustment to increase.

5. The signal offset calibration method according to claim 4, characterized in that: If the sampling result output is a high level, outputting a low level signal to the counter to control the offset adjustment reduction includes: If the sampling result output is a high level, the control signal outputs a low level to control the counter to decrease, so as to control the offset adjustment to decrease.

6. The signal offset calibration method according to claim 4, characterized in that: If the sampling result output is a low level, outputting a high level signal to the counter to control the offset adjustment to increase includes: If the output sampling result is a low level, the control signal outputs a high level to control the counter to increment, so as to control the offset adjustment to increase.

7. The signal offset calibration method according to claim 1, wherein: The step of adjusting the signal output by the DFE adder according to the offset adjustment direction until the level state of the signal output by the sampler changes is specifically: If the offset adjustment direction is offset adjustment increase, adjusting the negative signal path; If the offset adjustment direction is offset adjustment reduction, adjusting the forward signal path; The negative signal path and the positive signal path are repeatedly adjusted until the level state of the signal output by the sampler changes, and it is determined that the calibration is completed, and the sampler outputs a square wave of a preset frequency.

8. A calibration device, characterized in that: The calibration device comprises: a memory, a processor, and a signal offset calibration program stored in the memory and executable on the processor, wherein the signal offset calibration program is configured to implement the signal offset calibration method according to any one of claims 1 to 7.

9. A high-speed DRAM interface, characterized in that: Comprising a calibration device as claimed in claim 8.

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