A high-reliability MBUS host device and a working method thereof

Abstract

The application belongs to the field of communication and provides a high-reliability MBUS host terminal device and a working method thereof, which comprises a host terminal receiving circuit and a host terminal overload protection circuit; the host terminal receiving circuit is connected by a first receiving branch and a second receiving branch; the input end of the first receiving branch is connected to an MBUS-signal end; the input end of the first receiving branch is also connected to a first operational amplifier; the output end of the first operational amplifier is connected to a second operational amplifier of the second receiving branch and an operational comparator; the second receiving branch comprises the second operational amplifier and the operational comparator connected in sequence; the output end of the second operational amplifier is connected to the operational comparator through two parallel branches; the first parallel branch is a reverse diode connected in series with a resistor; and the second parallel branch is a forward diode connected in series with a resistor. By connecting a pair of diodes in parallel, the voltage difference between the voltage after the capacitor integration and the original voltage value is effectively limited.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a highly reliable MBUS host device and its operating method. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] MBUS, as a master-slave communication technology for data exchange between intelligent instruments and data acquisition devices, features strong anti-interference capabilities, long communication distances, and flexible power supply options, and is widely used in data acquisition for various intelligent instruments. However, existing MBUS master circuits typically suffer from drawbacks such as complex and redundant circuitry, fragile and slow overload response, incomplete protection functions, poor communication rate compatibility, and low meter reading success rates, making equipment selection, installation, and maintenance extremely complex. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a highly reliable MBUS master-side device and its operating method. This invention provides a master-side MBUS circuit that is simple and reliable in structure, comprehensive and flexible in function, sensitive and complete in protection, and has good compatibility with slave devices. The overload detection and protection circuit adopts a direct connection structure of precision operational amplifiers and relays, ensuring accurate judgment, rapid response, and reliable disconnection, thus preventing equipment damage. The MBUS transceiver circuit has no capacitor charging / discharging timing circuit, providing good compatibility with various communication rates. The microcontroller control circuit, through its ingenious structure, has control over all the above circuits, making the device's functions flexible and efficient.

[0005] According to some embodiments, the first aspect of the present invention provides a highly reliable MBUS host device, employing the following technical solution:

[0006] A highly reliable MBUS host device includes a host receiving circuit and a host overload protection circuit.

[0007] The host-side receiving circuit consists of a first receiving branch and a second receiving branch connected together. The input terminal of the first receiving branch is connected to the MBUS- signal terminal, and the input terminal of the first receiving branch is also connected to a first operational amplifier. The output terminal of the first operational amplifier is connected to the second operational amplifier and the operational comparator of the second receiving branch respectively. The second receiving branch includes a second operational amplifier and an operational comparator connected in sequence. The output terminal of the second operational amplifier is connected to the operational comparator through two parallel branches. The first parallel branch is a reverse diode and a resistor connected in series, and the second parallel branch is a forward diode and a resistor connected in series.

[0008] The input terminal of the overload protection circuit is also connected to the MBUS- signal terminal, which is connected to the +IN / B pin of the hysteresis comparator through an input resistor. The input resistor is also connected in parallel with a recovery circuit. The positive voltage is connected to the -IN / B pin of the hysteresis comparator through a positive resistor for comparison with the input level of the MBUS- signal terminal. The output terminal of the overload protection circuit is connected to a microprocessor to provide an alarm for overload of the MBUS- signal terminal.

[0009] Furthermore, the input terminal of the first receiving branch is connected to ground through two low-impedance resistors, and the two low-impedance branches are also connected in parallel with a first tantalum capacitor; one end of the first tantalum capacitor is grounded, and the other end of the first tantalum capacitor is connected to a second resistor, the second resistor is connected in parallel with the first resistor, the first resistor is connected to the OUT / A pin of the first operational amplifier; the second resistor is also connected to the -IN / A pin of the first operational amplifier; the output terminal INPUT1 of the first operational amplifier is also connected between the first resistor and the OUT / A pin of the first operational amplifier.

[0010] Furthermore, the OUT / A pin of the first operational amplifier is also grounded through the first capacitor;

[0011] The +IN / A pin of the first operational amplifier is connected to a +1.5V voltage via a fourth resistor, the +VS pin of the first operational amplifier is connected to a +24V voltage, and the -VS pin of the first operational amplifier is grounded.

[0012] Furthermore, the output of the first operational amplifier is connected to the +IN / A pin of the second operational amplifier through a fifth resistor, and the OUT / A pin of the second operational amplifier outputs SIGNAL1 to the parallel branch;

[0013] The +VS pin of the second operational amplifier is connected to a +24V voltage, and the -VS pin of the second operational amplifier is grounded.

[0014] Furthermore, the output of the first operational amplifier is connected to the 1IN+ pin of the operational comparator, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator; the two parallel branches are grounded through a tenth resistor, and the tenth resistor is also connected in parallel with a second tantalum capacitor, one end of the second tantalum capacitor is grounded, and the other end of the second tantalum capacitor is connected to the 1IN- pin of the operational comparator.

[0015] Furthermore, the 1OUT pin of the operational comparator is connected to a +3.3V voltage through a seventh resistor, and the 1OUT pin of the operational comparator is also grounded through a second capacitor.

[0016] Furthermore, the OUT / B pin of the hysteresis comparator is connected to the transistor of the operational amplifier branch through an output resistor; the +IN / B pin of the hysteresis comparator is also connected between the OUT / B pin of the hysteresis comparator and the output resistor through a signal resistor.

[0017] Furthermore, in the operational amplifier branch, the collector of the transistor is connected to the microprocessor; the base of the transistor is connected to the output resistor; and the emitter of the transistor is grounded.

[0018] According to some embodiments, the second aspect of the present invention provides a method for operating a highly reliable MBUS host device, employing the following technical solution:

[0019] A method for operating a highly reliable MBUS host device includes:

[0020] The MBUS- signal terminal is connected to the input terminal of the first receiving branch. The first receiving branch amplifies the voltage signal of the MBUS- signal terminal to obtain the first input signal that is finally compared.

[0021] The first input signal is also connected to the input terminal of the second operational amplifier in the second receiving branch. The second operational amplifier generates a follower signal with the same potential as the input signal. The follower signal passes through two parallel branches to form the second input signal that is finally compared. The first input signal and the second input signal are input to the operational comparator. After the operational comparator judges, the output level is determined.

[0022] The MBUS- signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit uses a hysteresis comparator to determine whether the voltage signal at the MBUS- signal terminal is higher than the threshold. If it is higher than the threshold, it sends a signal higher than the threshold to the microprocessor to trigger an alarm.

[0023] Furthermore, the first input signal and the second input signal are input to the operational comparator. After the operational comparator makes its judgment, the output level is determined, specifically as follows:

[0024] When the MBUS bus is in a silent state, the MBUS- signal level remains stable, and the first input signal formed after passing through the first receiving branch also remains stable. The second input signal formed after passing through the first receiving branch will undergo a charging process, and the level will rise. As the silent state time increases, the level of the second input signal also tends to stabilize. Due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal. At this time, the output of the operational comparator is high.

[0025] When the MBUS bus signal switches from "0" to "1", the voltage at the MBUS- signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, its level being lower than the second input signal. At this time, the output of the operational comparator is low.

[0026] When the MBUS bus signal switches from "1" to "0", the voltage at the MBUS- signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, with its level being higher than that of the second input signal. At this time, the output of the operational comparator is high.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] In this invention, the receiving circuit effectively limits the voltage difference between the voltage after capacitor integration and the original voltage value by connecting a pair of diodes in parallel in the bypass circuit; the master-side overload protection circuit can automatically detect, disconnect, and restore slave overloads. The circuit structure of this invention is simple, reliable, stable, and efficient. The overload detection and protection circuit adopts a direct connection structure of precision operational amplifiers and relays, ensuring accurate judgment, rapid response, and reliable disconnection, thus preventing equipment damage; the MBUS transceiver circuit has no capacitor charging / discharging timing circuit, providing good compatibility with various communication rates; the microcontroller control circuit, through its ingenious structure, has control over all the above circuits, making the equipment flexible and efficient.

[0029] The receiving circuit of this invention employs a structure of a pair of reverse diodes and a resistor connected in parallel, one circuit being responsible for charging the capacitor and the other for discharging it. Because the diodes themselves have a voltage drop, the voltage on the capacitor will always lag behind the output voltage of the current receiving amplifier circuit, regardless of the charging and discharging time, as it cannot be fully charged or discharged. This simplifies the selection of resistor and capacitor values. The entire circuit has no capacitor charging and discharging timing circuit, making it highly adaptable to different baud rates and exhibiting high reliability and stability.

[0030] The overload judgment circuit of this invention, composed of a hysteresis comparator, directly controls the overload power-off relay through a diode amplifier circuit, resulting in fast response and reliable protection. After the overload fault is cleared, the overload judgment circuit can be automatically reset by direct control of the microcontroller. At the same time, the microcontroller also has the function of forcing the judgment circuit to enter the overload state and then forcibly cutting off the power. Attached Figure Description

[0031] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0032] Figure 1 This is a schematic diagram of the first receiving circuit of the host-side receiving circuit in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the second receiving circuit of the host-side receiving circuit in an embodiment of the present invention;

[0034] Figure 3 This is a diagram showing the relationship between the first received signal and the second received signal in an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the host-side overload protection circuit in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the microprocessor control circuit in an embodiment of the present invention. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0039] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0040] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0041] Example 1

[0042] This embodiment provides a highly reliable MBUS host device, which includes a host receiving circuit and a host overload protection circuit.

[0043] The host-side receiving circuit consists of a first receiving branch and a second receiving branch connected together. The input terminal of the first receiving branch is connected to the MBUS- signal terminal, and the input terminal of the first receiving branch is also connected to the first operational amplifier U1. The output terminal of the first operational amplifier U1 is connected to the second operational amplifier U2 and the operational comparator U3 of the second receiving branch respectively. The second receiving branch includes the second operational amplifier U2 and the operational comparator U3 connected in sequence. The output terminal of the second operational amplifier U2 is connected to the operational comparator U3 through two parallel branches. The first parallel branch is a reverse diode D1 connected in series with a resistor R8, and the second parallel branch is a forward diode D2 connected in series with a resistor R9.

[0044] The input terminal of the overload protection circuit is also connected to the MBUS- signal terminal, which is connected to the +IN / B pin of the hysteresis comparator U4 through an input resistor R16. The input resistor R16 is also connected in parallel with a recovery circuit OLD RST. The positive voltage +3.3V is connected to the -IN / B pin of the hysteresis comparator U4 through a positive resistor R14 to generate a reference level for comparison with the input level of the MBUS- signal terminal. The output terminal of the overload protection circuit is connected to the microprocessor U5 to provide an alarm for overload of the MBUS- signal terminal.

[0045] It should be noted that the reason for setting the OLD RST for the recovery circuit is as follows: 1. During the power-up process, the +IN / B and -IN / B input levels of U4 are prone to instability, leading to false overload signal triggering. Therefore, during the power-up phase, the microprocessor U5 forcibly pulls the +IN / B signal low, releasing it only after the operating state stabilizes. 2. When the MBUS- signal is reset, i.e., the current is zero, the voltage generated on the +IN / B pin of U4 minus the voltage on the -IN / B pin is less than the reset threshold voltage of U4, and this overload signal does not reset automatically. To reset the hysteresis comparator, the microprocessor U5 needs to forcibly pull the +IN / B signal low.

[0046] like Figure 1 As shown, the input terminal of the first receiving branch is connected to ground through two low-impedance resistors R3 and R6. The two low-impedance branches are also connected in parallel with a first tantalum capacitor CT1. One end of the first tantalum capacitor CT1 is grounded, and the other end of the first tantalum capacitor CT1 is connected to a second resistor R2. The second resistor R2 is connected in parallel with the first resistor R1. The first resistor R1 is connected to the OUT / A pin of the first operational amplifier U1. The second resistor R2 is also connected to the -IN / A pin of the first operational amplifier U1. The output terminal INPUT1 of the first operational amplifier U1 is also connected between the first resistor R1 and the OUT / A pin of the first operational amplifier U1.

[0047] The OUT / A pin of the first operational amplifier U1 is also grounded through the first capacitor C1;

[0048] The +IN / A pin of the first operational amplifier U1 is connected to a +1.5V voltage through a fourth resistor R4, the +VS pin of the first operational amplifier U1 is connected to a +24V voltage, and the -VS pin of the first operational amplifier U1 is grounded.

[0049] like Figure 2 As shown, the output terminal INPUT1 of the first operational amplifier U1 is connected to the +IN / A pin of the second operational amplifier U2 through the fifth resistor R5, and the OUT / A pin of the second operational amplifier U2 outputs SIGNAL1 to the parallel branch;

[0050] The +VS pin of the second operational amplifier U2 is connected to a +24V voltage, and the -VS pin of the second operational amplifier U2 is grounded.

[0051] The output terminal INPUT1 of the first operational amplifier U1 is connected to the 1IN+ pin of the operational comparator U3, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator U3. The two parallel branches are grounded through the tenth resistor R10. The tenth resistor R10 is also connected in parallel with the second tantalum capacitor CT2. One end of the second tantalum capacitor CT2 is grounded, and the other end of the second tantalum capacitor CT2 is connected to the 1IN- pin of the operational comparator U3.

[0052] It should be noted that the value of the second tantalum capacitor CT2 is generally selected from 2.2uF to 22uF.

[0053] The 1OUT pin of the operational comparator U3 is connected to a +3.3V voltage through the seventh resistor R7, and the 1OUT pin of the operational comparator U3 is also grounded through the second capacitor C2.

[0054] U3 is a 2-channel comparator. This schematic only uses one channel. The principle is to compare the levels of 1IN+ and 1IN-. If the level of 1IN+ is higher than the level of 1IN-, a high level is output on the 1OUT pin, and vice versa.

[0055] The input terminal of the second receiving branch is also the output terminal of the first receiving branch, namely the OUT / A pin of the first operational amplifier U1. The input terminal of the second receiving circuit is connected to the +INA pin of the second operational amplifier U2. The -IN / A pin of the second operational amplifier U2 is connected to the OUT / A pin of the second operational amplifier U2 to form a follower, so that the level of the OUT / A pin follows the level of the +IN / A pin without affecting the level of the +IN / A pin. The OUT / A pin of the second operational amplifier U2 is connected to a diode and resistor circuit structure in parallel with the two branches.

[0056] The 1IN+ pin of the second operational amplifier U2 is connected to the output terminal INPUT1 of the first receiving branch, and the 1IN- pin of the operational comparator U3 is connected to the output terminal of the two parallel branches.

[0057] like Figure 4 , Figure 5 As shown, the OUT / B pin of the hysteresis comparator U4 is connected to the transistor Q1 of the operational amplifier branch through the output resistor R12; the +IN / B pin of the hysteresis comparator U4 is also connected between the OUT / B pin of the hysteresis comparator U4 and the output resistor R12 through the signal resistor R13.

[0058] In the operational amplifier branch, the collector 3 of transistor Q1 is connected to the microprocessor; the base 1 of transistor Q1 is connected to the output resistor R12; the emitter 2 of transistor Q1 is grounded; and the grounding resistor R15 is connected to the positive resistor R14.

[0059] The overload protection circuit includes U4, R12, R13, R15, and R16. The difference between the hysteresis comparator U4 and a regular comparator is that a regular comparator, when comparing two positive and negative input levels, will immediately change its output when the magnitude of the input levels changes. This can lead to unstable output levels, fluctuating between high and low, when the input levels are similar. The hysteresis comparator, on the other hand, incorporates a threshold design for the input level difference. The output only changes when the difference exceeds the threshold, thus preventing output instability.

[0060] After MBUS is powered on, all current flows through the low-impedance path R3-R6, generating an input voltage signal. This voltage signal is then amplified in reverse by operational amplifier U1 (the factor is determined by R1 and R2) to generate the first received signal INPUT1. U2 acts as a follower, with its output completely identical to INPUT1, ensuring no interference with the INPUT1 level. The follower's output uses a pair of reverse diodes connected in parallel with a resistor, one circuit charging the capacitor and the other discharging it to generate the INPUT2 signal. Because the diodes themselves have a voltage drop, the capacitor will never be fully charged or discharged, regardless of the charging / discharging time. Therefore, the INPUT2 signal voltage always lags behind the INPUT1 signal voltage, simplifying the selection of resistor and capacitor values. The entire circuit lacks a capacitor-free charging / discharging timing circuit, making it highly adaptable to different baud rates and significantly improving reliability and stability.

[0061] The hysteresis comparator composed of operational amplifier U4 requires resistor parameters that ensure the following: when the MBUS- signal current is too high, the voltage at the +IN / B pin of U4 minus the voltage at the -IN / B pin is greater than the operating threshold voltage of U4; when the MBUS- signal is reset (i.e., the current is zero), the voltage at the +IN / B pin of U4 minus the voltage at the -IN / B pin is less than the reset threshold voltage of U4, ensuring that the overload signal does not automatically reset after the MBUS- signal is reset. To reset the hysteresis comparator, simply pull the voltage level at pin 5 of U4 (where the microprocessor is connected) to GND.

[0062] Example 2

[0063] This embodiment provides a method for operating a highly reliable MBUS host device, including:

[0064] The MBUS- signal terminal is connected to the input terminal of the first receiving branch. The first receiving branch amplifies the voltage signal of the MBUS- signal terminal to obtain the first input signal that is finally compared.

[0065] The first input signal is also connected to the input terminal of the second operational amplifier in the second receiving branch. The second operational amplifier generates a follower signal with the same potential as the input signal. The follower signal passes through two parallel branches to form the second input signal that is finally compared. The first input signal and the second input signal are input to the operational comparator. After the operational comparator judges, the output level is determined.

[0066] The MBUS- signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit uses a hysteresis comparator to determine whether the voltage signal at the MBUS- signal terminal is higher than the threshold. If it is higher than the threshold, it sends a signal higher than the threshold to the microprocessor to trigger an alarm.

[0067] like Figure 3As shown, the first and second input signals are input to the operational comparator. After the operational comparator makes its judgment, the output level is determined, specifically as follows:

[0068] When the MBUS bus is in a silent state, the MBUS- signal level remains stable, and the first input signal formed after passing through the first receiving branch also remains stable. The second input signal formed after passing through the first receiving branch will undergo a charging process, and the level will rise. As the silent state time increases, the level of the second input signal also tends to stabilize. Due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal. At this time, the output of the operational comparator is high.

[0069] When the MBUS bus signal switches from "0" to "1", the voltage at the MBUS- signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, its level being lower than the second input signal. At this time, the output of the operational comparator is low.

[0070] When the MBUS bus signal switches from "1" to "0", the voltage at the MBUS- signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, with its level being higher than that of the second input signal. At this time, the output of the operational comparator is high.

[0071] It should be noted that the MBUS receive signal is characterized by representing data bits by changing the current on the MBUS bus, and the change is made by increasing the current of the bus, rather than generating a fixed current value. In the silent state, the MBUS bus maintains a stable bus current. When a receive signal is generated, if a data bit "1" is generated, the MBUS bus current is raised; if a data bit "0" is generated, the bus current returns to normal. This signal, when connected to the receiving circuit in Example 1, will generate different voltages at the MBUS- terminal.

[0072] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A highly reliable MBUS host device, characterized in that, This includes the host-side receiving circuit and the host-side overload protection circuit; The host-side receiving circuit consists of a first receiving branch and a second receiving branch connected together. The input terminal of the first receiving branch is connected to the MBUS- signal terminal, and the input terminal of the first receiving branch is also connected to a first operational amplifier. The output terminal of the first operational amplifier is connected to the second operational amplifier and the operational comparator of the second receiving branch respectively. The second receiving branch includes a second operational amplifier and an operational comparator connected in sequence. The output terminal of the second operational amplifier is connected to the operational comparator through two parallel branches. The first parallel branch is a reverse diode and a resistor connected in series, and the second parallel branch is a forward diode and a resistor connected in series. The input terminal of the overload protection circuit is also connected to the MBUS- signal terminal, which is connected to the +IN / B pin of the hysteresis comparator through an input resistor. The input resistor is also connected in parallel with a recovery circuit. The positive voltage is connected to the -IN / B pin of the hysteresis comparator through a positive resistor for comparison with the input level of the MBUS- signal terminal. The output terminal of the overload protection circuit is connected to a microprocessor to provide an alarm for overload of the MBUS- signal terminal.

2. The highly reliable MBUS host device as described in claim 1, characterized in that, The input terminal of the first receiving branch is connected to ground through two low-impedance resistors, and the two low-impedance branches are also connected in parallel with a first tantalum capacitor; one end of the first tantalum capacitor is grounded, and the other end of the first tantalum capacitor is connected to a second resistor, which is connected in parallel with the first resistor. The first resistor is connected to the OUT / A pin of the first operational amplifier; the second resistor is also connected to the -IN / A pin of the first operational amplifier; the output terminal INPUT1 of the first operational amplifier is also connected between the first resistor and the OUT / A pin of the first operational amplifier.

3. The highly reliable MBUS host device as described in claim 2, characterized in that, The OUT / A pin of the first operational amplifier is also grounded through the first capacitor; The +IN / A pin of the first operational amplifier is connected to a +1.5V voltage via a fourth resistor, the +VS pin of the first operational amplifier is connected to a +24V voltage, and the -VS pin of the first operational amplifier is grounded.

4. The highly reliable MBUS host device as described in claim 1, characterized in that, The output of the first operational amplifier is connected to the +IN / A pin of the second operational amplifier through the fifth resistor, and the OUT / A pin of the second operational amplifier outputs SIGNAL1 to the parallel branch; The +VS pin of the second operational amplifier is connected to a +24V voltage, and the -VS pin of the second operational amplifier is grounded.

5. The highly reliable MBUS host device as described in claim 1, characterized in that, The output of the first operational amplifier is connected to the 1IN+ pin of the operational comparator, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator. The two parallel branches are grounded through the tenth resistor, and the tenth resistor is also connected in parallel with a second tantalum capacitor. One end of the second tantalum capacitor is grounded, and the other end of the second tantalum capacitor is connected to the 1IN- pin of the operational comparator.

6. The highly reliable MBUS host device as described in claim 5, characterized in that, The 1OUT pin of the operational comparator is connected to a +3.3V voltage through a seventh resistor, and the 1OUT pin of the operational comparator is also grounded through a second capacitor.

7. The highly reliable MBUS host device as described in claim 1, characterized in that, The OUT / B pin of the hysteresis comparator is connected to the transistor of the operational amplifier branch through an output resistor; the +IN / B pin of the hysteresis comparator is also connected between the OUT / B pin of the hysteresis comparator and the output resistor through a signal resistor.

8. A highly reliable MBUS host device as described in claim 7, characterized in that, In the operational amplifier branch, the collector of the transistor is connected to the microprocessor; the base of the transistor is connected to the output resistor; and the emitter of the transistor is grounded.

9. A method for operating a highly reliable MBUS host device, characterized in that, The MBUS- signal terminal is connected to the input terminal of the first receiving branch. The first receiving branch amplifies the voltage signal of the MBUS- signal terminal to obtain the first input signal that is finally compared. The first input signal is also connected to the input terminal of the second operational amplifier in the second receiving branch. The second operational amplifier generates a follower signal with the same potential as the input signal. The follower signal passes through two parallel branches to form the second input signal that is finally compared. The first input signal and the second input signal are input to the operational comparator. After the operational comparator judges, the output level is determined. The MBUS- signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit uses a hysteresis comparator to determine whether the voltage signal at the MBUS- signal terminal is higher than the threshold. If it is higher than the threshold, it sends a signal higher than the threshold to the microprocessor to trigger an alarm.

10. The operating method of a highly reliable MBUS host device as described in claim 9, characterized in that, The first and second input signals are input to the operational comparator. After the operational comparator makes its judgment, the output level is determined, specifically as follows: When the MBUS bus is in a silent state, the MBUS- signal level remains stable, and the first input signal formed after passing through the first receiving branch also remains stable. The second input signal formed after passing through the first receiving branch will undergo a charging process, and the level will rise. As the silent state time increases, the level of the second input signal also tends to stabilize. Due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal. At this time, the output of the operational comparator is high. When the MBUS bus signal switches from "0" to "1", the voltage at the MBUS- signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, its level being lower than that of the second input signal. At this time, the output of the operational comparator is low. When the MBUS bus signal switches from "1" to "0", the voltage at the MBUS- signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, with its level being higher than that of the second input signal. At this time, the output of the operational comparator is high.

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