Port Fault Detection Method, Device, Equipment and Medium for FC Bus-Type Network

Abstract

The present invention relates to the technical field of high-speed serial data transmission, and provides a method, device, equipment and medium for detecting port faults in an FC bus-type network. The method includes: when a periodic pulse signal is generated in the FC bus-type network; detecting a port to be tested of the FC bus-type network through a port detection circuit to obtain a first comparison value and a second comparison value; performing an exclusive OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; and determining the fault type of the port to be tested based on the first comprehensive result. By performing an exclusive OR operation, the present invention obtains a unique comprehensive result, thereby improving the detection efficiency and reducing the detection complexity.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial data transmission, and particularly relates to a method, device, equipment and medium for detecting port faults of an FC bus-type network. Background Art

[0002] A high-speed (Fiber Channel, FC) bus-type network connects all nodes to a single bus, featuring easy implementation, low cost, flexible wiring, and good scalability. For an FC bus-type network, if there are states such as open circuit, short circuit, or grounding in the node ports, it will directly affect signal transmission.

[0003] In related detection methods, an analog circuit is used to directly give the test result. However, during testing, when the line is a medium short line, the echo signal of the far-end open circuit will overlap with the excitation signal, thereby changing the level of the test signal, making the output level the same as that of other port conditions and indistinguishable. Therefore, in order to further distinguish, a secondary judgment is required, resulting in complex detection operations and low efficiency. Summary of the Invention

[0004] The present invention provides a method, device, equipment and medium for detecting port faults of an FC bus-type network, aiming to solve the defect in the prior art that a secondary judgment is required due to the overlap of the echo signal of the far-end open circuit with the excitation signal, and to achieve a unique comprehensive result through exclusive OR processing, thereby improving the detection efficiency and reducing the detection complexity.

[0005] The present invention provides a method for detecting port faults of an FC bus-type network, including:

[0006] When a periodic pulse signal is generated in the FC bus-type network; detecting the port to be tested of the FC bus-type network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the port to be tested when it is at a first level and at least one first reference level of the port to be tested, and the second comparison value is used to represent the comparison result between the port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times;

[0007] Performing exclusive OR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result;

[0008] Determining the fault type of the port to be tested based on the first comprehensive result.

[0009] A method for detecting port faults in an FC bus - type network provided by the present invention. Based on the first comprehensive result, determining the fault type of the port of the node to be measured includes: when the first comprehensive result is the first preset result, detecting the port of the node to be measured in the FC bus - type network through a pulse counter, and obtaining the pulse value measured by the pulse counter by the pulse counter; the first preset result is used to represent the output result detected by the port detection circuit; when the pulse value is the preset pulse value, determining that the fault type of the port of the node to be measured is normal; when the pulse value is not the preset pulse value, determining that the fault type of the port of the node to be measured is remote open - circuit.

[0010] A method for detecting port faults in an FC bus - type network provided by the present invention. Based on the first comprehensive result, determining the fault type of the port of the node to be measured includes: when the first comprehensive result is the second preset result, determining that the fault type of the port of the node to be measured is remote open - circuit; the second preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the third preset result, determining that the fault type of the port of the node to be measured is proximal open - circuit; the third preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the fourth preset result, determining that the fault type of the port of the node to be measured is remote short - circuit; the fourth preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the fifth preset result, determining that the fault type of the port of the node to be measured is proximal short - circuit; the fifth preset result is used to represent the output result detected by the port detection circuit. The first preset result, the second preset result, the third preset result, the fourth preset result, and the fifth preset result are all different output results, and different output results respectively correspond to different fault types.

[0011] A method for detecting port faults in an FC bus - type network provided by the present invention, wherein the port to be tested includes at least two ports to be tested, and the proximal short - circuit includes proximal mutual short - circuit and floating and proximal mutual short - circuit to ground; determining that the fault type of the port to be tested is a proximal short - circuit includes: controlling the output circuit of the FC bus - type network to be single - tube effective, detecting the closed port to be tested through the port detection circuit to obtain a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed port to be tested at the third level and each of the first reference levels, and the fourth comparison value is used to represent the comparison result between the closed port to be tested at the fourth level and each of the first reference levels, where the third level and the fourth level are levels at different times; based on the port detection circuit, performing an exclusive - OR operation on the third comparison value and the fourth comparison value to obtain a second comprehensive result; in the case where the second comprehensive result is the first preset result, determining that the fault type of the port to be tested is proximal mutual short - circuit and floating; in the case where the second comprehensive result is the fifth preset result, determining that the fault type of the port to be tested is proximal mutual short - circuit to ground.

[0012] A method for detecting port faults of an FC bus - type network provided by the present invention, wherein the port to be tested includes at least two ports to be tested. The remote short - circuit includes: remote mutual short - circuit and floating, remote mutual short - circuit to one end of the termination, remote mutual short - circuit to both ends of the termination, and remote mutual short - circuit to ground. Determining that the fault type of the port to be tested is a remote short - circuit includes: controlling the output circuit of the FC bus - type network to be single - tube effective, detecting the closed port to be tested through the port detection circuit to obtain a fifth comparison value and a sixth comparison value. The fifth comparison value is used to represent the comparison result between the closed port to be tested at the fifth level and each of the first reference levels, and the sixth comparison value is used to represent the comparison result between the closed port to be tested at the sixth level and each of the first reference levels. The fifth level and the sixth level are levels at different times. Based on the port detection circuit, an exclusive - OR operation is performed on the fifth comparison value and the sixth comparison value to obtain a third comprehensive result. When the third comprehensive result is the first preset result, it is determined that the fault type of the port to be tested is remote mutual short - circuit and floating. When the third comprehensive result is the sixth preset result, it is determined that the fault type of the port to be tested is remote mutual short - circuit to one end of the termination. The sixth preset result is used to represent the output result of the port detection circuit. When the third comprehensive result is the seventh preset result, it is determined that the fault type of the port to be tested is remote mutual short - circuit to both ends of the termination. The seventh preset result is used to represent the output result of the port detection circuit. Both the sixth preset result and the seventh preset result are output results different from the first preset result, the second preset result, the third preset result, the fourth preset result, and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types. When the third comprehensive result is the fifth preset result, it is determined that the fault type of the port to be tested is remote mutual short - circuit to ground.

[0013] A method for detecting port faults of an FC bus - type network provided by the present invention, wherein the port detection circuit is formed by paralleling at least one comparator. The positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminals of the comparators are connected to an exclusive - OR processing unit. Each value in the first comparison value corresponds to a comparator one - to - one, and each value in the second comparison value corresponds to a comparator one - to - one. The step of performing an exclusive - OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result includes: performing an exclusive - OR operation on each value in the first comparison value corresponding to the same comparator and each value in the second comparison value to obtain a first comprehensive result.

[0014] A method for detecting port faults in an FC bus - type network provided by the present invention, the pulse counter includes: at least one inverter and at least one flip - flop. The inverters are connected in series in sequence, and the inverter at the end of the series is respectively connected to each of the flip - flops. Detecting a port to be measured of the FC bus - type network through the pulse counter, and obtaining the pulse value measured by the pulse counter by the pulse counter, including: inputting an input signal into the inverter at the first position through the pulse counter, adjusting the edge of the input signal and the level waveform of the input signal to obtain a target signal; the input signal is obtained based on the periodic pulse signal; performing pulse counting on the target signal based on the flip - flop to obtain the pulse value.

[0015] The present invention also provides a device for detecting port faults in an FC bus - type network, including:

[0016] An acquisition module, configured to, when a periodic pulse signal is generated in the FC bus - type network; detect a port to be measured of the FC bus - type network through a port detection circuit, and obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the port to be measured when it is at a first level and at least one first reference level of the port to be measured, and the second comparison value is used to represent the comparison result between the port to be measured when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times;

[0017] A processing module, configured to perform an exclusive - OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result;

[0018] A determination module, configured to determine the fault type of the port to be measured based on the first comprehensive result.

[0019] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the method for detecting port faults in an FC bus - type network as described in any one of the above.

[0020] The present invention also provides a non - transitory computer - readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the method for detecting port faults in an FC bus - type network as described in any one of the above.

[0021] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the method for detecting port faults in an FC bus - type network as described in any one of the above.

[0022] The port fault detection method, device, equipment and medium of the FC bus-type network provided by the present invention, when a periodic pulse signal is generated in the FC bus-type network, uses a port detection circuit to detect the port of the node to be tested in the FC bus-type network, and obtains the comparison result (i.e., the first comparison value) between the port of the node to be tested when it is at the first level and at least one first reference level of the port of the node to be tested, and the comparison result (the second comparison value) between the port of the node to be tested when it is at the second level and the first reference level. The first level and the second level are levels at different times; the port detection circuit performs an exclusive OR operation on the first comparison value and the second comparison value to obtain a unique first comprehensive result, and thus uses the unique first comprehensive result to determine the fault type of the port of the node to be tested. In this way, the fault type of the port of the node to be tested can be directly judged using the unique first comprehensive result, without secondary judgment, improving the efficiency of fault detection and reducing the judgment complexity of fault detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 is one of the flow diagrams of the port fault detection method for the FC bus-type network provided by the present invention.

[0025] Figure 2 is a schematic diagram of the periodic pulse signal (Vi) provided by the present invention.

[0026] Figure 3 is a schematic diagram of the excitation signal (Vi_d) provided by the present invention.

[0027] Figure 4 is a schematic diagram of a test signal (Vin) provided by the present invention.

[0028] Figure 5 is a schematic diagram of the structure of the FC long-line bus-type network provided by the present invention.

[0029] Figure 6 is a schematic diagram of the structure of the port detection circuit provided by the present invention.

[0030] Figure 7A is a schematic diagram of the test waveform in the normal state provided by the present invention.

[0031] Figure 7B is a schematic diagram of the test waveform of the proximal open circuit provided by the present invention.

[0032] Figure 7C It is one of the schematic diagrams of the test waveform with an open circuit at the far end provided by the present invention.

[0033] Figure 7D It is one of the schematic diagrams of the test waveform with a short circuit at the far end provided by the present invention.

[0034] Figure 7E It is the schematic diagram of the test waveform with a short circuit at the near end provided by the present invention.

[0035] Figure 8A It is the second schematic diagram of the test waveform with an open circuit at the far end provided by the present invention.

[0036] Figure 8B It is the second schematic diagram of the test waveform with a short circuit at the far end provided by the present invention.

[0037] Figure 9 It is the schematic diagram of an output circuit of a serial interface transceiver provided by the present invention.

[0038] Figure 10 It is the schematic diagram of the structure of a pulse counter provided by the present invention.

[0039] Figure 11 It is the schematic diagram of a reset signal (Reset) provided by the present invention.

[0040] Figure 12A It is the second schematic diagram of the flow of the method for detecting port faults in an FC bus-type network provided by the present invention.

[0041] Figure 12B It is the third schematic diagram of the flow of the method for detecting port faults in an FC bus-type network provided by the present invention.

[0042] Figure 13 It is the schematic diagram of the structure of a port fault detection device for an FC bus-type network provided by the present invention.

[0043] Figure 14 It is the schematic diagram of the structure of an electronic device provided by the present invention.

[0044] Reference numerals:

[0045] 210: High-speed node; 220: First directional coupler; 230: Second directional coupler; 1001: First inverter; 1002: Second inverter; 1003: First D flip-flop; 1004: Second D flip-flop; 1005: Third inverter. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0047] Currently, the node ports of the FC bus network need to be detected. The traditional methods for node ports mainly include the following: One is manual detection, that is, when an error occurs during communication, an additional tester is used to perform open / short circuit detection, which is not only cumbersome but also inefficient; the other is online automatic detection: However, there are incomplete test items, such as short-to-short floating, short-to-short termination, and short-to-short grounding cannot be distinguished, resulting in the need for manual secondary analysis of the detection results.

[0048] With the development of technology, a method for detecting the near and far ports of a long-line high-speed bus node has been proposed, which directly gives the test result using an analog circuit. However, this method has the following deficiencies during testing: One is that when the line is a medium or short line, the echo signal of the open circuit at the far end will overlap with the excitation signal, thereby changing the level of the test signal, making the output level the same as that of other port conditions. Therefore, in order to further distinguish, a secondary judgment is still required; the other is that when the line is a long line, the echo signal of the open circuit at the far end does not overlap with the excitation signal. In order to distinguish it from the normal port condition, pulse number statistics are required at this time. The traditional method is to use an analog-to-digital converter (ADC) for sampling and then make a judgment in the digital domain, which additionally increases the ADC circuit, and the sampling period should be less than the pulse width of the excitation signal, otherwise the echo signal is easily missed. The power consumption of the ADC is positively correlated with the sampling frequency, so the circuit power consumption is increased.

[0049] Based on the above problems, the present invention provides a method for detecting port faults in an FC bus network, which can directly determine the fault type of the node port to be tested using a unique first comprehensive result, without the need for secondary judgment, improving the efficiency of fault detection and reducing the judgment complexity of fault detection.

[0050] The following combines Figure 1 - Figure 1 Figure 2 to describe the method for detecting port faults in the FC bus network of the present invention. The execution subject of this method can be an electronic device or a method for detecting port faults in the FC bus network provided in the electronic device. The detection of port faults in the FC bus network can be implemented through software, hardware, or a combination of both.

[0051] Figure 1 is one of the flow diagrams of the method for detecting port faults in the FC bus network provided by the present invention. As shown inFigure 1 As shown, the method includes the following:

[0052] Step 101: When a periodic pulse signal is generated in the FC bus network, detect the ports of the nodes to be tested in the FC bus network through a port detection circuit to obtain a first comparison value and a second comparison value;

[0053] Wherein, the first comparison value is used to represent the comparison result between at least one first reference level of the port to be tested when the port to be tested is at a first level, and the second comparison value is used to represent the comparison result between each first reference level when the port to be tested is at a second level; the first level and the second level are levels at different times.

[0054] Here, the number of port detection circuits can be two, and the ports of the nodes to be tested can also be two, such as a P port and an n port. Among them, one port detection circuit detects the P port, and the other port detection circuit detects the n port.

[0055] Exemplarily, Figure 2 is a schematic diagram of the periodic pulse signal (Vi) provided by the present invention, as Figure 2 shown, T0 is the period of the periodic pulse signal (Vi); T0 - T1 is the pulse width; T1 is the duration of the low level of the pulse. Here, in order to ensure that the delay duration Td of the return signal of the periodic pulse signal does not coincide with the next period signal T0, T0 can be made much larger than T1. For example, T0 is 10 times T1.

[0056] It should be noted that the periodic pulse signal is delayed to obtain an excitation signal.

[0057] Exemplarily, Figure 3 is a schematic diagram of the excitation signal (Vi_d) provided by the present invention, as Figure 3 shown, the excitation signal (Vi_d) is obtained by delaying the periodic pulse signal (Vi) by Td0 (Td0 > T1), and T1 is the pulse width of the excitation signal.

[0058] It should be noted that the first level and the second level can be the same or different.

[0059] It should be noted that if the first level or the second level is greater than the first reference level, the comparison result is 1; if the first level or the second level is less than the first reference level, the comparison result is 0. A comparison value includes multiple comparison results, and the number of comparison results is the same as the number of first reference levels. For example, if the comparison value is 01110, it means there are 5 reference levels.

[0060] Here, the first reference level can be a pre-set appropriate level. For example, the first reference level ref1 is Vref - 0.25×V0, the second reference level ref2 is Vref + v3, the third reference level ref3 is Vref + v2, the fourth reference level ref4 is Vref + v1, and the fifth reference level ref5 is Vref + 1.5×V0. Here, 0 < v3 < V03 < v2 < V02 < v1 < V01 < V0, and from ref1 to ref5, their corresponding values increase gradually.

[0061] It should be noted that the port detection circuit detects the port of the node to be tested, essentially by detecting the level of the test signal on the port of the node to be tested. The first level can be the high level on the test signal, and the second level can be the low level on the test signal. Among them, the test signal can be obtained after the serial interface transceiver processes the excitation signal.

[0062] Exemplarily, Figure 4 is a schematic diagram of a test signal (Vin) provided by the present invention. As Figure 4 shown, the low level of the test signal (Vin) is Vref (reference level), the high level is Vref + V0, V0 is the auxiliary voltage, T1 is the pulse width of the test signal, and Td is the delay of the test signal.

[0063] The first level and the second level can be adjacent levels. For example, the first level is the high level at the first moment, and the second level is the low level at the second moment.

[0064] Here, the exclusive - OR operation is a logical operation, where the result is 0 for the same values and 1 for different values.

[0065] Figure 5 is a schematic structural diagram of the FC long - line bus - type network provided by the present invention. As Figure 5 shown, the high - speed node 210 is connected to the first directional coupler 220 and the second directional coupler 230 through differential cables Lp / Ln, and finally accesses the differential bus - type network (corresponding to bus p and bus n in the figure). Among them, the high - speed node 210 uses time - division multiplexing, that is, the working type of the transceiver of the bus - type network (also known as the high - speed serial transceiver) is of the time - division multiplexing type. For the differential ports p / n, the reception is always connected, and the transmission is selected to be connected or disconnected according to the instruction through switches T11 / T12. For the high - speed serial transceiver, Figure 5Ports 7 and 8 among them are receiving ports, both with high input impedance. C11 / C12 isolate the input bias, and R11 / R12 are used for input matching. Ports 5 and 6 are for transmission, both with open-drain outputs. R11 / R12 are used for output matching. R11 and R12 are connected through VDD to supply power to ports 5 and 6. C13 / C14 are connected to ports p / n through blocking capacitors. Ports p / n are connected to the 3rd ports (coupling ports) of directional couplers D1 / D2 through differential cables Lp / Ln. C15 / C16 are connected to the signal terminals of R11 / R12 through blocking capacitors. Thus, C13 / C14 and C15 / C16 isolate DC for test points vp / vn. The DC of vp / vn is provided by Vref through bias resistors R15 / R16. C17 / C18 are connected to the signal 1 ports of pulse counter 1 / pulse counter 2 through blocking capacitors, and the other ends are connected to test points vp / vn. The DC of the signal 1 ports of pulse counter 1 / pulse counter 2 is provided by Vbias through bias resistors R17 / R18 to ensure that the signal is within the amplitude input range of the pulse counter. The signal 2 ports of pulse counter 1 / pulse counter 2 are recovery ports (reset). The signal 3 port of pulse counter 1 is the first clock pulse input port (Operation Pulse. OPP1). The signal 4 port of pulse counter 1 is the second clock pulse input port (Operation Pulse. OPP2). The signal 3 port of pulse counter 2 is the first enable port (onn1). The signal 4 port of pulse counter 2 is the second enable port (onn2). Tx_rp means that port 1 of the digital controller sends certain parameters, protocols or ports related to port 1 of the high-speed serial transceiver. Tx_rn means that port 2 of the digital controller sends certain devices, networks, protocols or functions related to port 2 of the high-speed serial transceiver. Rx_rp means that port 3 of the digital controller receives certain parameters, protocols or ports sent by port 3 of the high-speed serial transceiver. Tx_rn means that port 4 of the digital controller receives certain devices, networks, protocols or functions sent by port 4 of the high-speed serial transceiver. TX_P and TX_N mean that the high-speed serial transceiver sends signals to port detection circuit 1 and port detection circuit 2 through ports 5 and 6 respectively. RX_P and RX_N mean that the high-speed serial transceiver receives signals sent by port detection circuit 1 and port detection circuit 2 through ports 7 and 8 respectively. Op1 - op5 in port detection circuit 1 represent 5 clock pulse input ports. On1 - on5 in port detection circuit 2 represent 5 enable ports. Port p is the first port to be measured of the node. Port n is the first port to be measured of the node.

[0066] Step 102: Based on the port detection circuit, perform an exclusive OR operation on the first comparison value and the second comparison value to obtain a first comprehensive result.

[0067] It should be noted that the first comparison value and the second comparison value are obtained by a plurality of comparators in the port detection circuit, and the number of comparators corresponds one-to-one to the number of the first reference levels.

[0068] Exemplarily, the port detection circuit is obtained by paralleling at least one comparator. The positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminals of the comparators are connected to an exclusive-OR processing unit; each value in the first comparison value corresponds to one of the comparators, and each value in the second comparison value corresponds to one of the comparators; performing an exclusive-OR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result, including: performing an exclusive-OR process on each value in the first comparison value corresponding to the same comparator and each value in the second comparison value to obtain the first comprehensive result.

[0069] It should be noted that the first value and the second digital value obtained by each comparator need to be exclusive-ORed one by one. For example, if the first comparison value is 01110 and the second comparison value is 11100, the first comprehensive result after exclusive-OR is 10010.

[0070] Exemplarily, Figure 6 is a schematic structural diagram of the port detection circuit provided by the present invention. As Figure 6 shown, the port detection circuit includes five comparators. The negative terminals of the five comparators are respectively connected to levels ref1 / ref2 / ref3 / ref4 / ref5. Port 1 is a signal input terminal and is connected to the positive terminal of the comparator, that is, the signal input terminal. The outputs of comparators 1 / 2 / 3 / 4 / 5 are respectively output ports 2 / 3 / 4 / 5 / 6. The output terminals of comparators 1, 2, 3, 4, and 5 (corresponding to ports 2, 3, 4, 5, and 6 in the figure) are used to output comparison results. It should be noted that Vref can also flow into the detection circuit through R15. Among them, the first comparison value or the second comparison value of the detection circuit can be constituted by five potential values (i.e., numerical values) respectively output by ports 2, 3, 4, 5, and 6. Each comparator is respectively connected to a delay unit, and each delay unit is respectively connected to an exclusive-OR unit. The delay unit is used for each exclusive-OR unit to perform an exclusive-OR on the first comparison result and the second comparison result of the corresponding comparator to obtain the first comprehensive result.

[0071] Furthermore, Figure 5Two port detection circuits are shown, namely port detection circuit 1 and port detection circuit 2. The 1 port of port detection circuit 1 is connected to the common point of C13 and C15, and the 1 port of port detection circuit 2 is connected to the common point of C14 and C16.

[0072] In one embodiment, the matching circuit load resistors corresponding to the FC bus type network can be Figure 5 equal to R11, R12, R13, and R14 in

[0073] That is, R11 = R12 = R13 = R14 = R. In another embodiment, let V0 = R×I, where I is the current value of the tail current source M1. Taking the first reference levels of ref1 - ref5 above as an example, ref1 is Vref - 0.25×V0, ref2 is Vref + v3, ref3 is Vref + v2, ref4 is Vref + v1, and ref5 is Vref + 1.5×V0. The first comprehensive result of the port detection of the node to be measured is obtained through the port detection circuit as shown in Table 1:

[0074] Table 1

[0075]

[0076] In Table 1, the highest level of the port signal is the first level, and the first level is Vref + V0. Comparing Vref + V0 with ref1 - ref5 respectively, the first comparison value is 01111. The lowest level of the port signal is the second level, and the second level is Vref. Comparing Vref with ref1 - ref5 respectively, the second comparison value is 00001. Exclusive - ORing 01111 and 00001 gives the first comprehensive result 01110; when the first level is Vref + 2×V0, comparing Vref + 2×V0 with ref1 - ref5 respectively, the first comparison value is 11111, and the second level is Vref. Comparing Vref with ref1 - ref5 respectively, the second comparison value is 00001. Exclusive - ORing 11111 and 00001 gives the first comprehensive result 11110. Similarly, other first comprehensive results are also obtained by exclusive - ORing the first comparison value and the second comparison value.

[0077] Exemplarily, Figure 7A is a schematic diagram of the test waveform in the normal state provided by the present invention. As Figure 7A shown, T0 is the period of the normal - state level signal, Vref is the lowest level, Vref + V0 is the highest level, and there is one waveform within one period.

[0078] Figure 7B is a schematic diagram of the test waveform of the proximal open - circuit provided by the present invention. As Figure 7BAs shown, Vref is the lowest level and Vref + 2V0 is the highest level.

[0079] Figure 7C is one of the schematic diagrams of the test waveform with the far - end open - circuited provided by the present invention. As Figure 7C shown, Vref is the lowest level, Vref + V0 is the highest level, and there are two waveforms within one period.

[0080] Figure 7D is one of the schematic diagrams of the test waveform with the far - end short - circuited provided by the present invention. As Figure 7D shown, Vref + V0 is the highest level, Vref is the intermediate level, and Vref - V0 is the lowest level.

[0081] Figure 7E is the schematic diagram of the test waveform with the near - end short - circuited provided by the present invention. As Figure 7E shown, the level of the near - end short - circuited waveform is always Vref.

[0082] In the embodiment of the present invention, by performing an exclusive - OR operation on adjacent levels, a unique comprehensive result is obtained, directly distinguishing various situations of the port, without the need for secondary judgment.

[0083] Step 103: Based on the first comprehensive result, determine the fault type of the port of the node to be tested.

[0084] It should be noted that the first comprehensive result needs to be combined with the mapping relationship to determine the fault type of the port of the node to be tested. Among them, the mapping relationship table is the corresponding relationship between the first comprehensive result and the fault type set in advance.

[0085] Exemplarily, Table 1 above can be a kind of mapping relationship. Among them, if the first comprehensive result is 01110, the port of the node to be tested is normal or the far - end is open - circuited; if the first comprehensive result is 11110, the port of the node to be tested has a near - end open - circuit; if the first comprehensive result is 00000, the port of the node to be tested has a near - end short - circuit; if the first comprehensive result is 00001, the port of the node to be tested has a far - end short - circuit.

[0086] It should be noted that the far - end is the coupling port corresponding to the port of the node to be tested, and the near - end is the port of the node to be tested. Therefore, a near - end open - circuit means that the port of the node to be tested is open - circuited, a near - end short - circuit means that the port of the node to be tested is short - circuited, a far - end open - circuit means that the coupling port corresponding to the port of the node to be tested is open - circuited, and a far - end short - circuit means that the coupling port corresponding to the port of the node to be tested is short - circuited.

[0087] Table 2 is the corresponding relationship table between the first comprehensive result and the fault type of the short - line bus - type network in FC. If the first comprehensive result is 10000, the port of the node to be tested has a far - end open - circuit.

[0088] Table 2

[0089]

[0090] Exemplary Figure 8A is the second schematic diagram of the test waveform with the far - end open - circuit provided by the present invention. As Figure 8A shown, Vref + 2×V0 is the highest level, Vref + V0 is the intermediate level, Vref is the lowest level, and the time relationship is T2 + T3 = T1, 0 <= T2 <= T1, 0 <= T3 <= T1; Figure 8B is the second schematic diagram of the test waveform with the far - end short - circuit provided by the present invention. As Figure 8B shown, Vref + V0 is the highest level, Vref is the intermediate level, Vref - V1 is the lowest level. The time relationship is T4 + T5 = T1, 0 <= T4 <= T1, 0 <= T5 <= T1.

[0091] Further, determining the fault type of the port to be tested based on the first comprehensive result includes: when the first comprehensive result is the first preset result, detecting the port to be tested of the FC bus - type network through a pulse counter to obtain the pulse value measured by the pulse counter for the pulse counter; the first preset result is used to characterize the output result detected by the port detection circuit; when the pulse value is the preset pulse value, determining that the fault type of the port to be tested is normal; when the pulse value is not the preset pulse value, determining that the fault type of the port to be tested is far - end open - circuit.

[0092] Here, the first preset result can be understood as the preset result set in the preset mapping relationship.

[0093] According to Table 1 above, when the first comprehensive result is 01110, the port to be tested may be normal or far - end open - circuit. Therefore, it is necessary to judge by the pulse value. When the pulse value is 01, the port to be tested is normal, otherwise the port to be tested is far - end open - circuit.

[0094] Further, the pulse counter includes: at least one inverter and at least one flip - flop. The inverters are connected in series in sequence, and the inverter at the end of the series is respectively connected to each of the flip - flops. Detecting the port to be tested of the FC bus - type network through the pulse counter to obtain the pulse value measured by the pulse counter for the pulse counter includes: inputting the input signal into the inverter at the first position of the series through the pulse counter, adjusting the edge and the level waveform of the input signal to obtain a target signal; the input signal is obtained based on the periodic pulse signal; performing pulse counting on the target signal based on the flip - flop to obtain the pulse value.

[0095] Here, the input signal can be a test signal, and the test signal can be the signal obtained after the serial interface transceiver.

[0096] Exemplarily, Figure 9 is a schematic diagram of the output circuit of a serial interface transceiver provided by the present invention. As Figure 9 shown, M1 is a tail current tube, vb is a bias voltage to ensure that M1 operates in the saturation region. M2 and M3 are differential input tubes of the same size, vin and vip are input signals, M4 and M5 are output tubes of the same size, vc1 and vc2 are control voltages, vc1 ensures that M4 operates in the saturation region, and GND represents ground.

[0097] Exemplarily, Figure 10 is a schematic diagram of the structure of a pulse counter provided by the present invention. As Figure 10 shown, the pulse counter includes a first inverter 1001, a second inverter 1002, a first D flip-flop 1003, and a second D flip-flop 1004. The pulse input signal Vin is subjected to edge and level waveform shaping through the first inverter 1001 and the second inverter 1002, and pulse counting is performed using the first D flip-flop 1003 and the second D flip-flop 1004. Among them, Figure 10 Q1 in represents the output of the first D flip-flop 1003, Q2 represents the output of the second D flip-flop 1004. The D port in the first D flip-flop 1003 and the second D flip-flop 1004 represents the data input port, the C port represents the clock input port, -Q represents the complementary output port of the Q1 port and the Q2 port, and the R port usually represents the reset input port. Additionally, Figure 10 the 2 port of the pulse counter in is the periodic pulse signal Vi, and the reset signal Reset generated after passing through the third inverter 1005, where it is a high-level reset. Since Td0 > T1, the counter is fully reset before the signal pulse arrives. Since T0 is 10 times T1, it is ensured that the echo pulse counting is sufficient before resetting. During the T0 period, Vin is a pulse input signal, and the output of the 3 / 4 port of the pulse counter is 01. When Vin is two pulses, the output of the 3 / 4 port of the pulse counter is 10.

[0098] Exemplarily, Figure 11 is a schematic diagram of the reset signal (Reset) provided by the present invention. As Figure 11 shown, T1 is the pulse width.

[0099] In the embodiment of the present invention, by adding a pulse counter that only operates at the signal edge of the test signal, the working time at the signal edge is greatly reduced, power consumption is saved, and when the echo signal does not overlap with the excitation signal, the state of the port of the node to be tested can be successfully judged at one time. At the same time, by introducing a pulse technique, the detection of the port of the node to be tested is carried out in the analog domain without introducing ADC conversion and without the need for secondary judgment in the digital domain. Therefore, it is fast, direct, simple and effective.

[0100] In another embodiment, determining the fault type of the port of the node to be tested based on the first comprehensive result includes: when the first comprehensive result is the second preset result, determining that the fault type of the port of the node to be tested is open circuit at the far end; the second preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the third preset result, determining that the fault type of the port of the node to be tested is open circuit at the near end; the third preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the fourth preset result, determining that the fault type of the port of the node to be tested is short circuit at the far end; the fourth preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is the fifth preset result, determining that the fault type of the port of the node to be tested is short circuit at the near end; the fifth preset result is used to represent the output result detected by the port detection circuit. The first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all different output results, and different output results respectively correspond to different fault types.

[0101] In the embodiment of the present invention, the port state is intelligently and automatically judged according to the first comprehensive result, and a complete process for detecting the port of the high-speed bus type node is given.

[0102] It should be noted that when there are at least two ports of nodes to be tested in the FC bus type network, a mutual short circuit fault type of multiple ports of nodes to be tested may occur. The following is a further classification of the mutual short circuit fault type of multiple ports of nodes to be tested.

[0103] In one embodiment, the port of the node to be tested includes at least two ports of nodes to be tested, and the short circuit at the near end includes mutual short circuit and floating at the near end and mutual short circuit to ground; determining that the fault type of the port of the node to be tested is short circuit at the near end includes:

[0104] Control the output circuit of the FC bus-type network to be single-tube effective, and detect the closed port of the node to be tested through the port detection circuit to obtain a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed port of the node to be tested at the third level and each of the first reference levels, and the fourth comparison value is used to represent the comparison result between the closed port of the node to be tested at the fourth level and each of the first reference levels, and the third level and the fourth level are levels at different times;

[0105] Based on the port detection circuit, perform an exclusive OR operation on the third comparison value and the fourth comparison value to obtain a second comprehensive result;

[0106] When the second comprehensive result is the first preset result, determine that the fault type of the port of the node to be tested is proximal short-circuit and floating;

[0107] When the second comprehensive result is the fifth preset result, determine that the fault type of the port of the node to be tested is proximal short-circuit to ground.

[0108] In another embodiment, the port of the node to be tested includes at least two ports of the node to be tested, and the remote short circuit includes: remote short-circuit and floating, remote short-circuit to one end of the termination, remote short-circuit to both ends of the termination, and remote short-circuit to ground;

[0109] The determination that the fault type of the port of the node to be tested is a remote short circuit includes:

[0110] Control the output circuit of the FC bus-type network to be single-tube effective, and detect the closed port of the node to be tested through the port detection circuit to obtain a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed port of the node to be tested at the fifth level and each of the first reference levels, and the sixth comparison value is used to represent the comparison result between the closed port of the node to be tested at the sixth level and each of the first reference levels, and the fifth level and the sixth level are levels at different times;

[0111] Based on the port detection circuit, perform an exclusive OR operation on the fifth comparison value and the sixth comparison value to obtain a third comprehensive result;

[0112] When the third comprehensive result is the first preset result, determine that the fault type of the port of the node to be tested is remote short-circuit and floating;

[0113] When the third comprehensive result is the sixth preset result, determine that the fault type of the port of the node to be tested is remote short-circuit to one end of the termination; the sixth preset result is used to represent the output result of the port detection circuit;

[0114] When the third comprehensive result is the seventh preset result, determine that the fault type of the node port to be measured is short - circuited remotely to both ends of the termination; the seventh preset result is used to represent the output result of the port detection circuit, and both the sixth preset result and the seventh preset result are output results different from the first preset result, the second preset result, the third preset result, the fourth preset result, and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types;

[0115] When the third comprehensive result is the fifth preset result, determine that the fault type of the node port to be measured is short - circuited remotely to ground.

[0116] In one embodiment, when it is determined that multiple node ports to be measured are short - circuited to each other, the output circuit of the chip (i.e., the serial interface transceiver) selects a single - transistor effective mode at this time. For example, select Figure 5 the p - path (5 - port) output is effective.

[0117] When it is determined that multiple node ports to be measured are short - circuited to each other, make Figure 9 switch T1 turn on and switch T2 turn off. At this time, vc2 = GND and M5 is cut off and disconnected. From Figure 9 it can be known that the current of M1 only enters and exits from the 5 - port. The AC equivalent circuit is as Figure 7A - 7B shown. The termination resistance is the input impedance R of the 3 - port of the directional coupler. It can be known that the number of parallel load Rs is different in different cases, so the high level and the low level are also different. According to the comparison reference values of ref1 / ref2 / ref3 / ref4 / ref5 in this first item, we detect the high level, and the second comprehensive result and the third comprehensive result are shown in Table 3:

[0118] Table 3

[0119]

[0120] In Table 3, the closed port can be Figure 5 the port N in. The high level of the closed - end signal may be the third level or the fifth level, the low level of the closed - end signal may be the fourth level or the sixth level, the comprehensive result may be the second comprehensive result or the third comprehensive result, and the port state is the fault type. Among them, Table 3 can be the mapping relationship between the second comprehensive result and the fault type, and the mapping relationship between the third comprehensive result and the fault type.

[0121] In the embodiment of the present invention, for differential short - circuits, details such as whether it is remote or proximal can be further distinguished, and whether the short - circuit point is grounded or floating can be determined, so as to accurately locate the fault.

[0122] In an embodiment of the present invention, when a periodic pulse signal is generated in an FC bus network, a port detection circuit is used to detect a port of a node to be tested in the FC bus network, and a comparison result (i.e., a first comparison value) between the port of the node to be tested at a first level and at least one first reference level of the port of the node to be tested and a comparison result (a second comparison value) between the port of the node to be tested at a second level and the first reference level are obtained. The first level and the second level are levels at different times. The port detection circuit performs an exclusive OR operation on the first comparison value and the second comparison value to obtain a unique first comprehensive result, and thus, the fault type of the port of the node to be tested is determined by using the unique first comprehensive result. In this way, the fault type of the port of the node to be tested can be directly determined by using the unique first comprehensive result without secondary determination, improving the efficiency of fault detection and reducing the complexity of fault detection determination.

[0123] The following is an application scenario of the port fault detection method for the FC bus network provided by the present invention. It includes a port P of a node to be tested and a port N of a node to be tested. Detection circuit 1 detects the port P of the node to be tested, and detection circuit 2 detects the port N of the node to be tested. Detection circuit 1 and detection circuit 2 are Figure 6 the detection circuits in

[0124] Figure 12A Figure 9 is the second schematic flowchart of the port fault detection method for the FC bus network provided by the present invention. As Figure 12A shown, it includes:

[0125] Step 1201: The chip sends a periodic pulse signal with a period of T0.

[0126] Step 1202: Determine whether detection circuit 1 outputs 10000. If so, execute step 1203; determine whether detection circuit 1 outputs 01110. If so, execute step 1204; determine whether detection circuit 1 outputs 11110. If so, execute step 1206; determine whether detection circuit 1 outputs 00001. If so, execute step 1207; determine whether detection circuit 2 outputs 00001. If so, execute step 1209.

[0127] Step 1203: Determine that the P port is open at the far end.

[0128] Step 1204: Determine whether pulse counter 1 outputs 01. If so, execute step 1205; otherwise, execute step 1203.

[0129] Step 1205: Determine that the P port is normal.

[0130] Step 1206: Determine that the P port is open at the near end.

[0131] Step 1207: Determine that the far end of the P port is short-circuited, and execute Step 1208.

[0132] Step 1208: Determine whether the detection circuit 2 outputs 00001. If so, execute Step 1211; otherwise, execute Step 1212.

[0133] Step 1209: Determine that the far end of the N port is short-circuited, and execute Step 1210;

[0134] Step 1210: Determine whether the detection circuit 1 outputs 00001. If so, execute Step 1211; otherwise, execute Step 1213.

[0135] Step 1211: The chip sends a pulsed differential signal with a period of T0, and the output circuit of the chip selects single-tube effectiveness, and execute Step 1214.

[0136] Here, for example, the 5th port outputs effectively. At this time, the detection circuit 1 tests the output end, and the detection circuit 2 tests the closed end.

[0137] Step 1212: Determine that the far end of the P port is short-circuited to the ground.

[0138] Step 1213: Determine that the far end of the N port is short-circuited to the ground.

[0139] Step 1214: Determine whether the detection circuit 2 outputs 01110. If so, execute Step 1215; determine whether the detection circuit 2 outputs 00110. If so, execute Step 1216; determine whether the detection circuit 2 outputs 00010. If so, execute Step 1217; determine whether the detection circuit 2 outputs 00000. If so, execute Step 1218;

[0140] Step 1215: Determine that the far end is mutually short-circuited and floating.

[0141] Step 1216: Determine that the far end is mutually short-circuited to one end of the termination.

[0142] Step 1217: Determine that the far end is mutually short-circuited to both ends of the termination.

[0143] Step 1218: Determine that the far end is mutually short-circuited to the ground.

[0144] Figure 12B It is the third flow diagram of the port fault detection method for the FC bus-type network provided by the present invention. As Figure 12B shown, it includes:

[0145] Step 1219: Determine whether detection circuit 1 outputs 00000. If so, execute Step 1220; determine whether detection circuit 2 outputs 00000. If so, execute Step 1227; determine whether detection circuit 2 outputs 11110. If so, execute Step 1230; determine whether detection circuit 2 outputs 01110. If so, execute Step 1231; determine whether 10000 is output. If so, execute Step 1233.

[0146] It should be noted that the determination in Step 1219 is made after the pulse differential signal is sent in Step 1201.

[0147] Step 1220: Determine that there is a short circuit near the P terminal, and execute Step 1221.

[0148] Step 1221: Determine whether detection circuit 2 outputs 00000. If so, execute Step 1222; otherwise, execute Step 1223.

[0149] Step 1222: The chip sends a pulse differential signal with a period of T0, and the output circuit of the chip selects a single transistor to be effective, and execute Step 1224.

[0150] Step 1223: Determine that the P port is shorted to ground near the end.

[0151] Step 1224: Determine whether detection circuit 2 outputs 01110. If so, execute Step 1225; determine whether detection circuit 2 outputs 00000. If so, execute Step 1226;

[0152] Step 1225: Determine that there is a short circuit and floating near the end.

[0153] Step 1226: Determine that there is a short circuit to ground near the end.

[0154] Step 1227: Determine that there is a short circuit near the N terminal, and execute Step 1228.

[0155] Step 1228: Determine whether detection circuit 1 outputs 00000. If so, execute Step 1222; otherwise, execute Step 1229.

[0156] Step 1229: Determine that the N port is shorted to ground near the end.

[0157] Step 1230: Determine that the N port is open near the end.

[0158] Step 1231: Determine whether the pulse counter 2 outputs 01. If so, execute Step 1232; otherwise, execute Step 1233.

[0159] Step 1232: Determine that the N port is normal.

[0160] Step 1233: Determine that the N-port is open at the far end.

[0161] The port fault detection device for the FC bus network provided by the present invention will be described below. The port fault detection device for the FC bus network described below can be correspondingly referred to the port fault detection method for the FC bus network described above.

[0162] Figure 13 is a schematic structural diagram of the port fault detection device for the FC bus network provided by the present invention. As Figure 13 shown, the port fault detection device 1300 for the FC bus network includes:

[0163] An acquisition module 1301, configured to, when a periodic pulse signal is generated in the FC bus network, detect a to-be-detected node port of the FC bus network through a port detection circuit, and obtain a first comparison value and a second comparison value; the first comparison value is used to represent a comparison result between the to-be-detected node port when it is at a first level and at least one first reference level of the to-be-detected node port, and the second comparison value is used to represent a comparison result between the to-be-detected node port when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times;

[0164] A processing module 1302, configured to perform an exclusive OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result;

[0165] A determination module 1303, configured to determine a fault type of the to-be-detected node port based on the first comprehensive result.

[0166] In some embodiments, the determination module 1303 is specifically configured to: when the first comprehensive result is a first preset result, detect the to-be-detected node port of the FC bus network through a pulse counter, and obtain a pulse value measured by the pulse counter by the pulse counter; the first preset result is used to represent an output result detected by the port detection circuit; when the pulse value is a preset pulse value, determine that the fault type of the to-be-detected node port is normal; when the pulse value is not the preset pulse value, determine that the fault type of the to-be-detected node port is open at the far end.

[0167] In some embodiments, the determining module 1303 is further specifically configured to: when the first comprehensive result is a second preset result, determine that the fault type of the to-be-tested node port is a remote open circuit; the second preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is a third preset result, determine that the fault type of the to-be-tested node port is a proximal open circuit; the third preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is a fourth preset result, determine that the fault type of the to-be-tested node port is a remote short circuit; the fourth preset result is used to represent the output result detected by the port detection circuit; when the first comprehensive result is a fifth preset result, determine that the fault type of the to-be-tested node port is a proximal short circuit; the fifth preset result is used to represent the output result detected by the port detection circuit, and the first preset result, the second preset result, the third preset result, the fourth preset result, and the fifth preset result are all different output results, and different output results respectively correspond to different fault types.

[0168] In some embodiments, the to-be-tested node port includes at least two to-be-tested node ports, and the proximal short circuit includes proximal mutual short circuit and floating and proximal mutual short circuit to ground; the determining module 1303 is further specifically configured to: the determining that the fault type of the to-be-tested node port is a proximal short circuit includes: controlling the output circuit of the FC bus type network to be single-tube effective, detecting the closed to-be-tested node ports through the port detection circuit, and obtaining a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed to-be-tested node port at a third level and each of the first reference levels, and the fourth comparison value is used to represent the comparison result between the closed to-be-tested node port at a fourth level and each of the first reference levels, and the third level and the fourth level are levels at different times; based on the port detection circuit, performing an exclusive OR operation on the third comparison value and the fourth comparison value to obtain a second comprehensive result; when the second comprehensive result is the first preset result, determining that the fault type of the to-be-tested node port is proximal mutual short circuit and floating; when the second comprehensive result is the fifth preset result, determining that the fault type of the to-be-tested node port is proximal mutual short circuit to ground.

[0169] In some embodiments, the node port to be measured includes at least two node ports to be measured, and the remote short circuit includes: remote mutual short circuit and floating, remote mutual short circuit to one end of the termination, remote mutual short circuit to both ends of the termination, and remote mutual short circuit to ground; the determining module 1303 is further specifically configured to: when determining that the fault type of the node port to be measured is a remote short circuit, control the output circuit of the FC bus network to be single-tube effective, detect the closed node port to be measured through the port detection circuit, and obtain a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be measured at the fifth level and each of the first reference levels, the sixth comparison value is used to represent the comparison result between the closed node port to be measured at the sixth level and each of the first reference levels, and the fifth level and the sixth level are levels at different times; based on the port detection circuit, perform an exclusive OR operation on the fifth comparison value and the sixth comparison value to obtain a third comprehensive result; when the third comprehensive result is the first preset result, determine that the fault type of the node port to be measured is remote mutual short circuit and floating; when the third comprehensive result is the sixth preset result, determine that the fault type of the node port to be measured is remote mutual short circuit to one end of the termination; the sixth preset result is used to represent the output result of the port detection circuit; when the third comprehensive result is the seventh preset result, determine that the fault type of the node port to be measured is remote mutual short circuit to both ends of the termination; the seventh preset result is used to represent the output result of the port detection circuit, and both the sixth preset result and the seventh preset result are output results different from the first preset result, the second preset result, the third preset result, the fourth preset result, and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; when the third comprehensive result is the fifth preset result, determine that the fault type of the node port to be measured is remote mutual short circuit to ground.

[0170] In some embodiments, the port detection circuit is formed by paralleling at least one comparator. The positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminals of the comparators are connected to an exclusive OR processing unit; each value in the first comparison value corresponds to a comparator one by one, and each value in the second comparison value corresponds to a comparator one by one; the processing module 1302 is configured to: when performing an exclusive OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result, perform an exclusive OR operation on each value in the first comparison value corresponding to the same comparator and each value in the second comparison value to obtain a first comprehensive result.

[0171] In some embodiments, the pulse counter includes: at least one inverter and at least one flip-flop. The inverters are connected in series in sequence, and the inverter at the last position is respectively connected to each of the flip-flops. The determining module 1303 is further specifically configured to: detect a port of a node to be measured in the FC bus network through the pulse counter, and obtain a pulse value measured by the pulse counter for the pulse counter, including: inputting an input signal into the inverter at the first position through the pulse counter, adjusting an edge of the input signal and a level waveform of the input signal to obtain a target signal; the input signal is obtained based on the periodic pulse signal; performing pulse counting on the target signal based on the flip-flop to obtain the pulse value.

[0172] Figure 14 is a schematic structural diagram of an electronic device provided by the present invention, as Figure 14 shown, the electronic device may include: a processor 1410, a communication interface 1420, a memory 1430, and a communication bus 1440. Among them, the processor 1410, the communication interface 1420, and the memory 1430 complete mutual communication through the communication bus 1440. The processor 1410 may call logic instructions in the memory 1430 to execute a method for detecting a port fault of an FC bus network, and the method includes: when a periodic pulse signal is generated in the FC bus network; detecting a port of a node to be measured in the FC bus network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent a comparison result between the port of the node to be measured when it is at a first level and at least one first reference level of the port of the node to be measured, and the second comparison value is used to represent a comparison result between the port of the node to be measured when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; performing an exclusive OR operation on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; determining a fault type of the port of the node to be measured based on the first comprehensive result.

[0173] In addition, when the logical instructions in the aforementioned memory 1430 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0174] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the port fault detection method of the FC bus-type network provided by the above-mentioned various methods. The method includes: when a periodic pulse signal is generated in the FC bus-type network; detecting the port of the node to be tested in the FC bus-type network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the port of the node to be tested when it is at a first level and at least one first reference level of the port of the node to be tested, and the second comparison value is used to represent the comparison result between the port of the node to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; based on the port detection circuit performing an exclusive OR operation on the first comparison value and the second comparison value to obtain a first comprehensive result; based on the first comprehensive result, determining the fault type of the port of the node to be tested.

[0175] In another aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a port fault detection method for an FC bus-type network provided by the above-mentioned various methods. The method includes: when a periodic pulse signal is generated in the FC bus-type network; detecting a to-be-tested node port of the FC bus-type network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent a comparison result between the to-be-tested node port when it is at a first electrical level and at least one first reference level of the to-be-tested node port, and the second comparison value is used to represent a comparison result between the to-be-tested node port when it is at a second electrical level and each of the first reference levels; the first electrical level and the second electrical level are electrical levels at different times; based on the port detection circuit performing an exclusive OR operation on the first comparison value and the second comparison value, obtaining a first comprehensive result; and based on the first comprehensive result, determining the fault type of the to-be-tested node port.

[0176] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0177] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting port failure in an FC bus network, characterized in that: include: In the case where the FC bus type network generates a periodic pulse signal; Detecting the node port to be tested of the FC bus network by a port detection circuit to obtain a first comparison value and a second comparison value; The first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; The first level and the second level are levels at different moments; Performing XOR processing on each numerical value in the first comparison value and each numerical value in the second comparison value corresponding to the same comparator to obtain a first comprehensive result; wherein the port detection circuit is obtained by connecting at least one comparator in parallel, the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to an XOR processing unit; each numerical value in the first comparison value corresponds to the comparator one-to-one, and each numerical value in the second comparison value corresponds to the comparator one-to-one; In the case where the first comprehensive result is the first preset result, the node port to be tested of the FC bus network is detected by a pulse counter to obtain the pulse value measured by the pulse counter; in the case where the pulse value is the preset pulse value, the fault type of the node port to be tested is determined to be normal; in the case where the pulse value is not the preset pulse value, the fault type of the node port to be tested is determined to be a remote open circuit; in the case where the first comprehensive result is the second preset result, the fault type of the node port to be tested is determined to be a remote open circuit; in the case where the first comprehensive result is the third preset result, the fault type of the node port to be tested is determined to be a remote open circuit. The fault type of the node port to be tested is a near-end open circuit; when the first comprehensive result is the fourth preset result, the fault type of the node port to be tested is determined to be a far-end short circuit; when the first comprehensive result is the fifth preset result, the fault type of the node port to be tested is determined to be a near-end short circuit; the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all used to characterize different output results detected by the port detection circuit, and different output results correspond to different fault types, wherein the far end is the coupling port corresponding to the node port to be tested, and the near end is the node port to be tested.

2. The method for detecting port failure of FC bus network according to claim 1, characterized in that: The node port to be tested includes at least two node ports to be tested, and the proximal end short circuit includes proximal ends being shorted to each other and suspended in the air and proximal ends being shorted to the ground; The determining that the fault type of the port of the node to be tested is a near-end short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fourth level, and the third level and the fourth level are levels at different times; Performing an XOR process on the third comparison value and the fourth comparison value based on the port detection circuit to obtain a second comprehensive result; When the second comprehensive result is the first preset result, determining that the fault type of the node port to be tested is near-end short and hanging; When the second comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a near-end short to ground.

3. The method for detecting port failure of FC bus network according to claim 1, characterized in that: The node port to be tested includes at least two node ports to be tested, and the remote short circuit includes: the remote ends are shorted to each other and suspended, the remote ends are shorted to one end of the terminal, the remote ends are shorted to both ends of the terminal, and the remote ends are shorted to the ground; The determining that the fault type of the port of the node to be tested is a remote short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fifth level, and the sixth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a sixth level, and the fifth level and the sixth level are levels at different times; Performing an XOR process on the fifth comparison value and the sixth comparison value based on the port detection circuit to obtain a third comprehensive result; When the third comprehensive result is the first preset result, determining that the fault type of the node port to be tested is a far-end short circuit and hanging; In the case where the third comprehensive result is the sixth preset result, determining that the fault type of the port of the node to be tested is a far-end short to a termination end; the sixth preset result is used to characterize the output result of the port detection circuit; In the case where the third comprehensive result is the seventh preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to both ends of the termination; the seventh preset result is used to characterize the output result of the port detection circuit, the sixth preset result and the seventh preset result are both output results different from the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; When the third comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to ground.

4. The port fault detection method of FC bus network according to claim 1, characterized in that: The pulse counter comprises: at least one inverter and at least one trigger, wherein the inverters are connected in series in sequence, and the last inverter in series is connected to each of the triggers respectively. The step of detecting the node port to be tested of the FC bus network by using a pulse counter to obtain the pulse value measured by the pulse counter comprises: The input signal is input to the inverter connected in series at the first position through the pulse counter, and the edge of the input signal and the level waveform of the input signal are adjusted to obtain the target signal; the input signal is obtained based on the periodic pulse signal; The target signal is pulse counted based on the trigger to obtain the pulse value.

5. A port fault detection device for an FC bus network, characterized in that: include: An acquisition module is used when the FC bus network generates a periodic pulse signal; Detecting the node port to be tested of the FC bus network by a port detection circuit to obtain a first comparison value and a second comparison value; The first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; The first level and the second level are levels at different moments; A processing module, used for performing XOR processing on each numerical value in the first comparison value and each numerical value in the second comparison value corresponding to the same comparator to obtain a first comprehensive result; wherein the port detection circuit is obtained by connecting at least one comparator in parallel, the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to the XOR processing unit; each numerical value in the first comparison value corresponds to the comparator one-to-one, and each numerical value in the second comparison value corresponds to the comparator one-to-one; A determination module is used to, when the first comprehensive result is a first preset result, detect the node port to be tested of the FC bus network through a pulse counter to obtain the pulse value measured by the pulse counter; when the pulse value is a preset pulse value, determine that the fault type of the node port to be tested is normal; when the pulse value is not the preset pulse value, determine that the fault type of the node port to be tested is a remote open circuit; when the first comprehensive result is a second preset result, determine that the fault type of the node port to be tested is a remote open circuit; when the first comprehensive result is a third preset result , determine that the fault type of the node port to be tested is a near-end open circuit; when the first comprehensive result is the fourth preset result, determine that the fault type of the node port to be tested is a far-end short circuit; when the first comprehensive result is the fifth preset result, determine that the fault type of the node port to be tested is a near-end short circuit; the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all used to characterize different output results detected by the port detection circuit, and different output results correspond to different fault types, wherein the far end is the coupling port corresponding to the node port to be tested, and the near end is the node port to be tested.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the port failure detection method for the FC bus type network according to any one of claims 1 to 4 is implemented.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the port failure detection method for an FC bus network according to any one of claims 1 to 4 is implemented.

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