Weapon system communication architecture design method based on real-time Ethernet

Abstract

The invention discloses a weapon system communication architecture design method based on a real-time Ethernet, and the method comprises the steps: employing an optical fiber bottom plate for the transmission and exchange of an optical signal, and achieving the conversion of the optical signal and an electric signal; the transition plate is used for connecting the bottom plate and various VPX function modules, providing a power supply for the VPX function modules and preventing system damage caused by overload operation of the controller; the data exchange board is used for exchanging external data of the platform and internal data of the platform to realize rapid exchange of the data; the protocol conversion module is used for realizing conversion between various protocols and a Powerlink-based real-time Ethernet protocol and realizing the universality of the platform to various task units; and the video coding and decoding module is used for carrying out decompression operation on the video data. All kinds of existing weapon system task load data are uniformly converted into real-time Ethernet protocol frames through a data exchange board, and the real-time Ethernet protocol frames are transmitted on an optical fiber bus.

Description

Technical Field

[0001] The present invention relates to the field of computer network technology, and in particular to a weapon system communication architecture design method based on real-time Ethernet. Background Art

[0002] With the development of big data, AR, VR, cloud computing, and high-definition video technology, the requirements of weapon systems for channel bandwidth are increasing. At present, we urgently need a high-reliability information platform that can carry large amounts of data for fast and reliable transmission of large amounts of mission data. We need a general platform with real-time Ethernet as the communication protocol and FC as the physical layer.

[0003] Industrial Ethernet is an Ethernet technology used in the field of industrial control. The speed of Ethernet is much faster than that of traditional fieldbus. Users do not need to invest in independent research on technology upgrades. In this regard, any existing fieldbus technology is incomparable. At the same time, the development of robotics and intelligent technology requires communication networks to have higher bandwidth and performance, and communication protocols to have higher flexibility. Ethernet can meet these requirements well.

[0004] However, there is no unified application layer protocol, resulting in numerous protocols, and many of them are protected by patents or special chip-level protection, which is prone to the risk of being blocked or cut off in the current international environment. PowerLink is different from traditional industrial real-time Ethernet technology, which requires a dedicated ASIC to implement. Users can implement its functions on various platforms, such as FPGA, ARM, x86, etc. PowerLink has made all source codes public, and anyone can download and use it for free. It is currently the most commonly used industrial real-time Ethernet technology. The introduction of PowerLink technology is an important guarantee for the high bandwidth and low latency of this system.

[0005] The development of the general weapon system information platform needs to meet the high-bandwidth transmission requirements of video while taking into account the real-time and protocol conversion requirements of other mission payloads. Therefore, the general weapon system information platform needs to be compatible with various protocols so that it can be promoted on various existing weapon systems.

[0006] In order to take into account the requirements of interface universality and high bandwidth, it is necessary to independently develop a set of high-bandwidth universal real-time Ethernet architecture system suitable for weapon systems. It can not only meet the bandwidth requirements of weapon systems for general information platforms in the current and even in the next five years, but also meet the platform's needs for unified analysis of various protocols. Summary of the invention

[0007] The present invention provides a weapon system communication architecture design method based on real-time Ethernet, which uniformly converts various existing weapon system mission load data into real-time Ethernet protocol frames through a high-performance data processing module and transmits them on a fiber optic bus.

[0008] The technical solutions to the above problems are as follows: A method for designing a weapon system communication architecture based on real-time Ethernet includes a real-time Ethernet protocol based on Powerlink and a general information processing platform. The general information processing platform includes: Optical fiber backplane, used for transmission and exchange of optical signals, and conversion between optical and electrical signals; The transition board is used to connect the baseboard and various VPX function modules, and to provide power supply for the VPX function modules to prevent the controller from overloading and causing system damage; Data exchange board, used for exchanging data between the platform's external and internal data, to achieve fast data exchange; The protocol conversion module is used to realize the conversion between various protocols and the real-time Ethernet protocol based on Powerlink, so as to realize the versatility of the platform for various task units; The video encoding and decoding module is used to decompress the video data.

[0009] Furthermore, the optical fiber backplane is provided with a plurality of board slots, the CAN and IPMB of these board slots share a common bus, and the board slots arranged in even-numbered positions define interface compatibility to achieve protocol conversion.

[0010] Furthermore, the core of the data exchange board is a data exchange module, which connects multiple devices to a computer network through a 10 Gigabit switch and forwards data to a destination by exchanging data packets.

[0011] Furthermore, the data exchange module uses XC7K325T as a processing chip.

[0012] Furthermore, the protocol conversion module uses XC7K325T as a processing chip.

[0013] Furthermore, the video codec module adopts a Xilinx Zynq Z-7045 SOC chip.

[0014] The advantages and characteristics of the equipment provided by the solution of the present invention are as follows: The equipment mainly realizes the universality of software and hardware interfaces for various mission payloads, and can solve the problem of inconsistent protocols for various mission payloads in one stop; the equipment can meet the requirements of high-definition video transmission; the equipment can meet the requirements of real-time data transmission of weapon systems.

[0015] The data encoding and decoding functions are realized through high-performance FPGA, and the conversion between various protocols to the real-time Ethernet PowerLink protocol is realized, and finally the data is transmitted on the optical fiber bus, realizing the system universality, high bandwidth and high reliability requirements.

[0016] The universal weapon system information platform can significantly improve the data transmission rate of the existing communication architecture while ensuring the real-time requirements of the system, and can also enable the mutual conversion between various mainstream protocols and the universal information platform protocol to achieve unified interface specifications. The highly universal, high-bandwidth, and high-real-time information platform of the present invention can meet the combat requirements in actual battlefield environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the structural block diagram of the weapon system information platform.

[0018] Figure 2 This is a schematic diagram of the weapon system information platform base.

[0019] Figure 3 This is a schematic diagram of the data exchange board.

[0020] Figure 4 This is a schematic diagram of the protocol conversion module.

[0021] Figure 5 Schematic diagram of the video module compression process.

[0022] Figure 6 Schematic diagram of the video module decompression process. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0024] like Figures 1 to 6 As shown, a weapon system communication architecture design method based on real-time Ethernet of the present invention includes a real-time Ethernet protocol based on Powerlink, and also includes a universal information processing platform. The universal information processing platform includes: an optical fiber baseboard, a transition board, a data exchange board, a protocol conversion module, and a video encoding and decoding module. Each part is described in detail below.

[0025] The PowerLink is an open source real-time Ethernet technology based on the standard Ethernet protocol, with fast transmission speed, no need for dedicated ASIC chips, and low economic cost. PowerLink is completely open source, with a large number of related open source materials and solutions, and can better customize and modify the real-time Ethernet protocol, making the protocol more suitable for environments with high bandwidth requirements and high reliability requirements.

[0026] The fiber optic backplane is used for the transmission and exchange of optical signals, and realizes the conversion between optical signals and electrical signals. There are multiple card slots on the fiber optic backplane, and the CAN and IPMB of these card slots share the bus, and the card slots arranged in even positions define interface compatibility to realize protocol conversion.

[0027] In this embodiment, the optical fiber backplane has 10 slots, among which SLOT2, SLOT4, SLOT6, SLOT8, and SLOT10 board slots define interfaces that are compatible, realize protocol conversion functions, and can realize mixed insertion, which is conducive to equipment maintenance and replacement. SLOT0 is a power module, SLOT1, SLOT3, and SLOT5 are embedded PCs, SLOT1 and SLOT2 communicate via PCIE, SLOT3 and SLOT4 communicate via PCIE, and video encoding and video decoding boards are connected via Ethernet. In addition, the CAN and IPMB of all board slots share a common bus.

[0028] The transition board is used to connect the baseboard and various VPX functional modules, and to provide power supply for the VPX functional modules to prevent the controller from overloading and causing system damage.

[0029] The transition board serves as an interactive bridge between the cables and each control board. The slots on the fiber optic backplane are connected by optical fibers, which are converted into electrical signals by photoelectric conversion devices and transmitted to the corresponding slots. A power supply unit is set on the transition board to provide various required power supplies for each fixed pin on the transition board connector. A current monitoring device is also set to prevent the controller from overloading and causing system damage. A suitable VPX functional module is selected and placed at the connection with the functional unit board to connect the functional unit and the transition board.

[0030] The data exchange board is used to exchange data outside the platform and data inside the platform to achieve fast data exchange. The core of the data exchange board is the data exchange module, which connects multiple devices to the computer network through a 10G switch and forwards data to the destination through data packet exchange.

[0031] In this embodiment, the data exchange module is mainly responsible for protocol conversion of data inside and outside the box, thereby completing the two-way interaction of data. The data exchange module connects multiple devices to the computer network through a 10G switch, and forwards the data to the destination through data packet exchange. It enables all kinds of task loads carried by each box to be connected to the optical fiber network through the switch. It also assumes the function of the PowerLink master node. After the system is powered on, it provides initialization information for each controlled node, and provides time synchronization data frames and access cycle frames, and coordinates the overall bandwidth resource allocation.

[0032] The data exchange module is the external interactive bridge between each task node inside the box. The limitation of its processing speed becomes the upper limit of the total bandwidth of each task node, and it is the most important part of the entire general weapon system information platform. When designing the preliminary data exchange plan, it is necessary to consider the conversion of photoelectric signals, the processing speed of electrical signals and the speed of data forwarding. The data exchange module preferably uses XC7K325T as the processing chip, which has the following characteristics.

[0033] 1) High-performance SelectIO technology, supporting DDR3 interfaces up to 1,866Mb / s.

[0034] 2), 36Kb dual-port BlockRAM with built-in FIFO logic for on-chip data buffering.

[0035] 3), PCI Express® (PCIe) integrated block, supporting up to x8 Gen3 endpoint and root port designs.

[0036] 4), advanced high-performance FPGA logic based on true 6-input look-up table (LUT) technology, configurable as distributed memory.

[0037] 5) A user-configurable analog interface (XADC) containing dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and power sensors.

[0038] 6) The DSP slice has 25×18 multipliers, 48-bit accumulators and pre-adders for high-performance filtering, including optimized symmetric coefficient filtering.

[0039] 7), Powerful Clock Management Tile (CMT), combining Phase-Locked Loop (PLL) and Mixed-Mode Clock Manager (MMCM) modules to achieve high accuracy and low jitter.

[0040] 8), multiple configuration options, including support for commodity memory, 256-bit AES encryption with HMAC / SHA-256 authentication, and built-in SEU detection and correction capabilities.

[0041] 9), adopts 28nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option, which can achieve high performance and low power consumption, and achieve lower power consumption.

[0042] 10), Low cost, wire bond, capless flip chip and high signal integrity flip chip packages, easy migration of family members in the same package. All packages are available in Pb options, lead-free and selected packages.

[0043] 11), high-speed serial connection, built-in multi-gigabit transceiver, rate of 600Mb / s, maximum rate of 6.6Gb / s, maximum rate of 28.05Gb / s, special low-power mode, optimized for chip-to-chip interface.

[0044] The data exchange board hardware solution design adopts BCM56504 switch chip and XC7K325T FPGA chip as the main architecture. The BCM56504 has 24 Gb E ports and 4 10Gb E uplink ports, and is designed for multi-functional, high-performance GbE and 10GbE switch applications to achieve IP data exchange and hot standby data synchronization. The XC7K325T chip realizes IP data transmission and reception, heartbeat detection and hot standby channel switching.

[0045] As attached Figure 3 As shown in the figure, the data exchange board includes not only the data exchange module, but also the 10G photoelectric conversion module, the digital processing module, the DDR3 storage module and the power module. The switch module adopts the TL-ST1008F full 10G Ethernet switch, which can better adapt to the design and application of 10G switches, support the needs of concurrent stacking and redundant 10G uplinks, thereby realizing multi-layer full-duplex packet processing capabilities, so that the demand for reliable, secure and high-performance networks is fundamentally solved from the architecture of the switching chip. The 10G optical port adopts a redundant design. When one port fails, another port can be enabled to improve the stability of the system.

[0046] The protocol conversion module is used to realize the conversion between various protocols and the real-time Ethernet protocol based on Powerlink, so as to realize the versatility of the platform for various task units. The protocol conversion module uses XC7K325T as the processing chip.

[0047] The universal weapon system information platform of the present invention is to unify the signals and protocols of various modules in the weapon system, facilitate the unified processing of the central computer and standardize the subsequent development architecture. The system adopts the PowerLink protocol as the data transmission protocol, and is compatible with many sub-modules in the current weapon system, and can support a universal protocol conversion module that converts multiple specific protocols into real-time Ethernet protocols.

[0048] In this embodiment, the protocol conversion module is applied to various existing functional boards and cards, and the data bits of various protocols are placed into the data bits of the Ethernet frame. It can convert various existing protocols into real-time Ethernet protocols, thereby achieving compatibility of the general weapon system information platform with existing sub-modules.

[0049] As attached Figure 4As shown in the figure, the protocol conversion module is mainly used to realize real-time data conversion between various protocols and Ethernet protocols, which can not only realize the universality of the data processed and transmitted by various task modules of this platform, but also meet the requirements of high bandwidth and high real-time performance when processing tasks. This module can process standard 422 interface, 485 interface, Ethernet, CAN, SSI, SDI and cameralink, as well as PCIE interface. On the VPX platform, various protocols can be converted into Ethernet protocols and sent to the computer network through the optical port switch. The protocol conversion module is connected to the chip with JTAG and simulated and verified. When the simulation is correct, the program needs to be solidified through JTAG. The protocol conversion module is cascaded with the VPX slot to realize the interaction function with the upper protocol (various task load protocols), convert the data frame into the PowerLink data frame format, and convert it into an optical signal through the optical fiber bus to realize communication between nodes.

[0050] In this embodiment, the protocol conversion module can process standard 422, 485, Ethernet, CAN, SSI and other interface data from peripherals at the extended interface. FPGA first puts the interface protocol data into FIFO for caching and data packetization; then, the data is parsed through the protocol conversion module, and the data is sent to the high-speed serial transceiver data packetization module. Finally, the packetized data is converted into light signal data by the sending module of the high-speed serial transceiver IP. At the same time, the protocol conversion module can process data interacted by the PCIE interface. The protocol conversion module communicates with the control end through PCIE. After the module parses the data and identifies the IP header address, it is sent to the data packetization module, and finally sent out through the sending module of the high-speed serial transceiver, which can be fed back to the control end for control. Similarly, the control end can also send control instructions to FPGA through PCIE. After receiving, FPGA parses the instruction data, and then identifies the IP target address and port number of the instruction. After identification, the instruction is converted into corresponding protocol data through the protocol conversion module and transmitted to the corresponding board device.

[0051] The video codec module is used to decompress video data. When transmitting video data, the general weapon system information platform must also consider the video data transmission of the unmanned combat platform. The data of the unmanned combat platform relies on radio for wireless communication transmission. It is not possible to directly transmit high-bandwidth data to the outside through the radio. The video data needs to be decompressed before wireless transmission. The use of the video codec module can greatly reduce the bandwidth occupancy rate of some nodes, can greatly reduce the demand for memory, and can reduce the storage module's requirements for data read and write rates.

[0052] In this embodiment, the decoding module uses a Xilinx Zynq Z-7045 professional SOC chip, and transplants the H.264 codec IP core (including AL-H264E-4KI422-HW encoder and AL-H264D-4KI422-HW decoder) developed by AtriaLogic. The IP core includes the following performance 1) Comprehensive modular design, supporting user customization and expansion.

[0053] 2) Support intra-frame H.264 and Hi422 5.1 encoding and decoding.

[0054] 3) Integrated HDMI2.0 receiving and transmitting subsystem.

[0055] 4) Support 8 / 10-bit codec.

[0056] 5), support RGB, YUV 4:2:2 / 4:4:4.

[0057] 6) Support variable bit rate (VBR) and constant bit rate (CBR) modes.

[0058] 7) Video quality 0.99% SSIM, or 50dB PSNR or higher.

[0059] 8), the video processing subsystem is used for pre / post-processing, including color space conversion, video scaling and density subsampling.

[0060] 9) Support Gbps Ethernet data stream output.

[0061] The use of the above IP core can greatly reduce the delay time of encoding and decoding, and it also has a mature anti-false alarm mechanism in bit error rate, and has been verified by a large number of projects.

[0062] The video encoding flow chart is as follows Figure 5 As shown, the core board outputs RGB888 video stream format, and then the video stream is encoded by HDMI_PHY encoding chip and encoded into HDMI video stream. Then the video stream is sent to the HiSilicon video compression board through the HDMI interface for compression. The compressed data stream is output at P1 through the Gigabit network RJ45.

[0063] The video decompression process diagram is as follows Figure 6 As shown in the figure, the compressed video stream is transmitted to the Gigabit RJ45 network port through the P1 port, and then output to the HiSilicon video compression and decompression board for video decompression. The decompressed video stream is then compiled into the HDMI video format, output through the HDMI interface, and then decompressed into RGB888 format by the HDMI_PHY video decompression chip, and finally output to the core board for use by other modules.

[0064] The video input and output of the video codec module designed in the present invention both use the HDMI interface, the compressed video stream is transmitted using a gigabit network, the video is compressed and output through the P1 gigabit network interface, the video decompression board receives the compressed video through the gigabit network interface P1, and then the Xilinx Zynq Z-7045 decompresses the video, and after decompression, it is encoded into an HDMI video stream format for output. The total delay of the 4K@60fps video stream from entering the video compression board in the form of an HDMI interface to being decompressed from the video decompression board and finally displayed through HDMI meets the time requirements for video decompression.

[0065] Finally, it should be noted that the above-described implementation mode is only a preferred embodiment of the present invention to illustrate the technical solution of the present invention, and does not limit it, let alone limit the protection scope of the present invention; although the invention is described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the protection scope of the claims.

Claims

1. A method for designing a weapon system communication architecture based on real-time Ethernet, including a real-time Ethernet protocol based on Powerlink, characterized in that: Also included is a general information processing platform, which includes: Optical fiber backplane, used for transmission and exchange of optical signals, and conversion between optical and electrical signals; The transition board is used to connect the baseboard and various VPX function modules, and to provide power supply for the VPX function modules to prevent the controller from overloading and causing system damage; Data exchange board, used for exchanging data between the platform's external and internal data, to achieve fast data exchange; The protocol conversion module is used to realize the conversion between various protocols and the real-time Ethernet protocol based on Powerlink, so as to realize the versatility of the platform for various task units; The video encoding and decoding module is used to decompress the video data.

2. The method for designing a weapon system communication architecture based on real-time Ethernet according to claim 1, characterized in that: The optical fiber backplane is provided with a plurality of board slots, the CAN and IPMB of these board slots share a common bus, and the board slots arranged in even-numbered positions define interface compatibility to achieve protocol conversion.

3. The method for designing a weapon system communication architecture based on real-time Ethernet according to claim 1, characterized in that: The core of the data exchange board is the data exchange module, which connects multiple devices to the computer network through a 10G switch and forwards data to the destination by exchanging data packets.

4. The method for designing a weapon system communication architecture based on real-time Ethernet according to claim 3, characterized in that: The data exchange module uses XC7K325T as a processing chip.

5. The method for designing a weapon system communication architecture based on real-time Ethernet according to claim 1, characterized in that: The protocol conversion module uses XC7K325T as the processing chip.

6. The method for designing a weapon system communication architecture based on real-time Ethernet according to claim 1, characterized in that: The video codec module uses a Xilinx Zynq Z-7045 SOC chip.

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