Streaming media interface test signal generating device

Abstract

The invention discloses a streaming media interface test signal generation device, which comprises a controller, a streaming media data generation component, a test signal generation component and a test signal generation component, the PCIE component receives the streaming media data and sends the streaming media data to the cache component; the streaming media data generation assembly obtains and analyzes the streaming media data in the cache assembly, adjusts the resolution and frame frequency of the streaming media data according to an external clock signal, and generates a streaming media data stream corresponding to a time sequence; the protocol logic control component acquires a streaming media data stream, converts the streaming media data stream into a coded data stream in a preset format, and sends the coded data stream to the streaming media display device to be tested through the high-speed data interface, and the protocol logic control component and the streaming media data generation component share an external clock signal. The resolution and the frame frequency of the output video are adjusted through the streaming media data generation assembly, the output flexibility of the device is improved, and the data transmission quality and stability in the ultra-high-definition resolution and high-frame-rate output mode are improved.

Description

Technical Field

[0001] The invention relates to the technical field of signal detection, and in particular to a streaming media interface test signal generating device. Background Art

[0002] When testing the performance of streaming media display devices and the video signal formats they can support, the signal source usually needs to adjust the output signal resolution, frame rate, image content, image format, etc. according to the test requirements. With the advancement of technology, large-size, high-definition display devices are changing with each passing day, and traditional video protocol test equipment is basically graphics card devices. The functions of such devices are severely limited by the capabilities of the graphics card, and the output signal format and capabilities are limited. They basically cannot meet the requirements for some specific resolutions and custom timing test scenarios, especially for resolutions above 8K, which are difficult to output, and basically cannot meet the testing requirements of full formats and full bit depths.

[0003] Specifically, the output signal format supported by traditional video protocol test equipment of graphics cards is limited by the graphics card itself, and only supports some common resolutions and video formats. It is basically impossible to output for some specific resolution requirements. Secondly, some equipment manufacturers will develop some non-standard timing display devices to meet the needs of certain specific scenarios, such as changing the number of cycles of line synchronization and field synchronization of video frames. For such scenarios, traditional equipment obviously cannot meet the needs. Thirdly, graphics cards are more positioned to output to desktop display devices, so it is difficult to output high resolution (above 8K) and high frame rate (120Hz), and basically cannot meet the testing requirements of full format and full bit depth. Finally, the characteristics of the graphics card device itself bring about the disadvantages of large video protocol test equipment, clumsy shape, high power consumption, and high noise. Summary of the invention

[0004] The purpose of an embodiment of the present invention is to provide a streaming media interface test signal generating device, which adjusts the resolution and frame frequency of the output video through a streaming media data generating component, thereby effectively improving the flexibility of the output of the test signal generating device and improving the data transmission quality and stability in ultra-high-definition resolution and high frame rate output modes.

[0005] To solve the above technical problems, an embodiment of the present invention provides a streaming media interface test signal generating device, comprising: a PCIE component, a cache component, a streaming media data generating component, a protocol logic control component and a controller;

[0006] The controller is in data communication with the streaming media data generating component and sends an external clock signal to the streaming media data generating component;

[0007] The PCIE component receives the streaming media data and sends the streaming media data to the cache component;

[0008] The streaming media data generation component obtains and parses the streaming media data in the cache component, adjusts the resolution and frame frequency of the streaming media data according to the external clock signal, and generates a streaming media data stream corresponding to the timing;

[0009] The protocol logic control component obtains the streaming media data stream and converts it into a coded data stream in a preset format, and sends the coded data stream to the streaming media display device to be tested through a high-speed data interface. The protocol logic control component and the streaming media data generation component share the external clock signal.

[0010] Furthermore, the controller sends an external clock signal to the streaming media data generating component via an IIC bus.

[0011] Furthermore, the controller is also electrically connected to the protocol logic control component to send configuration information of the streaming media data to the protocol logic control component;

[0012] The configuration information includes: video resolution, front and back porch timing information, frame rate, sampling space and / or bit depth.

[0013] Further, the cache component includes a cache controller and a cache chip;

[0014] The cache controller controls the cache chip to receive or send the streaming media data according to a control signal of the controller.

[0015] Furthermore, the PCIE component is a PCIE 3.0x16 structure.

[0016] Furthermore, the preset format of the encoded data stream includes: HDMI protocol or DP protocol.

[0017] Further, the streaming media interface test signal generating device further comprises: a PHY component;

[0018] The PHY component is connected to the protocol logic control component and the high-speed data interface respectively, converts the encoded data stream output by the protocol logic control component into a physical electrical signal suitable for circuit transmission, and sends it to the streaming media display device to be tested through the high-speed data interface.

[0019] Further, the streaming media interface test signal generating device further comprises: a Re-driver component;

[0020] The Re-driver component is connected to the PHY component and the high-speed data interface respectively to perform signal preprocessing on the physical electrical signal;

[0021] The signal preprocessing includes: signal equalization, signal amplification and pre-emphasis processing.

[0022] Furthermore, the PCIE component, the cache component, the streaming media data generation component, the protocol logic control component and the controller are integrated on one or more FPGA boards.

[0023] The above technical solution of the embodiment of the present invention has the following beneficial technical effects:

[0024] 1. Output videos of any combination of resolutions and formats on demand, supporting non-standard resolution and frame rate output;

[0025] 2. Define the timing information of the output video as needed, such as the number of cycles of the front porch, back porch, synchronization, etc. of the line field;

[0026] 3. It can support the output of large resolution (above 10K), high frame rate (above 120Hz), full sampling space, and full bit depth dynamic configuration, which can meet the requirements of most test scenarios of current video transmission protocols;

[0027] 4. Compared with traditional equipment, the structure size is simplified, and the power consumption and noise are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The present invention is a schematic diagram of the principle of a streaming media interface test signal generating device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0030] Please refer to Figure 1The embodiment of the present invention provides a streaming media interface test signal generating device, including: a PCIE component, a cache component, a streaming media data generating component, a protocol logic control component and a controller; the controller is data-connected with the streaming media data generating component, and sends an external clock signal to the streaming media data generating component; the PCIE component receives the streaming media data and sends the streaming media data to the cache component; the streaming media data generating component obtains the streaming media data in the cache component and parses it, adjusts the resolution and frame frequency of the streaming media data according to the external clock signal, and generates a streaming media data stream corresponding to the timing; the protocol logic control component obtains the streaming media data stream and converts it into a coded data stream in a preset format, and sends the coded data stream to the streaming media display device to be tested through a high-speed data interface, and the protocol logic control component and the streaming media data generating component share the external clock signal.

[0031] The above-mentioned streaming media interface test signal generating device realizes efficient and flexible data processing and accurate generation of streaming media data streams through the coordinated work of PCIE components, cache and streaming media data generation components. The introduction of external clock signals is crucial, which ensures the synchronization between the streaming media data generation components and the protocol logic control components, so that the generated data streams strictly correspond to the timing, thereby improving the accuracy and reliability of the test and ensuring that the streaming media display device can correctly parse and display data.

[0032] The above-mentioned streaming media interface test signal generating device is mainly used to solve the shortcomings of traditional video protocol testing equipment, follow up the current demand for ultra-high-definition display devices, and form a video protocol testing equipment product with ultra-high-definition output capability, flexible configuration, and comprehensive test formats.

[0033] Furthermore, the controller sends an external clock signal to the streaming media data generation component through the IIC bus; the streaming media data generation component adjusts the resolution and frame frequency of the streaming media data according to the external clock signal, effectively improving the flexibility of the output of the test signal generating device, and effectively improving the data transmission quality and stability when testing ultra-high-definition resolution and high frame rate output mode.

[0034] The controller communicates with the streaming data generation component via the IIC (Inter-Integrated Circuit) bus to send a precise external clock signal. The IIC bus is a synchronous multi-host serial communication protocol that allows the controller to transfer data between two devices without occupying a large number of pin resources.

[0035] The external clock signal plays a vital role in streaming media data processing, and determines the timing of data generation component processing and outputting data. The streaming media data generation component synchronizes its internal data processing flow according to the received external clock signal. That is, when the streaming media data generation component receives the clock signal sent by the controller, it adjusts the resolution and frame rate of its output streaming media data according to the frequency and phase of this clock signal. The stability and accuracy of the external clock signal are crucial to ensure smooth and delay-free video playback. If the clock signal is unstable, it may cause video playback to freeze, skip frames, or tear. Therefore, accurate synchronization between the controller and the streaming media data generation component is the key to achieving high-quality streaming media testing.

[0036] Resolution refers to the pixel density of video data, that is, the number of pixels that can be displayed on the screen, while frame rate refers to the number of video frames that can be played per second. By adjusting these two parameters, the streaming media data generation component can generate a video stream suitable for a specific display device. For example, if the tested streaming media display device supports HD resolution and a frame rate of 60 frames per second, the streaming media data generation component will generate a video data stream of corresponding quality based on the external clock signal.

[0037] The above control method realizes dynamic adjustment of the output parameters of the streaming media data generation component through precise control of the IIC bus and the external clock signal to adapt to different test requirements and display device characteristics, thereby ensuring the quality of streaming media data and the accuracy of the test.

[0038] also, Figure 1 CLK1 is the reference clock of the PCIE module; CLK2 is the reference clock of the DDR4 module; CLK5 is the reference clock of the PHY part.

[0039] Furthermore, the controller is also electrically connected to the protocol logic control component to send configuration information of the streaming media data to the protocol logic control component; the configuration information includes: video resolution, front and back shoulder timing information, frame rate, sampling space and / or bit depth; the flexibility and high configurability of the application of the video protocol test equipment are greatly improved, so that the device of the present invention can flexibly cover all test scenarios in the field of ultra-high video protocol testing.

[0040] By adjusting these parameters in real time, the test equipment can adapt to different streaming formats and display device requirements, thereby ensuring effective performance evaluation and quality control under various conditions. Specifically, the configuration of video resolution can affect the clarity and detail of the image, while the adjustment of frame rate is directly related to the smoothness of the video. In addition, the configuration of front and back shoulder timing information ensures the synchronization of the signal, and the setting of sampling space and bit depth affects the color performance and dynamic range. These flexible configuration options enable the test signal generation device to meet the needs of different application scenarios, thereby improving the comprehensiveness and accuracy of the test.

[0041] Furthermore, the cache component includes a cache controller and a cache chip; the cache controller controls the cache chip to receive or send streaming media data according to the control signal of the controller. In streaming media applications, the cache component can effectively reduce the delay of data transmission and improve the efficiency of data transmission. At the same time, the cache component can also provide a certain degree of data redundancy when the network conditions are unstable to ensure the continuity and stability of streaming media services. By dynamically adjusting the cache size and cache strategy, the cache component can adapt to different application scenarios and user needs to achieve efficient resource management and optimization.

[0042] Specifically, the PCIE component is mainly used to drive the PCIE data interface.

[0043] Optionally, the PCIE component is a PCIE 3.0x16 structure with a single lane peak rate of 8GT / s and an available bandwidth of 15.754GB / s, which can fully meet the transmission requirements of various ultra-high-definition video data.

[0044] Specifically, when the PCIE component is a PCIE 3.0x16 structure, it provides an extremely high data transfer rate. The PCIE3.0 standard supports a transfer rate of 8GT / s (Giga transfers per second) per channel. In a x16 configuration, that is, 16 channels, a transfer rate of 128GT / s can be achieved in theory. However, the actual available bandwidth depends on the encoding scheme. PCIE 3.0 uses a 128b / 130b encoding method, in which each 130-bit transmission signal contains 128 bits of valid data and 2 extra bits for error detection. Therefore, the effective bandwidth of each channel is 8GT / s multiplied by 128 / 130, that is, each channel has a bandwidth of approximately 7.877Gbps. For a x16 configuration, the total bandwidth is approximately 7.877Gbps multiplied by 16, which is approximately 126.032Gbps, or 15.754GB / s. This level of bandwidth is ideal for transmitting ultra-high-definition video data, as it can easily handle the amount of data required for 4K, 8K, and even higher resolution videos. For example, 8K video typically requires at least 48Gbps of bandwidth to support uncompressed 4:4:4 chroma sampling, and the bandwidth provided by PCIE 3.0x16 far exceeds this requirement, ensuring that video data can be transmitted quickly and without delay.

[0045] Furthermore, the preset format of the encoded data stream includes: HDMI protocol or DP protocol.

[0046] The protocol logic control component plays a core role in streaming media data transmission and processing. It is mainly responsible for receiving streaming media data streams and converting them into data streams suitable for specific display devices according to preset format requirements. In this process, HDMI protocol and DP protocol are two common preset formats, which correspond to different transmission interfaces and data encoding methods respectively.

[0047] During the conversion of streaming media data, the protocol logic control component needs to select the appropriate encoding and encapsulation method based on the input streaming media data characteristics and the interface requirements of the target display device. For example, for high-definition video data, if the target device supports the HDMI interface, the protocol logic control component may select the H.264 or H.265 encoding format and encapsulate it into a data stream that complies with the HDMI protocol. If the target device supports the DP interface, the protocol logic control component may use a more efficient encoding method, such as H.265 or VP9, ​​and encapsulate the data according to the requirements of the DP protocol.

[0048] In this way, the protocol logic control component ensures that the streaming media data can be transmitted to the target display device in the correct format and encoding, thereby achieving a high-quality video and audio playback experience. This flexibility and configurability enables the component to adapt to a variety of streaming media transmission needs and meet the performance requirements of different application scenarios.

[0049] Furthermore, the streaming media interface test signal generating device also includes: a PHY component; the PHY component is connected to the protocol logic control component and the high-speed data interface respectively, converts the encoded data stream output by the protocol logic control component into a physical electrical signal suitable for circuit transmission, and sends it to the streaming media display device to be tested through the high-speed data interface.

[0050] The PHY (Physical Layer Device) component is a key device that connects the data link layer to the physical medium. It is responsible for converting the encoded data stream output by the protocol logic control component into physical electrical signals suitable for circuit transmission. These signals are then sent to the streaming media display device to be tested through a high-speed data interface. The connection between the PHY component and the protocol logic control component ensures that the data can be transmitted in the correct format and encoding method. It converts digital signals into analog signals at the transmitting end and performs the opposite operation at the receiving end, that is, converting analog signals back to digital signals. This process involves encoding and decoding of signals, as well as possible signal amplification and adjustment to ensure the integrity and reliability of the signal. The PHY component is also responsible for processing all electrical characteristics related to the transmission medium, such as the voltage level of the signal, impedance matching, etc. In high-speed data transmission, the PHY component also involves the functions of clock recovery and data synchronization to ensure the accuracy and stability of the data stream. In the test environment, the PHY component enables the test equipment to simulate the actual signal transmission process, thereby comprehensively evaluating the performance of the streaming media display device. In this way, it can be verified whether the display device can correctly process and display streaming media data and whether it meets specific technical standards and specifications.

[0051] The PHY component is an indispensable part of the streaming media interface test signal generator, which directly affects the quality of the test signal and the accuracy of the test results. Through the high-speed data interface, the PHY component can convert the encoded data stream into a physical electrical signal suitable for circuit transmission, thereby achieving efficient data transmission and device evaluation in the test environment.

[0052] Furthermore, the streaming media interface test signal generating device also includes: a Re-driver component; the Re-driver component is connected to the PHY component and the high-speed data interface respectively to perform signal preprocessing on the physical electrical signal; the signal preprocessing includes: signal equalization, signal amplification and pre-emphasis processing.

[0053] The re-driver component performs signal equalization processing on the physical electrical signal to achieve high-pass filtering of the physical electrical signal, thereby enhancing the high-frequency components of the signal to counteract the attenuation of the high-frequency signal by the transmission medium, thereby reducing inter-symbol interference (ISI); the re-driver component enhances the physical electrical signal to ensure that the signal can still maintain sufficient strength and quality after long-distance transmission. Through pre-emphasis processing, the high-frequency component is enhanced at the signal transmission end to counteract the high-frequency attenuation of the signal in the transmission medium. Pre-emphasis processing helps to ensure that the rising and falling edges of the signal at the receiving end are clear, thereby improving the overall quality of the signal.

[0054] Furthermore, the PCIE component, cache component, streaming media data generation component, protocol logic control component and controller are integrated on one or more FPGA boards. By adopting FPGA boards, the size of the device is effectively reduced in space, making the device more convenient as a whole; compared with graphics card devices with large resolution output, the present invention has relatively low power consumption, saves energy, and eliminates the noise problem caused by high-power fans, making the device more green and environmentally friendly.

[0055] The embodiment of the present invention aims to protect a streaming media interface test signal generating device, including: a PCIE component, a cache component, a streaming media data generating component, a protocol logic control component and a controller; the controller is data-connected with the streaming media data generating component, and sends an external clock signal to the streaming media data generating component; the PCIE component receives the streaming media data, and sends the streaming media data to the cache component; the streaming media data generating component obtains the streaming media data in the cache component and parses it, adjusts the resolution and frame frequency of the streaming media data according to the external clock signal, and generates a streaming media data stream corresponding to the timing; the protocol logic control component obtains the streaming media data stream and converts it into a coded data stream in a preset format, and sends the coded data stream to the streaming media display device to be tested through a high-speed data interface, and the protocol logic control component and the streaming media data generating component share the external clock signal. The above technical solution has the following effects:

[0056] 1. Output videos of any combination of resolutions and formats on demand, supporting non-standard resolution and frame rate output;

[0057] 2. Define the timing information of the output video as needed, such as the number of cycles of the front porch, back porch, synchronization, etc. of the line field;

[0058] 3. It can support the output of large resolution (above 10K), high frame rate (above 120Hz), full sampling space, and full bit depth dynamic configuration, which can meet the requirements of most test scenarios of current video transmission protocols;

[0059] 4. Compared with traditional equipment, the structure size is simplified, and the power consumption and noise are reduced.

[0060] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A streaming media interface test signal generating device, characterized in that: include: PCIE components, cache components, streaming data generation components, protocol logic control components and controllers; The controller is in data communication with the streaming media data generating component and sends an external clock signal to the streaming media data generating component; The PCIE component receives the streaming media data and sends the streaming media data to the cache component; The streaming media data generation component obtains the streaming media data in the cache component and parses it, adjusts the resolution and frame frequency of the streaming media data according to the external clock signal, and generates a streaming media data stream corresponding to the timing; The protocol logic control component obtains the streaming media data stream and converts it into a coded data stream in a preset format, and sends the coded data stream to the streaming media display device to be tested through a high-speed data interface. The protocol logic control component and the streaming media data generation component share the external clock signal.

2. The streaming media interface test signal generating device according to claim 1, characterized in that: The controller sends an external clock signal to the streaming media data generating component via the IIC bus.

3. The streaming media interface test signal generating device according to claim 1, characterized in that: The controller is also electrically connected to the protocol logic control component and sends configuration information of streaming media data to the protocol logic control component; The configuration information includes: video resolution, front and back porch timing information, frame rate, sampling space and / or bit depth.

4. The streaming media interface test signal generating device according to claim 1, characterized in that: The cache component includes a cache controller and a cache chip; The cache controller controls the cache chip to receive or send the streaming media data according to a control signal of the controller.

5. The streaming media interface test signal generating device according to claim 1, characterized in that: The PCIE component has a PCIE 3.0x16 structure.

6. The streaming media interface test signal generating device according to claim 1, characterized in that: The preset format of the encoded data stream includes: HDMI protocol or DP protocol.

7. The streaming media interface test signal generating device according to claim 1, characterized in that: Also includes: PHY components; The PHY component is connected to the protocol logic control component and the high-speed data interface respectively, converts the encoded data stream output by the protocol logic control component into a physical electrical signal suitable for circuit transmission, and sends it to the streaming media display device to be tested through the high-speed data interface.

8. The streaming media interface test signal generating device according to claim 7, characterized in that: Also includes: Re-driver component; The Re-driver component is connected to the PHY component and the high-speed data interface respectively to perform signal preprocessing on the physical electrical signal; The signal preprocessing includes: signal equalization, signal amplification and pre-emphasis processing.

9. The streaming media interface test signal generating device according to any one of claims 1 to 8, characterized in that: The PCIE component, the cache component, the streaming media data generation component, the protocol logic control component and the controller are integrated on one or more FPGA boards.

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