Triple conversion gain pixel

Abstract

The invention relates to a triple conversion gain pixel. A pixel array includes a plurality of pixel cells, each pixel cell including: a photodiode configured to photogenerate an image charge in response to incident light; a first floating diffusion (FD) coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first FD; a second FD coupled between the first FD and ground; a first dual FD transistor is coupled between the first and second FDs. And a second FD coupling the first and second pixel cells. And a second FD coupling the third and fourth pixel cells.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like (e.g., resolution, power consumption, dynamic range) in as many ways as possible, both through device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to advance rapidly. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges after absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies depending on the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted to a digital value to generate a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to a readout circuit that includes an input stage having an analog-to-digital conversion (ADC) circuit to convert those analog image signals from the pixel array into digital image signals. Summary of the invention

[0004] An embodiment of the present disclosure provides a pixel array, comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a corresponding image signal in response to incident light, wherein each of the pixel cells includes: a photodiode configured to photogenerate image charge in response to the incident light; a first floating diffusion (FD) coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first FD; a second FD coupled between the first FD and ground; and a first double floating diffusion transistor coupled between the first and second FDs, wherein the second FD of a first one of the pixel cells is coupled to the second FD of a second one of the pixel cells, and wherein the second FD of a third one of the pixel cells is coupled to the second FD of a fourth one of the pixel cells.

[0005] Another embodiment of the present disclosure provides a pixel array, comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a corresponding image signal in response to incident light, wherein each of the pixel cells includes: a photodiode configured to photogenerate image charge in response to the incident light; a first floating diffusion (FD) coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first FD; a second FD coupled between the first FD and ground; a first double floating diffusion transistor coupled between the first and second FDs; a third FD coupled between the second FD and ground; and a second double floating diffusion transistor coupled between the second and third FDs, wherein the third FD of the first of the pixel cells is coupled to the third FD of the second of the pixel cells.

[0006] Yet another embodiment of the present disclosure provides an imaging system, comprising: a pixel array, comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a corresponding image signal in response to incident light, wherein each of the pixel cells comprises: a plurality of photodiodes configured to photogenerate image charge in response to the incident light; a first floating diffusion (FD) coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first FD; a second FD coupled between the first FD and ground; a first double floating diffusion transistor coupled between the first and second FDs; a third FD coupled between the second FD and ground; and a second double floating diffusion transistor, which is coupled between the second and third FDs, wherein the second FD of the first of the pixel cells is coupled to the second FD of the second of the pixel cells, wherein the second FD of the third of the pixel cells is coupled to the second FD of the fourth of the pixel cells, wherein the third FD of the first of the pixel cells is coupled to the third FD of the third of the pixel cells, and wherein the third FD of the second of the pixel cells is coupled to the third FD of the fourth of the pixel cells; a plurality of bit lines coupled to the pixel array; a control circuit system coupled to the pixel array to control the operation of the pixel array; and a readout circuit system coupled to the pixel array through the bit lines to read out image data from the pixel array. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exclusive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1An example of an imaging system according to the teachings of the present disclosure is described.

[0009] Figure 2A and 2B Schematic diagram illustrating an example pixel cell according to the teachings of the present disclosure.

[0010] Figure 3A , 3B , 3C and 3D illustrate schematic diagrams of multiple example pixel cells according to the teachings of the present disclosure.

[0011] Figure 4 A timing diagram illustrating an example pixel cell in accordance with the teachings of the present disclosure.

[0012] Corresponding reference symbols indicate corresponding components throughout the several views of the drawings. The skilled person will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common and well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate intuitive understanding of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Examples of imaging systems with pixel cells providing triple conversion gain are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, a person skilled in the relevant art should recognize that the techniques described herein may be practiced without one or more of the specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid making certain aspects unclear.

[0014] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Thus, the phrases "in one example" or "in one embodiment" that appear in different places throughout this specification do not necessarily all refer to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0015] For ease of description, spatially relative terms such as "under", "below", "above", "below", "above", "up", "top", "bottom", "left", "right", "center", "middle" and the like may be used herein to describe the relationship between one element or feature illustrated in the figures and another (some) element or feature. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figure. For example, if the device in the figure is rotated or flipped, then the element described as being "under" or "under" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, the exemplary terms "under" and "below" can cover both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or there can also be one or more intervening elements.

[0016] Several technical terms are used throughout this specification. These terms have ordinary meanings in the technologies from which they are derived, unless explicitly defined herein or the context of their use clearly states otherwise. It should be noted that element names and symbols (e.g., Si and silicon) may be used interchangeably throughout this document; however, both have the same meaning.

[0017] As will be discussed, various examples of imaging systems having pixel cells that provide triple conversion gain (TCG) are disclosed. In conventional imaging systems, dual conversion gain (DCG) is used to improve signal-to-noise ratio (SNR) and dynamic range (DR). For example, high conversion gain (HCG) is used in low-light areas to keep readout noise low, and low conversion gain (LCG) is used in bright-light areas to fully utilize the full well capacity (FWC) of the pixel cell. However, when supporting, for example, 50-megapixel images using 4-cell pixel cells and / or 12.5-megapixel images using 16-cell pixel cells with sufficiently high SNR and DR, a third conversion gain mode, medium conversion gain (MCG), may be required.

[0018] In some imaging systems that provide TCG, a first double floating diffusion transistor, a second double floating diffusion transistor, and a reset transistor are coupled in series in the vertical direction. Therefore, although the second floating diffusions of vertically adjacent pixel cells can be coupled, the small pixel cell layout area makes it difficult to couple the third floating diffusions of vertically adjacent pixel cells. Some capacitors corresponding to the floating diffusions may also need to include vertically oriented metal plates. In addition, horizontally adjacent pixel cells do not couple their floating diffusions, making horizontal grading difficult. The target conversion gain ratios between HCG, MCG, and LCG may also be difficult to achieve.

[0019] It will be appreciated that, according to the teachings of the present disclosure, pixel cells providing TCG each include first and second dual floating diffusion transistors coupled in parallel. In addition, coupling the second floating diffusions of vertically adjacent pixel cells, and coupling the third floating diffusions of horizontally adjacent cells, allows for horizontal grading during, for example, LCG readout. Target conversion gain ratios between HCG, MCG, and LCG can also be more easily achieved.

[0020] Thus, as will be shown and described in various examples below, an example pixel array includes a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a respective image signal in response to incident light, wherein each of the pixel cells includes: a photodiode configured to photogenerate image charge in response to incident light; a first floating diffusion (FD) coupled to receive image charge from the photodiode; a reset transistor coupled between a voltage source and the first FD; a second FD coupled between the first FD and the reset transistor; a first double floating diffusion transistor coupled between the first and second FDs; a third FD coupled between the second FD and ground; and a second double floating diffusion transistor coupled between the second and third FDs. The second FD of the first of the pixel cells is coupled to the second FD of the second of the pixel cells. The second FD of the third of the pixel cells is coupled to the second FD of the fourth of the pixel cells. The third FD of the first of the pixel cells is coupled to the third FD of the third of the pixel cells. The third FD of the second of the pixel cells is coupled to the third FD of the fourth of the pixel cells.

[0021] To illustrate, Figure 1 An example of an imaging system 100 having a readout circuit 106 according to the teachings of the present disclosure is shown. Specifically, Figure 1 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1-Ry) and columns (e.g., C1-Cx) to acquire image data of a person, place, object, etc., which may then be used to render an image of the person, place, object, etc.

[0022] In various examples, readout circuitry 106 may be configured to read out image signals via column bit lines 112. As will be discussed, in various examples, readout circuitry 106 may include an analog-to-digital converter (ADC) 107 in accordance with the teachings of the present disclosure. In an example, the digital image data values ​​generated by the analog-to-digital converter in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying image post effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other).

[0023] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect, such as a flash.

[0024] In one example, the imaging system 100 may be included in a digital camera, a cell phone, a laptop computer, an endoscope, a security camera, or an imaging device for an automobile, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, a wireless transmitter, an HDMI port, etc.), a light / flash, an electrical input (keyboard, a touch display, a touch pad, a mouse, a microphone, etc.), and / or a display. The other hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0025] Figure 2A and 2B Schematic diagram illustrating an example pixel cell (ie, pixel circuit) 204 according to the teachings of the present disclosure. It should be appreciated that Figure 2A and 2B The pixel cell 204 may be included in Figure 1 An example of one of the pixel circuits 104 in the imaging system 100 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and operate below.

[0026] refer to Figure 2A, pixel cell 204 includes: a photodiode 214, which is configured to photogenerate image charge in response to incident light; a first floating diffusion portion FD1 218, which is coupled to receive image charge from the photodiode 214; a reset transistor RST 234, which is coupled between a voltage source PIXVDD 260 and FD1 218; a second floating diffusion portion FD2 228, which is coupled between FD1 218 and the reset transistor 234; a first dual floating diffusion transistor DFD1 224, which is coupled between FD1 218 and FD2 228; a third floating diffusion portion FD3 238, which is coupled between FD2 228 and ground; and a second dual floating diffusion transistor DFD2 226, which is coupled between FD2 228 and FD3 238. A first capacitor 219 is coupled between FD1 218 and ground, a second capacitor 229 is coupled between FD2 228 and ground, and a third capacitor 239 is coupled between FD3 238 and ground. The first, second, and third capacitors 219, 229, 239 are configured to store image charge at FD1 218, FD2 228, and FD3 238, respectively.

[0027] FD1 218 is coupled to the gate terminal of source follower transistor SF 220. Source follower transistor 220 is coupled between voltage source PIXVDD 260 and bit line 212 and is configured to convert the charge from FD1 218 into a corresponding voltage signal. Row select transistor RS 222 is coupled between source follower transistor 220 and bit line 212 and is configured to send a voltage signal from source follower transistor 220 to bit line 212 in response to a row select control signal.

[0028] refer to Figure 2B, pixel cell 204 includes: a photodiode 214, which is configured to photogenerate image charge in response to incident light; a first floating diffusion portion FD1 218, which is coupled to receive image charge from the photodiode 214; a reset transistor RST 234, which is coupled between a voltage source PIXVDD 260 and FD1 218; a second floating diffusion portion FD2 228, which is coupled between FD1 218 and ground; a first double floating diffusion transistor DFD1 224, which is coupled between FD1 218 and FD2 228; a third floating diffusion portion FD3 238, which is coupled between FD2 228 and ground; and a second double floating diffusion transistor DFD2 226, which is coupled between FD2 228 and FD3 238. The first capacitor 219 is coupled between FD1 218 and ground, the second capacitor 229 is coupled between FD2 228 and ground, and the third capacitor 239 is coupled between FD3 238 and ground. The first, second, and third capacitors 219, 229, 239 are configured to store image charge at FD1 218, FD2 228, and FD3 238, respectively. In some embodiments, the pixel cell 204 may not include FD3 238 or the third capacitor 239, as will be described below with respect to FIG. Figure 3C Described in further detail.

[0029] and Figure 2A Compared to the example pixel cell 204 illustrated in FIG. Figure 2B The example pixel cell 204 illustrated in FIG. 1 includes FD1 218 coupled between a reset transistor RST 234 and a first dual floating diffusion transistor DFD1 224. However, in Figure 2A and 2B In both, FD1 218, FD2 228, and FD3 238 are coupled in series, while the first double floating diffusion transistor DFD1 224 and the second double floating diffusion transistor DFD2 226 are coupled in parallel between FD2 228 and ground.

[0030] It should also be understood that Figure 2A and 2BIn both, the first, second and third capacitors 219, 229, 239 may have different capacitance ratios. For example, the second capacitor 229 may have the same capacitance as the first capacitor 219, and the third capacitor 239 may have twice the capacitance of the first capacitor 219. In another example, the second capacitor 229 may have 1.5 times the capacitance of the first capacitor 219, and the third capacitor 239 may also have 1.5 times the capacitance of the first capacitor 219. It should be further understood that each of the first, second and third capacitors 219, 229, 239 may be a horizontal or vertical metal-insulator-metal capacitor. Horizontal is defined as such that the metal plates of the capacitor are substantially parallel to the rows of the pixel array (e.g., Figure 1 Vertical is defined as such that the metal plates of the capacitor are substantially parallel to the columns of the pixel array (e.g., Figure 1 Columns C1 to Cx) of the pixel array 102 illustrated in FIG. 1 extend.

[0031] Figure 3A , 3B , 3C and 3D illustrate multiple example pixel cells 304a, 304b, 304c, 304d ( Figure 3D 304a and 304b). Certain circuit components of each pixel cell (e.g., photodiode, transfer transistor, source follower transistor, row select transistor) are omitted from the illustrated schematics so as not to obscure the novel features of the present disclosure. It should be understood that Figure 3A , 3B Each of the pixel cells 304a, 304b, 304c, 304d of 3C and 3D may be included in Figure 1 An example of one of the pixel circuits 104 in the imaging system 100 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and operate below.

[0032] refer to Figure 3A , each of the pixel cells 304a to d may be Figure 2A. In the illustrated example, the first pixel cell 304a is arranged vertically adjacent to the second pixel cell 304b and horizontally adjacent to the third pixel cell 304c. Vertically adjacent is defined such that the first and second pixel cells 304a, 304b are located in adjacent (e.g., adjacent) rows (e.g., rows R1 and R2 of the pixel array 102). Horizontally adjacent is defined such that the first and third pixel cells 304a, 304c are located in adjacent (e.g., adjacent) columns (e.g., columns C1 and C2 of the pixel array 102). Continuing with the illustrated example, the second pixel cell 304b is arranged horizontally adjacent to the fourth pixel cell 304d. The third pixel cell 304c is arranged vertically adjacent to the fourth pixel cell 304d.

[0033] Each pixel cell 304 includes (labeled with a, b, c or d) a first floating diffusion FD1 318, a first capacitor 319, a second floating diffusion FD2 328, a second capacitor 329, a third floating diffusion FD3 338, a third capacitor 339, a first double floating diffusion transistor DFD1 324, a second double floating diffusion transistor DFD2 326 and a reset transistor RST 334 coupled to a voltage source PIXVDD360, which can be a global voltage source coupled to all pixel cells in the pixel array.

[0034] The circuit elements of the first pixel cell 304a and the circuit elements of the second pixel cell 304b can be arranged in the same or substantially similar manner, as shown. Similarly, the circuit elements of the third pixel cell 304c and the circuit elements of the fourth pixel cell 304d can be arranged in the same or substantially similar manner, as shown. On the other hand, the circuit elements of the first pixel cell 304a and the circuit elements of the third pixel cell 304c can be arranged in a substantially mirrored (i.e., symmetrical) manner, as shown. Similarly, the circuit elements of the second pixel cell 304b and the circuit elements of the fourth pixel cell 304d can also be arranged in a substantially mirrored (i.e., symmetrical) manner, as shown. These arrangements provide the advantage of achieving easier connection between individual pixel cells, as will be described in further detail below.

[0035] FD2 328a of the first pixel cell 304a may be vertically coupled (e.g., across adjacent rows) to FD2 328b of the second pixel cell 304b via a first vertical connection 352. Similarly, FD2 328c of the third pixel cell 304c may be vertically coupled (e.g., across adjacent rows) to FD2 328d of the fourth pixel cell 304d via a second vertical connection 354.

[0036] FD3 338a of the first pixel cell 304a may be horizontally coupled (e.g., across adjacent columns) to FD3 338c of the third pixel cell 304c via a first horizontal connection 356. Similarly, FD3 328b of the second pixel cell 304b may be horizontally coupled (e.g., across adjacent columns) to FD3 338d of the fourth pixel cell 304d via a second horizontal connection 358.

[0037] The pixel cell arrangement described above provides several advantages. A group of four pixel cells 304 includes a total of eight floating diffusions: four FD1 318, two vertically shared FD2 328, and two horizontally shared FD3 338. This layout is more feasible than other layouts that incorporate three floating diffusions per pixel cell. Since FD3 338 is horizontally coupled, this layout also achieves horizontal grading. In addition, the first, second, and third capacitors 319, 329, 339 can be formed using horizontally oriented metal plates, reducing the number of cross-couplings of the first capacitor 319 without changing the existing control lines.

[0038] In some embodiments, the second floating diffusion FD2 328 of each pixel cell may be coupled to the second floating diffusion FD2 328 of a horizontally adjacent pixel cell via a horizontal connection. In some embodiments, the third floating diffusion FD3 338 of each pixel cell may be coupled to the third floating diffusion FD3 338 of a vertically adjacent pixel cell via a vertical connection.

[0039] refer to Figure 3B , each of the pixel cells 304a to d may be Figure 2B 328a of the first pixel cell 304a is vertically coupled (e.g., spanning adjacent rows) to FD2 328b of the second pixel cell 304b via a first vertical connection 352. Similarly, FD2 328c of the third pixel cell 304c is vertically coupled (e.g., spanning adjacent rows) to FD2 328d of the fourth pixel cell 304d via a second vertical connection 354. FD3 338a of the first pixel cell 304a is horizontally coupled (e.g., spanning adjacent columns) to FD3 338c of the third pixel cell 304c via a first horizontal connection 356. Similarly, FD3 328b of the second pixel cell 304b is horizontally coupled (e.g., spanning adjacent columns) to FD3 338d of the fourth pixel cell 304d via a second horizontal connection 358.

[0040] refer to Figure 3C, the second floating diffusions FD2 of the first pixel cell 304a and the second pixel cell 304b may be coupled together or "merged" to form a first shared second floating diffusion FD2 328-1. The first shared second capacitor 329-1 may be coupled to FD2 328-1. Similarly, the second floating diffusions FD2 of the third pixel cell 304c and the fourth pixel cell 304d may be coupled together or "merged" to form a second shared second floating diffusion FD2 328-2. The second shared second capacitor 329-2 may be coupled to FD2 328-2. In addition, the third floating diffusion of each pixel may not be included or "merged" with the second floating diffusion FD2 of the adjacent pixel. For example, FD2 328-2 may be used as the third floating diffusion of the first and second pixel cells 304a, 304b, while FD2 328-1 may be used as the third floating diffusion of the third and fourth pixel cells 304c, 304d. The shared second floating diffusion transistor DFD2 326 may be coupled between the first and second shared second floating diffusions FD2 328 - 1 , 328 - 2 via a horizontal connection 356 .

[0041] refer to Figure 3D , the third floating diffusions FD3 338a, 338b of the first and second pixel cells 304a, 304b may be coupled together or "merged" via a vertical connection 352. In the illustrated example, Figure 3A In contrast to the embodiment illustrated in C, the first and second pixel cells 304a, 304b are not coupled to other pixel cells (eg, via horizontal connections) such that each group of pixel cells includes two pixel cells.

[0042] Figure 4 A timing diagram illustrating an example pixel cell providing triple conversion gain (TCG) according to the teachings of the present disclosure. The timing diagram includes a high conversion gain (HCG) readout, a medium conversion gain (MCG) readout, and a low conversion gain (LCG) readout. It should be understood that Figure 4 The timing diagram of may be an example timing diagram for each of the pixel circuits 304a, 304b, 304c, 304d as shown in FIG. 3, and similarly named and numbered elements described above are similarly coupled and operate below.

[0043] In the illustrated example, both the first double floating diffusion control signal DFD1 424 and the second double floating diffusion control signal DFD2 426 are configured to be turned off at the beginning of the readout cycle. During HCG readout, because both the first and second double floating diffusion transistors are turned off, the image charge photogenerated by the photodiode can only be stored in the first floating diffusion (e.g., FD1 318a illustrated in FIG. 3). By preventing access to other floating diffusions, HCG readout is configured to maintain low readout noise.

[0044] After HCG readout and before MCG readout, the first dual floating diffusion control signal DFD1 426 is configured to be turned on, while the second dual floating diffusion control signal DFD2 426 is configured to remain off. During MCG readout, because only the first dual floating diffusion transistor is turned on, the image charge photogenerated by the photodiode can be stored in both the first floating diffusion and the second floating diffusion (e.g., FD2 328a).

[0045] After MCG readout and before LCG readout, the second dual floating diffusion control signal DFD2 426 is configured to be turned on, while the first dual floating diffusion control signal DFD1 426 is configured to remain on. During LCG readout, because both the first and second dual floating diffusion transistors are turned on, image charge photogenerated by the photodiode can be stored in the first floating diffusion, the second floating diffusion, and the third floating diffusion (e.g., FD3 338a). By allowing access to three floating diffusions, LCG readout is configured to maximize utilization of the full well capacity of the pixel cell and thereby increase dynamic range.

[0046] Figure 4 The timing diagram illustrated in provides several advantages. By providing triple conversion gain, the pixel cell has an improved dynamic range and allows the imaging system to capture images with different brightness areas with more detail and image quality. The imaging system also has greater flexibility because it can choose from three different conversion gain modes (rather than just one or two). In addition, by coupling the floating diffusion portions of different pixel cells together, the full well capacity of each pixel cell and the conversion gain ratio between the three different conversion gain modes are increased. For example, an imaging system configured according to the teachings of the present disclosure may have a conversion gain ratio of 16:4:1 between HCG:MCG:LCG. In various instances, the effective conversion gain of the HCG and MCG readouts is half of the aforementioned conversion gain, resulting in an effective conversion gain ratio of 8:2:1 between HCG:MCG:LCG.

[0047] The above description of the illustrated examples of the present disclosure (including what is described in the Abstract) is not intended to be exclusive or to limit the present disclosure to the precise forms disclosed. As will be appreciated by those skilled in the relevant art, although specific examples of the present disclosure are described herein for illustrative purposes, various modifications within the scope of the present disclosure are possible.

[0048] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the present disclosure to the specific examples disclosed in this specification. Rather, the scope of the present disclosure should be determined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

Claims

1. A pixel array, comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a respective image signal in response to incident light, wherein each of the pixel cells comprises: a photodiode configured to photogenerate image charge in response to the incident light; a first floating diffusion coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first floating diffusion; a second floating diffusion coupled between the first floating diffusion and ground; and a first double floating diffusion transistor coupled between the first and second floating diffusions, wherein a second floating diffusion of a first one of the pixel cells is coupled to a second floating diffusion of a second one of the pixel cells, and The second floating diffusion of a third one of the pixel cells is coupled to the second floating diffusion of a fourth one of the pixel cells. 2 . The pixel array of claim 1 , further comprising a second double floating diffusion transistor coupled to the second floating diffusions of the first, second, third, and fourth ones of the pixel cells.

3. The pixel array of claim 1 , wherein each of the pixel cells further comprises: a third floating diffusion coupled between the second floating diffusion and ground; and a second double floating diffusion transistor coupled between the second and third floating diffusions, wherein a third floating diffusion of the first one of the pixel cells is coupled to a third floating diffusion of the third one of the pixel cells, and The third floating diffusion of the second one of the pixel cells is coupled to the third floating diffusion of the fourth one of the pixel cells.

4. A pixel array according to claim 3, wherein the first and second dual floating diffusion transistors of each of the pixel cells are configured to be turned off during a high conversion gain readout, wherein the first dual floating diffusion transistor of each of the pixel cells is configured to be turned on during a medium conversion gain readout and the second dual floating diffusion transistor of each of the pixel cells is configured to be turned off during a medium conversion gain readout, and wherein the first and second dual floating diffusion transistors of each of the pixel cells are configured to be turned on during a low conversion gain readout.

5. The pixel array of claim 1 , wherein the second floating diffusion of the first of the pixel cells is vertically coupled to the second floating diffusion of the second of the pixel cells, and wherein the second floating diffusion of the third of the pixel cells is vertically coupled to the second floating diffusion of the fourth of the pixel cells.

6. The pixel array of claim 3, wherein the third floating diffusion of the first of the pixel cells is horizontally coupled to the third floating diffusion of the third of the pixel cells, and wherein the third floating diffusion of the second of the pixel cells is horizontally coupled to the third floating diffusion of the fourth of the pixel cells.

7. The pixel array of claim 3, wherein each of the pixel cells further comprises: a first capacitor coupled between the first floating diffusion and ground; a second capacitor coupled between the second floating diffusion and ground; and A third capacitor is coupled between the third floating diffusion and ground. 8 . The pixel array of claim 7 , wherein the second capacitor has the same capacitance as the first capacitor, and wherein the third capacitor has twice the capacitance of the first capacitor. 9 . The pixel array of claim 7 , wherein the second capacitor has a capacitance 1.5 times that of the first capacitor, and wherein the third capacitor has a capacitance 1.5 times that of the first capacitor.

10. The pixel array of claim 7, wherein each of the first, second, and third capacitors is a horizontal metal-insulator-metal capacitor.

11. A pixel array comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a respective image signal in response to incident light, wherein each of the pixel cells comprises: a photodiode configured to photogenerate image charge in response to the incident light; a first floating diffusion coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first floating diffusion; a second floating diffusion coupled between the first floating diffusion and ground; a first dual floating diffusion transistor coupled between the first and second floating diffusions; a third floating diffusion coupled between the second floating diffusion and ground; and a second double floating diffusion transistor coupled between the second and third floating diffusions, Wherein a third floating diffusion of a first one of the pixel cells is coupled to a third floating diffusion of a second one of the pixel cells.

12. An imaging system comprising: A pixel array comprising: a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is configured to generate a respective image signal in response to incident light, wherein each of the pixel cells comprises: a plurality of photodiodes configured to photogenerate image charge in response to the incident light; a first floating diffusion coupled to receive the image charge from the photodiode; a reset transistor coupled between a voltage source and the first floating diffusion; a second floating diffusion coupled between the first floating diffusion and ground; a first dual floating diffusion transistor coupled between the first and second floating diffusions; a third floating diffusion coupled between the second floating diffusion and ground; and a second double floating diffusion transistor coupled between the second and third floating diffusions, wherein a second floating diffusion of a first one of the pixel cells is coupled to a second floating diffusion of a second one of the pixel cells, wherein the second floating diffusion of a third one of the pixel cells is coupled to the second floating diffusion of a fourth one of the pixel cells, wherein a third floating diffusion of the first one of the pixel cells is coupled to a third floating diffusion of the third one of the pixel cells, and wherein a third floating diffusion of the second one of the pixel cells is coupled to a third floating diffusion of the fourth one of the pixel cells; a plurality of bit lines coupled to the pixel array; control circuitry coupled to the pixel array to control operation of the pixel array; and Readout circuitry is coupled to the pixel array through the bit lines to read out image data from the pixel array.

13. An imaging system according to claim 12, wherein the first and second dual floating diffusion transistors of each of the pixel cells are configured to be turned off during a high conversion gain readout, wherein the first dual floating diffusion transistor of each of the pixel cells is configured to be turned on during a medium conversion gain readout and the second dual floating diffusion transistor of each of the pixel cells is configured to be turned off during a medium conversion gain readout, and wherein the first and second dual floating diffusion transistors of each of the pixel cells are configured to be turned on during a low conversion gain readout.

14. The imaging system of claim 12, wherein the second floating diffusion of the first of the pixel cells is vertically coupled to the second floating diffusion of the second of the pixel cells, and wherein the second floating diffusion of the third of the pixel cells is vertically coupled to the second floating diffusion of the fourth of the pixel cells.

15. The imaging system of claim 12, wherein the third floating diffusion of the first of the pixel cells is horizontally coupled to the third floating diffusion of the third of the pixel cells, and wherein the third floating diffusion of the second of the pixel cells is horizontally coupled to the third floating diffusion of the fourth of the pixel cells.

16. The imaging system of claim 12, wherein the first and second ones of the pixel cells are arranged symmetrically with the third and fourth ones of the pixel cells.

17. The imaging system of claim 12, wherein each of the pixel cells further comprises: a first capacitor coupled between the first floating diffusion and ground; a second capacitor coupled between the second floating diffusion and ground; and A third capacitor is coupled between the third floating diffusion and ground.

18. The imaging system of claim 17, wherein the second capacitor has the same capacitance as the first capacitor, and wherein the third capacitor has twice the capacitance of the first capacitor.

19. The imaging system of claim 17, wherein the second capacitor has a capacitance 1.5 times that of the first capacitor, and wherein the third capacitor has a capacitance 1.5 times that of the first capacitor.

20. The imaging system of claim 17, wherein each of the first, second, and third capacitors is a horizontal metal-insulator-metal capacitor.

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