Image sensor

Abstract

To provide an image sensor with high quality by preventing coupling between constituent elements in a pixel circuit.SOLUTION: An image sensor according to the present invention includes a pixel array including a plurality of pixels arranged in matrix. Each of the pixels includes at least one photoelectric conversion element, at least one floating diffusion region to which a charge of the photoelectric conversion element is transmitted, a reset transistor that transmits the voltage of a reset node to at least one floating diffusion region, a source follower transistor having one end connected to a pixel voltage node and outputting a sampling voltage corresponding to the charge in the floating diffusion region, and a selection transistor having one end connected to a source node of the source follower transistor and outputting the sampling voltage to an output node.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal, and can be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type.

[0003] The CMOS image sensor is abbreviated as CIS. The CIS has a plurality of pixels arranged dimensionally. Each pixel includes a photodiode (PD) and a pixel circuit connected thereto.

[0004] As image sensors become more sophisticated and smaller, pixel circuits are becoming increasingly miniaturized. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent No. 11,317,043 B2 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to prevent coupling between components in a pixel circuit to provide a high quality image sensor. [Means for solving the problem]

[0007] According to an embodiment of the present invention, an image sensor includes a pixel array having a plurality of pixels arranged in a matrix, each of the plurality of pixels including at least one photoelectric conversion element, at least one floating diffusion region to which charges of the photoelectric conversion element are transferred, a reset transistor transferring a voltage of a reset node to the at least one floating diffusion region, a source follower transistor having one end connected to a pixel voltage node and outputting a sampling voltage corresponding to charges of the floating diffusion region, and a selection transistor having one end connected to the source follower transistor and outputting the sampling voltage to an output node. A shielding portion doped with impurities is provided between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel.

[0008] In one embodiment of the invention, the shielding portion may be provided between at least one floating diffusion region of the first pixel and the pixel voltage node of the second pixel.

[0009] In one embodiment of the present invention, the shielding portion may be a region in the semiconductor substrate doped with impurities having a first conductivity type, and the floating diffusion region may be a region in the semiconductor substrate doped with impurities having a second conductivity type opposite to the first conductivity type.

[0010] In one embodiment of the present invention, the shielding portion may be configured to have a constant voltage applied thereto.

[0011] In one embodiment of the present invention, the shielding portion may be provided along a row direction of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel.

[0012] In one embodiment of the present invention, the shielding portion may be provided along a column direction of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel.

[0013] In one embodiment of the present invention, the shielding portion may be provided along row and column directions of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel.

[0014] In an embodiment of the present invention, at least one floating diffusion region of the first pixel may be adjacent to an output node of the second pixel via the shielding portion.

[0015] In an embodiment of the present invention, at least one floating diffusion region of the first pixel may be adjacent to a source node of the source follower transistor of the second pixel via the shielding portion.

[0016] The image sensor according to an embodiment of the present invention may further include a first semiconductor substrate and a second semiconductor substrate stacked in sequence, in which the photoelectric conversion element may be provided on the first semiconductor substrate, and the at least one floating diffusion region, the reset transistor, the source follower transistor, and the selection transistor may be provided on the second semiconductor substrate. Effect of the Invention

[0017] An image sensor according to an embodiment of the present invention prevents coupling between components in a pixel circuit, thereby reducing defects resulting from the coupling.

[0018] In particular, an image sensor according to an embodiment of the present invention provides a high quality image sensor by preventing coupling between the floating diffusion region and other components and preventing white ghost spot defects caused by the coupling. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram of an image sensor according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram of a pixel in an image sensor according to an embodiment of the present invention. [Figure 3A] 1 is a diagram conceptually illustrating a layout of an image sensor according to an embodiment of the present invention. [Figure 3B] 1 is a diagram conceptually illustrating a layout of an image sensor according to an embodiment of the present invention. [Figure 4] 1 is a plan view of an image sensor according to an embodiment of the present invention; [Figure 5A] 2 is a diagram showing first and second pixels adjacent to each other along a first direction in an image sensor. [Figure 5B] 5 is a plan view showing a part of the configuration provided in the first structure in FIG. 4. [Figure 5C] FIG. 5 is a plan view showing a part of the configuration provided in the second structure in FIG. 4. [Figure 6] 5 is a cross-sectional view taken along line AA' in FIG. 4. [Figure 7A] FIG. 5B is a cross-sectional view corresponding to line AA' in FIG. 5A, showing a case where no shielding portion is provided. [Figure 7B] 5B is a cross-sectional view corresponding to line AA' in FIG. 5A, showing a case where a shielding portion is provided. [Figure 8A] FIG. 5B is a cross-sectional view corresponding to line BB' in FIG. 5A, showing a case where no shielding portion is provided. [Figure 8B] 5B is a cross-sectional view corresponding to line BB' in FIG. 5A, showing a case where a shielding portion is provided. [Figure 9] 4 is a diagram showing a first pixel and a second pixel adjacent to each other along a second direction in an image sensor. [Figure 10A] FIG. 9B is a cross-sectional view corresponding to line CC' in FIG. 9A, showing a case where no shielding portion is provided. [Figure 10B] FIG. 9B is a cross-sectional view corresponding to line CC' in FIG. 9A, showing a case where a shielding portion is provided. [Figure 11] 10A and 10B are diagrams illustrating an image sensor according to an embodiment of the present invention in which a shape of a shielding portion is different from that of the above-described embodiment. [Figure 12] 10A and 10B are diagrams illustrating an image sensor according to an embodiment of the present invention in which a shape of a shielding portion is different from that of the above-described embodiment. [Figure 13] 1 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Since the present invention can be modified in various ways and can have various forms, a specific embodiment is illustrated in the drawings and described in detail in the text, but this is not intended to limit the present invention to the specific embodiment, and it should be understood that the present invention includes all modifications, equivalents, and alternatives included in the spirit and technical scope of the present invention.

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0022] FIG. 1 is a block diagram of an image sensor according to an embodiment of the present invention.

[0023] Referring to FIG. 1, an image sensor according to an embodiment of the present invention includes a pixel array (1), a row decoder (2), a row driver (3), a column decoder (4), a timing generator (5), a correlated double sampler (CDS; 6), an analog to digital converter (ADC; 7), and an input / output buffer (I / O buffer; 8).

[0024] The pixel array 1 includes a plurality of unit pixels arranged two-dimensionally, and converts optical signals into electrical signals. The pixel array 1 can be driven by a pixel selection signal, a reset signal, a charge transfer signal, and a plurality of drive signals from a row driver 3. The converted electrical signals are provided to a correlated double sampler 6.

[0025] The row driver 3 provides a number of drive signals for driving a number of unit pixels to the pixel array 1 according to the result decoded by the row decoder 2. When the unit pixels are arranged in a matrix, a drive signal may be provided for each row.

[0026] A timing generator 5 provides timing and control signals to the row decoder 2 and the column decoder 4 .

[0027] The correlated double sampler 6 receives, holds, and samples the electrical signal generated by the pixel array 1. The correlated double sampler double samples a specific noise level and a signal level according to the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0028] The analog-to-digital converter 7 converts the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal.

[0029] The input / output buffer 8 latches the digital signals, and outputs the latched signals to a video signal processor (not shown) in sequence according to the result of decoding by the column decoder 4 .

[0030] FIG. 2 is a circuit diagram of a pixel in an image sensor according to an embodiment of the present invention.

[0031] Referring to FIG. 2, a pixel PXL of an image sensor may include at least one photoelectric conversion element PD, at least one floating diffusion region to which the at least one photoelectric conversion element PD is transferred, a plurality of transistors, and a plurality of nodes. The floating diffusion region may optionally include a first floating diffusion region FD1 and a second floating diffusion region FD2. The pixel PXL may be a unit pixel of the pixel array 1 disclosed in FIG. 1 or may correspond thereto. According to an embodiment, the floating diffusion region may include only the first floating diffusion region FD1 among the first and second floating diffusion regions FD1 and FD2. The transistors included in the pixel PXL may include a transfer transistor (TD), a reset transistor (RX), a source follower transistor (SF), a selection transistor (SEL), and a dual conversion gain transistor (DCX).

[0032] In this embodiment, one pixel PXL is disclosed as including one transmission transistor TX and one photoelectric conversion element PD, but the present invention is not limited thereto, and the number of transmission transistors TX and / or photoelectric conversion elements PD in each pixel PXL may be two or more.

[0033] The photoelectric conversion element PD can generate and accumulate electric charges corresponding to incident light. The photoelectric conversion element PD can be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0034] The transfer transistor TX is connected to the first floating diffusion region FD1 and transfers the charges accumulated in the photoelectric conversion element PD to the first floating diffusion region FD1.

[0035] The first floating diffusion region FD1 receives and cumulatively stores the charges generated by the photoelectric conversion element PD, and the source follower transistor SF can be controlled according to the amount of photocharges stored in the first floating diffusion region FD1.

[0036] The reset transistor RX transfers the voltage of the reset node to at least one floating diffusion region, for example, the second floating diffusion region FD2. In response to a reset signal applied to the reset gate RG, charges stored in the first floating diffusion region FD1 and the second floating diffusion region FD2 may be periodically reset. The drain of the reset transistor RX may be connected to the dual conversion gain transistor DCX, and the source may be connected to the pixel power supply voltage Vdd. In this case, the reset node may be the same as or different from the pixel voltage node. However, the reset node and the pixel voltage node may be different from each other in other embodiments.

[0037] When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power supply voltage Vdd is transferred to the first and second floating diffusion regions FD1 and FD2, so that the charges accumulated in the first and second floating diffusion regions FD1 and FD2 are discharged and the first and second floating diffusion regions FD1 and FD2 may be reset.

[0038] The dual conversion gain transistor DCX may be connected between the first floating diffusion region FD1 and the second floating diffusion region FD2. The dual conversion gain transistor DCX may be connected in series with the reset transistor RX through the second floating diffusion region FD2. That is, the dual conversion gain transistor DCX may be connected between the first floating diffusion region FD1 and the reset transistor RX. The dual conversion gain transistor DCX may vary the conversion gain of the pixel PXL by varying the first capacitance CFD1 of the first floating diffusion region FD1 in response to a dual conversion gain control signal.

[0039] Specifically, when an image is captured, low or high illuminance light may be incident on the pixel array, or strong or weak light may be incident on the pixel array. Thus, the conversion gain of each pixel PXL may be variable according to the incident light. When the dual conversion gain transistor DCX is turned off, the unit pixel PXL may have a first conversion gain, and when the dual conversion gain transistor DCX is turned on, the unit pixel PXL may have a second conversion gain lower than the first conversion gain. That is, different conversion gains may be provided in a first conversion gain mode (or high illuminance mode) and a second conversion gain mode (or low illuminance mode) according to the operation of the dual conversion gain transistor DCX.

[0040] When the dual conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion region FD1 may correspond to the first capacitance CFD1. When the dual conversion gain transistor DCX is turned on, the first floating diffusion region FD1 is connected to the second floating diffusion region FD2, and the capacitance of the first and second floating diffusion regions FD1 and FD2 may be a combination of the first and second capacitances CFD1 and CFD2. In other words, when the dual conversion gain transistor DCX is turned on, the capacitance of the first or second floating diffusion region FD1 or FD2 increases, and the conversion gain decreases, and when the dual conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion region FD1 decreases, and the conversion gain increases.

[0041] The source follower transistor SF has one end connected to a pixel voltage node and outputs a sampling voltage corresponding to the charge of the floating diffusion region FD. The source follower transistor SF may be a source follower buffer amplifier that generates a source-drain current in proportion to the amount of charge of the first floating diffusion region FD1 input to a source follower gate. The source follower transistor SF amplifies a potential change in the first floating diffusion region FD1 and outputs the amplified sampling voltage to an output line Vout through the selection transistor SEL. The drain of the source follower transistor SF may be connected to a pixel power supply voltage Vdd, and the source of the source follower transistor SF may be connected to the selection transistor SEL.

[0042] A selection transistor SEL is connected to the other end of the source follower transistor SF and outputs the sampling voltage to an output node. The selection transistor SEL can select a unit pixel to be read out row by row in a pixel array (e.g., pixel array 1 in FIG. 1). When the selection transistor SEL is turned on by a selection signal applied to the gate of the selection transistor, the selection transistor SEL can output an electrical signal output to the source of the source follower transistor SF to an output line Vout.

[0043] In one embodiment of the present invention, the pixel PXL may be implemented on at least one structure including a semiconductor substrate. The structure may be formed as one or more structures. When the structure is formed as multiple structures, they may be stacked sequentially.

[0044] 3A and 3B are diagrams conceptually illustrating a layout of an image sensor according to an embodiment of the present invention, and FIG. 4 is a plan view showing the image sensor of FIGS. 3A and 3B.

[0045] 3A, 3B, and 4, the image sensor may include a plurality of structures stacked along one direction. For example, the image sensor may include a first structure S1 and a second structure S2 stacked along a third direction D3 as shown in FIG 3A, or a first to third structures S1, S2, and S3 stacked along the third direction D3 as shown in FIG 3B.

[0046] The multiple structures may form a chip, and the sizes of the structures may be the same or different from each other. For example, the area of ​​the first structure S1 in a plan view may be smaller than the area of ​​the second structure S2 and / or the third structure S3.

[0047] A joint (not shown) for joining the two structures adjacent to each other may be provided between the two structures. In the following, the direction in which the second structure S2 and the first structure S1 are stacked is described as a third direction D3 (vertical direction in the drawing), and two directions that intersect with each other on a plane perpendicular to the third direction D3 are described as a first direction D1 and a second direction D2. However, in this description, the first to third directions D1, D2, and D3 are relative directions set for the sake of simplicity of description, and may be configured in different directions in the actual product.

[0048] The first structure S1 to the third structure S1, S2, and S3 may include a pixel array region APS and a pad region PDA adjacent to the pixel array region APS. The pixel array region APS may be disposed in the center of the image sensor in a plan view. The pixel array region APS may include a plurality of pixels PXL.

[0049] The pixels PXL can output photoelectric signals from incident light. The pixels PXL can be arranged in rows and columns in a two-dimensional manner. The rows can be parallel to a first direction D1. The columns can be parallel to a second direction D2.

[0050] The pad area PDA may correspond to an edge portion of the image sensor, and may be provided in at least one of the first structure S1 to the third structure S3.

[0051] In a plan view, the pad area PDA may surround the pixel array area APS. A signal pad SPD may be provided on the pad area PDA. The signal pad SPD may output an electrical signal generated in the pixel PXL to the outside. Alternatively, an external electrical signal or voltage may be transmitted to the pixel PXL through the signal pad SPD. Since the pad area PDA is an edge area of ​​the first semiconductor substrate 10, the signal pad SPD may be easily connected to the outside.

[0052] In the present invention, components in one pixel may be provided in different structures and connected to each other. When a pixel is provided in a plurality of stacked structures, for example, a first structure and a second structure, some components may be provided in the first structure and the remaining components may be provided in the second structure. For example, a photoelectric conversion element, a transfer transistor, and a first floating diffusion region may be provided in the first structure, and the remaining first and second floating diffusion regions and transistors (for example, a reset transistor, a source follower transistor, a selection transistor, and a dual conversion gain transistor) may be provided in the second structure. A logic circuit for controlling the pixel may be provided in the second and / or third structures S2 and S3. Here, the first floating diffusion region of the first structure corresponds to the same node as the first floating diffusion region of the second structure, as they are directly connected to each other through another wiring.

[0053] The logic circuitry may include circuitry for processing pixel signals from the pixels, for example, the logic circuitry may include a control register block, a timing generator, a row driver, a readout circuit, a ramp signal generator, an image signal processor, etc.

[0054] In an embodiment of the present invention, a memory element may be further disposed in the second and / or third structures S2, S3. As the memory element, a dynamic random access memory (DRAM) element, a static random access memory (SRAM) element, a spin transfer torque magnetic random access memory (STT-MRAM) element, a flash memory element, etc. may be formed in an embedded form. The image sensor temporarily stores a frame image and performs signal processing using such a memory element, thereby minimizing the zero effect and improving the operating characteristics of the image sensor. In addition, the memory element of the image sensor may be formed together with a logic element in an embedded form, thereby simplifying the manufacturing process and reducing the size of the product.

[0055] In one embodiment of the present invention, the first and second floating diffusion regions, the reset transistor, the source follower transistor, the select transistor, the dual conversion gain transistor, etc. may be provided in the second structure S2, and the logic circuitry may be provided in the third structure S3. In another embodiment, some of the first and second floating diffusion regions, the reset transistor, the source follower transistor, the select transistor, the dual conversion gain transistor, etc. may be provided in the second structure S2, and other parts of the first and second floating diffusion regions, the reset transistor, the source follower transistor, the select transistor, the dual conversion gain transistor, etc., and the logic circuitry may be provided in the third structure S3. Alternatively, in some embodiments, the first and second floating diffusion regions, the reset transistor, the source follower transistor, the select transistor, the dual conversion gain transistor, etc., and the logic circuitry may all be provided in the second structure S2.

[0056] In the following, for the sake of simplicity, it will be described as an example that pixel components are provided in the first structure and the second structure, specifically, the first structure is provided with a photoelectric conversion element, a transfer transistor, and a first floating diffusion region, and the second structure is provided with first and second floating diffusion regions, a reset transistor, a source follower transistor, a selection transistor, and a dual conversion gain transistor.

[0057] Fig. 5A shows first and second pixels adjacent to each other along a first direction in an image sensor. Fig. 5B is a plan view showing a part of the configuration provided to the first structure in Fig. 4, and Fig. 5C is a plan view showing a part of the configuration provided to the second structure in Fig. 4. Fig. 6 is a cross-sectional view taken along line A-A' in Fig. 4. Figs. 5A to 5C mainly show transistors for ease of explanation, and in Fig. 5A, for ease of explanation, components arranged in the first structure are indicated by solid lines and components arranged in the second structure are indicated by dotted lines.

[0058] 4, 5A-5C, and 6, an image sensor according to an embodiment of the present invention may include first and second structures S1 and S2 stacked along a third direction D3. The first structure S1 and the second structure S2 may be stacked while contacting each other, as shown in FIG.

[0059] The first structure S1 may include a first semiconductor substrate 10 on which a photoelectric conversion element PD, a transfer transistor TX, and a first floating diffusion region FD1 are formed, a first conductive pattern 100 provided on the first semiconductor substrate 10, an isolation film 150, a color filter CF, and a microlens ML. The first conductive pattern 100 may include a first contact CT1 connected to each component (e.g., a transfer transistor TX, a ground region GND, etc.) provided on the first semiconductor substrate 10, and at least one layer of first wiring 110 connected to the first contact CT1. First vias 110v may be provided between the first contacts CT1, between the first wiring 110, and between the first contacts CT1 and the wiring 110.

[0060] The second structure S2 may include a second semiconductor substrate 20 on which a plurality of transistors other than the photoelectric conversion element PD and the transmission transistor TX, a plurality of nodes, and a shielding portion SLD are formed, and a second conductive pattern 200 provided on the second semiconductor substrate 20. The second conductive pattern 200 may include second contacts CT2 connected to each component (e.g., a reset transistor RX, a source follower transistor SF, a selection transistor SEL, a dual conversion gain transistor DCX, etc.) provided on the second semiconductor substrate 20, and at least one layer of second wiring 210 connected to the second contact CT2. Second vias 210v may be provided between the second contacts CT2, between the second wiring 210, and between the second contacts CT2 and the second wiring 210.

[0061] Here, each pixel PXL may include a photoelectric conversion element PD, at least one floating diffusion region FD1, FD2, transistors (transmission transistor TX, reset transistor RX, source follower transistor SF, selection transistor SEL, and / or dual conversion gain transistor DCX, etc.), and nodes connected to the transistors. Among the photoelectric conversion element PD, the transmission transistor TX, and the floating diffusion regions FD1, FD2, some may be provided in a first structure S1, and some of the floating diffusion regions FD1, FD2 and the remaining transistors (reset transistor RX, source follower transistor SF, selection transistor SEL, and dual conversion gain transistor DCX) may be provided in a second structure S2 and / or a third structure S3.

[0062] According to this embodiment, the photoelectric conversion element PD, the first floating diffusion region FD1, and the transfer transistor TX provided in the first structure S1, and the reset transistor RX, the source follower transistor SF, the selection transistor SEL, and the dual conversion gain transistor DCX provided in the second structure S2 are provided in different structures in a plan view, and therefore can be arranged overlapping each other. Therefore, in FIG. 5A, the components arranged in the first structure S1 are shown with dotted lines to distinguish them from the components arranged in the second structure S2.

[0063] In one embodiment of the present invention, the transistors provided in the second semiconductor substrate 20 are n-MOS type transistors, and the source and drain of each transistor may be regions doped with a second conductivity type impurity, i.e., n-type impurities. However, the transistors are p-MOS type transistors, and therefore the locations of the source and drain of each transistor may vary.

[0064] The transistors of the second semiconductor substrate 20 may be connected to each other or to an external component through the second contact CT2 and the second wiring 210. For example, the second contact CT2 provided to the source follower gate SFG and the second contact CT2 provided to the first floating diffusion region FD1 may be connected to each other through the second wiring 210 within one pixel. A pixel voltage Vpix may be applied to the drain of the source follower transistor SF through the second contact CT2, and a pixel power supply voltage Vdd may be applied to the drain of the reset transistor RX through the second contact CT2. Here, the pixel voltage Vpix and the pixel power supply voltage Vdd may be the same voltage.

[0065] In the following, first, a specific embodiment of the first structure S1 will be described in detail, and then a specific embodiment of the second structure will be described.

[0066] In the first structure S1, the first semiconductor substrate 10 may have a first surface 10a and a second surface 10b facing each other. The first surface 10a of the first semiconductor substrate 10 may be a front surface, and the second surface 10b may be a back surface. Light may be incident on the second surface 10b of the first semiconductor substrate 10.

[0067] The first semiconductor substrate 10 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first semiconductor substrate 10 may further include a group 3 element. The group 3 element is an impurity of a first conductivity type. Thus, the first semiconductor substrate 10 may have a first conductivity type. For example, the impurity of the first conductivity type may include p-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). In the following embodiments, the first conductivity type is described as being p-type, but this is merely an example, and it goes without saying that the first conductivity type may be n-type.

[0068] The first semiconductor substrate 10 may include, for each pixel PXL, a photoelectric conversion element PD, a transfer transistor TX, a first floating diffusion region FD1, and a ground region GND.

[0069] The photoelectric conversion element PD may be interposed between the first surface 10a and the second surface 10b of the first semiconductor substrate 10. The photoelectric conversion element PD may be a doped region including impurities of a second conductivity type. In one embodiment of the present invention, the photoelectric conversion element PD may include a group 5 element, which may be an impurity of the second conductivity type. The impurities of the second conductivity type may have a conductivity type opposite to that of the impurities of the first conductivity type. The impurities of the second conductivity type may include n-type impurities, such as phosphorus, arsenic, bismuth, and / or antimony.

[0070] The ground region GND may be formed in the first semiconductor substrate 10. The ground region GND may have a first conductivity type. In some embodiments, the ground region GND may have the first conductivity type at a higher impurity concentration than the first semiconductor substrate 10. For example, the ground region GND may be an impurity region formed by ion-implanting a high concentration of p-type impurities (p++) into the first semiconductor substrate 10, which is p-type.

[0071] The first floating diffusion region FD1 may be formed in the first semiconductor substrate 10. The first floating diffusion region FD1 may be separated from the photoelectric conversion element PD and the ground region GND. The first floating diffusion region FD1 may have the second conductivity type, and therefore, for example, the first floating diffusion region FD1 may be an impurity region having the second conductivity type formed by ion-implanting n-type impurities into the first semiconductor substrate 10, which is p-type.

[0072] In some embodiments, the first floating diffusion region FD1 may have the second conductivity type with a higher impurity concentration than the photoelectric conversion element PD. For example, the floating diffusion region FD may be formed by ion-implanting a high concentration of n-type impurities (n+) into the first semiconductor substrate 10, which is p-type. A channel region may be formed between the photoelectric conversion element PD and the first floating diffusion region FD1.

[0073] A first contact CT1 provided in a first floating diffusion region FD1 of the first structure S1 is serially connected to a second contact CT2 provided in a first floating diffusion region FD1 of a second structure (to be described later).

[0074] The transfer transistor TX may include a transfer gate TG that forms a transfer channel between the photoelectric conversion element PD and the first floating diffusion region FD1, a gate insulating film that insulates the first semiconductor substrate 10 from the transfer gate TG, and a gate spacer provided on a side of the transfer gate. The transfer gate TG may have a buried gate structure.

[0075] The transfer transistor TX is connected to other components through a first contact CT1, which is connected to the transfer gate TG, the first floating diffusion region FD1 region FD, and the ground region GND, respectively, and at least two layers of first wiring 110 connected to the first contact CT1, and a first via 110v connecting the first wiring 110.

[0076] A first upper insulating film 120 may be provided on the first surface 10a on which the transmission gate TG is formed. In one embodiment, the first upper insulating film 120 may be provided as a single film or a multi-layer film, and may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. As an example, the first upper insulating film 120 may include USG (Undoped Silicate Glass).

[0077] Between adjacent pixels PXL, an element isolation film 150 can be provided to partition each pixel PXL. In particular, adjacent pixels PXL can be isolated by the element isolation film 150. The element isolation film 150 can be provided, for example, along the periphery of the photoelectric conversion element PD in a plan view.

[0078] The element isolation film 150 may include a first isolation film 151 surrounding the photoelectric conversion element PD, and a second isolation film 153 provided at a shallower depth than the first isolation film 151 in a plan view.

[0079] The first isolation layer 151 may be formed in the first semiconductor substrate 10 to surround each of the pixels PXL. The first isolation layer 151 may be provided, for example, in a form in which an insulating material is filled in a deep trench (151t) formed by patterning the first semiconductor substrate 10, i.e., a deep trench isolation (DTI). The deep trench 151t may be provided in a form penetrating the first semiconductor substrate 10. For example, the deep trench 151t may be provided in a form penetrating the first surface 10a and the second surface 10b of the first semiconductor substrate 10.

[0080] In one embodiment of the present invention, the first isolation layer 151 may include a conductive isolation layer 151b filled with a conductive material in the deep trench 151t, and an insulating liner 151a provided between the first semiconductor substrate 10 and the conductive isolation layer 151b. The conductive isolation layer 151b may include a crystalline semiconductor material, for example, polysilicon. In one embodiment of the present invention, the conductive isolation layer 151b may further include a dopant, and the dopant may include impurities of a first conductivity type or impurities of a second conductivity type. For example, the conductive isolation layer 151b may include doped polysilicon. A negative voltage or a ground voltage may be applied to the conductive isolation layer 151b, thereby improving the dark current.

[0081] An insulating liner 151a may be provided along a sidewall of the deep trench 151t. The insulating liner 151a may include, for example, a silicon-based insulating material (e.g., silicon nitride (Si3N4), silicon oxide (SiO2, silicate), and / or silicon carbonitride (SiCN)) and / or a high-k metal oxide (e.g., hafnium oxide (HfOx), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3, alumina), etc.). Here, the conductive isolation layer 151b may be separated from the first semiconductor substrate 10 by the insulating liner 151a, and thus, the conductive isolation layer 151b may be electrically isolated from the first semiconductor substrate 10 during operation of the image sensor.

[0082] The second isolation film 153 is provided in a shallow trench recessed to a predetermined depth from the first surface 10a when viewed in cross section. Unlike the deep trench 151t, the shallow trench is recessed to a predetermined depth from the first surface 10a of the first semiconductor substrate 10 and does not penetrate the first semiconductor substrate 10.

[0083] The second isolation film 153 is provided at the edge immediately adjacent to the floating diffusion region FD, thereby preventing defects, such as dark current, caused by the combination of electrons in the floating diffusion region FD and holes accumulated on the first isolation film 151 side. When a negative voltage is applied to the first isolation film 151, the dark current can be improved, but when the second isolation film 153 is not provided, the holes accumulated adjacent to the first isolation film 151 can strongly combine with the electrons in the floating diffusion region FD. Such electron-hole combination pairs may move to the light conversion region and cause defects. To prevent this, the second isolation film 153 is formed at the edge adjacent to the floating diffusion region FD so that the electrons in the floating diffusion region FD and the holes near the second isolation film 153 are not combined. That is, the second isolation film 153 is formed only near the floating diffusion region FD to separate the electrons in the floating diffusion region FD from the holes near the second isolation film 153. Therefore, the drain leakage in the floating diffusion region FD induced by the transmission gate TG, that is, gate induced drain leakage (GIDL), can be reduced.

[0084] The second isolation layer 153 may be provided in a form in which an insulating material is filled in a shallow trench, i.e., a shallow trench isolation (STI). The second isolation layer 153 is provided adjacent to the first surface 10a of the first semiconductor substrate 10, and for example, the second isolation layer 153 may be extended from the first surface 10a of the first semiconductor substrate 10. Although not shown, in an embodiment of the present invention, the second isolation layer 153 may be formed of a multi-layer. The second isolation layer 153 may also include at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. The first isolation layer 151 is provided below the region in which the second isolation layer 153 is formed. That is, when viewed in a cross section, the first isolation layer 151 and the second isolation layer 153 are provided in a form vertically stacked around the pixel adjacent to the floating diffusion region FD.

[0085] A first lower insulating film 120b may be provided on the second surface 10b. The first lower insulating film 120b may cover the second surface 10b of the first semiconductor substrate 10 and may be provided in a multi-layer structure. The first lower insulating film 120b may include a silicon-based insulating material such as, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0086] A color filter CF is provided on the first lower insulating layer 120b.

[0087] The color filters CF may be disposed for each pixel PXL on the second surface 10b of the first semiconductor substrate 10. For example, the color filters CF may be provided at positions corresponding to the photoelectric conversion elements PD. Each of the color filters CF may include any one of a red filter, a blue filter, and a green filter, but is not limited thereto, and filters of other colors may be provided. The color filters CF may form a color filter array. For example, the color filters CF may form an array arranged along a first direction D1 and a second direction D2 in a plan view.

[0088] The microlens ML may be disposed on the second surface 10b of the first semiconductor substrate 10. For example, the microlens ML may be disposed on the color filter CF. The microlens ML may include a lens pattern and a planarized portion. The planarized portion of the microlens ML may be provided on the color filter CF. The lens pattern may be provided on the planarized portion. The lens pattern may be integrally formed with the planarized portion and connected without an interface. The lens pattern may include the same material as the planarized portion. As another example, the planarized portion may be omitted and the lens pattern may be disposed directly on the color filter CF.

[0089] The lens pattern may be hemispherical. The lens pattern can condense incident light. The lens pattern may be provided at a position corresponding to the photoelectric conversion element PD of the first semiconductor substrate 10. For example, the lens pattern may be provided on the photoelectric conversion element PD of the first pixel region of the first semiconductor substrate 10.

[0090] The microlens ML is transparent, allowing light to pass through. The microlens ML may include an organic material, such as a polymer. For example, the microlens ML may include a photoresist material or a thermosetting resin.

[0091] Although not shown, a protective layer is provided on the microlens ML, and the protective layer may include organic and / or inorganic materials. According to an embodiment, the protective layer may include a silicon-containing material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon-oxide, silicon carbon-nitride, and / or silicon carbon-oxynitride. As another example, the protective layer may include aluminum oxide, zinc oxide, and / or hafnium oxide. The protective layer may have insulating properties, but is not limited thereto. The protective layer may be light-transmitting.

[0092] In the second structure S2, the second semiconductor substrate 20 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second semiconductor substrate 20 may further include a group 3 element. The group 3 element is an impurity of the first conductivity type. Therefore, the second semiconductor substrate 20 may have the first conductivity type.

[0093] In the second semiconductor substrate, in a plan view, each pixel is provided with an active area ACT separated by a third isolation film 253. The active area ACT may be doped with impurities of a second conductivity type. In one embodiment of the present invention, the active area ACT may be doped with n-type impurities.

[0094] The third isolation layer 253 may be provided in a form in which an insulating material is filled in a shallow trench, i.e., a shallow trench isolation (STI). In an embodiment of the present invention, the third isolation layer 253 may be formed of a multi-layer. The third isolation layer 253 may also include at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. The third isolation layer 253 may be provided along the periphery of one pixel PXL such that the active region ACT of one pixel PXL is separated from the active region ACT of an adjacent pixel PXL. In the embodiment, the third isolation layer 253 is provided on the second semiconductor substrate 20, but is not limited thereto, and the third isolation layer 253 may be omitted. Of course, if one pixel PXL has an area sufficient for isolating the active region ACT, the third isolation layer 253 may not be provided or may be provided only in a part of the pixel PXL.

[0095] The gates of the transistors may be provided on the active region ACT. In one embodiment of the present invention, a reset gate RG, a source follower gate, a selection gate SG, and a dual conversion gain gate DCG may be provided on the active region ACT. Through the gates of the transistors, the active regions ACT on both sides may function as a source or a drain.

[0096] In this embodiment, the active region ACT arranged on one side of the dual conversion gain transistor DCX corresponds to the first floating diffusion region FD1, and the active region ACT arranged between the dual conversion gain transistor DCX and the reset transistor RX corresponds to the second floating diffusion region FD2. More specifically, the first floating diffusion region FD1 is connected to the source of the dual conversion gain transistor DCX, and the second floating diffusion region FD2 is connected to the drain of the dual conversion gain transistor DCX and the source of the reset transistor RX. The drain of the reset transistor RX is connected to the drain of the source follower transistor SF. The drain of the reset transistor RX, the drain of the source follower transistor SF, and the active region ACT between the drain of the reset transistor RX and the source follower transistor SF correspond to a reset node receiving a reset voltage through the second contact CT2 and a pixel voltage node receiving a pixel voltage Vpix. The source of the source follower transistor SF is connected to the drain of the selection transistor SEL, and the source of the selection transistor SEL corresponds to an output node outputting a sampling voltage through the second contact CT2.

[0097] A shielding portion SLD is provided between two adjacent pixels PXL, as will be described later.

[0098] A second insulating layer 220 is provided on the transistor of the second semiconductor substrate 20, and the second insulating layer 220 may be provided as a multi-layer structure.

[0099] A junction for connecting the first structure S1 and the second structure S2 may be provided at the top of the first wiring 130 (inverted and displayed at the bottom in the drawing) and the top of the second wiring 230. The junction may include a bonding pad BP arranged on the first structure S1 and the second structure S2 to face each other. The bonding pad BP may be made of various conductive materials that can be bonded by heating, etc., and may be integrated through bonding after the first structure S1 and the second structure S2 are manufactured. The bonding pad BP may include metals such as aluminum, copper, tungsten, titanium, tantalum, or alloys thereof. In one embodiment of the present invention, the bonding pad BP may be made of copper, through which the first and second structures S1 and S2 may be bonded by copper-copper bonding.

[0100] The first conductive pattern 100 of the first structure S1 and the second conductive pattern 200 of the second structure S2 can be connected to each other through the first wiring 130, the bonding pad BP, and the second wiring 230, and the pixel can be driven through such connection.

[0101] The image sensor according to an embodiment of the present invention having the above-mentioned structure includes a shielding portion SLD for preventing the occurrence of parasitic capacitance or junction capacitance due to coupling that may occur between nodes of two adjacent pixels.

[0102] A shielding portion SLD may be provided between adjacent pixels PXL, and thus between the floating diffusion region FD of each pixel and a pixel adjacent to the floating diffusion region FD of said each pixel.

[0103] For ease of explanation, the two pixels PXL adjacent to each other along the first direction will be referred to as a first pixel PXL1 and a second pixel PXL2 in the following explanation.

[0104] Specifically, a shielding portion SLD is provided between the floating diffusion region FD in the first pixel PXL1 and a node of the second pixel PXL2 so that no coupling occurs between the floating diffusion region FD in the first pixel PXL1 and a node of the second pixel PXL2 adjacent to the first pixel PXL1. In an embodiment of the present invention, the node of the second pixel PXL2 may be, for example, a source node of the source follower transistor SF and an output node. The node of the second pixel PXL2 may be, for example, a source of the source follower transistor SF corresponding to the source node of the source follower transistor SF and a source of the selection transistor SEL corresponding to the output node. Therefore, a shielding portion SLD is provided so that the floating diffusion region FD in the first pixel PXL1 is not adjacent to the source of the source follower transistor SF and the source of the selection transistor SEL of the second pixel PXL2.

[0105] A predetermined voltage is applied to the shielding portion SLD, and in one embodiment of the present invention, a constant voltage (eg, a pixel power supply voltage, a ground voltage, etc.) may be applied thereto.

[0106] The shielding portion SLD may be formed by doping impurities into the second semiconductor substrate 20, rather than forming a separate wiring using a conductive material such as a metal. The impurities of the shielding portion SLD may have a conductivity type opposite to that of the impurities doped into the floating diffusion region FD. For example, when the impurities doped into the floating diffusion region FD have a second conductivity type, the impurities doped into the shielding portion SLD may be of the first conductivity type. The impurities of the first conductivity type may be p-type impurities.

[0107] In an embodiment of the present invention, the shielding part SLD may have the same function as the shielding part SLD made of other metal wiring to prevent coupling between two adjacent nodes, but the shielding part SLD according to an embodiment of the present invention may also effectively prevent coupling with components formed on the second semiconductor substrate 20, particularly with node parts (e.g., source and / or drain of each transistor, floating diffusion region FD) implemented in the active region ACT among various nodes. Various components of the second semiconductor substrate 20 may be easily formed by doping the second semiconductor substrate 20 with impurities of various conductive types, but since such components are substantially formed to a predetermined depth in the second semiconductor substrate 20, even if another metal wiring is formed on the second semiconductor substrate 20, the shielding effect for the components in the second semiconductor substrate 20 is not large. However, in the case of the shielding part SLD according to an embodiment of the present invention, it is formed to a predetermined depth in the second semiconductor substrate 20, and effectively prevents coupling of the nodes implemented in the active region ACT.

[0108] A shielding portion SLD may be provided between at least one floating diffusion region FD1, FD2 of the first pixel PXL1 and at least one of the source node of the source follower transistor SF of the second pixel PXL2 and the output node, or conversely, between at least one floating diffusion region FD1, FD2 of the second pixel PXL2 and at least one of the source node of the source follower transistor SF of the first pixel PXL1 and the output node.

[0109] In an embodiment of the present invention, the shielding portion SLD may extend along a column direction (i.e., a second direction D2) between a first pixel PXL1 and a second pixel PXL2 adjacent to each other. The shielding portion SLD may have a bar shape formed long along the second direction D2. As illustrated, the shielding portion SLD may be provided for each column, separated between a number of pixels PXL including the first and second pixels PXL1 and PXL2.

[0110] In an embodiment of the present invention, the shielding part SLD may be provided in a part of a region where the third isolation layer 253 is formed. The shielding part SLD may be provided in at least a part of a region between the first and second pixels PXL1 and PLX2 adjacent to each other in the region where the third isolation layer 253 is provided. However, the region where the shielding part SLD is provided is not limited thereto, and the shielding part SLD may be provided in a region that partially overlaps or does not overlap the third isolation layer 253, regardless of the position of the third isolation layer 253.

[0111] When a parasitic capacitance or a junction capacitance is formed between at least one of the source node and the output node of the source follower transistor SF of the first pixel PXL1 and the floating diffusion region FD of the second pixel PXL2 due to coupling, the parasitic capacitance or the junction capacitance may cause a voltage fluctuation in the floating diffusion region FD, such as a voltage drop in the floating diffusion region FD. Such a voltage fluctuation in the floating diffusion region FD may eventually cause a ghost white spot. In an embodiment of the present invention, a shielding portion SLD is provided between at least one of the source node and the output node of the source follower transistor SF of the second pixel PXL2 and the floating diffusion regions FD1, FD2 of the first pixel PXL1 so that a parasitic capacitance or a junction capacitance is not formed, thereby reducing such a ghost white spot defect.

[0112] More specifically, the shielding part SLD according to an embodiment of the present invention is provided between the first floating diffusion region FD1 and the output node to prevent coupling between the first floating diffusion region FD1 and the output node.

[0113] 7A and 7B are cross-sectional views corresponding to line A-A' in FIG. 5A, showing only a part of the second structure, where FIG. 7A is a cross-sectional view in the case where the shielding portion SLD is not provided, and FIG. 7B is a cross-sectional view in the case where the shielding portion SLD is provided.

[0114] 7A, the first floating diffusion region FD1 of the first pixel PXL1 and the output node of the second pixel PXL2, for example, the source of the selection gate SG, are disposed adjacent to each other in a plan view. Therefore, the first floating diffusion region FD1 and the output node of the second pixel PXL2 are coupled to each other, and as a result, a parasitic capacitance is formed between the first floating diffusion region FD1 and the output node of the second pixel PXL2. Such a parasitic capacitance may cause a voltage fluctuation, for example, a voltage drop, of the first floating diffusion region FD1.

[0115] In contrast, referring to FIG. 7B, when a conductive shielding portion SLD is provided between the first floating diffusion region FD1 and the output node of the second pixel PXL2, coupling between the first floating diffusion region FD1 and the output node of the second pixel PXL2 is prevented.

[0116] 7A and 7B, the first floating diffusion region FD1 and the output node of the second pixel PXL2, for example, the source of the selection gate SG, are prevented from coupling, but the present invention is not limited thereto, and the first floating diffusion region FD1 and the coupling to other nodes of the second pixel PXL2 are also prevented. Of course, according to an embodiment of the present invention, the shielding part SLD can also prevent coupling between the first floating diffusion region FD1 and the drain node of the selection transistor SEL.

[0117] According to an embodiment of the present invention, the shielding portion SLD prevents coupling not only between the first floating diffusion region FD1 and the output node, but also between the second floating diffusion region FD2 and other nodes.

[0118] 8A and 8B are cross-sectional views corresponding to the line BB' in FIG. 5A, showing only a part of the second structure, where FIG. 8A is a cross-sectional view in the case where the shielding portion SLD is not provided, and FIG. 8B is a cross-sectional view in the case where the shielding portion SLD is provided.

[0119] 8A, the second floating diffusion region FD2 of the first pixel PXL1 and a node (e.g., the source of the source follower transistor SF or the drain of the select transistor SEL) of the second pixel PXL2 are disposed adjacent to each other in a plan view. Therefore, a parasitic capacitance is formed by coupling between the second floating diffusion region FD2 and the drain node of the select transistor SEL of the second pixel PXL2. Such a parasitic capacitance may cause a voltage fluctuation, e.g., a voltage drop, of the second floating diffusion region FD2. In contrast, referring to FIG. 8B, a conductive shielding portion SLD is provided between the second floating diffusion region FD2 and the drain node of the select transistor SEL of the second pixel PXL2, thereby preventing coupling between the first floating diffusion region FD1 and the drain node of the select transistor SEL.

[0120] 8A and 8B, the prevention of coupling between the second floating diffusion region FD2 of the first pixel PXL1 and the source node of the source follower transistor SF of the second pixel PXL2 has been described, but the present invention is not limited thereto, and coupling between the second floating diffusion region FD2 of the first pixel PXL1 and other nodes of the second pixel PXL2 may also be prevented. For example, according to an embodiment of the present invention, it goes without saying that coupling between the first floating diffusion region FD1 of the first pixel PXL1 and the output of the second pixel PXL2 may also be prevented by the shielding part SLD.

[0121] In an image sensor having the above-described structure, a shielding portion SLD is provided between two adjacent pixels, thereby preventing coupling between the floating diffusion region FD and nodes to which different signals are applied, thereby reducing ghost white spots.

[0122] In an image sensor according to an embodiment of the present invention, the shielding portion may be provided differently from the above-described embodiment. For example, the shielding portion SLD according to an embodiment of the present invention may be provided between two pixels adjacent to each other in the second direction D2 (i.e., the column direction), and in this case, coupling between the first floating diffusion region FD1 and the pixel voltage node may be prevented.

[0123] Fig. 9 shows first and second pixels PXL1 and PXL2 adjacent to each other along the second direction D2 in an image sensor. Fig. 10A and Fig. 10B are cross-sectional views corresponding to line CC' in Fig. 9A, showing only a part of the second structure. Fig. 10A is a cross-sectional view when no shielding part SLD is provided, and Fig. 10B is a cross-sectional view when a shielding part SLD is provided.

[0124] Referring to Figures 9, 10A, and 10B, when two pixels adjacent to each other in the second direction D2 are a first pixel PXL1 and a second pixel PXL2, the shielding portion SLD may also be provided between the second pixel PXL2 adjacent to the first pixel PXL1.

[0125] In an embodiment of the present invention, the shielding portion SLD may extend along a row direction (i.e., a first direction D1) between a first pixel PXL1 and a second pixel PXL2 adjacent to each other. The shielding portion SLD may have a bar shape formed long along the first direction D1. As illustrated, the shielding portion SLD may be provided for each row, separated between a number of pixels PXL including the first and second pixels PXL1 and PXL2.

[0126] In this embodiment, the first floating diffusion region FD1 of the first pixel PXL1 and the pixel voltage node (or reset node) of the second pixel PXL2 are arranged adjacent to each other in a planar view. Specifically, the first floating diffusion region FD1 of the first pixel PXL1 and the drain of the reset transistor RX or the drain of the source follower transistor SF of the second pixel PXL2 are arranged adjacent to each other in a planar view.

[0127] A coupling may occur between the first floating diffusion region FD1 of the first pixel PXL1 and the pixel voltage node of the second pixel PXL2, and thus a parasitic capacitance may be formed. Such a parasitic capacitance may cause a voltage fluctuation, for example a voltage drop, of the first floating diffusion region FD1 of the first pixel PXL1. In comparison, according to an embodiment of the present invention, a conductive shielding portion SLD is provided between the first floating diffusion region FD1 of the first pixel PXL1 and the pixel voltage node of the second pixel PXL2, thereby preventing a coupling between the first floating diffusion region FD1 of the first pixel PXL1 and the pixel voltage node of the second pixel PXL2.

[0128] As described above, the shielding portion according to an embodiment of the present invention may be provided along a column direction or a row direction between two adjacent pixels among a number of pixels arranged in a matrix shape, but the shape of the shielding portion is not limited thereto and may be modified in various ways.

[0129] 11 and 12 show an image sensor according to an embodiment of the present invention in which the shape of the shielding portion is different from that of the above-described embodiment.

[0130] 11, the shielding portion SLD may be provided between two adjacent pixels PXL and may be provided in an Irish shape. The shielding portion SLD in the Irish shape may be provided in various numbers and at various positions, and may be arranged in accordance with positions where coupling is likely to occur. For example, the shielding portion SLD may be provided between the first floating diffusion region FD1 and / or the second floating diffusion region FD2 of one pixel PXL and a node of a pixel PXL of another pixel PXL facing the first floating diffusion region FD1 and / or the second floating diffusion region FD2 of the one pixel PXL. In addition, the shielding portion SLD may be provided between two adjacent pixels PXL in a diagonal direction to prevent coupling with a node of another pixel PXL arranged in a diagonal direction, for example, in a direction inclined other than a row or column direction, with respect to the first floating diffusion region FD1 and / or the second floating diffusion region FD2 of one pixel PXL.

[0131] 12, the shielding portion SLD may be provided in a bar shape that extends long in one direction. The shielding portion SLD in a bar shape that extends long may be disposed between the pixels PXL in all row and column directions. The shielding portions SLD disposed between the pixels PXL may be connected to each other to form a lattice shape. In this case, the shielding portion SLD is provided in a form that completely surrounds each pixel PXL, and in this case, coupling between two adjacent pixels PXL may be more effectively prevented.

[0132] In one embodiment of the present invention, additional shielding can be provided for nodes that can affect the voltage of the first floating diffusion region between two adjacent pixels.

[0133] 13 is a cross-sectional view showing an image sensor according to an embodiment of the present invention. In the following embodiment, differences from the above-mentioned embodiment will be mainly described.

[0134] 13, a second contact CT2 connected to each transistor and at least one layer of second wiring 210 directly or indirectly connected to the second contact CT2 are included on a second semiconductor substrate 20. Here, the second contact CT2 and a part of the second wiring 210, for example, the second contact CT2 and the second wiring 210 connected to a first floating diffusion region FD1, correspond to the same node as the first floating diffusion region FD1, i.e., a first floating diffusion node. The first floating diffusion node is coupled to another adjacent node, and the voltage of the first floating diffusion node may be changed due to such coupling.

[0135] In an embodiment of the present invention, between two adjacent pixels PXL, an additional shielding part ASLD may be provided between the first floating diffusion node of one pixel PXL and a node of the other adjacent pixel PXL. The additional shielding part ASLD is provided between the first floating diffusion node of one pixel PXL (e.g., a wiring connected to at least one of the first floating diffusion region FD1) and a node of the other adjacent pixel PXL (e.g., a source node of the source follower transistor SF, the output node, and a wiring connected to at least one of the pixel PXL voltage node) to prevent coupling between the first floating diffusion node of one pixel PXL and the node of the other adjacent pixel PXL.

[0136] A constant voltage (eg, pixel PXL power supply voltage, ground voltage, etc.) can be applied to the additional shielding portion ASLD.

[0137] The additional shielding portion ASLD may be made of a metal wiring and may be formed using the same material and process as other wirings provided in the same layer.

[0138] By providing such an additional shielding portion ASLD, coupling between the first floating diffusion node and other nodes that may affect the first floating diffusion node is prevented, and therefore more stable driving of each pixel PXL is possible without ghost white spots.

[0139] As described above, according to an embodiment of the present invention, the image sensor includes a shielding portion that prevents coupling between nodes that causes ghost white spots, thereby improving the quality of the image element.

[0140] In the above embodiment, a part of the transistor of each pixel is provided in the first semiconductor substrate of the first structure, and the remaining part is provided in the second semiconductor substrate of the second structure, but the present invention is not limited thereto. The transistor of each pixel may be provided in a semiconductor substrate of one structure. Also, the number of floating diffusion regions included in each pixel, the type and number of transistors, and the nodes connected thereto may also be changed. For example, one or more floating diffusion regions may be provided. The present invention includes an embodiment in which a shielding portion is formed between the floating diffusion region and the node facing it even when the positions of the floating diffusion region and the node adjacent thereto are different. Also, an embodiment in which a shielding portion is formed between the floating diffusion region and the node facing it even when a part of the transistor is omitted.

[0141] Although the invention has been described above with reference to a preferred embodiment, it will be understood that a person skilled in the art or having ordinary knowledge in the art can modify and change the invention in various ways without departing from the spirit and scope of the invention as described in the claims below.

[0142] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0143] ASP Pixel Array Area BP Bonding Pad CT1, CT2 Contacts DCX Dual Conversion Gain Transistor FD1, FD2 Floating Diffusion Areas PD photoelectric conversion element PDA Pad Area PXL Pixel RX Reset Transistor SEL Select transistor S source follower transistor SLD shielding part SPD signal pad TG Transmission Gate

Claims

1. An image sensor including a pixel array in which a plurality of pixels, including a first pixel and a second pixel arranged adjacent to each other, are arranged in a matrix shape, The plurality of pixels each include At least one photoelectric conversion element; at least one floating diffusion region to which the charge of the at least one photoelectric conversion element is transferred; a reset transistor that transmits a voltage of a reset node to the at least one floating diffusion region; a source follower transistor having one end connected to a pixel voltage node and outputting a sampling voltage corresponding to the charge of the floating diffusion region; a selection transistor having one end coupled to the source follower transistor and configured to output the sampling voltage to an output node; Including, a doped shield is provided between the at least one floating diffusion region of the first pixel and at least one of a source node of the source follower transistor of the second pixel, the output node of the second pixel, and the pixel voltage node of the second pixel; Image sensor.

2. the shielding portion is provided between at least one floating diffusion region of the first pixel and the pixel voltage node of the second pixel; 2. The image sensor of claim 1.

3. the shielding portion is a first region doped with an impurity having a first conductivity type in a semiconductor substrate; the floating diffusion region is a second region in a semiconductor substrate doped with impurities having a second conductivity type opposite to the first conductivity type; 2. The image sensor of claim 1.

4. The shielding portion is configured to be applied with a constant voltage.

4. The image sensor according to claim 3.

5. the shielding portion is provided along a row direction of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel; 4. The image sensor according to claim 3.

6. the shielding portion is provided along a column direction of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel; 4. The image sensor according to claim 3.

7. the shielding portion is provided along row and column directions of the matrix between the at least one floating diffusion region of a first pixel among the plurality of pixels and at least one of a source node of the source follower transistor, the output node, and the pixel voltage node of a second pixel adjacent to the first pixel; 4. The image sensor according to claim 3.

8. At least one floating diffusion region of the first pixel is adjacent to an output node of the second pixel through the shielding portion.

2. The image sensor of claim 1.

9. At least one floating diffusion region of the first pixel is adjacent to a source node of the source follower transistor of the second pixel through the shielding portion.

2. The image sensor of claim 1.

10. An image sensor, A plurality of pixels arranged in a matrix form; and a plurality of stacked structures including a first structure and a second structure, Each of the plurality of pixels comprises: A photoelectric conversion element provided in one of the plurality of stacked structures; At least one floating diffusion region to which charges of the photoelectric conversion element provided in at least one of the plurality of stacked structures are transferred; A plurality of transistors and a plurality of nodes; Including, The at least one floating diffusion region, the plurality of transistors, and the plurality of nodes are provided in the first structure, and the photoelectric conversion element is provided in the second structure; a shielding portion formed by doping an impurity into a semiconductor substrate is provided between two adjacent pixels among the plurality of pixels; The shielding portion prevents coupling between two adjacent pixels. Image sensor.

Images