Semiconductor device

Abstract

A semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having bit lines coupled to each of the memory cells arranged in the row. The bit line has a first section coupled to the first portion of the memory cell and a second section coupled to the second portion of the memory cell. The first section has a first width and the second section has a second width less than the first width.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC size (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] This reduction in integrated circuit technology has not only complicated the manufacturing process, but also posed specific challenges in the design and functionality of memory arrays within memory devices. For example, the operation of memory cells at different locations in a memory array requires tailored structural designs for signal lines (e.g., bit lines) coupled to the memory cells. The traditional approach of employing bit lines with uniform width across all memory cells in the same row is increasingly inadequate because this does not optimally meet the different performance requirements of these memory cells. The uniform width of the bit lines deployed in a memory array may result in poor performance, where the specific requirements of memory cells at different locations in the memory array are not fully met. This difference highlights the need for a differentiated approach in bitline architecture to improve the overall efficiency and performance of memory devices, especially in the context of advanced semiconductor technologies. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a memory array comprising a plurality of memory cells arranged in rows; and an interconnect structure disposed above the memory cells and comprising a bit line, wherein the bit line is coupled to each memory cell arranged in the row, wherein the bit line has a first segment coupled to a first portion of the memory cell and a second segment coupled to a second portion of the memory cell, and wherein the first segment has a first width and the second segment has a second width smaller than the first width.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a plurality of memory cells arranged along a first direction, wherein each memory cell includes at least a transfer gate transistor formed on an n-type active region and a pull-up transistor formed on a p-type active region; a voltage line suspended above the memory cell and extending longitudinally along the first direction, wherein the voltage line is coupled to the pull-up transistor of the memory cell; and a signal line suspended above the memory cell and extending longitudinally along the first direction, wherein the signal line includes a first segment of the transfer gate transistor coupled to a first portion of the memory cell and a second segment of the transfer gate transistor coupled to a second portion of the memory cell, and wherein the first segment has a first width and the second segment has a second width less than the first width.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a memory array comprising memory cells arranged in M ​​rows and N columns, M and N being both integers; a logic region adjacent to the memory array and coupled to the memory cells; and an interconnect structure arranged above the memory array and the logic region, wherein the interconnect structure comprises a signal line suspended directly above one of the M rows of memory cells, and wherein: the signal line comprises a first segment and a second segment, the first segment being coupled to the memory cells in the first to (Q-1)th columns in the M rows, Q being an integer greater than 1 and less than N, the first column being closer to the logic region than the Nth column, and the first segment having a first width, and the second segment having a second width less than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a block diagram of a semiconductor device having a memory macro according to various aspects of the present disclosure.

[0009] Figure 2 is a block diagram of a memory macro having a memory array according to various aspects of the present disclosure.

[0010] Figure 3 is a circuit schematic of a static random access memory (SRAM) cell according to various aspects of the present disclosure.

[0011] Figure 4 Cross-sectional views of various layers of a memory device according to various aspects of the present disclosure are shown.

[0012] Figure 5 and Figure 6The following are respectively shown according to various aspects of the present disclosure. Figure 3 The layout of the SRAM cell shown includes the device layer and the metal layer.

[0013] Figure 7 and Figure 8 The following are shown according to various aspects of the present disclosure. Figure 2 A portion of a memory macro is shown including layouts of device and metal layers, respectively.

[0014] Fig. 9 A layout of a metal layer including a portion of a memory circuit including a bit line having two different widths is shown in accordance with various aspects of the present disclosure.

[0015] Fig.10 The invention is shown along the Fig. 9 Partial cross-sectional views of sections AA, BB, A'-A' and B'-B'.

[0016] Fig.11 A layout of a metal layer including a portion of a memory circuit including bit lines having three different widths is shown in accordance with various aspects of the present disclosure.

[0017] Fig.12 A layout of a metal layer including a portion of a memory circuit including bit lines extending from two opposing I / O regions is shown according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0020] In addition, when a number or series of numbers is described using "about," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer with a thickness of "about 5nm" may include a size range of 4.5nm to 5.5nm, where the manufacturing tolerance associated with depositing material layers is known to those of ordinary skill in the art to be + / - 10%. When describing aspects of transistors, the source / drain regions may be referred to individually or collectively as the source or drain, depending on the context.

[0021] Static random access memory (SRAM) is a semiconductor memory that retains data statically as long as power is applied. Unlike dynamic random access memory (DRAM), SRAM is faster, more reliable, and does not need to be constantly refreshed. SRAM macros include memory cells and logic cells. Memory cells are also called bit cells and are configured to store memory bits. When forming an array, memory cells can be arranged in rows and columns. Logic cells can be standard cells (STD cells) such as inverters (INV), AND, OR, NAND, NOR, flip-flops (Flip-flip), scanners (SCAN), etc. Logic cells are arranged around memory cells and are configured to implement various logic functions. Multilayer interconnect structures provide metal tracks (metal lines) for interconnecting power lines and signal lines between memory cells and logic cells. Memory cells in different locations may have different structural design requirements to achieve optimal performance. For example, a memory cell located near a logic cell may need to have a structural design for its bit line to minimize resistance because other memory cells in the same row will also "experience" series resistance. Bit lines with low resistance provide greater voltage margin. In contrast, memory cells that are far from logic cells may need a structural design for their bit lines that minimizes delays by reducing parasitic capacitance, as such memory cells typically suffer from reduced circuit speed. Therefore, having a consistent bit line width between different memory cells in an SRAM array may result in poor performance because it does not meet the unique requirements of each memory cell.

[0022] The present invention introduces a bit line structure that provides different bit line widths in an SRAM array. In one embodiment, the SRAM array can have two or more bit line widths for memory cells at different distances from logic cells, thereby improving circuit performance.

[0023] Reference now Figure 1 . Figure 11 is a simplified block diagram of a semiconductor device (or IC) 10 according to some embodiments of the present disclosure. The semiconductor device 10 may be, for example, a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), or a portion thereof, and the semiconductor device 10 includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs (Fin Field Effect Transistors), full-all-around gate (GAA) transistors (such as nanosheet FETs or nanowire FETs), other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. The exact functionality of the semiconductor device 10 is not limited to the subject matter provided.

[0024] The conductor device 10 includes a memory macro (hereinafter referred to as macro) 20. In some embodiments, the macro 20 is a static random access memory (SRAM) macro, such as a single-port SRAM macro, a dual-port SRAM macro, or another type of SRAM macro. However, the present disclosure contemplates embodiments in which the macro 20 is another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory, a flash memory, or another suitable memory. For clarity, Figure 1 It is simplified to better understand the inventive concepts of the present disclosure. Additional components may be added to macro 20, and some of the components described below may be replaced, modified, or eliminated in other embodiments of macro 20.

[0025] In some embodiments, the macro 20 includes a memory cell and a peripheral circuit. The memory cell is also referred to as a bit cell and is configured to store a memory bit. The peripheral cell is also referred to as a logic cell, which is arranged around the bit cell and is configured to implement various logic functions. The logic functions of the logic cell include, for example, write and / or read decoding, word line selection, bit line selection, data drive, and memory self-test. For the purpose of explanation, the logic functions of the above-mentioned logic cells are given. Various logic functions of the logic cell are within the intended scope of the present disclosure. In the illustrated embodiment, the macro 20 includes a circuit area 22, in which at least one memory array 24 and at least one peripheral circuit 26 are positioned very close to each other. The memory array 24 includes many memory cells arranged in rows and columns. The peripheral circuit 26 includes a logic cell. Typically, the peripheral circuit 26 may include many logic cells to provide read operations and / or write operations to the memory cells in the memory array 24. The macro 20 may include more than one memory array 24 and more than one peripheral circuit 26. The transistors in one or more memory arrays 24 and one or more peripheral circuits 26 can be implemented with various PFETs and NFETs, such as planar transistors or non-planar transistors, including various FinFET (fin field effect) transistors, GAA transistors, or combinations thereof. A GAA transistor refers to a transistor having a gate electrode surrounding a transistor channel, such as a vertically stacked gate surrounding a horizontal nanowire or nanosheet MOSFET device. The following disclosure will continue with one or more GAA examples to illustrate various embodiments of the present disclosure. However, it should be understood that the application should not be limited to a specific type of device unless specifically required. For example, aspects of the present disclosure may also be applied to implementations based on FinFETs or planar FETs.

[0026] Figure 2 A portion of a macro 30 is shown, which includes a memory array 32, input / output (I / O) circuits 34, word line drivers 36, and control circuits 38. In some embodiments, macro 30 may be implemented as Figure 1 The memory array 32 can be implemented as Figure 1 and the input / output (I / O) circuit 34, the word line driver 36 and the control circuit 38 may be implemented together as Figure 1 For the sake of clarity, Figure 2 It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to macro 30, and some of the features described below may be replaced, modified, or eliminated in other embodiments of macro 30.

[0027] The memory array 32 includes memory cells arranged in rows and columns. In the illustrated embodiment, the memory cells are arranged from Row 1 to Row M, each memory cell extending along a first direction (here, in the X direction), and in Column 1 to Column N, each memory cell extending along a second direction (here, in the Y direction), where M and N are positive integers. Typically, N is a power of 2, such as 64, 128, 256, 512, etc. The present disclosure contemplates that N is any other integer. For simplicity of description, Figure 2 Only a few rows and columns and the corresponding memory cells are shown. Each memory cell stores one bit of data. Therefore, according to the position of the memory cell in the memory array 32, the memory cell is also called a bit cell or represented as a BC. MN , where M represents rows and N represents columns. For example, BC 11 BC represents the memory cell located in the first row (Row 1) and the first column (Column 1), which is the memory cell closest to the I / O circuit 34 in the first row (Row 1); 12 BC represents a memory cell located in the first row (Row 1) and the second column (Column 2), which is the memory cell in the first row (Row 1) that is the second closest to the I / O circuit 34; 1N BC represents a memory cell located in the first row (Row 1) and the last column (Column N), which is the memory cell farthest from the I / O circuit 34 in the first row (Row 1); MN Represents the memory cell located in the last row (Row M) and the last column (Column N). For simplicity, the memory cell BC MN It can be called BC.

[0028] Rows 1 to M each include a bit line pair extending in the X direction, such as a bit line (BL) and an inverted bit line (BLB) (also referred to as a complementary bit line), which facilitates reading data from and / or writing data to each memory cell BC in true and complementary form row by row. Rows 1 to M each include a word line (WL) that facilitates accessing each memory cell BC column by column. Each memory cell BC is electrically connected to a corresponding BL, a corresponding BLB, and a corresponding WL.

[0029] I / O circuit 34 is coupled to memory array 32 through bit line pair BL and BLB. In some embodiments, I / O circuit 34 is configured to select one of the rows in memory array 32 and provide a bit line signal on one of the bit line pairs arranged on the selected row. The bit line signal is transmitted to the corresponding memory cell BC through the selected bit line pair BL and BLB for writing bit data into the corresponding memory cell BC or reading bit data from the corresponding memory cell BC.

[0030] The word line driver 36 is coupled to the memory array 32 through the word lines WL. In some embodiments, the word line driver 36 is configured to select one of the columns in the memory array 32 and provide a word line signal on one of the word lines WL arranged on the selected column. The word line signal is transmitted to the corresponding memory cell BC through the selected word line WL for writing bit data into the corresponding memory cell BC or reading bit data from the corresponding memory cell BC.

[0031] The control circuit 38 is coupled to the I / O circuit 34 and the word line driver 36 and is disposed adjacent to the I / O circuit 34 and the word line driver 36. The control circuit 38 configures the I / O circuit 34 and the word line driver 36 to generate one or more signals to select at least one WL and at least one bit line pair (here BL and BLB) to access at least one of the memory cells BC for a read operation and / or a write operation. The control circuit 38 includes any circuit suitable for facilitating a read / write operation from the memory cell BC to the memory cell BC, including but not limited to a column decoder circuit, a row decoder circuit, a column selection circuit, a row selection circuit, a read / write circuit (e.g., configured to read data from and / or write data to the memory cell BC corresponding to the selected bit line pair (in other words, the selected column), other suitable circuits or combinations thereof. In some embodiments, the control circuit 38 is implemented by a processor. In some other embodiments, the control circuit 38 is integrated with the processor. The processor is implemented by a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0032] In a write or read operation, the I / O circuit 34 and the word line driver 36 select at least one pair of bit lines and at least one word line WL, respectively. When a word line WL on a corresponding column is selected, a bit line signal is transmitted from the I / O circuit 34 to a corresponding memory cell BC, or the bit line signal is transmitted from the memory cell BC to the I / O circuit 34. Memory cells far from the I / O circuit 34, such as the memory cell BC 1N, which is more sensitive to the delay affected by parasitic capacitance. However, the transmission path along the signal lines in the bit line pair (here, BL and BLB extending through columns 1 to N) to such a memory cell is relatively long and is prone to introducing large parasitic capacitance. Therefore, memory cells far from the I / O circuit 34 may want to "experience" narrower signal lines to reduce parasitic capacitance. In contrast, for memory cells located near the I / O circuit 34, such as memory cell BC 11 , the transmission path along the signal lines in the bit line pair (here, BL and BLB extend through columns 1 to N) is relatively short, and the memory cells are less sensitive to parasitic capacitance. Therefore, memory cells located near the I / O circuit 34 may want to "experience" a wider signal line to expand the voltage margin. Therefore, in order to further optimize performance, memory cells located in different columns of the memory array have different requirements for the size of the signal line (e.g., the width of BL and BLB in the bit line pair).

[0033] Figure 3 is a circuit diagram of an exemplary SRAM cell 50, which may be implemented as Figure 2 The memory cell BC in Figure 1 In the semiconductor device 10 of FIG. 1 , the SRAM cell 50 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, the SRAM cell 50 may be other types of memory cells, such as a dual-port memory cell or a memory cell having more than six transistors. For clarity, Figure 3 It is simplified for better understanding of the inventive concepts of the present disclosure. Additional components may be added in the single-port SRAM cell 50 , and some of the components described below may be replaced, modified, or eliminated in other embodiments of the single-port SRAM cell 50 .

[0034] The exemplary SRAM cell 50 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a storage portion of the SRAM cell 50, which includes a pair of cross-coupled inverters (inverter 52 and inverter 54). Inverter 52 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and inverter 54 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type FinFET transistors or p-type GAA transistors, and the pull-down transistors PD-1 and PD-2 are configured as n-type FinFET crystals or n-type GAA transistors.

[0035] The gate of the pull-up transistor PU-1 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of the pull-down transistor PD-1 is inserted between the source (electrically coupled to the power supply voltage (VSS), which may be electrically grounded) and the first common drain. The gate of the pull-up transistor PU-2 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is inserted between the source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in true form, and the second common drain CD2 is a complementary storage node SNB that stores data in complement form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are coupled to the second common drain CD2, and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are coupled to the first common drain CD1. The gate of the transfer gate transistor PG-1 is inserted between the source (electrically coupled to the bit line BL) and the drain, and the drain is electrically coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-2 is inserted between the source (electrically coupled to the complementary bit line BLB) and the drain, and the drain is electrically coupled to the second common drain (CD2). The gates of the transfer gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some embodiments, the transfer gate transistors PG-1 and PG-2 provide access to the storage nodes SN and SNB during a read operation and / or a write operation. For example, the transfer gate transistors PG-1 and PG-2 couple the storage nodes SN and SNB to the bit lines BL and BLB, respectively, in response to the voltage applied to the gates of the transfer gate transistors PG-1 and PG-2 by the word line WL.

[0036] Figure 4 1 is a partial schematic cross-sectional view of a semiconductor device 100 according to various aspects of the present disclosure, the semiconductor device 100 including a portion of a memory device (eg, Figure 2 Memory macro 30) and / or a portion of an SRAM cell (such as Figure 3 The various layers (levels) of the SRAM cell 50). Figure 4In the embodiment, each layer includes a device layer DL and a multi-layer interconnect MLI disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation component 64, and a transistor T. In the illustrated embodiment, the transistor T includes a suspended channel layer 70 and a gate structure 68 disposed between the source / drain 72, wherein the gate structure 68 surrounds and / or surrounds the suspended channel layer 70. Each gate structure 68 has a metal gate stack formed by a gate electrode 74 disposed on a gate dielectric 76, and a gate spacer 78 is disposed along the sidewall of the metal gate stack. The multi-layer interconnect MLI electrically couples the various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements of the memory.

[0037] In the depicted embodiment, the multilayer interconnect MLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero (M0) level, a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates multilayer interconnect MLIs with more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the multilayer interconnect MLI is 2 to 10. Each layer of the multilayer interconnect MLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level (e.g., M0 level) of the multilayer interconnect MLI are formed simultaneously. In some embodiments, conductive features at the same level of the multilayer interconnect MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially planar to each other. The CO level includes a source / drain contact (MD) disposed in the dielectric layer 66; the V0 level includes a gate via VG, a source / drain contact via VD, and a butt contact disposed in the dielectric layer 66; the M0 level includes an M0 metal line disposed in the dielectric layer 66, wherein the gate via VG connects the gate structure to the M0 metal line, the source / drain contact via VD connects the source / drain to the M0 metal line, and the butt contact connects the gate structure and the source / drain together and to the M0 metal line ; The V1 level includes a V1 via set in the dielectric layer 66, wherein the V1 via connects the M0 metal line to the M1 metal line; the M1 layer includes the M1 metal line set in the dielectric layer 66; the V2 level includes a V2 via set in the dielectric layer 66, wherein the V2 via connects the M1 metal line to the M2 metal line; the M2 level includes the M2 metal line set in the dielectric layer 66; the V3 level includes a V3 via set in the dielectric layer 66, wherein the V3 via connects the M2 metal line to the M3 metal line.

[0038] According to various aspects of the present disclosure, an exemplary manufacturing process for forming a device layer DL and a multilayer interconnect MLI of the semiconductor device 100 may include forming an active region on a substrate, forming an isolation structure (e.g., shallow trench isolation (STI)) between adjacent active regions, forming a dummy gate on the active region, forming a gate spacer on a sidewall of the dummy gate, recessing the active region to form a source / drain recess, forming an internal spacer and a source / gate component in the source / source recess, depositing an interlayer dielectric (ILD) layer over the source / drain component and the dummy gate structure, performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to expose the dummy gate structure, replacing the dummy gate structure with a metal gate structure, and forming contacts, vias, and metal layers in the multilayer interconnect MLI.

[0039] For the sake of clarity, Figure 4 It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added in various layers of the memory, and some of the features described may be replaced, modified or eliminated in other embodiments of the memory. Figure 4 This is merely an example and may not reflect an actual cross-sectional view of the memory macro 30 and / or the SRAM cell 50 discussed in further detail below.

[0040] Figure 5 and Figure 6 It shows that Figure 3 An exemplary layout 200 of an SRAM cell 50 is shown, wherein Figure 5 The DL level, CO level and V0 level of the layout 200 are shown. Figure 6 The V0 level and the M0 level of the layout 200 are shown. The SRAM cell 50 has Figure 5 and Figure 6 . The cell boundary 202 is represented by the dotted line in . The cell boundary 202 is a rectangular box that is longer in the Y direction than in the X direction (e.g., about 3.5 times to about 6 times longer). The first dimension of the cell boundary 202 in the X direction is represented as the cell width W, and the second dimension of the cell boundary 202 in the Y direction is represented as the memory cell height H. In the case where the SRAM cell 50 is repeated in the memory array, the cell width W can be represented and referred to as the memory cell pitch in the memory array along the X direction, and the cell height H can be represented and referred to as the memory cell pitch in the memory array along the Y direction. In the embodiment shown, the cell width W is twice the poly pitch. The poly pitch refers to the minimum center-to-center distance between two adjacent gate structures in the X direction.

[0041] The SRAM cell 50 includes an active region 205 (including 205A, 205B, 205C, and 205D) oriented longitudinally along the X direction, and a gate structure 240 (including 240A, 240B, 240C, and 240D) oriented longitudinally along the Y direction perpendicular to the X direction. The active regions 205B and 205C are disposed above an n-type well (or n-well) 204N. The active regions 205A and 205D are disposed above a p-type well 204P located on both sides of the n-well 204N along the Y direction. The gate structure 240 joins the channel regions of the respective active regions 205 to form a transistor. In this regard, gate structure 240A is joined to the channel region of active region 205A to form an n-type transistor as a pass gate transistor PG-1; gate structure 240B is joined to the channel region of active region 205A to form an n-type transistor as a pull-down transistor PD-1, and is joined to the channel region of active region 205B to form a p-type transistor as a pull-up transistor PU-1; gate structure 240C is joined to the channel region of active region 205D to form an n-type transistor as a pull-down transistor PD-2, and is joined to the channel region of active region 205 to form a p-type transistor as a pull-up transistor PU-2; gate structure 240D is joined to the channel region of active region 205D to form an n-type transistor as a pass gate transistor PG-2. In this embodiment, each channel region is in the form of a vertically stacked nanostructure, and each transistor PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a GAA transistor. Alternatively, each channel region is in the form of a fin, and each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a FinFET transistor.

[0042] Different active areas in different transistors of the SRAM cell 50 may have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. In more detail, the active area 205A of the pull-down transistor PD-1 and the transfer gate transistor PG-1 has a width W1, the active area 205B of the pull-up transistor PU-1 has a width W2, the active area 205C of the pull-up transistor PU-2 has a width W2, and the active area 205D of the transfer gate PG-2 and the pull-down transistor PD-2 has a width W1. The widths W1 and W2 may also be measured in portions of the active area corresponding to the channel region. In other words, these portions of the active area (from which the widths W1 and W2 are measured) are the channel regions of the transistors (e.g., the vertically stacked nanostructures of the GAA device). In order to optimize SRAM performance, in some embodiments, the width W1 is configured to be greater than the width W2 (W1>W2) to balance the speed between the n-type transistor and the p-type transistor. In some embodiments, the ratio of W1 / W2 may be in the range of about 1.1 to about 3.

[0043] Width W1 being greater than width W2 increases the strength of the n-type transistor in SRAM cell 50, which results in a higher current handling capability of SRAM cell 50. This configuration of active regions is suitable for high current applications (such SRAM cells are referred to as high current SRAM cells). In some other embodiments, widths W1 and W2 may be the same (W1=W2). Reduced width W1 allows SRAM cell 50 to have a smaller cell height H. This configuration of active regions is suitable for high density applications (such SRAM cells are referred to as high density SRAM cells). Figure 1 Taking the macro 20 in FIG. 1 as an example, in one embodiment, the memory macro 20 may include a memory array 24 made entirely of high-current SRAM cells; in another embodiment, the memory macro 20 may include a memory array 24 made entirely of high-density SRAM cells; and in another embodiment, the memory macro 20 may include some memory arrays 24 made of high-current SRAM cells and some other memory arrays 24 composed of high-density SRAM cells.

[0044] The SRAM cell 50 also includes conductive components at the CO level, the V0 level, the M0 level, and even higher metal levels (e.g., the M1 level, the M2 level, etc.). The gate contact 260A electrically connects the gate of the pass-gate transistor PG-1 (formed by the gate structure 240A) to the first word line WL pad 280A. The first WL pad 280A is electrically coupled to the word line WL at the higher metal level. The gate contact 260L electrically connects the gate of the pass-gate transistor PG-2 (formed by the gate structure 240D) to the second word line WL pad 280L. The second WL pad 280L is electrically coupled to the word line WL at the higher metal level. Source / drain (S / D) contact 260K electrically connects the drain region of pull-down transistor PD-1 (formed on active region 205A, which may include n-type epitaxial source / drain components) and the drain region of pull-up transistor PU-1 (formed on active region 205B, which may include p-type epitaxial source / drain components), such that the common drain of pull-down transistors PD-1 / PU-1 forms storage node SN. Gate contact 260B may be a butt contact adjacent to source / drain contact 260K. Source / drain contact 260C electrically connects the drain region of pull-down transistor PD-2 (formed on active region 205D, which may include n-type epitaxial source / drain components) to the drain region of pull-up transistor PU-2 (formed on active region 205C, which may include p-type epitaxial source / drain components), such that the common drain of pull-down transistor PD-2 and pull-up transistor PU-2 forms a complementary storage node SNB. Gate contact 260D electrically connects the gate of pull-up transistor PU-1 (formed by gate structure 240B) and the gate of pull-down transistor PD-1 (also formed by gate structure 240B) to complementary storage node SNB. Gate contact 260D may be a butt contact adjacent to S / D contact 260C.

[0045] The S / D contact 260E and the S / D contact via 270E landed thereon electrically connect the source region of the pull-up transistor PU-1 (formed on the active area 205B, which may include a p-type epitaxial source / drain component) to the VDD line 280E. The VDD line 280E is electrically coupled to the power supply voltage VDD. The S / D contact 260F and the S / D contact via 270F landed thereon electrically connect the source region of the pull-up transistor PU-2 (formed on the active area 205C, which may include a p-type epitaxial source / drain component) to the VDD line 280E. The S / D contact 260G and the S / D contact via 270G landed thereon electrically connect the source region of the pull-down transistor PD-1 (formed on the active area 205A, which may include an n-type epitaxial source / drain component) to the first VSS landing pad 280G. The first VSS landing pad 280G is electrically coupled to the electrical ground VSS. The S / D contact 260H and the S / D contact via 270H landing thereon electrically connect the source region of the pull-down transistor PD-2 (formed on the active area 205D, which may include an n-type epitaxial source / drain component) to the second VSS landing pad 280H. The second VSS landing pad 280H is electrically coupled to the electrical ground VSS. The S / D contact 260G and the S / D contact 260H may be device-level contacts shared by adjacent SRAM cells 50 (e.g., four SRAM cells 50 adjacent at the same corner may share one S / D contact 260H). The S / D contact 260I and the S / D contact via 270I landing thereon electrically connect the source region of the pass-gate transistor PG-1 (formed on the active area 205A, which may include an n-type epitaxial source / drain component) to the bit line BL 280I. S / D contact 260J and S / D contact via 270J landing thereon electrically connect the source region of pass-gate transistor PG- 2 (formed on active region 205D, which may include n-type epitaxial source / drain features) to complementary bit line (bar bit line) BLB 280J.

[0046] Conductive components in the CO level, M0 level, and higher metal levels (e.g., M1 level, M2 level, etc.) are routed along a first routing direction or a second routing direction different from the first routing direction. For example, the first routing direction is the X direction (and is substantially parallel to the longitudinal direction of the active regions 205A-205D), and the second routing direction is the Y direction (and is substantially parallel to the longitudinal direction of the gate structures 240A-240D). In the depicted embodiment, the source / drain contacts (260C, 260E, 260F, 260G, 260H, 260I, 260J) have a longitudinal (length) direction substantially along the Y direction (i.e., the second routing direction), and the butt contacts (260B, 260D) have a longitudinal direction substantially along the X direction (i.e., the first routing direction). The metal lines of the even-numbered metal layers (i.e., the M0 and M2 levels) are wired along the X direction (i.e., the first wiring direction), and the metal lines of the odd-numbered metal layers (i.e., the M1 and M3 levels) are wired along the Y direction (i.e., the second wiring direction). Figure 6 In the M0 level shown, the bit line 280I, the inverted bit line 280J, the VDD line 280E, the VSS landing pad 280G, the VSS landing pad 280H, the word line landing pad 280A, and the word line landing pad 280L have a longitudinal direction substantially along the X direction. In addition, since the metal lines in the same metal layer (e.g., the M0 layer) have the same longitudinal direction, the metal lines can be located in a metal track arranged in parallel. The metal track can include one or more metal lines. For example, the metal track can include a single metal line extending through the entire SRAM cell, or the metal track can include one or more local metal lines that do not extend through the entire SRAM cell.

[0047] The metal lines shown are generally rectangular (i.e., each metal line is longer than its width), but the present disclosure contemplates metal lines having different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce density). For example, VDD line 280E may optionally be added as Figure 6 The stepped portion of VDD line 280E has a greater width than other portions of VDD line 280E. The step may add about 1% to about 50% additional width to VDD line 280E. The step is added to the interconnection region (area) of VDD line 280E to increase the cross-sectional area of ​​the interconnection region. Increasing the cross-sectional area of ​​the interconnection region of VDD line 280E allows for increasing the cross-sectional area of ​​S / D contact vias 270E and 270F in the V0 level, which reduces the wiring resistance between the connection of VDD line 280E and the corresponding source / drain contacts (thereby reaching the source / drain regions below).

[0048] A "landing pad" generally refers to a metal line in a metal layer that provides an intermediate local interconnect for an SRAM cell, such as an intermediate local interconnect between (1) a device-level component (e.g., a gate or source / drain) and a bit line, an inverted bit line, a word line, a voltage line, or (2) an intermediate local interconnect between a bit line, a word line, or a voltage line. For example, VSS landing pad 280G is connected to source / drain contact 260G of transistor PD-1 and further connected to a VSS line at a higher metal level, VSS landing pad 280H is connected to source / drain contact 260H of pull-down transistor PD-2 and further connected to a VSS line at a higher metal level, word line landing pad 280A is connected to the gate of pass-gate transistor PG-1 and further connected to word line WL at a higher metal level, and word line landing pad 280L is connected to the gate of pass-gate transistor PG-2 and further connected to word line WL at a higher metal level. The landing pad has a sufficiently large longitudinal dimension to provide sufficient landing area for the overlying via (thereby minimizing overlap issues and providing greater patterning flexibility). In the depicted embodiment, the longitudinal dimension of the landing pad is smaller than the dimension of the SRAM cell 50, for example, the dimension along the X direction is smaller than the cell width W, and the dimension along the Y direction is smaller than the cell height H. Compared with the landing pad, the bit line 280I, the inverted bit line 280J, and the VDD line 280E have a longitudinal dimension along the X direction that is larger than the cell width W of the SRAM cell 50. When they pass through the entire SRAM cell 50 along the X direction, the bit line 280I, the inverted bit line 280J, and the VDD line 280E of the M0 level are also referred to as global metal lines, while the other lines are referred to as local metal lines (including the landing pad). In some embodiments, the length of each of the bit line 280I, the inverted bit line 280J, and the VDD line 280E is sufficient to allow multiple SRAM cells in a column (or row) to be electrically connected to the corresponding global metal line.

[0049] The metal lines (global metal lines and local metal lines) in the SRAM cell 50 at the M0 level can have different widths. For example, the VDD line 280E has a width Wa, and the bit line 280I and the inverted bit line 280J both have a width Wb. In some embodiments, the width Wb is greater than the width Wa (Wb>Wa). The maximum width reserved for the bit line 280I and the inverted bit line 280J allows the signal line in the bit line pair to generally benefit from the reduction in resistance, thereby reducing the voltage drop along the signal line. In some embodiments, the ratio of the width Wb to the width Wa (i.e., Wb / Wa) is about 1.1 to about 2. In some embodiments, the width Wa is greater than the width Wb (Wa>Wb). The maximum width reserved for the VDD line 280E allows the VDD line 280E to generally benefit from the reduction in resistance, thereby benefiting from the reduction in voltage drop along the power line. In some embodiments, the ratio of the width Wa to the width Wb (i.e., Wa / Wb) is about 1.1 to about 2.

[0050] Figure 7 Memory macro 30 ( Figure 2 ), which includes the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit (or I / O region) 34. For clarity, Figure 7 Simplified to better understand the inventive concept of the present disclosure. For example, the memory array 32 ( Figure 2 ) of the first two columns and rows of SRAM cells (i.e., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 ) in the V0 level active area, gate structure, gate cut isolation components and vias, and Figure 7 Many other parts are omitted.

[0051] The SRAM cells in the memory array 32 include active regions of the first type (e.g., 205A and 205B), and the logic cells in the I / O region 34 include active regions of the second type (e.g., 305). The active regions in the memory array 32 are arranged along the Y direction and are longitudinally oriented along the X direction. As described above, the active regions (e.g., 205A and 205B) may have different widths and / or the same width (e.g., Figure 5 3 and 4). In other words, the memory array 32 may include high current SRAM cells or high density SRAM cells according to application needs. In addition, the memory macro 30 may include a first memory array 32 composed of high current SRAM cells and a second memory array 32 composed of high density SRAM cells. Each memory array 32 composed of high current or high density SRAM cells may adopt a bit line structure with non-uniform width, which will be explained in further detail below.

[0052] The active areas in the I / O region 34 are arranged along the Y direction and are longitudinally oriented in the X direction. In the illustrated embodiment, the active areas 305 are uniformly distributed along the Y direction, and each active area has a uniform width. The memory macro also includes a gate structure 340 arranged along the X direction and extending longitudinally in the Y direction. In the illustrated embodiment, the gate structures 340 are uniformly distributed along the X direction, and the distance between two adjacent gate structures 340 is uniform. The uniform distance is expressed as a gate pitch or a polysilicon pitch ("PP"). The SRAM cell width W can also be measured by the number of polysilicon pitches. In the illustrated embodiment, the SRAM cell width W is twice the polysilicon pitch. The width of the memory array 32 along the X direction can also be measured by the number of polysilicon pitches. Since the width W of each SRAM cell is twice the polysilicon pitch, for the case where there are N SRAM cells in a row, the width of the memory array 32 is 2*N polysilicon pitches.

[0053] The gate structure 340 intersects the active region when forming transistors. The transistors formed at the intersection of the active region and the gate structure 340 within the memory array 32 are dedicated to forming SRAM cells. The transistors formed at the intersection of the active region and the gate structure 340 within the I / O region 34 are dedicated to forming logic cells. In the illustrated embodiment, the transistors in the SRAM array 32 form a plurality of SRAM cells, such as SRAM cell BC. 11 , B.C. 12 , B.C. 21 , B.C. 22 (collectively referred to as SRAM cells BC). Each SRAM cell BC in the array can be used as follows Figure 5 Layout 200 of the SRAM cell 50 is shown. In some embodiments, two adjacent SRAM cells in the X direction are symmetrical with respect to the common boundary between them, and two adjacent SRAM cells in the Y direction are also symmetrical with respect to the common boundary between them. That is, the SRAM cells BC 12 It is SRAM cell BC 11 A replica of the cell, but flipped on the Y axis; SRAM cell BC 22 It is SRAM cell BC 12 A replica of the cell, but flipped on the X axis; SRAM cell BC 21 It is SRAM cell BC 11 A copy of the cell, but flipped on the X axis.

[0054] Some active regions extend across multiple SRAM cells in a row. For example, SRAM cell BC 11 The active regions of transistors PD-1 and PG-1 extend through the SRAM cell BC. 12As the active area of ​​its transistors PG-1, PD-1, and further through other SRAM cells BC in row 1; SRAM cell BC 11 The active regions of transistors PG-2 and PD-2 extend through the SRAM cell BC. 12 As the active area of ​​its transistors PD-2, PG-2, and further through other SRAM cells BC in row 1; SRAM cell BC 11 The active area of ​​transistor PU-2 in the SRAM cell BC extends to 12 The active area of ​​the transistor PU_2 is used as the active area of ​​the SRAM cell BC. 21 , B.C. 22 The active regions in are arranged similarly. Figure 7 Also shown in FIG. 5 is a through hole at the V0 level in the SRAM cell.

[0055] In the illustrated embodiment, the transistors in the I / O region 34 form a plurality of logic cells. The logic cells may be standard cells, such as inverters (INV), AND, OR, NAND, NOR, flip-flops, SCAN, etc. The logic cells implement various logic functions for the SRAM cells BC. The logic functions of the logic cells include, for example, write and / or read decoding, word line selection, bit line selection, data drive, and memory self-test. As shown, each logic cell has a logic cell height CH, which is half the height H of the SRAM cell. Therefore, the two logic cells have a border, whose opposite edges are aligned with the opposite edges of the border of one SRAM cell, the edges are spaced apart in the Y direction, and each edge extends in the X direction.

[0056] Between the relative boundary lines of the SRAM cells in the memory array 32 and the logic cells in the I / O area 34 is an active area transition area 40, or simply referred to as a transition area. In the transition area 40, the active area 205A extending from the edge column of the SRAM cell intersects with the active area 305 extending from the edge column of the logic cell. Since the intersecting pair of active areas 205A, 305 can have different widths, a step is generated where the active areas 205A, 305 intersect. A step refers to the junction where two parts of different widths intersect. For example, in the area 372A represented by the dotted circle, the relatively wide active area 205A intersects with the relatively narrow active area 305, thereby forming a step. The upper edges of the active areas 205A, 305 are aligned, and the lower edges of the active areas 205A, 305 form a step profile. Similarly, in region 372B represented by another dotted circle, relatively narrow active region 205B intersects relatively wide active region 305, thereby creating another step. The lower edges of active regions 205B, 305 are aligned, while the upper edges of active regions 205A, 305 form a stepped profile.

[0057] As shown in the layout 300, the transition region 40 has a span of one polysilicon pitch along the X direction between the opposite boundary lines of the SRAM cell and the logic cell. In the transition region 40, the dielectric component (or isolation component) 374 is oriented longitudinally in the Y direction and provides isolation between the active area in the memory array 32 and the I / O area 34. The dielectric component 374 overlaps the step. In the exemplary layout 300, the dielectric component 374 extends continuously along the boundary line of the SRAM cell and the logic cell in the Y direction. In other words, the dielectric component 374 is higher than the SRAM cell height H.

[0058] The dielectric component 374 can be formed in a continuous polycrystalline diffusion edge (CPODE) process. In the CPODE process, the polysilicon gate is replaced by a dielectric component. For the purpose of this disclosure, a "diffusion edge" can be equivalently referred to as an active edge, where, for example, the active edge abuts an adjacent active area. Before the CPODE process, the active edge can include a pseudo GAA structure having a pseudo gate structure (e.g., a polysilicon gate) and a plurality of vertically stacked nanostructures as a channel layer. In addition, an internal spacer can be disposed between adjacent nanostructures at the lateral ends of the nanostructure. In various examples, the source / drain epitaxial component is disposed on either side of the pseudo GAA structure so that the adjacent source / drain epitaxial component contacts the internal spacer and nanostructure of the pseudo GAA structure. The subsequent CPODE etching process removes the pseudo gate structure and the channel layer from the pseudo GAA structure to form a CPODE trench. The dielectric material that fills the CPODE trench for isolation is called a CPODE component. In some embodiments, after the CPODE component is formed, in a replacement gate (last gate) process, the remaining dummy gate structure is replaced by a metal gate structure. In other words, in some embodiments, the CPODE component replaces part or all of the originally continuous gate structure and is confined between the relative gate spacers of the replaced portion of the gate structure. The dielectric component 374 is also referred to as a gate cutting component or a CPODE component. Since the CPODE component 374 is formed by replacing the previously formed polysilicon gate structure, the CPODE structure 374 inherits the arrangement of the gate structure 340. That is, the CPODE component 374 can have the same width as the gate structure 340 and the same pitch as the gate structure 340.

[0059] Figure 8 Memory macro 30 ( Figure 2), which includes the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit 34. At the M0 level, the I / O region 34 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 300, two adjacent logic cells include eleven metal tracks arranged in sequence from the first (M0 track 1) to the eleventh (M0 track 11) along the Y direction. The center line of the metal track is Figure 8 The dotted line in .

[0060] The metal lines in the SRAM cells are aligned with the metal tracks in the I / O region 34, allowing the metal lines in the logic cells to extend into the SRAM cells. Therefore, no edge cells are required to provide metal transitions between the SRAM cells and the logic cells. In the M0 track 1, the VSS line extends to the SRAM cell BC 11 and merged with the VSS landing pad. In M0 track 2, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 3, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 4, the metal line as the bit line BL in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the bit line BL of multiple SRAM cells in the same row. In M0 track 5, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 6, the metal line as the VDD line in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the VDD line of multiple SRAM cells in the same row. In M0 track 7, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 8, the metal line as the inverted bit line BLB in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the inverted bit line BLB of multiple SRAM cells in the same row. In M0 track 9, the metal lines as signal lines in the logic cells are kept in the boundaries of the corresponding logic cells. In M0 track 10, the metal lines as signal lines in the logic cells are kept in the boundaries of the corresponding logic cells. In M0 track 11, the metal lines as VSS lines in the logic cells can extend through the boundaries of the respective logic cells but do not contact the word line WL landing pads.

[0061] The boundary of the SRAM cell can be adjacent to the boundary of one or two logic cells. One or two logic cells provide 2*N+1 metal tracks, where N is an integer. The metal line in the center metal track (the N+1th metal track) extends into the SRAM cell as a common VDD line for the SRAM cell and one or two logic cells. The two metal lines in the two metal tracks equidistant from the center metal track extend into the SRAM cell as a bit line BL and an inverted bit line BLB, respectively, for the SRAM cell and one or two logic cells. The two metal lines in the first and (2*N+1)th metal tracks extend across the boundary of one or two logic cells and are connected to one of the VSS landing pads in the SRAM cell.

[0062] In the illustrated embodiment, the metal lines in metal tracks 4 and 8 extend from the logic cell and pass through the SRAM cells in the same row, respectively, as the bit line BL and the inverted bit line BLB. Alternatively, depending on the layout, it may be the metal lines in metal tracks 2 and 10, or metal tracks 3 and 9, or metal tracks 5 and 7, which extend from the logic cell and pass through the SRAM cell as the bit line BL and the inverted bit line BLB. In this context, if not separately indicated, the bit line BL and the complementary bit line BLB may also be collectively referred to as the bit line.

[0063] In semiconductor memory design, a consistent bit line width is typically deployed between SRAM cells in a memory array. However, the preference for bit line width may differ depending on whether the SRAM cell is located near a logic cell in the I / O region 34 or at a certain distance from the logic cell in the I / O region 34. For SRAM cells in columns far from the I / O region 34, narrower bit lines help achieve a reduction in parasitic capacitance, thereby achieving faster access time and lower power consumption. In contrast, for SRAM cells in columns close to the I / O region 34, wider bit lines help achieve a reduction in resistance, which helps maintain voltage margin and signal integrity along the bit line. In the illustrated embodiment, each bit line (BL or BLB) has a non-uniform width (multiple widths), for example, for SRAM cells in columns closer to the I / O region 34, the width Wb1 is larger, while for columns at a certain distance from the I / O region 34, the width Wb2 is smaller (Wb2<Wb1). The non-uniform width balances the performance requirements of SRAM cells at different locations in the memory array. The details of the non-uniform widths of the bit lines are explained further below.

[0064] Fig. 9 Similar to Figure 8 , further showing columns Q-1 and Q, where a transition in bit line width from Wb1 to Wb2 occurs. Figure 8 similar, Fig. 9 Also shown is a memory macro 30 ( Figure 2) The V0 and M0 levels of the layout 300 of a part. For simplicity, Fig. 9 Only the first two rows (Row1 - Row2) of the memory array 32 are shown in

[0065] In the memory array 32, each bit line (BL or BLB) is shared by the memory cells in the same row from column 1 to column N. In other words, N memory cells in the same row are coupled to (or fed by) the same bit line (BLB or BL). In some embodiments, N is a power of 2, such as 64, 128, 256, 512, etc. In some further embodiments, N is greater than 128 (e.g., N≥256). The present disclosure contemplates that N is any other integer. Each bit line is a straight line in the X direction, but has a first part (or section) connected to the SRAM cells from column 1 to column Q - 1, and a second part (or section) connected to the SRAM cells from column Q to column N. The first part of the straight line has a larger width Wb1, and the second part of the straight line has a smaller width Wb2 (Wb2 < Wb1). That is to say, the first part of the straight line feeds Q - 1 SRAM cells located closer to the I / O area 34, and the second part of the straight line feeds P = N - Q + 1 SRAM cells located farther from the I / O area 34. In some embodiments, Q = N - 63, which means the last 64 (P = 64) SRAM cells are fed by the narrower part of the bit line, while the remaining N - 64 SRAM cells in the same row are fed by the wider part of the bit line. In some embodiments, Q = N - 31, which means the last 32 (P = 32) SRAM cells are fed by the narrower part of the bit line, while the remaining N - 32 SRAM cells in the same row are fed by the wider part of the bit line. In some embodiments, P is greater than 0 and not greater than 64 (0 < P ≤ 64). This range is not arbitrary or insignificant because the last 64 SRAM cells may be most affected by parasitic capacitance. In some embodiments, P is not less than 32 and not greater than 64 (32 ≤ P ≤ 64). In some embodiments, P can be equal to one - quarter of N (P = N / 4), which means that the last quarter of the distal SRAM cells with respect to the I / O periphery is fed by the narrower part of the bit line. In some other embodiments, P can be equal to half of N (P = N / 2), which means that the last half of the distal SRAM cells with respect to the I / O periphery is fed by the narrower part of the bit line.

[0066] Since the bit line width affects the parasitic capacitance, which may impede the circuit speed, a smaller width Wb2 reduces the parasitic capacitance, thereby increasing the circuit speed and reducing the power consumption of the SRAM cells in the last few columns of the memory array 32, without affecting the voltage margin of the remaining SRAM cells along the bit line. At the same time, a larger width Wb1 reduces the resistance, which increases the voltage margin along the bit line and improves the signal integrity. Although the larger width Wb1 introduces more parasitic capacitance for the first few columns of the memory array 32, the benefit of having a smaller voltage drop for all SRAM cells along the bit line outweighs the slight circuit speed trade-off due to having slightly more parasitic capacitance. In various embodiments, the ratio between the larger width Wb1 and the width W1 of the active region 205A ( Figure 5 ) in the high-current SRAM cells (i.e., SRAM cells with W1>W2) ranges between about 1.5 and about 5 (1.5 < Wb1 / W1 ≤ 5), and the ratio between the smaller width Wb2 and the width W1 of the active region 205A in the high-current SRAM cells ranges between about 1 and about 1.5 (1 < Wb2 / W1 ≤ 1.5). These ranges are not trivial or arbitrary. If Wb1 / W1 is less than about 1.5, there may not be enough voltage margin for the long bit line; if Wb1 / W1 is greater than about 5, the bit line may be too wide and intersect adjacent power / signal lines; if Wb2 / W1 is less than about 1, the bit line may become too resistive, thereby reducing the circuit speed in reverse; and if Wb2 / W1 is greater than about 1.5, the parasitic capacitance may be too large and the circuit speed may be impaired. Similarly, in various embodiments, the ratio between the larger width Wb1 and the width W1 of the active region 205A ( Figure 5 ) in the high-density SRAM cells (i.e., SRAM cells with W1 = W2) ranges between about 3 and about 15 (3 < Wb1 / W1 ≤ 15), and the ratio between the smaller width Wb2 and the width W1 of the active region 205A in the high-density DRAM cells ranges between about 2 and about 3 (2 < Wb2 / W1 ≤ 3).

[0067] The transition from the larger width Wb1 to the smaller width Wb2 may occur at the cell boundary between column Q-1 and column Q. In other words, the transition from the larger width Wb1 to the smaller width Wb2 creates a step, which may be located at the cell boundary between column Q-1 and column Q. Alternatively, the width transition (or step) may be within the cell boundary of the SRAM cell in column Q-1 or within the SRAM cell boundary of column Q. Fig. 9An enlarged view of the area 350 where the step is located is shown. Each bit line (BL or BLB) has a first edge facing away from the VDD line (oppositely facing the VSS landing pad) and a second edge facing the VDD line. The step has a first distance J1 to the first edge and a second distance J2 to the second edge. In the illustrated embodiment, J1<J2, which means that the center line of the narrower section of the bit line is offset from the VDD line relative to the center line of the wider section of the bit line. In other words, the step may not necessarily be located at the center of the bit line, but away from the VDD line (but towards the VSS landing pad). This structural design is to provide a source / drain contact through hole 270I (or 270J, such as 270J) that can be offset from the center line of the bit line. Figure 6 In other words, since the step and source / drain contact vias 270I / 270J may both be located at the cell boundary between column Q-1 and column Q, and therefore overlap, offsetting the step from the centerline of the bitline may provide a larger landing area for the source / drain contact vias 270I / 270J to mitigate overlay errors during manufacturing. Alternatively, depending on the exact location of the source / drain contact vias 270I / 270J, the step may be located at the center of the bitline (J1=J2) or offset toward the VDD line (J1>J2). With respect to the VDD line sandwiched between the BL and BLB lines, the step position on the BL line with distances J1 and J2 is symmetrical to the step position on the BLB line with distances J1 and J2.

[0068] Fig.10 The Fig. 9 Partial cross-sectional views of sections AA, BB, A'-A' and B'-B'. Fig. 9 As shown, the cross section AA is along the memory cell BC 11 and B.C. 12 Between and memory cell BC 21 and B.C. 22 The cell boundary between the two passes through the source / drain region; the cross section BB passes through the memory cell BC 11 and B.C. 21 The gate structure 340; the cross section A'-A' is along the memory cell BC 1Q-1 and B.C. 1Q Between and memory cell BC 2Q-1 and B.C. 2Q The cell boundary between the two passes through the source / drain region; the cross section B'-B' passes through the memory cell BC 1Q and B.C. 2Q The gate structure 340. Fig.10 In the example, each section is symmetric with respect to the mirror axis MA.

[0069] Now referring to cross sections AA and BB together, they show a wider bit line width Wb1. Active region 205A includes a plurality of nanostructures as channel layers stacked vertically above a fin-shaped substrate. The channel layers provide a channel region for n-type pass gate transistor PG-1. Active region 205A has a width W1 measured on the topmost channel layer. In the source / drain region, source / drain epitaxial features SD 205A Epitaxial growth is performed on the fin-shaped substrate of the active area 205A. The source / drain epitaxial component SD 205A Electrically coupled to the bit line BL through the S / D contact 260I and the S / D contact through-hole 270I. A portion of the bit line BL has a first width Wb1, and the first width Wb1 is greater than the second width Wb2. The active area 205B includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-1. Measured on the topmost channel layer, the active area 205B has a width W2. In a high-current SRAM cell, the width W2 is less than the width W1 (W2<W1); in a high-density SRAM cell, the width W2 can be equal to the width W1 (W1=W2). The active area 205C includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-2. Measured on the topmost channel layer, the active area 205C has a width W2. In the source / drain region, the source / drain epitaxial component SD 205C Epitaxial growth is performed on the fin-shaped substrate of the active region 205C. The source / drain epitaxial component SD 205C Electrically coupled to the VDD line through the S / D contact 260F and the S / D contact via 270F. Section AA can be cut along the stepped portion of the VDD line, and its width Wa' is greater than the width Wa of the VDD line in section BB. As shown, the width Wb1 of the bit line BL can be wider than both the width Wa and Wa'; alternatively, the width Wb1 can be greater than the width Wa but less than the width Wa' of the stepped portion. The selection of the width may depend on specific circuit performance requirements. The active area 205D includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the n-type pull-down transistor PD-2. Measured on the topmost channel layer, the active area 205D has a width W1. In the source / drain region, the source / drain epitaxial component SD 205D Epitaxial growth is performed on the fin-shaped substrate of the active region 205D. The source / drain epitaxial component SD 205D The S / D contact 260H and S / D contact via 270H are electrically coupled to the VSS landing pad. The mirrored placement of the SRAM cell allows a larger S / D contact 260H to land on the source / drain epitaxial feature SD. 205DSections AA and BB also depict a bit bar line BLB disposed between the VDD line and the VSS landing pad. Portions of the bit bar line BLB have the same width Wb1 as portions of the bit line BL.

[0070] Referring now to cross sections A'-A' and B'-B' together, they show a narrower bit line width Wb2. Active region 205A includes a plurality of nanostructures as channel layers stacked vertically above a fin-shaped substrate. The channel layers provide a channel region for an n-type pass gate transistor PG-1. Active region 205A has a width W1 measured on the topmost channel layer. In the source / drain region, source / drain epitaxial features SD 205A Epitaxial growth is performed on the fin-shaped substrate of the active area 205A. The source / drain epitaxial component SD 205A Electrically coupled to the bit line BL through the S / D contact 260I and the S / D contact through-hole 270I. A portion of the bit line BL has a second width Wb2 that is less than the first width Wb1. The active area 205B includes a plurality of nanostructures as a channel layer stacked vertically above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-1. Measured on the topmost channel layer, the active area 205B has a width W2. In a high-current SRAM cell, the width W2 is less than the width W1 (W2<W1); in a high-density SRAM cell, the width W2 can be equal to the width W1 (W1=W2). The active area 205C includes a plurality of nanostructures as a channel layer stacked vertically above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-2. Measured on the topmost channel layer, the active area 205C has a width W2. In the source / drain region, the source / drain epitaxial component SD 205C Epitaxial growth is performed on the fin-shaped substrate of the active region 205C. The source / drain epitaxial component SD 205C Electrically coupled to the VDD line through the S / D contact 260F and the S / D contact via 270F. Section A'-A' can be cut along the stepped portion of the VDD line, and its width Wa' is greater than the width Wa of the VDD line in section B'-B'. As shown, the width Wb2 of the bit line BL can be wider than both the width Wa and Wa'; alternatively, the width Wb2 can be greater than the width Wa of the stepped portion but less than the width Wa'. The selection of the width may depend on specific circuit performance requirements. The active area 205D includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the n-type pull-down transistor PD-2. Measured on the topmost channel layer, the active area 205D has a width W1. In the source / drain region, the source / drain epitaxial component SD 205D Epitaxial growth is performed on the fin-shaped substrate of the active region 205D. The source / drain epitaxial component SD 205DThe S / D contact 260H and S / D contact via 270H are electrically coupled to the VSS landing pad. The mirrored placement of the SRAM cell allows a larger S / D contact 260H to land on the source / drain epitaxial feature SD. 205D Sections A'-A' and B'-B' also depict a bit bar line BLB disposed between the VDD line and the VSS landing pad. Portions of the bit bar line BLB have the same width Wb2 as portions of the bit line BL.

[0071] In some further embodiments, the semiconductor memory design may optionally provide a third bit line width Wb3 that is even smaller than Wb2 ( Wb3 < Wb2 < Wb1 ). Fig.11 Such an embodiment is shown. Specifically, Fig.11 Memory macro 30 ( Figure 2 ), wherein each of the bit lines (BL or BLB) includes a first portion (or segment) having a larger width Wb1 of the SRAM cells at the proximal end relative to the I / O periphery, a second portion (or segment) having a medium width Wb2 of the SRAM cells in the middle of the memory array, and a third portion (or segment) having a narrower width Wb3 of the SRAM cells at the distal end relative to the I / O periphery. The width transition from Wb1 to Wb2 (first step) may occur at a cell boundary between the SRAM cells at column Q1-1 and column Q1, and the width transition from Wb2 to Wb3 (second step) may occur at a cell edge between the SRAM cells at column Q2-1 and column Q2. In one example, the memory array has a total of N columns, which are divided into 8 memory banks, and each memory bank has N / 8 columns of SRAM cells; in the same row, the last memory bank of the SRAM cells (the last N / 8 columns) is fed by the third part of the bit line with a narrower width Wb3, the first five memory banks of the SRAM cells (the first 5N / 8 columns) are fed by the first part of the bit line with a width Wb1, and the remaining 2 memory banks (the middle N / 4 columns) are fed by the second part of the bit line with a medium width Wb2. Taking N=256 as an example, each memory bank has 32 columns of SRAM cells, the SRAM cells of the last memory bank (32 columns) are coupled to the third part of the bit line with a width of Wb3, the SRAM cells of the first to fifth memory banks (160 columns) are coupled to the first part of the bit line with a width of Wb1, and the SRAM cells of the sixth to seventh memory banks (64 columns) are coupled to the second part of the bit line with a width of Wb2.

[0072] If a third bit line width Wb3 is provided in the semiconductor memory design, then in some embodiments, the minimum width Wb3 in the high current SRAM cell is consistent with the active area 205A ( Figure 5) The ratio between the width W1 of is between about 0.3 and about 1 (0.3 < Wb3 / W1 ≤ 1). Similarly, these ranges are not trivial or arbitrary. If Wb3 / W1 is less than about 0.3, the bit lines may become too resistive, which in turn reduces the circuit speed of the microcache; if Wb3 / W1 is greater than about 1, the parasitic capacitance may be too large and impede the circuit speed of the microcache. Similarly, in a high-density SRAM cell, the ratio between the minimum width Wb3 (if present) and the width W1 of the active region 205A is between about 0.5 and about 2 (0.5 < Wb3 / W1 ≤ 2).

[0073] To facilitate some embodiments, a semiconductor memory design may optionally provide a second I / O region that is distally coupled to the memory array relative to the first I / O region. Each bit line (BL or BLB) extends continuously through the memory array and enters the first and second I / O regions from both ends. Fig.12 Such an embodiment is shown. Specifically, Fig.12 shows the V0 level and the M0 level of the layout 500 of a portion of the memory macro 30 ( Figure 2 ), which portion includes the first two rows (Row1-2) of the memory array 32 and a portion of the logic units in the first and second I / O regions 34. The first and second I / O regions sandwich the memory array 32 in between. The memory array 32 has 2N columns. For simplicity, Fig.12 only the first two rows (Row1-2) of the memory array 32 are shown. In the same row, each bit line (BL or BLB) has two end portions with a larger width Wb1 and a middle portion with a smaller width Wb2. In other words, the 2N-column memory array 32 can be considered to have a first array of N columns and a second array of N columns, where the bit lines of the N columns have two different widths and are arranged as discussed in the embodiment with reference to Fig. 9 , and the bit lines of the N-column second array are arranged in a mirror image of the first array with respect to the cell boundary between column N and column N+1. Similarly, the 2N-column memory array 32 can be considered to have a first array of N columns and a second array of N columns, where the bit lines of the N columns have three different widths and are arranged as discussed in the embodiment with reference to Fig.11 , and the position of the N-column first array is arranged in a mirror image of the first array with respect to the cell boundary between column N and column N+1.

[0074] Various embodiments of the present disclosure show bit lines with non-uniform widths (e.g., different widths along the bit lines) in an SRAM array. In one embodiment, the SRAM array may have two or more bit line widths for memory cells at different distances from the I / O periphery, thereby improving circuit performance. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0075] In one exemplary aspect, the present disclosure provides a semiconductor device. The semiconductor device includes a memory array and an interconnect structure, the memory array including a plurality of memory cells arranged in a row, the interconnect structure being disposed above the memory cells and including a bit line. The bit line is coupled to each memory cell arranged in the row. The bit line has a first segment coupled to a first portion of the memory cell and a second segment coupled to a second portion of the memory cell, and the first segment has a first width, and the second segment has a second width less than the first width. In some embodiments, the number of the second portions of the memory cells is less than the number of the first portions of the memory cells. In some embodiments, the number of the second portions of the memory cells is not greater than 64. In some embodiments, the number of the second portions of the memory cells is not less than 32. In some embodiments, the number of the second portions of the memory cells is one-fourth the number of the memory cells arranged in the row. In some embodiments, the bit line is a third segment coupled to a third portion of the memory cell, and wherein the third segment has a third width less than the second width. In some embodiments, the number of the third portions of the memory cells is less than the number of the second portions of the memory cells, and wherein the number of the second portions of the memory cells is less than the number of the first portions. In some embodiments, the semiconductor device further comprises a logic circuit disposed beside the memory array and coupled to the memory cells arranged in a row, wherein a first portion of the memory cell is closer to the logic circuit than a second portion of the memory cell. In some embodiments, the logic circuit is a first logic circuit, and the semiconductor device further comprises a second logic circuit disposed beside the memory array and coupled to the memory cells arranged in a row. The first logic circuit and the second logic circuit sandwich the memory array along the length direction of the row. The bit line has a third section coupled to a third portion of the memory cell. The third portion of the memory cell is closer to the second logic circuit than the first portion of the memory cell. The third section has a third width equal to the first width. In some embodiments, the interconnect structure further comprises a complementary bit line coupled to each memory cell arranged in a row, wherein the complementary bit line has a first section coupled to the first portion of the memory cell and a second section coupled to the second portion of the memory cell, and the first section of the complementary bit line is narrower than the second section of the complementary bit line.

[0076] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a plurality of memory cells arranged along a first direction, wherein each memory cell includes at least a transmission gate transistor formed on an n-type active region and a pull-up transistor formed on a p-type active region; a voltage line suspended above the memory cell and extending longitudinally along the first direction, wherein the voltage line is coupled to the pull-up transistor of the memory cell; and a signal line suspended above the memory cell and extending longitudinally along the first direction, wherein the signal line includes a first section of a transmission gate transistor coupled to a first portion of the memory cell and a second section of a transmission gate transistor coupled to a second portion of the memory cell, and wherein the first section has a first width and the second section has a second width that is less than the first width. In some embodiments, the signal line is a bit line. In some embodiments, the n-type active region has a third width, and the fourth width of the p-type active region is less than the third width. In some embodiments, the ratio of the first width to the third width is in the range of about 1.5 to about 5, and the ratio of the second width to the third width is in the range of about 1 to about 1.5. In some embodiments, the n-type active region has a third width, and the fourth width of the p-type active region is equal to the third width. In some embodiments, a ratio of the first width to the third width is in a range of about 3 to about 15, and a ratio of the second width to the third width is in a range of about 2 to about 3. In some embodiments, a centerline of the second segment is offset from the voltage line relative to a centerline of the first segment.

[0077] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a memory array including memory cells arranged in M ​​rows and N columns, M and N are both integers; a logic region adjacent to the memory array and coupled to the memory cells; and an interconnect structure arranged above the memory array and the logic region, wherein the interconnect structure includes a signal line suspended directly above one of the M rows of memory cells. The signal line includes a first segment and a second segment, the first segment is coupled to the memory cells in the first column to the (Q-1)th column in the M rows, Q is an integer greater than 1 and less than N, the first column is closer to the logic region than the Nth column, and the first segment has a first width, and the second segment has a second width less than the first width. In some embodiments, N is greater than 128 and N-Q+1 is not greater than 64. In some embodiments, N-Q+1 is one quarter of N.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a memory array comprising a plurality of memory cells arranged in rows; as well as An interconnect structure is disposed above the memory cell and includes a bit line, wherein the bit line is coupled to each of the memory cells arranged in a row, wherein the bit line has a first segment coupled to a first portion of the memory cell and a second segment coupled to a second portion of the memory cell, and wherein the first segment has a first width and the second segment has a second width less than the first width.

2. The semiconductor device according to claim 1, wherein The number of the second portion of the memory cells is less than the number of the first portion of the memory cells.

3. The semiconductor device according to claim 2, wherein: The number of the second portion of the memory cells is one fourth the number of the memory cells arranged in the row.

4. The semiconductor device according to claim 1, wherein: The bit line serves as a third segment coupled to a third portion of the memory cell, and wherein the third segment has a third width that is smaller than the second width.

5. The semiconductor device according to claim 1, further comprising: A logic circuit is disposed adjacent to the memory array and coupled to the memory cells arranged in the row, wherein the first portion of the memory cell is closer to the logic circuit than the second portion of the memory cell.

6. The semiconductor device according to claim 5, wherein: The logic circuit is a first logic circuit, and the semiconductor device further includes: a second logic circuit disposed adjacent to the memory array and coupled to the memory cells arranged in the row, in: The first logic circuit and the second logic circuit sandwich the memory array along the length direction of the row, the bit line having a third section coupled to a third portion of the memory cell, The third portion of the memory cell is closer to the second logic circuit than the first portion of the memory cell, and The third section has a third width equal to the first width.

7. The semiconductor device according to claim 1, wherein The interconnect structure also includes a complementary bit line coupled to each of the memory cells arranged in the row, wherein the complementary bit line has a first segment coupled to the first portion of the memory cell and a second segment coupled to the second portion of the memory cell, and the first segment of the complementary bit line is narrower than the second segment of the complementary bit line.

8. A semiconductor device comprising: A plurality of memory cells are arranged along a first direction, wherein each of the memory cells at least comprises a transmission gate transistor formed on an n-type active region and a pull-up transistor formed on a p-type active region; a voltage line suspended above the memory cell and extending longitudinally along the first direction, wherein the voltage line is coupled to the pull-up transistor of the memory cell; and A signal line is suspended above the memory cell and extends longitudinally along the first direction, wherein the signal line includes a first section of the pass-gate transistor coupled to a first portion of the memory cell and a second section of the pass-gate transistor coupled to a second portion of the memory cell, and wherein the first section has a first width and the second section has a second width less than the first width.

9. The semiconductor device according to claim 8, wherein: A centerline of the second segment is offset from the voltage line relative to a centerline of the first segment.

10. A semiconductor device comprising: A memory array includes memory cells arranged in M ​​rows and N columns, where M and N are both integers; a logic region adjacent to the memory array and coupled to the memory cells; as well as an interconnect structure disposed above the memory array and the logic region, wherein the interconnect structure includes a signal line suspended directly above one of the M rows of memory cells, and in: The signal line includes a first section and a second section, the first section being coupled to the memory cells in the first column to the (Q-1)th column in the M rows, Q is an integer greater than 1 and less than N, The first column is closer to the logic region than the Nth column, and The first section has a first width, and the second section has a second width that is smaller than the first width.

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