Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the substrate comprises a plurality of active columns arranged in an array; the active column comprises a column body; the cylinder is provided with an inner hole; the conductive structure is located at the bottom of the inner hole; and the insulating dielectric layer is located on the conductive structure and fills the inner hole. The semiconductor structure has relatively small leakage current and relatively high switch ratio, and is beneficial to improving the electrical performance of a semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of dynamic random access memory (DRAM) technology, the size of storage cells is getting smaller and smaller, and its array architecture is from 8F to 2 Go to 6F 2 Then to 4F 2 (F: minimum pattern size obtainable under given process conditions).

[0003] In order to reduce the area of ​​a single array transistor as much as possible and pursue higher chip area utilization, vertical channel array transistor (VCT) technology has emerged. However, traditional VCTs are prone to leakage current during operation, which seriously affects the electrical performance of VCTs. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, in order to address the deficiencies in the prior art.

[0005] On the one hand, the present application provides a semiconductor structure, characterized in that it includes a substrate; the substrate includes a plurality of active pillars arranged in an array;

[0006] The active column comprises:

[0007] A column; the column having an inner hole;

[0008] A conductive structure located at the bottom of the inner hole;

[0009] The insulating medium layer is located on the conductive structure and fills the inner hole.

[0010] In some embodiments, the inner hole is located at the center of the column, and the ratio of the size of the inner hole to that of the column in the same direction is in a range of 1 / 3 to 1 / 2.

[0011] In some embodiments, the semiconductor structure further comprises:

[0012] A plurality of bit lines arranged at intervals along a second direction; the bit lines are located below the active pillars and extend along a first direction, the first direction intersecting the second direction;

[0013] The bit line includes: the conductive structures located in the same column along the first direction, and a connecting portion connecting the conductive structures adjacent to each other in the first direction.

[0014] In some embodiments, a material constituting the conductive structure is the same as or similar to a material constituting the connecting portion.

[0015] In some embodiments, the active pillar includes a channel region;

[0016] The semiconductor structure further includes a plurality of gates; the gates correspond to the active pillars one by one and cover the channel regions corresponding to the active pillars.

[0017] In some embodiments, the semiconductor structure further comprises: a gate dielectric layer; the gate dielectric layer at least conformally covers the sidewalls of the channel region;

[0018] The gate is located on a surface of the gate dielectric layer away from the active pillar.

[0019] On the other hand, the present application also provides a method for preparing a semiconductor structure, comprising:

[0020] A substrate is provided; a plurality of active pillars arranged in an array are formed on a surface of one side of the substrate; the active pillars include a pillar body, and the pillar body is formed with an inner hole;

[0021] forming a conductive structure at the bottom of the inner hole;

[0022] An insulating dielectric layer is filled in the inner hole.

[0023] In some embodiments, providing a substrate comprises:

[0024] Providing an initial substrate; performing a first patterning on the initial substrate to form a plurality of inner holes arranged in an array on a surface of one side of the initial substrate;

[0025] The initial substrate is patterned for the second time to form a plurality of active pillars arranged in an array in the initial substrate, and the inner holes correspond to the active pillars one by one; the retained initial substrate is used as the substrate.

[0026] In some embodiments, the preparation method further comprises:

[0027] A plurality of spaced-apart bit lines are formed below the active pillars; the bit lines extend along a first direction to connect with the conductive structures in the same row.

[0028] In some embodiments, forming a plurality of spaced-apart bit lines below the active pillars includes:

[0029] Etching the substrate to form a plurality of bit line trenches arranged at intervals and extending along the first direction below the active pillars; the bit line trenches expose the conductive structure;

[0030] A connecting portion of the bit line is formed in the bit line trench; each of the conductive structures located in the same column along the first direction and a connecting portion connected between adjacent conductive structures in the first direction together constitute the bit line.

[0031] In some embodiments, after the inner hole is filled with an insulating dielectric layer, the method for preparing the semiconductor structure further includes:

[0032] forming a gate dielectric layer; the gate dielectric layer at least conformally covers the sidewalls of the channel region of the active pillar;

[0033] A gate is formed; the gate covers the channel region of the active pillar.

[0034] In some embodiments, the method for preparing the semiconductor structure further includes:

[0035] Filling a first isolation dielectric layer in a space between adjacent active pillars in the first direction, and filling a second isolation dielectric layer in a space between adjacent active pillars in the second direction;

[0036] The forming of the gate comprises:

[0037] Etching the first isolation dielectric layer and the second isolation dielectric layer to expose the gate dielectric layer in the channel region;

[0038] The gate is formed on the exposed surface of the gate dielectric layer, and the gate covers the channel region of the active column.

[0039] The semiconductor structure and the method for preparing the same provided by the present application have at least the following beneficial effects:

[0040] In an embodiment of the present application, an inner hole is formed in the column body of the active column, and an insulating dielectric layer is filled in the inner hole. By providing an insulating dielectric layer, the high electric field area and the low electric field area in the active column can be effectively isolated, and the electron tunneling effect can be reduced, which is beneficial to reducing the leakage current of the semiconductor structure during operation, so that the semiconductor structure has a higher switching ratio and improves the electrical performance of the semiconductor structure. In an embodiment of the present application, a conductive structure is provided at the bottom of the inner hole. The conductive structure can be used as a component of the bit line to achieve continuous extension of the bit line and reduce the risk of bit line disconnection; and the provision of the conductive structure is also beneficial to reduce the contact resistance between the bit line and the active column, so that the bit line and the active column are in good contact, thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present application;

[0043] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the structure shown in the ff' direction;

[0044] Figure 3 When some embodiments of the present application are applied to a transistor structure, an output characteristic curve diagram of the transistor structure;

[0045] Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;

[0046] Figure 5 A schematic flow chart of step S100 in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0047] Figure 6 A schematic diagram of a process for forming a plurality of spaced-apart bit lines in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0048] Figure 7 A schematic diagram of the aa' direction and the cc' direction in the method for preparing a semiconductor structure provided in some embodiments of the present application;

[0049] Figure 8 A schematic cross-sectional view of a structure obtained by sequentially depositing a first silicon oxide layer, a polysilicon layer, a first silicon oxynitride layer, a spin-coated hard mask layer, and a second silicon oxynitride layer on a surface of one side of a substrate in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0050] Fig. 9 A schematic diagram of a cross-sectional structure of a structure obtained after forming a patterned photoresist in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0051] Fig.10 A schematic cross-sectional view of a structure obtained after a mask pattern is transferred to a second silicon oxynitride layer and a spin-coated hard mask layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0052] Fig.11A schematic cross-sectional view of a structure obtained after a second silicon oxide layer is deposited on the sidewalls and top of a retained second silicon oxynitride layer and a spin-coated hard mask layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0053] Fig.12 A schematic cross-sectional view of a structure obtained after removing the second silicon oxide layer, the second silicon oxynitride layer and the spin-coated hard mask layer located on top of the second silicon oxynitride layer and the spin-coated hard mask layer in the method for preparing the semiconductor structure provided in some embodiments of the present application;

[0054] Fig.13 A schematic diagram of a cross-sectional structure of a structure obtained after etching a first silicon oxynitride layer and a polysilicon layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0055] Fig.14 A schematic diagram of a cross-sectional structure of a structure obtained after forming a plurality of inner holes arranged in an array in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0056] Fig.15 A schematic diagram of a cross-sectional structure of a structure obtained after a conductive structure is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0057] Fig.16 A schematic diagram of a cross-sectional structure of a structure obtained after forming an insulating dielectric material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0058] Fig.17 A schematic diagram of a cross-sectional structure of a structure obtained after forming an insulating dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0059] Fig.18 A schematic diagram of a cross-sectional structure during a second patterning process of an initial substrate in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0060] Fig.19 A schematic cross-sectional view of a structure obtained after forming a plurality of active pillars arranged in an array in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0061] Fig. 20 A schematic diagram of a cross-sectional structure of a structure obtained after a gate dielectric layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0062] Fig.21 A schematic diagram of a cross-sectional structure of a structure obtained after a bit line trench is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0063] Fig. 22A schematic cross-sectional view of a structure obtained after forming a connecting portion of a bit line in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0064] Fig.23 A schematic cross-sectional view of a structure obtained after forming a first isolation dielectric material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0065] Fig.24 A schematic cross-sectional view of a structure obtained after forming a first isolation dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0066] Fig.25 for Fig.24 A partial enlarged view of region A in the structure shown;

[0067] Fig.26 A schematic diagram of the cross-sectional structure of region A of a structure obtained after etching the first isolation dielectric layer and the second isolation dielectric layer in the method for preparing a semiconductor structure provided in some embodiments of the present application in the aa' direction;

[0068] Fig. 27 for Fig.26 A schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0069] Fig.28 A schematic diagram of the cross-sectional structure of region A of the structure obtained after forming a gate in the method for preparing a semiconductor structure provided in some embodiments of the present application;

[0070] Fig.29 This is a schematic diagram of the cross-sectional structure of region A of the structure obtained after forming a protective layer in the method for preparing a semiconductor structure provided in some embodiments of the present application.

[0071] Description of reference numerals:

[0072] 1. Substrate; 1', initial substrate; 11. Active pillar; 11a, channel region; 111, pillar; 111a, inner hole; 112, conductive structure; 113, insulating dielectric layer; 113', insulating dielectric material layer; 12A, first silicon oxide layer; 12B, polysilicon layer; 12C, first silicon oxynitride layer; 12D, spin-on hard mask layer; 12E, first silicon oxynitride layer; 12F, patterned photoresist layer; 12G, second silicon oxide layer; 2. Bit line; 21, connecting portion; 22, bit line groove; 3. Gate; 4. Gate dielectric layer; 5. First isolation dielectric layer; 5', first isolation dielectric material layer; 6. Second isolation dielectric layer; 7. Protective layer. DETAILED DESCRIPTION

[0073] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It should be understood that when an element or layer is referred to as being "located on...", "adjacent..." or "connected to" another element or layer, it may be directly located on, adjacent to or connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first and second may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction; the first direction and the second direction are different directions.

[0076] Spatially relative terms such as "below", "above", etc., may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "below" will be oriented as "above" other elements or features. Therefore, the exemplary term "below" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0077] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0079] In order to reduce the area of ​​a single array transistor as much as possible and pursue higher chip area utilization, vertical channel array transistor (VCT) technology has emerged. However, traditional VCTs are prone to leakage current during operation, which seriously affects the electrical performance of VCTs.

[0080] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, the details of which will be described in subsequent embodiments.

[0081] According to some embodiments, the present application provides a semiconductor structure.

[0082] As an example, the semiconductor structure can be used to form a semiconductor device (such as a DRAM), and the DRAM can include a transistor structure and a capacitor structure connected to the transistor structure, the capacitor structure is used to store data, and the transistor structure is used to read data in the capacitor structure or write data into the capacitor structure. It can be understood that the semiconductor structure provided in the embodiment of the present application can be used as a component of the transistor structure in the DRAM, for example, it can be a vertical channel array transistor (VCT), but it is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0083] See also Figure 1 and Figure 2 In some embodiments, the semiconductor structure may include a substrate including a plurality of active pillars 11 arranged in an array.

[0084] Specifically, the active pillar 11 may include a pillar body 111, a conductive structure 112 and an insulating dielectric layer 113. The pillar body 111 has an inner hole; the conductive structure 112 is located at the bottom of the inner hole; and the insulating dielectric layer 113 is located on the conductive structure 112 and fills the inner hole.

[0085] In the semiconductor structure provided in the above embodiment, an inner hole is formed in the column 111 of the active column 11, and an insulating dielectric layer 113 is filled in the inner hole. By providing the insulating dielectric layer 113, the high electric field area and the low electric field area in the active column 11 can be effectively isolated, and the electron tunneling effect can be reduced, which is beneficial to reducing the leakage current of the semiconductor structure during operation, so that the semiconductor structure has a higher switching ratio and improves the electrical performance of the semiconductor structure. In the semiconductor structure provided in the above embodiment, a conductive structure 112 is provided at the bottom of the inner hole. The conductive structure 112 can be used as a component of the bit line to achieve continuous extension of the bit line and reduce the risk of bit line disconnection. In addition, the provision of the conductive structure 112 is also beneficial to reducing the contact resistance between the bit line and the active column 11, so that the bit line is in good contact with the active column 11, thereby improving the electrical performance of the semiconductor structure.

[0086] The semiconductor structure provided in the embodiment of the present application can be used as a component of the transistor structure in DRAM. Figure 3 Understand, in Figure 3 In the figure, L shows the output characteristic curve of the transistor structure when the semiconductor structure provided by the embodiment of the present application is applied to the transistor structure, and L' shows the output characteristic curve of the transistor structure when the traditional semiconductor structure is applied to the transistor structure; V g Represents the gate voltage of the transistor structure, I d Represents the drain current of the transistor structure, I off The on / off ratio represents the ratio of the on-state current of the transistor structure to the off-state current of the transistor structure. Figure 3 As shown, the semiconductor structure provided by the embodiment of the present application is applied, compared with the application of the traditional transistor structure, I off It can be seen that the semiconductor structure provided in the embodiment of the present application can effectively reduce the turn-off current of the transistor structure, thereby achieving a higher switching ratio.

[0087] As an example, Figure 1 and Figure 2 As shown in , the inner hole can be located at the center of the column 111. That is, the symmetry center of the inner hole coincides with the symmetry center of the column 111.

[0088] In some embodiments, the ratio of the size of the inner hole to the pillar 111 in the same direction may be 1 / 3 to 1 / 2. For example, the ratio of the size of the inner hole to the pillar 111 in the same direction may be 1 / 3, 2 / 5 or 1 / 2, etc. The same direction may be, for example, the extension direction of the bit line.

[0089] In the semiconductor structure provided in the above embodiment, the size of the inner hole can be at least 1 / 3 of the size of the pillar 111, so that the size of the insulating dielectric layer 113 filled in the inner hole can also be at least 1 / 3 of the size of the pillar 111, so as to ensure a good isolation effect, thereby effectively reducing the leakage current of the semiconductor structure during operation, so that the semiconductor structure has a higher switching ratio, and further improves the electrical performance of the semiconductor structure. In addition, the size of the inner hole is not greater than 1 / 2 of the size of the pillar 111, which can avoid the storage capacity or reading capacity of the active pillar 11 being adversely affected by the insulating dielectric layer 113 being too large.

[0090] In some embodiments, the semiconductor structure may further include a plurality of bit lines arranged at intervals. The bit lines are located below the active pillars 11 and extend along the first direction. The following describes the embodiments of the present application by taking the first direction as the X direction as an example.

[0091] Please continue reading Figure 1 As an example, the bit line 2 may include conductive structures 112 located in the same column along a first direction (eg, X direction), and a connecting portion 21 connected between adjacent conductive structures 112 in the first direction (eg, X direction).

[0092] In the semiconductor structure provided in the above embodiment, the bit line 2 includes a conductive structure 112 disposed at the bottom of the inner hole of the active pillar 11, and the conductive structure 112 and the connecting portion 21 together constitute the bit line 2, thereby realizing continuous extension of the bit line 2 and reducing the risk of breaking the bit line 2. In addition, the provision of the conductive structure 112 is also conducive to reducing the contact resistance between the bit line 2 and the active pillar 11, so that the bit line 2 and the active pillar 11 are in good contact, thereby improving the electrical performance of the semiconductor structure.

[0093] As an example, the constituent material of the conductive structure 112 can be the same or similar to the constituent material of the connecting portion 21. Using the conductive structure 112 and the connecting portion 21 with the same or similar constituent materials can make the bit line 2 have good structural consistency and stability, and improve the production yield and use reliability of the semiconductor structure.

[0094] It should be noted that, in the embodiment of the present application, the constituent material of the conductive structure 112 is similar to the constituent material of the connecting portion 21, which means that the constituent material of the conductive structure 112 and the constituent material of the connecting portion 21 contain the same elements; or, the chemical properties and / or conductive performance deviations of the constituent material of the conductive structure 112 and the constituent material of the connecting portion 21 are within a small range.

[0095] The present application embodiment does not specifically limit the constituent materials of the conductive structure 112 and the constituent materials of the connecting portion 21. As an example, the constituent materials of the conductive structure 112 and the constituent materials of the connecting portion 21 may include at least one of metal silicide (Salicide) or metal. In some embodiments, the constituent materials of the conductive structure 112 and the constituent materials of the connecting portion 21 may only include metal silicide, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi2), etc.

[0096] Please continue reading Figure 1 In some embodiments, the active pillar 11 may include a channel region 11 a .

[0097] In some embodiments, the semiconductor structure may further include a plurality of gates 3. Figure 1 and Figure 2 As shown, the gate 3 covers the channel regions 11 a of the active pillars 11 located in the same row.

[0098] Please continue reading Figure 1 and Figure 2 In some embodiments, the semiconductor structure may further include a gate dielectric layer 4. The gate dielectric layer 4 at least conformally covers the sidewalls of the channel region 11a.

[0099] It can be understood that in the semiconductor structure provided by the above embodiment, the gate 3 is located on the surface of the gate dielectric layer 4 away from the active pillar 11 .

[0100] In some embodiments, the semiconductor structure may further include a plurality of word lines (WL) arranged at intervals. Each of the word lines extends along the second direction. Each word line sequentially connects the gates 3 in the same row in series.

[0101] Please combine Figure 1 and Figure 2 It is understood that in the embodiment of the present application, the second direction intersects with the first direction. The embodiment of the present application is described below by taking the first direction as the X direction and the second direction as the Y direction as an example.

[0102] As an example, the word line and the gate 3 in the same row may be an integral structure. For example, the gate 3 may be a component of the word line.

[0103] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided by some of the above embodiments.

[0104] See also Figure 4 In some embodiments, the method for preparing the semiconductor structure may include the following steps:

[0105] S100: providing a substrate; forming a plurality of active pillars arranged in an array on a surface of one side of the substrate; the active pillars include a pillar body, and the pillar body is formed with an inner hole.

[0106] S200: forming a conductive structure at the bottom of the inner hole.

[0107] S300: Filling the inner hole with an insulating dielectric layer.

[0108] In the method for preparing a semiconductor structure provided in the above embodiment, an inner hole is formed in the column body of the active column, and an insulating dielectric layer is filled in the inner hole. By forming an insulating dielectric layer, the high electric field area and the low electric field area in the active column can be effectively isolated, and the electron tunneling effect can be reduced, which is beneficial to reducing the leakage current of the semiconductor structure during operation, so that the semiconductor structure has a higher switching ratio and improves the electrical performance of the semiconductor structure. In the method for preparing a semiconductor structure provided in the above embodiment, a conductive structure is formed at the bottom of the inner hole. The conductive structure can be used as a component of the bit line to achieve continuous extension of the bit line and reduce the risk of bit line disconnection; and the provision of the conductive structure is also beneficial to reducing the contact resistance between the bit line and the active column, so that the bit line and the active column are in good contact, thereby improving the electrical performance of the semiconductor structure.

[0109] See also Figure 5 In some embodiments, step S100 may specifically include the following steps:

[0110] S110: providing an initial substrate; performing a first patterning on the initial substrate to form a plurality of inner holes arranged in an array on a surface of one side of the initial substrate.

[0111] S120: performing a second patterning on the initial substrate to form a plurality of active pillars arranged in an array in the initial substrate, and making the inner holes correspond to the active pillars one by one; the retained initial substrate is used as the substrate.

[0112] In some embodiments, the method for preparing the semiconductor structure may further include the following steps:

[0113] A plurality of spaced-apart bit lines are formed below the active pillars; the bit lines extend along a first direction to connect with the conductive structures in the same row.

[0114] See also Figure 6In some embodiments, the following steps may be used to form a plurality of spaced-apart bit lines, including:

[0115] S410: etching the substrate to form a plurality of bit line trenches arranged at intervals and extending along a first direction below the active pillars; the bit line trenches expose the conductive structure.

[0116] S420: forming a connecting portion of a bit line in the bit line trench; each conductive structure located in the same column along the first direction and a connecting portion connected between adjacent conductive structures in the first direction together constitute a bit line.

[0117] It should be understood that although Figures 4 to 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 4 to 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0118] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 7 to 29 Understand some embodiments of the present application.

[0119] In step S100, refer to Figures 8 to 19 , providing a substrate 1. A plurality of active pillars 11 arranged in an array are formed on one surface of the substrate 1; the active pillars 11 include a pillar body 111, and the pillar body 111 is formed with an inner hole 111a.

[0120] The embodiments of the present application do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on an insulator.

[0121] In some embodiments, the aforementioned step S100 may be specifically expressed as the following steps S110 to S120.

[0122] In step S110, refer to Figures 8 to 14 , providing an initial substrate 1'; performing a first patterning on the initial substrate 1' to form a plurality of inner holes 111a arranged in an array on a surface of one side of the initial substrate 1'.

[0123] In step S120, refer to Figures 15 to 19 , the initial substrate 1 ′ is patterned for the second time to form a plurality of active pillars 11 arranged in an array in the initial substrate 1 ′, and the inner holes 111 a correspond one by one to the active pillars 11 ; the retained initial substrate 1 ′ is used as substrate 1 .

[0124] The embodiment of the present application does not specifically limit the manner in which the initial substrate 1' is patterned for the first time in step S110 to form a plurality of inner holes 111a. As an example, a self-aligned double patterning (SADP) process may be used to pattern the initial substrate 1' for the first time to form a plurality of inner holes 111a. The specific steps may include but are not limited to:

[0125] like Figure 8 As shown, a first silicon oxide (SiO2) layer 12A, a polysilicon (Poly) layer 12B, a first silicon oxynitride (SiON) layer 12C, a spin-on hard mask (SOH) layer 12D, and a second silicon oxynitride layer 12E are sequentially deposited on a surface of one side of the substrate 1 by a deposition process. It can be understood that in the embodiment of the present application, the spin-on hard mask layer 12D can be formed by a spin coating process; for example, the spin-on hard mask layer 12D can be a hydrocarbon (C x H y ) system, which may include a silicon hard mask material, a carbon hard mask material, an organic hard mask material, and the like.

[0126] like Fig. 9 As shown, a photoresist (PR) layer is formed on the surface of the structure obtained in the above steps, and the photoresist layer is exposed and developed to form a mask pattern in the photoresist layer, thereby forming a patterned photoresist layer 12F.

[0127] like Fig.10 As shown, the second silicon oxynitride layer 12E and the spin-on hard mask layer 12D are etched based on the patterned photoresist layer 12F to transfer the mask pattern into the second silicon oxynitride layer 12E and the spin-on hard mask layer 12D, and remove the patterned photoresist layer 12F.

[0128] like Fig.11As shown, a second silicon oxide layer 12G is deposited on the sidewalls and top of the remaining second silicon oxynitride layer 12E and the spin-on hard mask layer 12D.

[0129] like Fig.12 As shown, the structure obtained in the above steps is etched back to remove the second silicon oxide layer 12G, the second silicon oxide layer 12E and the spin-coated hard mask layer 12D located on the top of the second silicon oxynitride layer 12E and the spin-coated hard mask layer 12D, and retain the second silicon oxide layer 12G located on the sidewalls of the second silicon oxynitride layer 12E and the spin-coated hard mask layer 12D. For example, this step can be etched back by anisotropic etching, which can selectively etch materials in a preset crystal direction or crystal plane direction, leaving only a few or almost no etching marks in other directions. In this step, the use of anisotropic etching for etching back can make the morphology of the obtained structure more accurate and controllable.

[0130] like Fig.13 As shown, the first silicon oxynitride layer 12C and the polysilicon layer 12B are etched using the second silicon oxide layer 12G retained in the previous step as a mask.

[0131] like Fig.14 As shown, the first silicon oxynitride layer 12C and the polysilicon layer 12B retained in the previous step are used as masks to continue etching the first silicon oxide layer 12A and the substrate 1, and the first silicon oxide layer 12A is removed, thereby forming a plurality of inner holes 111a arranged in an array on one side surface of the initial substrate 1'.

[0132] As an example, step S120 may be performed after step S200 and step S300, and its details will be described in more detail later.

[0133] In step S200, refer to Fig.15 , a conductive structure 112 is formed at the bottom of the inner hole 111 a.

[0134] In step S300, refer to Figure 16 to Figure 17 , an insulating dielectric layer 113 is filled in the inner hole 111a.

[0135] The present embodiment does not specifically limit the constituent material of the insulating dielectric layer 113. As an example, the constituent material of the insulating dielectric layer 113 may include but is not limited to insulating dielectric materials; insulating dielectric materials such as silicon oxide, silicon nitride (SiN), hafnium oxide (HfO2), etc.

[0136] As an example, the following steps may be used to fill the inner hole 111a with the insulating dielectric layer 113, including:

[0137] like Fig.16 As shown, a deposition process is used to form an insulating dielectric material layer 113' filling the inner hole 111a and covering the surface of the initial substrate 1'.

[0138] like Fig.17 As shown, the insulating dielectric material layer 113 ′ located above the top surface of the initial substrate 1 ′ is removed, and the insulating dielectric material layer 113 ′ filled in the inner hole 111 a is retained as the insulating dielectric layer 113 .

[0139] As an example, after forming the insulating dielectric layer 113 in step S300, step S120 may be performed. The specific steps of performing the second patterning on the initial substrate 1' in step S120 can be found in the first patterning on the initial substrate 1', which will not be described again.

[0140] See also Figure 18 to Figure 19 , the initial substrate 1 ′ is patterned for the second time to form a plurality of active pillars 11 arranged in an array in the initial substrate 1 ′, and the inner holes 111 a correspond one by one to the active pillars 11 ; the retained initial substrate 1 ′ is used as substrate 1 .

[0141] The embodiment of the present application does not specifically limit the manner in which the plurality of active pillars 11 arranged in an array are formed in the initial substrate 1' in the above steps. As an example, the specific steps of forming the plurality of active pillars 11 arranged in an array in the initial substrate 1' may include but are not limited to:

[0142] like Fig.18 As shown, a first silicon oxide layer 12A, a polysilicon layer 12B, a first silicon oxynitride layer 12C, a spin-on hard mask layer 12D, and a second silicon oxynitride layer 12E are sequentially deposited on one side of the initial substrate 1' by a deposition process. It can be understood that in the embodiment of the present application, the spin-on hard mask layer 12D can be formed by a spin coating process; for example, the spin-on hard mask layer 12D can be a hydrocarbon (C x H y ) system, which may include a silicon hard mask material, a carbon hard mask material, an organic hard mask material, and the like.

[0143] like Fig.19 As shown, the initial substrate 1' is patterned for the second time using a self-aligned double imaging process to form a plurality of active pillars 11. The specific process of the second patterning can refer to the aforementioned Figures 9 to 14 to understand the relevant description.

[0144] In some embodiments, see Fig. 20 After forming the active pillar 11 and the insulating dielectric layer 113, the method for preparing the semiconductor structure may further include the following steps:

[0145] A gate dielectric layer 4 is formed, and the gate dielectric layer 4 conformally covers at least the sidewalls of the channel region 11 a of the active pillar 11 .

[0146] In some embodiments, see Figure 21 to Figure 22 , the method for preparing the semiconductor structure may further include the following steps:

[0147] A plurality of bit lines 2 arranged at intervals are formed below the active pillars 11 ; the bit lines 2 extend along a first direction (eg, X direction) to connect to the conductive structures 112 located in the same row.

[0148] In some embodiments, the following steps S410 to S420 may be specifically used to form a plurality of bit lines 2 arranged at intervals below the active pillars 11:

[0149] In step S410, refer to Fig.21 , the substrate 1 is etched to form a plurality of bit line trenches 22 arranged at intervals and extending along a first direction (eg, X direction) below the active pillars 11 ; the bit line trenches 22 expose the conductive structures 112 .

[0150] In step S420, refer to Fig. 22 , forming a connection portion 21 of the bit line 2 in the bit line trench 22; each conductive structure 112 located in the same column along the first direction (eg, X direction) and the connection portion 21 connected between adjacent conductive structures 112 in the first direction (eg, X direction) together constitute the bit line 2.

[0151] As an example, after forming a plurality of bit lines 2 arranged at intervals below the active pillars 11 , the method for preparing the semiconductor structure may further include the step of forming a plurality of gates.

[0152] See also Figure 23 to Figure 24 In some embodiments, after forming a plurality of spaced-apart bit lines 2 below the active pillars 11 and before forming a plurality of gates, the method for preparing the semiconductor structure may further include the following step: filling a first isolation dielectric layer 5 in the intervals between adjacent active pillars 11 in a first direction (e.g., the X direction).

[0153] The present embodiment of the application does not specifically limit the constituent material of the first isolation dielectric layer 5. As an example, the constituent material of the first isolation dielectric layer 5 may include but is not limited to silicon nitride.

[0154] As an example, the first isolation dielectric layer 5 may be filled by the following steps, for example:

[0155] like Fig.23As shown, a first isolation dielectric material layer 5' is first formed, and the first isolation dielectric material layer 5' fills the interval between adjacent active pillars 11 in the first direction (eg, the X direction) and covers the top surface of the structure obtained in the previous step. Fig.24 As shown, the first isolation dielectric material layer 5 ′ located on the top surface of the structure obtained in the previous step is removed, and the first isolation dielectric material layer 5 ′ filled in the interval between adjacent active pillars 11 in the first direction (eg, X direction) is retained as the first isolation dielectric layer 5 .

[0156] It can be understood that in the above steps, the top surface of the structure obtained in the previous step is, for example, that the gate dielectric layer 4 is parallel to the surface of the substrate 1 .

[0157] In order to more clearly illustrate some possible embodiments of the present application, Fig.25 Shows Fig.24 A partial enlarged view of area A in the structure shown.

[0158] In some embodiments, before forming a plurality of gates, the method for preparing the semiconductor structure may further include the following step: filling a second isolation dielectric layer 6 in the interval between adjacent active pillars 11 in the second direction (eg, the Y direction).

[0159] The present embodiment of the application does not specifically limit the constituent material of the second isolation dielectric layer. As an example, the constituent material of the second isolation dielectric layer can be the same as or similar to the constituent material of the gate dielectric layer 4.

[0160] As an example, multiple gates may be formed by the following steps, for example:

[0161] like Fig.26 and Fig. 27 As shown, the first isolation dielectric layer 5 and the second isolation dielectric layer 6 are etched to expose the gate dielectric layer 4 in the channel region 11 a.

[0162] like Fig.28 As shown, a gate 3 is formed on the exposed surface of the gate dielectric layer 4 , and the gate 3 covers the channel region 11 a of the active pillar 11 .

[0163] In some embodiments, the method for preparing the semiconductor structure may further include the following steps: forming a plurality of word lines arranged at intervals. Each of the word lines extends along a second direction (eg, direction Y). Each word line sequentially connects gates 3 in the same row.

[0164] See also Fig.29 In some embodiments, after forming a plurality of gates 3, the method for preparing the semiconductor structure may further include the following step: forming a protective layer 7 on the top surface of the obtained structure.

[0165] In the method for preparing the semiconductor structure provided in the above embodiment, the protective layer 7 can be used to protect the underlying structure from the influence of the external environment, provide a certain mechanical strength and corrosion resistance, and prevent external moisture, oxidants and other harmful substances from corroding and damaging the underlying structure, thereby improving the production yield of the preparation method and the reliability of the obtained semiconductor structure.

[0166] It should be noted that the preparation methods of the semiconductor structures provided in the embodiments of the present application can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.

[0167] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that The invention comprises a substrate; the substrate comprises a plurality of active pillars arranged in an array; The active pillar comprises: A column having an inner hole; a conductive structure located at the bottom of the inner hole; The insulating dielectric layer is located on the conductive structure and fills the inner hole.

2. The semiconductor structure according to claim 1, wherein: The inner hole is located at the center of the column, and the ratio of the size of the inner hole to that of the column in the same direction is in a range of 1 / 3 to 1 / 2.

3. The semiconductor structure according to claim 1 or 2, characterized in that: Also includes: a plurality of bit lines arranged at intervals along the second direction; The bit line is located below the active pillar and extends along a first direction, wherein the first direction intersects the second direction; The bit line includes: the conductive structures located in the same column along the first direction, and a connecting portion connecting adjacent conductive structures in the first direction.

4. The semiconductor structure according to claim 3, wherein: The conductive structure is made of the same or similar material as the connecting portion.

5. The semiconductor structure according to claim 1 or 2, characterized in that: The active pillar includes a channel region; The semiconductor structure further includes a plurality of gates; the gates correspond to the active pillars one by one and cover the channel regions corresponding to the active pillars.

6. The semiconductor structure according to claim 5, wherein: Also includes: a gate dielectric layer; The gate dielectric layer at least conformally covers the sidewalls of the channel region; The gate is located on a surface of the gate dielectric layer away from the active pillar.

7. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided; a plurality of active pillars arranged in an array are formed on one surface of the substrate; the active pillars include a pillar body, and the pillar body is formed with an inner hole; forming a conductive structure at the bottom of the inner hole; An insulating dielectric layer is filled in the inner hole.

8. The method for preparing a semiconductor structure according to claim 7, wherein: The providing of the substrate comprises: Providing an initial substrate; performing a first patterning on the initial substrate to form a plurality of inner holes arranged in an array on one side surface of the initial substrate; The initial substrate is patterned for the second time to form a plurality of active pillars arranged in an array in the initial substrate, and the inner holes correspond one-to-one to the active pillars; the retained initial substrate is used as the substrate.

9. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that: Also includes: forming a plurality of spaced-apart bit lines below the active pillars; The bit lines extend along a first direction to connect with the conductive structures in the same column.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The step of forming a plurality of spaced-apart bit lines below the active pillars includes: Etching the substrate to form a plurality of bit line trenches arranged at intervals below the active pillars and extending along the first direction; the bit line trenches expose the conductive structure; A connecting portion of the bit line is formed in the bit line trench; each of the conductive structures located in the same column along the first direction and the connecting portion connecting the adjacent conductive structures in the first direction together constitute the bit line.

11. The method for preparing a semiconductor structure according to claim 9, wherein: After the inner hole is filled with an insulating dielectric layer, the method for preparing the semiconductor structure further comprises: forming a gate dielectric layer; wherein the gate dielectric layer conformally covers at least the sidewalls of the channel region of the active pillar; A gate is formed; the gate covers the channel region of the active pillar.

12. The method for preparing a semiconductor structure according to claim 11, wherein: Also includes: Filling a first isolation dielectric layer in a space between adjacent active pillars in the first direction, and filling a second isolation dielectric layer in a space between adjacent active pillars in the second direction; The forming of the gate includes: Etching the first isolation dielectric layer and the second isolation dielectric layer to expose the gate dielectric layer in the channel region; The gate is formed on the exposed surface of the gate dielectric layer, and the gate covers the channel region of the active pillar.

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