3D semiconductor memory device

Abstract

A three-dimensional (3D) semiconductor memory device is provided. The device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including memory cells arranged in a vertical direction; and a connection region including end portions of word lines connected to the memory cells, where the end portions form a stepped configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region in the vertical direction. The peripheral circuit region includes a first main pass transistor electrically connected to a first word line of the word lines, and a first dummy pass transistor electrically separated from the word lines. The first main transfer transistor and the first dummy transfer transistor are arranged in a first direction perpendicular to the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0094620 filed on July 20, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to three-dimensional semiconductor memory devices. Background Art

[0004] To meet the demands for superior performance and economy, there is a growing need to increase the integration density of semiconductor devices. For two-dimensional or planar semiconductor devices, the integration density is primarily influenced by the area occupied by one memory cell and is therefore highly dependent on the state of the micropatterning technology. However, increasing the fineness of multiple patterns requires specialized equipment, which makes the gains in integration density of 2D semiconductor devices incremental but somewhat limited. Therefore, there is a need to characterize three-dimensional semiconductor memory devices with memory cells arranged in a 3D configuration. Summary of the invention

[0005] One or more example embodiments provide a semiconductor memory device having improved reliability.

[0006] According to one aspect of the embodiment, a 3D semiconductor memory device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including a plurality of memory cells arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells, wherein the ends form a step configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region in a vertical direction. The peripheral circuit region includes a first main transfer transistor electrically connected to a first word line of a plurality of word lines, and a first dummy transfer transistor electrically separated from the plurality of word lines. The first main transfer transistor and the first dummy transfer transistor are arranged along a first direction perpendicular to the vertical direction.

[0007] According to one aspect of the embodiment, a 3D semiconductor memory device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including a plurality of memory cells arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells. The peripheral circuit includes a peripheral circuit region overlapping the connection region in a vertical direction. The peripheral circuit region includes a plurality of main transfer transistors electrically connected to the plurality of word lines, and a plurality of dummy transfer transistors electrically separated from the plurality of word lines. The plurality of main transfer transistors are arranged along a first direction perpendicular to the vertical direction.

[0008] According to one aspect of the embodiment, a 3D semiconductor memory device includes: a memory cell region; and a peripheral circuit region configured to control the memory cell region. The memory cell region includes a plurality of blocks. Each of the plurality of blocks includes a plurality of cell array regions, the plurality of cell array regions including: a plurality of memory cells arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells. The peripheral circuit region includes a peripheral circuit region overlapping the connection regions of the plurality of blocks, respectively. Each of the peripheral circuit regions includes a plurality of main transfer transistors electrically connected to the plurality of word lines, and a plurality of dummy transfer transistors electrically separated from the plurality of word lines. The plurality of main transfer transistors are arranged along a first direction perpendicular to the vertical direction.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of example embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages will become more apparent from the following description of example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1A is a block diagram illustrating a memory device including a semiconductor memory device according to some example embodiments.

[0012] Figure 1B is a block diagram illustrating a flash memory according to some example embodiments.

[0013] Figure 1C is a circuit diagram illustrating a memory block of a memory cell array according to some example embodiments.

[0014] Figure 1D is a circuit diagram illustrating a cell string selected by a first string selection line SSL1 according to some example embodiments.

[0015] Figure 2A is a conceptual diagram of a semiconductor memory device according to some example embodiments.

[0016] Figure 2B is a diagram of a memory cell region and a peripheral circuit region according to some example embodiments.

[0017] Figure 3 is a plan view of a memory cell region according to some example embodiments.

[0018] Figure 4 is a diagram of connection areas included in a block according to some example embodiments.

[0019] Figure 5 is a plan view of a peripheral circuit region according to some example embodiments.

[0020] Fig. 6A and Figure 6B is a diagram of a second peripheral circuit region included in a block according to some example embodiments.

[0021] Figure 6C is a cross-sectional view of a second peripheral circuit region according to some example embodiments.

[0022] Fig.6D is a cross-sectional view of a second peripheral circuit region according to some example embodiments.

[0023] Figure 7 is a diagram of a semiconductor memory device according to some example embodiments.

[0024] Figure 8 is a cross-sectional view of a second peripheral circuit region according to some example embodiments.

[0025] Fig. 9 is a diagram of a second peripheral circuit region corresponding to one block according to some example embodiments.

[0026] Fig.10 is a diagram of a second peripheral circuit region corresponding to one block according to some example embodiments.

[0027] Fig.11 is a diagram of a second peripheral circuit region corresponding to one block according to some example embodiments.

[0028] Fig.12 Connection regions included in a plurality of blocks according to some example embodiments are shown.

[0029] Fig.13A and Fig. 13B is a diagram illustrating a second peripheral circuit region corresponding to a plurality of blocks according to some example embodiments. DETAILED DESCRIPTION

[0030] Hereinafter, the example embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and their repeated descriptions are omitted. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer, directly connected to or coupled to the other element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described here are example embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. Each example embodiment provided in the following description does not exclude the association of one or more features of another example or another example embodiment that is also provided or not provided but consistent with the present disclosure. It should also be understood that even if a specific step or operation of a manufacturing device or structure is described later than another step or operation, the step or operation can also be performed later than another step or operation, unless another step or operation is described as being performed after the step or operation.

[0031] Figure 1A is a block diagram showing a memory device including a semiconductor memory device.

[0032] Reference Figure 1A , the storage device 1000 may be a flash memory device based on the flash memory 1100. For example, the storage device 1000 may be a solid state drive (SSD), a universal flash memory (UFS), or a memory card.

[0033] The storage device 1000 includes a flash memory 1100 and a memory controller 1200. The flash memory 1100 and the memory controller 1200 may be connected through a data input / output line IO, a control line CTRL, and a power line PWR. The storage device 1000 may store data in the flash memory 1100 under the control of the memory controller 1200.

[0034] The flash memory 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may have a vertical 3D structure. Each memory block may include a plurality of memory cells. In an example embodiment, multi-bit data may be stored in each memory cell.

[0035] In terms of design layout structure, the memory cell array 1110 can be located next to or above the peripheral circuit 1115. The structure in which the memory cell array 1110 is located above the peripheral circuit 1115 is called a cell-on-periphery (COP) structure. The memory cell array 1110 can be manufactured as a chip separated from the peripheral circuit 1115. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuit 1115 can be connected to each other by a bonding method. This structure is called a C2C (chip-to-chip) structure.

[0036] The peripheral circuit 1115 may include an analog circuit or a digital circuit for storing or reading data in the memory cell array 1110. The peripheral circuit 1115 may receive external power (PWR) from the memory controller 1200 and generate various levels of internal power (eg, Vcc).

[0037] The peripheral circuit 1115 may receive a command, an address, and data from the memory controller 1200 through an input / output line IO. The peripheral circuit 1115 may store data in the memory cell array 1110 according to the control of the control signal CTRL. In addition, the peripheral circuit 1115 may read the data stored in the memory cell array 1110 and provide the data to the memory controller 1200.

[0038] Figure 1B According to some example embodiments, Figure 1A A block diagram of a flash memory such as the flash memory shown.

[0039] Reference Figure 1B The flash memory 1100 includes a memory cell array 1110 , an address decoder 1120 , a page buffer circuit 1130 , a data input / output circuit 1140 , a word line voltage generator 1150 , and a control logic 1160 .

[0040] The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may be composed of a plurality of pages. Each page may include a plurality of memory cells. Multi-bit data may be stored in each memory cell. Each memory block is an erase unit, and each page may be a read or write unit.

[0041] The memory cell array 1110 may be formed in a direction perpendicular to the substrate. Gate electrode layers and insulating layers may be alternately deposited on the substrate. Each memory block (eg, BLK1) may be connected to a string selection line SSL, a plurality of word lines WL1 to WLm, and a ground selection line GSL.

[0042] The address decoder 1120 may be connected to the memory cell array 1110 through the selection lines SSL and GSL and the word lines WL1 to WLm. The address decoder 1120 may select a word line in a program operation or a read operation. The address decoder 1120 may receive a word line voltage VWL from a word line voltage generator 1150 and may provide a program voltage or a read voltage to the selected word line.

[0043] The page buffer circuit 1130 may be connected to the memory cell array 1110 through the bit lines BL1 to BLz. The page buffer circuit 1130 may temporarily store data to be programmed into the memory cell array 1110 and / or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to each bit line BL. Each page buffer may include a plurality of latches for the purpose of storing and / or reading multi-bit data.

[0044] The data input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through data lines, and may be externally connected to the memory controller 1200 (see FIG. 10 ) through input / output lines IO1 to IOn. Figure 1A ) connection. During a program operation, the data input / output circuit 1140 may receive program data from the memory controller 1200. During a read operation, the data input / output circuit 1140 may provide the memory controller 1200 with data read from the memory cell array 1110.

[0045] The word line voltage generator 1150 may be supplied with internal power from the control logic 1160 and may generate a word line voltage VWL for reading or writing data. The word line voltage VWL may be provided to a selected word line sWL or an unselected word line uWL through the address decoder 1120 .

[0046] The word line voltage generator 1150 may include a program voltage generator 1151 and a pass voltage generator 1152. The program voltage generator 1151 may generate a program voltage Vpgm provided to a selected word line sWL during a program operation. The pass voltage generator 1152 may generate a pass voltage Vpass provided to a selected word line sWL and an unselected word line uWL.

[0047] The word line voltage generator 1150 may include a read voltage generator 1153 and a read pass voltage generator 1154. The read voltage generator 1153 may generate a selected read voltage Vrd provided to a selected word line sWL during a read operation. The read pass voltage generator 1154 may generate a read pass voltage Vrdps provided to an unselected word line uWL. The read pass voltage Vrdps may be a voltage sufficient to turn on a memory cell connected to an unselected word line uWL during a read operation.

[0048] The control logic 1160 may control the programming, reading, and erasing operations of the flash memory device 1100 by using a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200. The address ADDR may include a block address (or a block selection address) for indicating and may be used to select a memory block, and a row address and a column address for indicating and may be used to select a memory cell of the selected memory block.

[0049] Figure 1C is a diagram showing an example embodiment according to some example embodiments Figure 1B The circuit diagram of the memory block BLK1 of the memory cell array shown in FIG.

[0050] 1C, in a memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. However, the number of cell strings and the number of memory cells included in each cell string may be determined as desired.

[0051] The string selection transistor SST may be connected to the string selection lines SSL1 to SSL8. The ground selection transistor GST may be connected to the ground selection lines GSL1 to GSL8. The string selection transistor SST may be connected to the bit lines BL1 to BLz, and the ground selection transistor GST may be connected to the common source line CSL.

[0052] The first to eighth word lines WL1 to WL8 may be connected to a plurality of memory cells MC1 to MC8 in a row direction. The first to z-th bit lines BL1 to BLz may be connected to a plurality of memory cells MC1 to MC8 in a column direction. The first to z-th page buffers PB1 to PBz may be connected to the first to z-th bit lines BL1 to BLz.

[0053] The first word line WL1 may be placed on the first to eighth ground selection lines GSL1 to GSL8. The first memory cell MC1 placed at the same height from the substrate may be connected to the first word line WL1. Similarly, the second to eighth memory cells MC2 to MC8 placed at the same height from the substrate may be connected to the second to eighth word lines WL2 to WL8, respectively.

[0054] Figure 1D is a circuit diagram of a cell string selected by a first string selection line SSL1 from among cell strings of a memory block BLK1 according to some example embodiments. 1-1th cell string STR11 to 1-zth cell string STR1z may be selected by the first string selection line SSL1. 1-1th cell string STR11 to 1-zth cell string STR1z may be connected to first to zth bit lines BL1 to BLz, respectively. First to zth page buffers PB1 to PBz may be connected to first to zth bit lines BL1 to BLz, respectively.

[0055] The 1-1 cell string STR11 is connected to the first bit line BL1 and the common source line CSL. A string selection transistor SST selected by the first string selection line SSL1, first to eighth memory cells MC1 to MC8 connected to the first to eighth word lines WL1 to WL8, and a ground selection transistor GST selected by the first ground selection line GSL1 may be included in the 1-1 cell string STR11. Similarly, the 1-2 cell string STR12 may be connected to the second bit line BL2 and the common source line CSL, and the 1-z cell string STR1z may be connected to the zth bit line BLz and the common source line CSL.

[0056] The first to fourth word lines WL1 to WL4 and the sixth to eighth word lines WL6 to WL8 may be unselected word lines uWL. The fifth word line WL5 may be a selected word line sWL. The first to fourth memory cells MC1 to MC4 and the sixth to eighth memory cells MC6 to MC8 may be unselected memory cells uMC. The fifth memory cell MC5 may be a selected memory cell sMC.

[0057] Memory cells selected by one string selection line and connected to one word line in one memory block may constitute one page. For example, the fifth memory cell MC5 selected by the first string selection line SSL1 and connected to the fifth word line WL5 in the memory block BLK1 may constitute one page. In some example embodiments, eight pages may be implemented by using memory cells connected to the fifth word line WL5 connected to one bit line. Among the eight pages, the page connected to the first string selection line SSL1 may be a selected page. However, example embodiments are not limited thereto, and more or fewer pages may be used.

[0058] Figure 2A is a conceptual diagram of a semiconductor memory device according to some example embodiments. Figure 2B yes Figure 2A A diagram showing the memory cell area and the peripheral circuit area separated. Figure 3 is a plan view of a memory cell region according to example embodiments. Figure 4 is a graph of the connected regions included in a block. Figure 5 is a plan view of a peripheral circuit region according to an example embodiment. Fig. 6A and Figure 6B is a diagram showing a second peripheral circuit region included in one block. Figure 6C is along Figure 6B A cross-sectional view taken along line AA′. Fig.6D is along Figure 6B For the sake of simplicity of explanation, the cross-sectional view taken along the line BB′ may not be described with reference to Figures 1A to 1D Describes essentially the same content.

[0059] Reference Figure 2A , Figure 2B , Figure 3 and Figure 5 , the semiconductor memory device 10 may include a memory cell region 100 and a peripheral circuit region 200. In example embodiments, the memory cell region 100 and the peripheral circuit region 200 may have a plate form parallel to a plane extending in a first direction D1 and a second direction D2. The memory cell region 100 may be on the peripheral circuit region 200 along a third direction D3.

[0060] The memory cell region 100 may include a plurality of memory blocks arranged along a second direction D2. The memory cell region 100 may include a cell array region 101 and a connection region 102. The cell array region 101 and the connection region 102 may be arranged along a first direction D1. For example, as shown in the figure, a pair of connection regions 102 may be spaced apart from each other along the first direction D1, and the cell array region 101 is between the pair of connection regions 102. In another example, one connection region 102 may be disposed between a pair of cell array regions 101 spaced apart along the first direction D1, or a plurality of connection regions 102 may be alternately arranged with a plurality of cell array regions 101. The arrangement of the connection region 102 and the cell array region 101 is not limited.

[0061] The cell array region 101 may include a plurality of cell strings extending along a third direction D3. The plurality of cell strings may be connected to the reference Figures 1A to 1DThe cell strings STR11 to STR8z described are substantially the same. Each of the multiple cell strings may include a string selection transistor, multiple memory cells, and a ground selection transistor. The multiple memory cells may be controlled by multiple stacked gate electrodes along a third direction D3. The multiple gate electrodes may be electrically connected to multiple word lines.

[0062] A plurality of word lines may extend along a first direction D1. Ends of the plurality of word lines may be located in the connection region 102. Ends of the plurality of word lines may have a stepped configuration, arranged within the connection region 102 along the first direction D1. Ends of the word lines protruding along the first direction D1 from the word lines forming the adjacent steps may be referred to as pads. The stepped structure formed by the plurality of word lines may become closer to the peripheral circuit region 200 or may be away from the peripheral circuit region 200 as it extends along the first direction D1. Exemplary configurations of the stepped structure may be discussed later.

[0063] like Figure 4 As shown, the connection area 102 within a storage block may include a plurality of pad areas PR arranged along a first direction D1. In a view along a third direction D3, at least one pad may be provided in each of the plurality of pad areas PR. For example, the width of the pad area PR along the first direction D1 (hereinafter referred to as the first width W1) may be substantially the same as the width of the pad along the first direction D1. In some examples, at least some of the plurality of first widths W1 in the plurality of pad areas PR may be the same. In some examples, at least some of the plurality of first widths W1 in the plurality of pad areas PR may be different from each other. In a view along a third direction D3, a plurality of pads within a pad area PR may be arranged along a second direction D2. The number of pads located in a pad area PR may be determined as required.

[0064] A plurality of pad regions PR may be classified into a plurality of pad groups PG. Each of the plurality of pad groups PG may include pad regions PR sequentially arranged along a first direction D1. Contact plugs electrically connected to pads may be provided in a plurality of sequentially arranged pad regions PR. For example, the number of contact plugs may be equal to the number of pads. A plurality of contact plugs may be positioned along a first direction D1 and a second direction D2 and overlap with pads along a third direction D3. In some examples, at least some of the contact plugs located in each pad group PG may be arranged at substantially uniform intervals along the first direction D1. In some examples, at least some of the contact plugs located in each pad group PG may be arranged at different intervals along the first direction D1. In one example embodiment, adjacent pad groups PG may be spaced apart from each other along the first direction D1. For example, according to processing or design requirements, an area where no pad is provided may be provided between adjacent pad groups PG. In another example embodiment, adjacent pad groups PG may contact along the first direction D1.

[0065] In order to locate the pad area PR, a length along the first direction D1 (hereinafter referred to as the first length L1) may be required. The first length L1 may be the sum of the distance between a pair of pad areas PR arranged at both ends along the first direction D1 and the sum of the first width W1 of the pair of pad areas PR. For ease of illustration, six pad groups PG are shown. The six pad groups PG arranged along the first direction D1 may be referred to as the first pad group PG, the second pad group PG, the third pad group PG, the fourth pad group PG, the fifth pad group PG, and the sixth pad group PG. Although each of the six pad groups PG is shown as including four pad areas PR along the first direction D1, this is only an example. In other examples, the pad group PG may include fewer or more pad areas PR.

[0066] The peripheral circuit region 200 may include a first peripheral circuit region 201 and a second peripheral circuit region 202. The first peripheral circuit region 201 may overlap the cell array region 101 along a third direction D3. The first peripheral circuit region 201 may include circuits for controlling various operations of the semiconductor memory device 10. In one block, the second peripheral circuit region 202 may overlap the connection region 102 along the third direction D3.

[0067] Reference Fig. 6A and Figure 6B , the second peripheral circuit region 202 may include a main region MR and a dummy region DR. At least one main transfer transistor MPT may be located in each main region MR. A plurality of main transfer transistors MPT in a main region MR may be arranged along the second direction D2. Although two main transfer transistors MPT are shown to be arranged in each main region MR along the second direction D2, this is only illustrative. In other examples, one or more than three main transfer transistors MPT may be located in the main region MR. The width of the main region MR (hereinafter referred to as the second width W2) may be substantially equal to the pitch of the main transfer transistor MPT. In one example, at least some of the second widths W2 of the plurality of main regions MR may be equal to each other. In another example, at least some of the second widths W2 of the plurality of main regions MR may be different from each other. In a view along the third direction D3, the central axis of the main region MR extending along the second direction D2 may overlap with the central axis of the main transfer transistor MPT placed in the main region MR extending along the second direction D2. The main transfer transistor MPT may be configured to send a pass voltage to a plurality of word lines. For example, each main transfer transistor MPT may be electrically connected to a pad. The main transfer transistor MPT may have a first polarity. For example, the main transfer transistor MPT may be an N-channel metal oxide semiconductor (NMOS) transistor formed on a p-type active pattern.

[0068] like Figure 6CAs shown, the main transfer transistor MPT may include a first source / drain region SD1, a second source / drain region SD2, a gate electrode GE, and a gate insulating layer GL. A device isolation pattern 204d may be disposed around the main transfer transistor MPT. The device isolation pattern 204d may be configured to electrically isolate the main transfer transistors MPT from each other, or to prevent unintended electrical connection between the main transfer transistor MPT and other elements. The main transfer transistor MPT and the device isolation pattern 204d may be formed on the well region 204c.

[0069] The well region 204c may have a first conductivity type. For example, the first conductivity type may be a p-type. For example, the well region 204c may be a silicon Si region including a Group 3 element (e.g., boron B, aluminum Al, gallium Ga, indium In, or a Group 2 element) as a first impurity. The p-type activation pattern may correspond to the well region 204c. The first source / drain region SD1 and the second source / drain region SD2 may have a second conductivity type. For example, the second conductivity type may be an n-type. A plurality of regions may be formed in the well region 204c by injecting a Group 5 element (e.g., phosphorus P, arsenic As, antimony Sb, a Group 6 or Group 7 element) as a second impurity. The well region 204c may be formed on top of the deep well region 204b.

[0070] The deep well region 204b may also have a second conductivity type. For example, the conductivity type of the deep well region 204b may be an n-type. In one example, the deep well region 204b may be a silicon Si region including a second impurity. The deep well region 204b may be disposed above the substrate region 204a.

[0071] The substrate region 204a may have a first conductivity type. For example, the conductivity type of the substrate region 204a may be a p-type. In one example, the substrate region 204a may be a region of the silicon substrate remaining after forming both the deep well 204b and the well region 204c.

[0072] The first source / drain region SD1 and the second source / drain region SD2 may be respectively connected to a first contact CT1 for applying a drain signal and a second contact CT2 for applying a pass voltage to a corresponding word line.

[0073] The number of main regions MR may be determined so that the number of pads is the same as the number of main transfer transistors MPT. In order to set a plurality of main transfer transistors MPT, a total length referred to as a second length L2 may be required, the second length L2 being equal to the sum of the second widths W2 of the main regions MR. The second length L2 may be shorter than the first length L1. Therefore, the length required for setting the pad along the first direction D1 (i.e., the first length L1) may be greater than the length required for setting the main transfer transistor MPT along the same first direction D1 (i.e., the second length L2). When the main transfer transistors MPT are arranged continuously along the first direction D1, the main transfer transistors MPT may be spaced apart from the corresponding pads along the first direction D1. As the number of pads and main transfer transistors MPT increases, the separation distance between the main transfer transistors MPT and the corresponding pads along the first direction D1 may increase. The distance between some pads and some main transfer transistors MPT along the first direction D1 may be longer. In the view along the third direction D3, as the separation distance between the corresponding pads and the main transfer transistors MPT increases along the first direction D1, the number of conductive lines (e.g., metal lines for electrical connection) may increase. For example, the required conductive lines may extend between the corresponding pads and the main pass transistor MPT along the first direction D1. As the number of required conductive lines increases, the process complexity and the time required for the process may also increase.

[0074] The main regions MR may be classified into main groups MG. Each of the plurality of main groups MG may include main regions MR sequentially arranged along the first direction D1. In an example embodiment, the immediately adjacent main groups MG may be spaced apart from each other along the first direction D1. The "spaced apart" of the immediately adjacent main groups MG may refer to a case where the distance between the nearest pair of main transfer transistors MPT belonging to each of the adjacent main groups MG along the first direction D1 is greater than the distance between the main transfer transistors MPT within each main group MG.

[0075] In an example embodiment, the immediately adjacent main groups MG may be in contact along the first direction D1. "Contact" between the immediately adjacent main groups MG may refer to a situation where a distance along the first direction D1 between a pair of main transfer transistors MPT that are closest to each other and each belongs to the immediately adjacent main group is substantially the same as a distance between the main transfer transistors MPT that belong to each of those immediately adjacent main groups MG.

[0076] The main groups MG may correspond to the pad groups PG, respectively. For the purpose of illustration, six main groups MG are shown. The six main groups MG arranged along the first direction D1 may be respectively referred to as the first main group, the second main group, the third main group, the fourth main group, the fifth main group, and the sixth main group. Although each of the plurality of six main groups MG is shown to include four main regions MR sequentially arranged along the first direction D1, this is provided only as an example. In other examples, the main group MG may include more or less than four main regions MR.

[0077] The dummy region DR may be disposed between adjacent main groups MG spaced apart along the first direction D1. The number of dummy regions DR between these adjacent main groups MG may be determined as needed. For example, one dummy region DR may be provided, or a plurality of dummy regions DR may be sequentially arranged along the first direction D1. At least one dummy transmission transistor DPT may be provided in each dummy region DR. A plurality of dummy transmission transistors DPT provided in a dummy region DR may be arranged along the second direction D2. Although it is shown that each dummy region DR includes two dummy transmission transistors DPT arranged along the second direction D2, this is provided only as an example. In other examples, the dummy region DR may include one or more than three dummy transmission transistors DPT. The width of the dummy region DR (referred to as the third width W3) may be substantially the same as the pitch of the dummy transmission transistor DPT. In one example, at least some of the third widths W3 of the plurality of dummy regions DR may be equal to each other. In one example, at least some of the third widths W3 of the plurality of dummy regions DR may be different from each other. The third width W3 of the dummy region DR may also be substantially the same as the second width W2 of the main region MR. In the view along the third direction D3, the central axis of the dummy region DR extending along the second direction D2 may overlap with the central axis of the dummy transfer transistor DPT extending along the second direction D2. The dummy transfer transistor DPT may have a first polarity. For example, the dummy transfer transistor DPT may be an NMOS transistor formed on a p-type active pattern. A plurality of dummy transfer transistors DPT may be configured not to send a voltage to a word line. For example, the dummy transfer transistor DPT may not be electrically connected to a pad (i.e., may be electrically isolated from the pad).

[0078] like Fig.6D As shown, the dummy transfer transistor DPT may include a first dummy source / drain region DSD1 and a second dummy source / drain region DSD2, a dummy gate electrode DGE, and a dummy gate insulating layer DGL disposed on the substrate region 204a, the deep well region 204b, and the well region 204c. The substrate region 204a, the deep well region 204b, the well region 204c, the first dummy source / drain region DSD1, the second dummy source / drain region DSD2, the dummy gate electrode DGE, and the dummy gate insulating layer DGL may be respectively connected to the reference Figure 6CThe substrate region 204a, deep well region 204b, well region 204c, first source / drain region SD1, second source / drain region SD2, gate electrode GE and gate insulating layer GL are described as being substantially the same. In one example, the dummy pass transistor DPT may be formed in the same process as the main pass transistor MPT.

[0079] In contrast to the main transfer transistor MPT, a contact may not be provided on the first and second dummy source / drain regions DSD1 and DSD2. Therefore, the first and second dummy source / drain regions DSD1 and DSD2 may not be electrically connected to the pad and may be configured not to transmit a voltage to the word line.

[0080] Figure 7 is a diagram illustrating a semiconductor memory device according to some example embodiments.

[0081] Reference Figure 7 , a semiconductor memory device 6000 may be provided. The semiconductor memory device 6000 may be Figure 2A and Figure 2B The semiconductor memory device 10 shown. The memory device 6000 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then at least one upper chip and a lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may indicate a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed by copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed by aluminum (Al) and / or tungsten (W).

[0082] The memory device 6000 may include at least one upper chip including a cell region. For example, the memory device 6000 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 6000 includes two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 6000. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined before each of the first upper chip and the second upper chip is flipped. In this regard, the upper portion of the lower chip may indicate an upper portion defined based on a +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may indicate an upper portion defined based on a -Z axis direction. However, example embodiments are not limited thereto. In some example embodiments, one of the first upper chip and the second upper chip may be flipped over and may then be connected to a corresponding chip through a bonding method.

[0083] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 6000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0084] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230 a , 230 b , and 230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240 a , 240 b , and 240 c may be formed of copper having a relatively low resistivity.

[0085] In some example embodiments, the first metal lines 230a, 230b, and 230c and the second metal lines 240a, 240b, and 240c are shown and described. However, the example embodiments are not limited thereto. In some example embodiments, at least one or more additional metal lines may also be formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 240a, 240b, and 240c.

[0086] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0087] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (e.g., including word lines 331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (e.g., the Z-axis direction). String selection lines and ground selection lines may be disposed on and below the word lines 330, and a plurality of word lines 330 may be disposed between the string selection lines and the ground selection lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (e.g., including word lines 431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (e.g., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0088] In some example embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 310.

[0089] In some example embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the channel length increases, it may be difficult to form a channel having a substantially uniform width due to the characteristics of the manufacturing process. The memory device 6000 according to some example embodiments may include a channel having improved width uniformity due to a lower channel LCH and an upper channel UCH formed through sequentially performed processes.

[0090] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in area "A2", the word line close to the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in a memory cell connected to the dummy word line. Alternatively, the number of pages corresponding to the memory cell electrically connected to the dummy word line may be less than the number of pages corresponding to the memory cell electrically connected to the normal word line. The voltage level applied to the dummy word line may be different from the voltage level applied to the general word line, and thereby the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0091] In the region "A2", the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, example embodiments are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationship of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as those of the channel structure CH disposed in the first cell region CELL1.

[0092] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. The first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. In some example embodiments, the first through electrode THV1 may also penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0093] In some example embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d may be formed at the bottom end of the first upper chip including the first cell region CELL1, and the second through metal pattern 472d may be formed at the top end of the second upper chip including the second cell region CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. The lower via 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper via 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected to each other by a bonding method.

[0094] In addition, in the bit line bonding area BLBA, an upper metal pattern 292 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 292 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 292 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some circuit elements 220c of the peripheral circuit area PERI may constitute a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c constituting the page buffer through the upper bonding metal pattern 370c of the first cell area CELL1 and the upper bonding metal pattern 270c of the peripheral circuit area PERI.

[0095] In the word line bonding area WLBA, the word line 330 of the first cell area CELL1 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (341 to 347). The area where the cell contact plugs 340 (341 to 347) are connected may be referred to as a pad. The first metal line 350b and the second metal line 360b may be sequentially connected to the cell contact plugs 340 electrically connected to the word line 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI.

[0096] The cell contact plug 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 220b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 340 may be electrically connected to the circuit element 220b constituting the row decoder through the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuit region PERI. In some example embodiments, the operating voltage of the circuit element 220b constituting the row decoder may be different from the operating voltage of the circuit element 220c constituting the page buffer. For example, the operating voltage of the circuit element 220c constituting the page buffer may be greater than the operating voltage of the circuit element 220b constituting the row decoder.

[0097] Likewise, in the word line bonding area WLBA, the word line 430 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (e.g., including contact plugs 441 to 447). The area where the cell contact plugs 340 (341 to 347) are connected may be referred to as a pad. The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower and upper metal patterns of the first cell area CELL1 and the cell contact plugs 348.

[0098] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0099] In the external pad bonding area PA, a lower metal pattern 371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected to each other by a bonding method in the external pad bonding area PA. Similarly, an upper metal pattern 372a may be formed in an upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0100] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material (e.g., a metal, a metal compound, and / or doped polysilicon). The common source line contact plug 380 of the first cell area CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell area CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell area CELL2.

[0101] The input / output pads 205, 405, and 406 may be disposed in the external pad bonding area PA. The lower insulating layer 206 may cover the bottom surface of the first substrate 210, and the first input / output pads 205 may be formed on the lower insulating layer 206. The first input / output pads 205 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit area PERI through the first input / output contact plug 203, and may be spaced apart from the first substrate 210 by the lower insulating layer 206. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0102] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. Second input / output pads 405 and / or third input / output pads 406 may be disposed on the upper insulating layer 401. The second input / output pads 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through second input / output contact plugs 403 and 303, and the third input / output pads 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through third input / output contact plugs 404 and 304.

[0103] In some example embodiments, the third substrate 410 may not be disposed in a region in which the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0104] In some example embodiments, as shown in region 'B1', the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. In this regard, the diameter of the channel structure CH described in region 'A1' may gradually decrease toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method.

[0105] In some example embodiments, as shown in region 'B2', the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually become smaller toward the upper insulating layer 401. In this regard, similar to the channel structure CH in region 'A1', the diameter of the third input / output contact plug 404 may gradually become smaller toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region ELL2 and the first cell region CELL1 are coupled to each other.

[0106] In some example embodiments, the input / output contact plug may overlap the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 along a third direction (e.g., Z-axis direction) and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0107] In some example embodiments, as shown in region “C1”, the opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in region “C1”, the diameter of the second input / output contact plug 403 may gradually increase toward the second input / output pad 405. However, example embodiments are not limited thereto, and in some example embodiments, the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405.

[0108] In some example embodiments, as shown in region “C2”, an opening 408 penetrating the third substrate 410 may be formed, and a contact portion 407 may be formed in the opening 408. One end of the contact portion 407 may be connected to the second input / output pad 405, and the other end of the contact portion 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact portion 407 in the opening 408. In this case, as shown in region “C2”, the diameter of the contact portion 407 may gradually increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact portion 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0109] In some example embodiments described in region "C3", compared to region "C2" discussed above, barrier 409 may also be formed on the bottom end of opening 408 of third substrate 410. Barrier 409 may be a metal line formed in the same layer as common source line 420. Alternatively, barrier 409 may be a metal line formed in the same layer as at least one word line 430. Second input / output contact plug 403 may be electrically connected to second input / output pad 405 through contact 407 and barrier 409.

[0110] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, a diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell region CELL1 may gradually become smaller or may gradually become larger toward the lower metal pattern 371e.

[0111] In some example embodiments, the slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. Alternatively, when viewed in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0112] In some example embodiments, as shown in region 'D1', slits 411 may be formed to penetrate third substrate 410. For example, slits 411 may be used to prevent or reduce occurrence of fine cracks in third substrate 410 when forming opening 408. However, example embodiments are not limited thereto, and in some example embodiments, slits 411 may be formed to have a depth ranging from about or exactly 60% to about or exactly 70% of the thickness of third substrate 410.

[0113] In some example embodiments, as shown in region "D2", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge leakage current generated when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0114] In some example embodiments, as shown in region 'D3', an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because the insulating material 413 is formed in the slit 411, it is possible to prevent or reduce a voltage provided through the second input / output pad 405 from affecting a metal layer disposed on the third substrate 410 in the word line bonding region WLBA.

[0115] In some example embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 6000 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, only the third input / output pad 406 disposed on the upper insulating layer 401, or some other combination.

[0116] In some example embodiments, at least one of the second substrate 310 of the first cell region CELL1 or the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, an upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0117] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, the relevant numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, the intention is not to require the accuracy of the geometric shape, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "generally" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerance (e.g., ±10%) values ​​or shapes around the numerical value.

[0118] The memory device 1000 (or other circuits, such as the flash memory 1100, the memory controller 1200, the memory cell array 1110, the peripheral circuit 1115, the ADDR decoder 1120, the page buffer circuit 1130, the data input / output circuit 1140, the word line voltage generator 1150, the control logic 1160 or other subcomponents) may include hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0119] Figure 8 is a cross-sectional view illustrating a stepped structure of a word line and a second peripheral circuit region according to example embodiments.

[0120] Reference Figure 8 , a stack structure can be provided. The stack structure may include a word line 114, a stack insulation layer 112, an insulation pattern 116, and a contact structure 120. The word line 114 may be connected to the reference Figure 7 The described word lines 330 are substantially the same. The stacked insulating layers 112 may be respectively disposed between the word lines 114. The insulating layers 112 and the word lines 114 may be alternately stacked along the third direction D3 to form a stack structure.

[0121] The insulating pattern 116 may be inserted into the stacked structure. For example, the insulating pattern 116 may be formed by alternately stacking insulating layers 112 and word lines 114 on top of the substrate, etching a portion of the stacked structure to form a pad, and filling the area where the stacked structure is removed with an insulating material. This process may be repeated multiple times. After forming a main stacked structure with the inserted insulating pattern 116, an auxiliary stacked structure with the insulating pattern 116 may be created by performing the same process on top of the main stacked structure. The auxiliary stacked structure may be formed by repeating this process three times. Figure 8 In one example, adjacent insulation patterns 116 along the third direction D3 may be connected.

[0122] The process of etching the stack structure can form a step region SR. The step region SR may include an end of a word line 114 having a step-like structure. The end protruding from a word line 114 may be referred to as a pad. The pad in a step region SR is shown as moving away from the second peripheral circuit region 202 along the first direction D1, but this is provided only as an example. In another example, the pad may be formed closer to the second peripheral circuit region 202 along the first direction D1. The step regions SR may correspond to the pad groups PG, respectively. For example, when viewed along the third direction D3, the step region SR may be disposed within the corresponding pad group PG.

[0123] Each pad group PG may include the previously described pad regions. The pad regions may be arranged along the first direction D1. In a view along the third direction D3, pads arranged along the second direction D2 may be disposed within each pad region. Figure 8 Eight pads arranged along the first direction D1 in each pad group PG are shown, but this is provided as an example only. In another example, less than 8 or more than 8 pads arranged along the first direction D1 may be provided in each pad group PG. The intervals between the pad groups PG may be determined as needed.

[0124] The contact structure 120 may be inserted into the stacked structure. The contact structure 120 may extend along a third direction D3. Each contact structure 120 may include a contact plug 122 located inside the contact structure when viewed along the third direction D3 and an insulating sidewall 124 surrounding the contact plug 122. Both the contact plug 122 and the insulating sidewall 124 may extend along the third direction D3. The contact plug 122 may be electrically connected to any pad. The insulating sidewall 124 may not be disposed between the electrically connected pad and the contact plug 122. For example, the pad may extend laterally to the side of the corresponding contact plug 122 to directly contact the contact plug 122. The contact plug 122 may be electrically connected to any one of the word lines 114. In the view along the third direction D3, the contact plug 122 may be disposed in a pad group PG corresponding to a step region SR including a pad electrically connected to the contact plug 122.

[0125] The second peripheral circuit region 202 may include a main group MG. Each main group MG may include the main region described previously. The main regions may be arranged along a first direction D1. In a view along a third direction D3, a main transfer transistor may be arranged in each main region along a second direction D2. The main transfer transistors within the main group MG may be electrically connected to contact plugs 122 disposed in corresponding pad groups PG, respectively. The main group MG may be arranged adjacent to the corresponding pad group PG. The length of the conductive line used for electrical connection between the main transfer transistor and the pads in the corresponding main group MG and pad group PG may be reduced. Accordingly, the manufacturing complexity and manufacturing time of the semiconductor memory device 10 may be reduced. A dummy region DR may be disposed between the main groups MG. The dummy region DR may be disposed adjacent to the reference FIG. 2A to FIG. 6D The described dummy regions DR are substantially the same.

[0126] Fig. 9 1 is a diagram showing a second peripheral circuit region corresponding to a block according to an example embodiment. FIG. 2A to FIG. 6D Describes essentially the same content.

[0127] Reference Fig. 6A and Fig. 9 , a second peripheral circuit region 202a corresponding to one block may be provided. The second peripheral circuit region 202a may include a main region MR provided with a main transfer transistor MPT and a dummy region DR provided with a dummy transfer transistor DPT. FIG. 2A to FIG. 6D Contrary to the description of FIG. 1 , the third contacts CT3 may be respectively connected to the first dummy source / drain regions DSD1 of the dummy pass transistor DPT. In an example, a source / drain signal may be applied to the first source / drain region DSD1 of the dummy pass transistor DPT through the third contacts CT3. Accordingly, one or more example embodiments provide a semiconductor memory device with improved reliability.

[0128] FIG. 10 is a diagram showing a second peripheral circuit region corresponding to a block according to an example embodiment. FIG. 2A to FIG. 6D Describes essentially the same content.

[0129] Reference Fig. 6A and Fig.10 , a second peripheral circuit region 202b corresponding to one block may be provided. The second peripheral circuit region 202b may include a main region MR provided with a main transfer transistor MPT and a dummy region DR provided with a dummy transfer transistor DPT. FIG. 2A to FIG. 6DContrary to the description of the third contact CT3 and the fourth contact CT4, the third contact CT3 and the fourth contact CT4 may be connected to the first dummy source / drain region DSD1 and the second dummy source / drain region DSD2 of the dummy transfer transistor DPT, respectively. The dummy transfer transistor DPT may have a second polarity different from that of the main transfer transistor MPT. For example, the dummy transfer transistor DPT may be a P-channel metal oxide semiconductor transistor formed with a p-type active pattern. For example, the dummy transfer transistor DPT may be a PMOS transistor formed with the same p-type active pattern as the main transfer transistor MPT. In one example, a body bias is applied to the first dummy source / drain region DSD1 and the second dummy source / drain region DSD2 of the dummy transfer transistor DPT through the third contact CT3 and the fourth contact CT4. In this case, the dummy transfer transistor DPT may apply a body bias and thus perform the function of a guard ring.

[0130] In another example, as shown in FIG. Fig.6D As described, the dummy pass transistor DPT may have the same first polarity as the main pass transistor MPT. For example, the dummy pass transistor DPT and the main pass transistor MPT may be NMOS transistors formed in a p-type active pattern.

[0131] In one example, the dummy pass transistor DPT may have a different function from the main pass transistor MPT. For example, the dummy pass transistor DPT may be configured to generate a drain signal applied to the main pass transistor MPT (eg, the first source / drain region SD1 ).

[0132] Fig.11 1 is a diagram showing a second peripheral circuit region corresponding to a block according to an example embodiment. FIG. 2A to FIG. 6D Describes essentially the same content.

[0133] Reference Fig. 6A and Fig.11 , a second peripheral circuit region 202c corresponding to one block may be provided. The second peripheral circuit region 202c may include a main region MR provided with a main transfer transistor MPT and a dummy region DR provided with a dummy transfer transistor DPT. FIG. 2A to FIG. 6DContrary to the description of , the dummy transfer transistor DPT may share a gate electrode GE with at least one of the main transfer transistors MPT adjacent to the dummy transfer transistor DPT. For example, the gate electrode GE of the main transfer transistor MPT may be configured to extend onto the active pattern of the adjacent dummy transfer transistor DPT. When the dummy transfer transistors DPT are arranged in series, a plurality of dummy transfer transistors DPT and the main transfer transistor MPT adjacent thereto may share a gate electrode GE. For example, the gate electrode GE of the main transfer transistor MPT may extend onto a plurality of dummy transfer transistors DPT.

[0134] Fig.12 Shown are connection areas included in a plurality of blocks according to example embodiments. Fig.13A and Fig. 13B 1 is a diagram showing a second peripheral circuit region corresponding to a plurality of blocks. FIG. 2A to FIG. 6D Describes essentially the same content.

[0135] Reference Fig.12 , a connection region 102 may be provided. As an example, three connection regions 102 are shown. The connection regions 102 may each be included in a plurality of blocks. The connection regions 102 may be arranged along the second direction D2. Each connection region 102 includes a pad region PR arranged along the first direction D1, a pad (e.g. Figure 7 and Figure 8 pads), pad groups PG for classifying pad regions PR, and contact plugs connected to pads. Figure 4 The connection regions 102 described are substantially the same, so description of each connection region 102 is omitted. Although the pad regions PR are shown as having the same arrangement structure within the connection regions 102, this is provided only as an example. In another example, the pad regions PR may have different arrangement structures within different connection regions 102.

[0136] Reference Fig.13A and Fig. 13B, a second peripheral circuit region 202 may be set. As an example, three second peripheral circuit regions 202 are shown. The second peripheral circuit regions 202 may correspond to a plurality of blocks, respectively. The second peripheral circuit regions 202 may overlap with the connection regions 102 included in the corresponding blocks along the third direction D3. The second peripheral circuit regions 202 may be arranged along the second direction D2. Each second peripheral circuit region 202 includes a main region MR in which a main transfer transistor MPT is set, a main group MG for classifying the main region MR, a dummy region DR in which a dummy transfer transistor DPT is set, and contacts CT1 and CT2 connected to a first source / drain region SD1 and a second source / drain region SD2 of the main transfer transistor MPT. Although Fig. 13B Each second peripheral circuit region 202 shown in FIG. Figure 6B The second peripheral circuit region 202a in is the same, but this is provided as an example only. In another example, Fig. 13B Each second peripheral circuit region 202 is shown as Fig. 9 The second peripheral circuit region 202a, Fig.10 The second peripheral circuit region 202b, or Fig.11 The description of each second peripheral circuit region 202 is omitted because it is similar to the reference Fig. 6A and Fig.6D The second peripheral circuit region 202a described is substantially the same. Although the main region MR and the dummy region DR are shown as having the same arrangement structure within the second peripheral circuit region 202, this is provided only as an example. In another example, the main region MR and the dummy region DR may have different arrangement structures within different second peripheral circuit regions 202. In one example, the arrangement structure of the main region MR may be determined according to the arrangement structure of the corresponding pad region PR, and the dummy region DR may be disposed between the main groups MG.

[0137] Accordingly, a semiconductor memory device with improved reliability can be provided.

[0138] In some example embodiments, according to example embodiments, Figure 1A and Figure 1BEach component represented by the block shown can be implemented as various numbers of hardware, software and / or firmware structures that perform the above-mentioned corresponding functions. For example, at least one of these components can include various hardware components, including digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuits using direct circuit structures, such as memories, processors, logic circuits, lookup tables, etc., which can perform corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components can include a part of a module, program or code, which contains one or more executable instructions for performing a specified logical function and is performed by one or more microprocessors or other control devices. Similarly, at least one of these components can also include a processor, such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding function, or can be implemented by a processor. The functional aspects of the example embodiments can be implemented in an algorithm executed on one or more processors. In addition, the components, elements, modules or units or processing steps represented by the blocks can use any number of related art technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0139] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional 3D semiconductor memory device, comprising: Storage unit area; as well as a peripheral circuit configured to control the memory cell region, Wherein, the storage unit area includes: a cell array region, comprising a plurality of memory cells arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells, wherein the ends form a staircase configuration, Wherein, the peripheral circuit includes a peripheral circuit area overlapping with the connection area along the vertical direction, wherein the peripheral circuit region includes a first main pass transistor electrically connected to a first word line among the plurality of word lines, and a first dummy pass transistor electrically separated from the plurality of word lines, and The first main transfer transistor and the first dummy transfer transistor are arranged along a first direction perpendicular to the vertical direction.

2. The 3D semiconductor memory device according to claim 1, wherein: The peripheral circuit region further includes: a second main transfer transistor electrically connected to a second word line of the plurality of word lines, and The first main transfer transistor and the second main transfer transistor are spaced apart from each other along the first direction, and the first dummy transfer transistor is interposed between the first main transfer transistor and the second main transfer transistor.

3. The 3D semiconductor memory device according to claim 2, wherein: The first main pass transistor is one of a plurality of first main pass transistors, and the second main pass transistor is one of a plurality of second main pass transistors, wherein the plurality of first main transfer transistors are sequentially arranged along the first direction, and The plurality of second main transfer transistors are sequentially arranged along a second direction perpendicular to each of the first direction and the vertical direction.

4. The 3D semiconductor memory device according to claim 3, wherein: The peripheral circuit area further includes: a second dummy transfer transistor electrically separated from the plurality of word lines, and The second dummy transfer transistor is disposed between the plurality of first main transfer transistors and the plurality of second main transfer transistors.

5. The 3D semiconductor memory device according to claim 1, wherein: The peripheral circuit area further includes: a second dummy transfer transistor electrically separated from the plurality of word lines, and The first dummy transfer transistor is arranged to be directly adjacent to the second dummy transfer transistor along the first direction.

6. The 3D semiconductor memory device according to claim 1, wherein: The first main transfer transistor includes a first source / drain region, a second source / drain region, a gate electrode and a gate insulating layer, The first dummy transfer transistor includes a first dummy source / drain region, a second dummy source / drain region, a dummy gate electrode and a dummy gate insulating layer, and The peripheral circuit region includes a first contact portion electrically connected to the first source / drain region, and a second contact portion electrically connected to the second source / drain region.

7. The 3D semiconductor memory device according to claim 6, wherein: The peripheral circuit region includes a third contact portion electrically connected to the first dummy source / drain region and configured to provide a source / drain signal to the first dummy source / drain region.

8. The 3D semiconductor memory device according to claim 6, wherein: The peripheral circuit region includes: a fourth contact portion electrically connected to the first dummy source / drain region and the second dummy source / drain region, wherein the fourth contact portion is configured to apply a body bias to the first dummy source / drain region and the second dummy source / drain region, and The polarity of the first dummy transfer transistor is opposite to the polarity of the first main transfer transistor.

9. The 3D semiconductor memory device according to claim 1, wherein: The width of the first main transfer transistor along the first direction is smaller than a protrusion width of an end portion of a second word line protruding from an end portion of an immediately adjacent first word line along the first direction.

10. The 3D semiconductor memory device according to claim 1, wherein: The first main pass transistor and the first dummy pass transistor are configured to share a gate electrode.

11. A three-dimensional 3D semiconductor memory device, comprising: Storage unit area; as well as a peripheral circuit configured to control the memory cell region, Wherein, the storage unit area includes: a cell array region, comprising a plurality of memory cells arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells, wherein the peripheral circuit includes a peripheral circuit region overlapping the connection region along the vertical direction, wherein the peripheral circuit region includes a plurality of main pass transistors electrically connected to the plurality of word lines, and a plurality of dummy pass transistors electrically separated from the plurality of word lines, and Wherein, the plurality of main transfer transistors are arranged along a first direction perpendicular to the vertical direction.

12. The 3D semiconductor memory device according to claim 11, wherein: The plurality of main pass transistors are classified into a plurality of main groups, and The first dummy pass transistor among the plurality of dummy pass transistors is disposed between a pair of main groups among the plurality of main groups.

13. The 3D semiconductor memory device according to claim 12, wherein: A second dummy pass transistor and a third dummy pass transistor of the plurality of dummy pass transistors are spaced apart from each other along the first direction, and a first main group of the plurality of main groups is interposed between the second dummy pass transistor and the third dummy pass transistor.

14. The 3D semiconductor memory device according to claim 12, wherein: The memory cell region further includes: a pad region arranged along the first direction, wherein each of the pad regions includes ends of the plurality of word lines arranged along a second direction intersecting the first direction in a plan view, The pad area is classified into a plurality of pad groups, and The plurality of pad groups respectively correspond to the plurality of main groups.

15. The 3D semiconductor memory device according to claim 14, wherein: The memory cell region further includes contact plugs connected to the ends of the plurality of word lines, respectively, and Wherein, in a plan view, the contact plugs are arranged along the first direction.

16. The 3D semiconductor memory device according to claim 14, wherein: Corresponding ends of the plurality of word lines overlap with the plurality of main pass transistors along the vertical direction.

17. The 3D semiconductor memory device according to claim 11, wherein: A width of each of the plurality of main pass transistors along the first direction is smaller than a protruding width of an end portion of a second word line protruding from an end portion of an immediately adjacent first word line along the first direction.

18. The 3D semiconductor memory device according to claim 11, wherein: The plurality of main pass transistors are classified into a plurality of main groups, and Some of the plurality of main groups are arranged adjacent to each other along the first direction.

19. A three-dimensional 3D semiconductor memory device, comprising: Storage unit area; as well as a peripheral circuit region configured to control the memory cell region, Wherein, the storage unit area includes a plurality of blocks, Each of the plurality of blocks includes a cell array region, and the cell array region includes: A plurality of storage units arranged in a vertical direction; and a connection region including ends of a plurality of word lines connected to the plurality of memory cells, wherein the peripheral circuit region includes a plurality of peripheral circuit regions respectively overlapping with the connection regions of the plurality of blocks, wherein each of the plurality of peripheral circuit regions includes a plurality of main pass transistors electrically connected to the plurality of word lines, and a plurality of dummy pass transistors electrically separated from the plurality of word lines, and Wherein, the plurality of main transfer transistors are arranged along a first direction perpendicular to the vertical direction.

20. The 3D semiconductor memory device according to claim 19, wherein A width of each of the plurality of main pass transistors along the first direction is smaller than a protruding width of an end portion of a second word line protruding from an end portion of an immediately adjacent first word line along the first direction.

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