Ferroelectric 3D NAND flash memory device and method of operation, fabrication method

Abstract

The application discloses a ferroelectric 3D NAND flash memory device and an operating method and a manufacturing method thereof. The 3D NAND flash memory device comprises a substrate and a stack structure on the surface of the substrate, the stack structure comprising a plurality of interlaced gate dielectric oxide layers and gate electrode layers; a channel hole penetrating through the stack structure; a first isolation layer on the side wall of the channel hole; a channel layer covering the first isolation layer and the bottom of the channel hole; a ferroelectric layer on the surface of the channel layer; a back gate layer on the surface of the ferroelectric layer; a filling layer filling the remaining space of the channel hole; an insulating layer covering the channel hole and the stack structure, the insulating layer having a first through hole and a second through hole, the first through hole exposing at least part of the surface of the channel layer, and the second through hole exposing at least part of the surface of the back gate layer; a drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole. The 3D NAND flash memory device uses a ferroelectric layer as a charge storage layer, and has a relatively high operating speed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a ferroelectric 3D NAND flash memory device and an operating method and manufacturing method thereof. BACKGROUND

[0002] A 3D NAND flash memory device is a non-volatile memory device that improves storage density and performance by vertically stacking storage units. Specifically, the vertical stacking of storage units in a 3D NAND flash memory device is mainly achieved by stacking gate metals and depositing thin films in high aspect ratio channel holes. The traditional channel structure of a 3D NAND flash memory device includes a metal gate, a blocking oxide layer, a charge storage layer, a tunnel oxide layer, a channel layer, and an oxide filling layer. The metal gate functions as a control gate of the 3D NAND flash memory device. The blocking oxide layer functions as a blocking layer to prevent charge leakage in the charge storage layer. The charge storage layer typically uses a silicon nitride (SiN) material, which stores charges and changes the threshold voltage of the 3D NAND flash memory device to achieve information storage. The tunnel oxide layer functions as a tunnel for charges to enter the charge storage layer. The channel layer serves as a semiconductor conductive channel, and the metal gate controls the conductive channel to achieve the function of controlling the channel current by controlling the gate voltage. The oxide filling layer fills the remaining space in the channel hole and serves as a support and insulator.

[0003] With the development of storage technology, users have increasingly high requirements for the operating speed of 3D NAND flash memory devices. Therefore, how to improve the operating speed of 3D NAND flash memory devices has become a research hotspot for those skilled in the art. SUMMARY

[0004] In view of the above problems, the present application provides a ferroelectric 3D NAND flash memory device and an operating method and manufacturing method thereof to improve the operating speed of the 3D NAND flash memory device. The specific solutions are as follows:

[0005] A ferroelectric 3D NAND flash memory device, comprising:

[0006] a substrate;

[0007] a stack structure located on a first surface of the substrate, the stack structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged in a staggered manner along a direction perpendicular to a plane in which the substrate is located;

[0008] a channel hole penetrating through the stack structure, the channel hole extending into the first surface of the substrate;

[0009] a first isolation layer located on a sidewall of the channel hole;

[0010] a channel layer covering the first isolation layer and the bottom of the channel hole;

[0011] a ferroelectric layer on the surface of the channel layer;

[0012] a back gate layer on the surface of the ferroelectric layer;

[0013] a filling layer filling the remaining space of the channel hole;

[0014] an insulating layer covering the channel hole and the stack structure, the insulating layer having a first through hole and a second through hole, wherein the first through hole exposes at least part of the surface of the channel layer, and the second through hole exposes at least part of the surface of the back gate layer;

[0015] a drain electrode electrically connected to the channel layer through the first through hole, and a back gate electrode electrically connected to the back gate layer through the second through hole.

[0016] Optionally, the ferroelectric layer is a single-layer ferroelectric film.

[0017] Optionally, the ferroelectric layer further comprises a silicon dioxide layer on the surface of the single-layer ferroelectric film away from the channel layer.

[0018] Optionally, the back gate electrode is made of a metal material capable of inducing the ferroelectric layer to form a ferroelectric phase.

[0019] Optionally, the back gate electrode is tungsten or titanium nitride.

[0020] Optionally, the channel layer is a polysilicon layer or an IGZO layer or a thin-layer molybdenum disulfide layer.

[0021] An operating method of a 3D NAND flash memory device, applied to the 3D NAND flash memory device described in any one of the preceding embodiments, the 3D NAND flash memory device comprising a plurality of memory cells, the operating method comprising at least one of the following:

[0022] When performing a read operation on the 3D NAND flash memory device, a read voltage is applied to the gate electrode of a memory cell to be read in the 3D NAND flash memory device, a pass voltage is applied to the gate electrode of other memory cells in the same channel hole, and a detection voltage is uniformly applied to the drain electrode of each of the memory cells in the same channel hole to detect whether the memory cell to be read is turned on, while the source electrode of each of the memory cells in the same channel hole is connected to zero potential and the back gate electrode is floating;

[0023] When performing a programming operation on the 3D NAND flash memory device, a programming voltage is applied to the gate electrode of a memory cell to be programmed in the 3D NAND flash memory device, the back gate electrode is connected to zero potential, and other electrodes are floating;

[0024] During an erase operation performed on the 3D NAND flash memory device, a zero potential is applied to the gate of the memory cell to be erased, an erase voltage is applied to the back gate, and the source and drain are left floating.

[0025] A method for manufacturing a ferroelectric 3D NAND flash memory device, comprising:

[0026] providing a substrate;

[0027] forming a stack structure on a first surface of the substrate, the stack structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged in a staggered manner along a direction perpendicular to a plane in which the substrate lies;

[0028] forming a channel hole extending through the stack structure and into the first surface of the substrate;

[0029] forming a first isolation layer on the sidewall of the channel hole;

[0030] sequentially forming a channel layer covering the first isolation layer and the bottom of the channel hole, a ferroelectric layer, a back gate layer, and a filling layer filling the remaining space of the channel hole;

[0031] forming an insulating layer covering the channel hole and the stack structure, the insulating layer having a first through-hole and a second through-hole, wherein the first through-hole exposes at least part of the surface of the channel layer, and the second through-hole exposes at least part of the surface of the back gate layer;

[0032] forming a drain electrode electrically connected to the channel layer through the first through-hole, and a back gate electrode electrically connected to the back gate layer through the second through-hole.

[0033] Optionally, sequentially forming a channel layer covering the surface of the first isolation layer and the bottom of the channel hole, a ferroelectric layer, a back gate layer, and a filling layer filling the remaining space of the channel hole comprises:

[0034] forming a channel layer covering the surface of the first isolation layer, the bottom of the channel hole, and the surface of the stack structure away from the substrate;

[0035] forming a ferroelectric layer covering the surface of the channel layer;

[0036] forming a back gate layer covering the surface of the ferroelectric layer away from the channel layer;

[0037] forming a filling layer covering the surface of the back gate layer away from the ferroelectric layer, and filling the remaining space of the channel hole;

[0038] removing the channel layer, the ferroelectric layer, the back gate layer, and the filling layer from the surface of the stack structure away from the substrate.

[0039] Optionally, after the first isolation layer is manufactured, before the channel layer is manufactured, the method further includes: performing ion implantation on the substrate through the channel hole. BRIEF DESCRIPTION OF DRAWINGS

[0040] The above and other features, aspects, and advantages of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or like reference numerals are used to represent the same or similar elements. It is to be understood that the drawings are schematically showing the elements and features, which are not necessarily drawn to scale.

[0041] Figure 1 A structure schematic diagram of a ferroelectric 3D NAND provided by the present application;

[0042] Figure 2 An equivalent circuit schematic diagram of the ferroelectric 3D NAND provided by the present application when performing a read operation;

[0043] Figure 3 An equivalent circuit schematic diagram of the ferroelectric 3D NAND provided by the present application when performing a program operation;

[0044] Figure 4 An equivalent circuit schematic diagram of the ferroelectric 3D NAND provided by the present application when performing an erase operation;

[0045] Figure 5 A flowchart of a manufacturing method of the ferroelectric 3D NAND provided by the present application;

[0046] Figures 6-18 A partial structure schematic diagram involved in the manufacturing process of the ferroelectric 3D NAND provided by the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present application will be described in detail below with reference to the drawings, obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0048] Various modifications and changes can be made to the present application in light of the above description, which is not to be construed as limiting the present application. Therefore, the present application intends to cover the modifications and changes of the present application falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0049] In order to make the above objectives, characteristics and advantages of the present application more apparent, further specific embodiments will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] As described in the background section, how to improve the operating speed of 3D NAND flash devices has become a research hotspot for those skilled in the art.

[0051] The inventors have found that ferroelectricity is a property possessed by certain dielectric crystals. In some dielectric crystals, the structure of the unit cell causes the centers of positive and negative charges to be misaligned, resulting in an electric dipole moment, which produces a non-zero electric polarization intensity, so that the crystal has a spontaneous polarization, and the direction of the electric dipole moment can change due to an external electric field, showing characteristics similar to ferromagnetic materials. The polarization degree of the crystal and the relationship curve of the electric field intensity are similar to the shape of the magnetic hysteresis loop of ferromagnetic materials. Based on the electric hysteresis phenomenon in ferroelectricity, the polarization charge generated by ferroelectric polarization can be used to store information. In a 3D NAND flash structure, a ferroelectric material can be used to manufacture a charge storage layer, and a ferroelectric type 3D NAND flash device can be implemented to improve the operating speed of the 3D NAND flash device.

[0052] Specifically, the hafnium-based ferroelectric material refers to a ferroelectric material with hafnium (Hf) as the base element. The hafnium-based ferroelectric material has the advantages of simple composition, thin thickness, excellent ferroelectricity, and compatibility with metal-oxide-semiconductor (CMOS) processes, and is an ideal ferroelectric material for 3D NAND flash applications.

[0053] However, the hafnium-based ferroelectric material needs specific process conditions to form a lattice structure with ferroelectricity. The high-temperature growth and long-time high-temperature annealing steps in the process steps of the 3D NAND flash device can cause the hafnium-based ferroelectric material to change from a ferroelectric phase to a paraelectric phase, so that it no longer has a storage function. In particular, during the growth of the polysilicon channel in the 3D NAND flash device, growth and long-time annealing at a temperature of about 800°C are required. Therefore, if the hafnium-based ferroelectric material is directly used to replace the SiN material of the charge storage layer, the hafnium-based ferroelectric material needs to be grown first and then the polysilicon channel is grown. This will cause the ferroelectric layer to change from a ferroelectric phase to a paraelectric phase, and the storage function will disappear.

[0054] Therefore, the present application provides a ferroelectric type 3D NAND flash device and a manufacturing method thereof to improve the operating speed of the 3D NAND flash device. In the manufacturing method of the 3D NAND flash device, the polysilicon channel is grown first and then the ferroelectric layer is grown, so as to prevent the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing during the growth of the polysilicon channel, thereby affecting the storage function of the 3D NAND flash device.

[0055] Specifically, as shown in FIG. 1, the ferroelectric type 3D NAND flash device comprises a substrate 1, a tunnel oxide layer 2, a charge storage layer 3, a blocking layer 4, a polysilicon channel 5, a gate oxide layer 6, a gate electrode 7, a gate insulating layer 8, a source electrode 9, and a drain electrode 10. Figure 1As shown, the ferroelectric 3D NAND flash device provided by the embodiments of the present application comprises:

[0056] A substrate 10, which is optionally a silicon substrate;

[0057] A stack structure 20 located on the first surface of the substrate 10, the stack structure 20 comprising a plurality of gate dielectric oxide layers 21 and gate electrode layers 22 arranged in a staggered manner along a direction perpendicular to the plane of the substrate, the gate dielectric oxide layer 21 being optionally an isolation oxide layer, which can be a silicon dioxide layer, and the gate electrode layer 22 being a metal layer, such as a tungsten metal layer, but the present application does not limit this, which is determined according to the specific circumstances;

[0058] A channel hole extending through the stack structure 20 and extending to the first surface of the substrate 10;

[0059] A first isolation layer 30 located on the sidewall of the channel hole, the first isolation layer serving to isolate the metal gate (i.e., the gate electrode layer) and the channel layer, the first isolation layer being optionally a silicon dioxide layer, an aluminum dioxide layer, or a hafnium dioxide layer, or a high-K oxide, but the present application does not limit this, which is determined according to the specific circumstances;

[0060] A channel layer 40 covering the first isolation layer 30 and the bottom of the channel hole, the channel layer 40 being optionally a polysilicon layer, an IGZO layer, or a thin-layer molybdenum disulfide layer, but the present application does not limit this, which is determined according to the specific circumstances;

[0061] A ferroelectric layer 50 located on the surface of the channel layer 40;

[0062] A back gate layer 60 located on the surface of the ferroelectric layer 50;

[0063] A filling layer 70 filling the remaining space of the channel hole, the filling layer 70 being optionally an oxide layer, such as a silicon dioxide layer, for filling the channel hole and serving as a support;

[0064] An insulating layer 80 covering the channel hole and the stack structure 20, the insulating layer 80 having a first through hole and a second through hole, wherein the first through hole exposes at least part of the surface of the channel layer 40, and the second through hole exposes at least part of the surface of the back gate layer 60;

[0065] A drain 91 electrically connected to the channel layer 40 through the first through hole, and a back gate 92 electrically connected to the back gate layer 60 through the second through hole.

[0066] The ferroelectric 3D NAND flash device provided in the embodiments of the present application uses a ferroelectric layer as a charge storage layer, and the ferroelectric material has a relatively fast flipping speed under an electric field, so that the operating speed of the ferroelectric 3D NAND flash device provided in the embodiments of the present application is relatively fast, which is specifically manifested as a programming speed and an erasing speed being fast, so as to improve the performance of the ferroelectric 3D NAND flash device, thereby matching the increasingly high requirements of users on the 3D NAND flash device.

[0067] Moreover, in the ferroelectric 3D NAND flash device provided in the embodiments of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, the ferroelectric 3D NAND flash device is manufactured by first manufacturing the channel layer and then manufacturing the ferroelectric layer, so as to prevent the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing in the manufacturing process of the channel layer, and the phenomenon of affecting the storage function of the 3D NAND flash device.

[0068] Optionally, in an embodiment of the present application, the ferroelectric layer is a single-layer ferroelectric film, and specifically, the single-layer ferroelectric film can be a hafnium-zirconium-oxygen film.

[0069] In another embodiment of the present application, the ferroelectric layer further includes a silicon dioxide layer located on the surface of the single-layer ferroelectric film away from the channel layer, that is, the ferroelectric layer includes the single-layer ferroelectric film and the silicon dioxide layer arranged away from the channel layer, so as to use the silicon dioxide layer to play a transition and isolation role between the channel layer and the single-layer ferroelectric film, to prevent excessive leakage current from being generated between the channel layer and the single-layer ferroelectric film, and at the same time, use the thermal expansion coefficient of the silicon dioxide layer to induce the single-layer ferroelectric film to form a ferroelectric phase.

[0070] On the basis of any of the above embodiments, in an embodiment of the present application, the thickness of the ferroelectric layer is in a range of 8 nm to 12 nm, and the present application does not limit this, which is specifically determined according to the situation.

[0071] On the basis of any of the above embodiments, in an embodiment of the present application, the back gate layer is made of a metal material capable of inducing the ferroelectric layer to form a ferroelectric phase, for example, tungsten or titanium nitride, so as to ensure that the back gate layer can conduct electricity, and at the same time, the thermal expansion coefficient of the back gate layer can induce the ferroelectric film to form a ferroelectric phase. It should be noted that the back gate layer functions as an electrode plate for the polarization of the ferroelectric layer when the 3D NAND memory device specifically works, and is used to add a programming voltage or an erasing voltage, so as to realize the ferroelectric polarization flipping of the ferroelectric layer.

[0072] Correspondingly, the application further provides an operating method of the 3D NAND flash memory device, which is applied to the 3D NAND flash memory device provided in any of the above embodiments, and specifically, the 3D NAND flash memory device comprises a plurality of memory cells, and the operating method comprises at least one of the following:

[0073] As shown in FIG. 4, when the read operation is performed on the 3D NAND flash memory device, the gate G of the memory cell to be read in the 3D NAND flash memory device is controlled to apply a read voltage V RD , the gate G of other memory cells in the same channel hole is controlled to apply a pass voltage V PS , and the drain D of each of the memory cells in the same channel hole is controlled to apply a detection voltage R BL , so as to detect whether the memory cell to be read is turned on, while the source S of each of the memory cells in the same channel hole is controlled to be grounded GND, and the back gate is floating. Figure 2 As shown in FIG. 5, when the programming operation is performed on the 3D NAND flash memory device, the gate G of the memory cell to be programmed in the 3D NAND flash memory device is controlled to apply a programming voltage V PRG , the back gate is grounded GND, and other electrodes are floating (that is, the gate G of other memory cells is floating, and the drain D and the source S of each of the memory cells are also floating).

[0074] Figure 3 As shown in FIG. 6, when the erasing operation is performed on the 3D NAND flash memory device, the gate G of the memory cell to be erased in the 3D NAND flash memory device is controlled to be grounded GND, the back gate is controlled to apply an erasing voltage V ERS , and the source S and the drain D of each of the memory cells are floating.

[0075] As shown in FIG. 7, when the programming operation is performed on the 3D NAND flash memory device, if it is required to erase a plurality of memory cells at the same time, the gate of all the memory cells to be erased is grounded GND, the back gate is controlled to apply an erasing voltage V ERS , and the source S and the drain D of each of the memory cells are floating. Figure 4

[0076] As shown in FIG. 7, when the programming operation is performed on the 3D NAND flash memory device, if it is required to erase a plurality of memory cells at the same time, the gate of all the memory cells to be erased is grounded GND, the back gate is controlled to apply an erasing voltage V ERS , and the source S and the drain D of each of the memory cells are floating. Figure 4

[0077] In summary, the ferroelectric 3D NAND flash memory device provided in the embodiments of the application uses a ferroelectric layer as a charge storage layer, and the ferroelectric material has a relatively fast flipping speed under an electric field, so that the operating speed of the ferroelectric 3D NAND flash memory device provided in the embodiments of the application is relatively fast, specifically, the programming speed and the erasing speed are fast, so as to improve the performance of the ferroelectric 3D NAND flash memory device, thereby matching the increasingly high requirements of users on the 3D NAND flash memory device. ​

[0078] Further, in the ferroelectric 3D NAND flash memory device provided by the embodiment of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, the ferroelectric 3D NAND flash memory device is manufactured by first manufacturing the channel layer and then manufacturing the ferroelectric layer, thereby preventing the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing in the manufacturing process of the channel layer, and preventing the phenomenon of affecting the storage function of the 3D NAND flash memory device from occurring.

[0079] In addition, the embodiment of the present application further provides a manufacturing method of a ferroelectric 3D NAND flash memory device, as shown in the figure, the manufacturing method comprises the following steps: Figure 5

[0080] S1: as shown in the figure, a substrate 10 is provided, and the substrate 10 is a silicon substrate. Figure 6

[0081] S2: as shown in the figure, a stack structure 20 is manufactured on the first surface of the substrate 10, the stack structure 20 comprises a plurality of gate dielectric oxide layers 21 and gate electrode layers 22 which are arranged in a staggered manner along the direction perpendicular to the plane in which the substrate is located, the gate dielectric oxide layer 21 is an isolation oxide layer, which can be a silicon dioxide layer, and the gate electrode layer 22 is a metal layer, such as a tungsten metal layer, but the present application does not make any limitation in this regard, and the specific implementation is determined according to the actual situation. Figure 7

[0082] S3: as shown in the figure, a channel hole 23 is manufactured through the stack structure 20, the channel hole 23 extends into the first surface of the substrate 10, and the forming process of the channel hole is an etching process. Figure 8

[0083] S4: a first isolation layer is manufactured on the side wall of the channel hole.

[0084] Optionally, in an embodiment of the present application, manufacturing the first isolation layer on the side wall of the channel hole comprises:

[0085] as shown in the figure, the first isolation layer 30 is manufactured on the surface of the channel hole 23 and the surface of the stack structure 20 away from the substrate 10 by using atomic layer deposition, and the function of the first isolation layer is to isolate the metal gate (i.e. the gate electrode layer) and the channel layer formed subsequently. Figure 9

[0086] as shown in the figure, the first isolation layer 30 is etched to remove the part of the first isolation layer 30 located at the bottom of the channel hole 23 and the part of the first isolation layer 30 located on the surface of the stack structure 20 away from the substrate 10, so as to ensure that the channel layer manufactured subsequently can be in communication with the substrate. Figure 10

[0087] ​​​​​​Based on the above embodiments, in one embodiment of this application, after the first isolation layer is fabricated, the method further includes: ion implantation of the substrate through the channel hole, so that the substrate portion located at the bottom of the channel hole forms an ohmic contact with the subsequently formed channel layer with low contact resistance. However, this application does not limit this, and it depends on the specific circumstances.

[0088] Specifically, in one embodiment of this application, the first isolation layer may be a silicon dioxide layer, an aluminum dioxide layer, or a high-k oxide such as hafnium dioxide. This application does not limit this, and it depends on the specific circumstances.

[0089] S5: Sequentially fabricate a channel layer, a ferroelectric layer, a back gate layer covering the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole.

[0090] Specifically, in one embodiment of this application, the sequential fabrication of a channel layer, a ferroelectric layer, a back gate layer covering the surface of the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole includes:

[0091] like Figure 11 As shown, a channel layer 40 is fabricated covering the surface of the first isolation layer 30, the bottom of the channel hole, and the surface of the stacked structure 20 away from the substrate 10;

[0092] like Figure 12 As shown, a ferroelectric layer 50 is fabricated to cover the surface of the channel layer 40;

[0093] like Figure 13 As shown, a back gate layer 60 is fabricated to cover the surface of the ferroelectric layer 50 away from the channel layer 30;

[0094] like Figure 14 As shown, a filling layer 70 is fabricated to cover the surface of the back gate layer 60 away from the ferroelectric layer 50 and to fill the remaining space of the channel hole. Optionally, the filling layer 70 is an oxide layer, such as a silicon dioxide layer, to fill the channel hole and provide support.

[0095] like Figure 15 As shown, the portions of the channel layer 40, the ferroelectric layer 50, the back gate layer 60, and the fill layer 70 located on the surface of the stacked structure 20 away from the substrate 10 are removed.

[0096] Optionally, in an embodiment of the present application, the channel layer covering the surface of the first isolation layer, the bottom of the channel hole and the surface of the stack structure away from the substrate side is prepared by chemical vapor deposition, and specifically, the channel layer is a channel film, and the material thereof can be polysilicon or other channel materials such as IGZO (indium gallium zinc oxide) and thin-layer molybdenum disulfide (MoS2), which are not limited in the present application and are determined according to actual conditions.

[0097] It should be noted that when the material of the channel layer is polysilicon material, the polysilicon material layer needs to be annealed after growth to ensure that the deposited polysilicon material layer can form a polysilicon film with a proper grain size.

[0098] On the basis of any of the above embodiments, in an embodiment of the present application, the ferroelectric layer is a single-layer ferroelectric film. In the present embodiment, the ferroelectric layer covering the surface of the channel layer is prepared by growing a ferroelectric layer on the surface of the channel layer by atomic layer deposition, and optionally, the thickness of the ferroelectric layer is 8 nm to 12 nm, which is not limited in the present application and is determined according to actual conditions.

[0099] In another embodiment of the present application, the ferroelectric layer includes a single-layer ferroelectric film and a silicon dioxide layer arranged away from the channel layer, so as to use the silicon dioxide layer to play a transition and isolation role between the channel layer and the single-layer ferroelectric film, and meanwhile, use the thermal expansion coefficient of the silicon dioxide layer to induce the single-layer ferroelectric film to form a ferroelectric phase. In the present embodiment, the ferroelectric layer covering the surface of the channel layer is prepared by:

[0100] first, a silicon dioxide layer is grown on the surface of the channel layer by atomic layer deposition, and optionally, the thickness of the silicon dioxide layer is 1 nm to 3 nm, which is not limited in the present application and is determined according to actual conditions;

[0101] then, a ferroelectric layer is grown on the surface of the silicon dioxide layer by atomic layer deposition, and optionally, the thickness of the ferroelectric layer is 8 nm to 12 nm, which is not limited in the present application and is determined according to actual conditions.

[0102] On the basis of any of the above embodiments, in an embodiment of the present application, the back gate layer is made of a metal material that is easy to induce a ferroelectric film to form a ferroelectric phase, for example, tungsten or titanium nitride, so as to ensure that the back gate layer can conduct electricity and at the same time, the thermal expansion coefficient of the back gate layer can induce the ferroelectric film to form a ferroelectric phase.

[0103] Based on any of the above embodiments, in one embodiment of this application, removing the portion of the channel layer, the ferroelectric layer, the back gate layer, and the fill layer located on the side of the stacked structure away from the substrate includes: removing the portion of the channel layer, the ferroelectric layer, the back gate layer, and the fill layer located on the side of the stacked structure away from the substrate by chemical mechanical polishing. However, this application does not limit this and it depends on the specific circumstances.

[0104] S6: Fabricate an insulating layer covering the channel hole and the stacked structure to provide insulation. The insulating layer has a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer to facilitate the subsequent extraction of electrodes from the channel hole.

[0105] Optionally, in one embodiment of this application, an insulating layer is fabricated covering the channel via and the stacked structure. The insulating layer has a first via and a second via, wherein the first via exposes at least a portion of the surface of the channel layer, and the second via exposes at least a portion of the surface of the back gate layer, including:

[0106] like Figure 16 As shown, an insulating layer 80 is fabricated to cover the channel holes and the stacked structure. Optionally, the insulating layer 80 is a silicon dioxide layer to provide insulation.

[0107] like Figure 17 As shown, the insulating layer 80 is etched to form a first via 81 and a second via 82 in the insulating layer 80, wherein the first via 81 exposes at least a portion of the surface of the channel layer 40, and the second via 82 exposes at least a portion of the surface of the back gate layer 60.

[0108] S7: As Figure 18 As shown, a drain 91 electrically connected to the channel layer 40 through the first via and a back gate 92 electrically connected to the back gate layer 60 through the second via are fabricated.

[0109] Optionally, in one embodiment of this application, fabricating a drain electrically connected to the channel layer through the first via and a back gate electrically connected to the back gate layer through the second via includes:

[0110] A metal electrode layer is deposited, which covers an insulating layer and fills the first via and the second via;

[0111] Etching the metal electrode layer to reserve the part of the metal electrode layer in the first via and the second via, forming a drain electrode electrically connected with the channel layer through the first via and a back gate electrode electrically connected with the back gate layer through the second via.

[0112] To sum up, the manufacturing method of the ferroelectric 3D NAND flash device provided in the embodiments of the present application uses a ferroelectric layer as a charge storage layer, and the ferroelectric material has a faster flipping speed under an electric field, so that the operation speed of the ferroelectric 3D NAND flash device provided in the embodiments of the present application is faster, specifically, the programming speed and the erasing speed are faster, so as to improve the performance of the ferroelectric 3D NAND flash device, thereby matching the increasingly high requirements of users on the 3D NAND flash device.

[0113] Moreover, in the ferroelectric 3D NAND flash device provided in the embodiments of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, the ferroelectric 3D NAND flash device is manufactured by first manufacturing the channel layer and then manufacturing the ferroelectric layer, so as to prevent the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing in the manufacturing process of the channel layer, and the phenomenon of affecting the storage function of the 3D NAND flash device.

[0114] The embodiments in the specification are described in a progressive, or parallel, or progressive and parallel combination manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0115] It should be noted that in the description of the present application, it should be understood that the drawings and the description of the embodiments are illustrative but not limiting. The same reference numerals in the embodiments throughout the specification indicate the same structure. It should also be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such article or device. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the article or device including the element.

[0116] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A ferroelectric 3D NAND flash memory device, characterized in that, include: Substrate; A stacked structure located on the first surface of the substrate, the stacked structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately along a direction perpendicular to the plane of the substrate; A channel hole penetrating the stacked structure, the channel hole extending into a first surface of the substrate; The first isolation layer is located on the sidewall of the channel hole; A channel layer covering the first isolation layer and the bottom of the channel hole; Ferroelectric layer located on the surface of the channel layer; The back gate layer located on the surface of the ferroelectric layer; A filling layer to fill the remaining space in the channel holes; An insulating layer covering the channel hole and the stacked structure, the insulating layer having a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer; The drain is electrically connected to the channel layer through the first via, and the back gate is electrically connected to the back gate layer through the second via.

2. The 3D NAND flash memory device of claim 1, wherein, The ferroelectric layer is a single-layer ferroelectric thin film.

3. The 3D NAND flash memory device of claim 2, wherein, The ferroelectric layer also includes a silicon dioxide layer located on the surface of the monolayer ferroelectric thin film on the side away from the channel layer.

4. The 3D NAND flash memory device of claim 1, wherein, The back gate is made of a metallic material that can induce the ferroelectric layer to form a ferroelectric phase.

5. The 3D NAND flash memory device of claim 4, wherein, The back gate is made of tungsten or titanium nitride.

6. The 3D NAND flash memory device of claim 1, wherein, The channel layer is a polycrystalline silicon layer, an IGZO layer, or a thin molybdenum disulfide layer.

7. A method of operating a 3D NAND flash memory device, the method comprising: Applied to the 3D NAND flash memory device according to any one of claims 1-6, the 3D NAND flash memory device comprising a plurality of memory cells, the method of operation includes at least one of the following: When performing a read operation on the 3D NAND flash memory device, a read voltage is applied to the gate of the memory cell to be read in the 3D NAND flash memory device, a pass voltage is applied to the gate of other memory cells in the same channel, and a detection voltage is applied to the drain of each memory cell in the same channel to detect whether the memory cell to be read is conducting. At the same time, the source of each memory cell in the same channel is connected to zero potential and the back gate is floated. When performing a programming operation on the 3D NAND flash memory device, a programming voltage is applied to the gate of the memory cell to be programmed in the 3D NAND flash memory device, the back gate is connected to zero potential, and the other electrodes are floating. When performing an erase operation on the 3D NAND flash memory device, the gate of the memory cell to be erased in the 3D NAND flash memory device is controlled to be at zero potential, the back gate is applied with an erase voltage, and the source and drain are floating.

8. A method of fabricating a ferroelectric 3D NAND flash memory device, the method comprising: include: Provide substrate; A stacked structure is fabricated on the first surface of the substrate, the stacked structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately along a direction perpendicular to the plane of the substrate; A channel hole is formed through the stacked structure, the channel hole extending into a first surface of the substrate; A first isolation layer is formed on the sidewall of the channel hole; A channel layer, a ferroelectric layer, a back gate layer, and a fill layer that fill the remaining space of the channel hole are sequentially fabricated to cover the first isolation layer and the bottom of the channel hole. forming an insulating layer covering the channel hole and the stack structure, the insulating layer having a first through hole and a second through hole, wherein the first through hole exposes at least part of a surface of the channel layer, and the second through hole exposes at least part of a surface of the back gate layer; forming a drain electrode electrically connected to the channel layer through the first through hole, and a back gate electrode electrically connected to the back gate layer through the second through hole.

9. The method of manufacturing according to claim 8, wherein, sequentially forming a channel layer covering a surface of the first isolation layer and a bottom of the channel hole, a ferroelectric layer, a back gate layer, and a filling layer filling a remaining space of the channel hole, comprises: forming a channel layer covering a surface of the first isolation layer, a bottom of the channel hole, and a surface of the stack structure away from the substrate; forming a ferroelectric layer covering a surface of the channel layer; forming a back gate layer covering a surface of the ferroelectric layer away from the channel layer; forming a filling layer covering a surface of the back gate layer away from the ferroelectric layer, and filling a remaining space of the channel hole; removing a part of the channel layer, the ferroelectric layer, the back gate layer, and the filling layer located on a surface of the stack structure away from the substrate.

10. The method of manufacturing according to claim 8, wherein, After the first isolation layer is formed, before the channel layer is formed, the method further comprises: ion implantation on the substrate through the channel hole.

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