Three-dimensional chip architecture

Abstract

A three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer. The integrated circuit may also include: a plurality of random access memory cores stacked on top of the interposer; and a plurality of computing cores. The plurality of computing cores may be stacked on top of respective ones of the plurality of random access memory cores such that the plurality of computing cores may be in electrical communication with the respective ones of the plurality of random access memory cores.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 514,970, filed on July 21, 2023, and U.S. Non-Provisional Application No. 18 / 743,518, filed on June 14, 2024, the entire contents of both applications are incorporated herein by reference. Technical Field

[0003] Examples of the present disclosure generally relate to methods, apparatus, and computer program products for providing a three-dimensional architecture for a computer chip. Background Art

[0004] For integrated circuits, electronic circuits can be fabricated on semiconductor dies, which can be formed into chips or chiplets. Each chip or chiplet can include one or more processing elements capable of performing a specified function on a given set of data or information.

[0005] Generally, the more processing elements a chip has, the greater the processing power of the chip. However, conventional techniques for increasing the processing power of a chip are limited. For example, in a two-dimensional approach, additional processing elements can be added along the width and length dimensions of a die. This two-dimensional approach is often limited by the size constraints (e.g., area) of the die, especially for microelectronics. Summary of the invention

[0006] The present invention summary is provided to introduce a series of concepts in a simplified form, which are further described in the following detailed description. The present invention summary is not intended to limit the scope of the claimed subject matter. The application described in more detail below largely satisfies the aforementioned needs.

[0007] A three-dimensional application-specific integrated circuit architecture is described herein. An integrated circuit may include a computing core that may be stacked on top of a random access memory core. In some cases, the stack may include a computing core stacked on top of another computing core. The stack may provide the computing core and the random access memory core with the ability to communicate with short, low latency and / or low attenuation. The stack may also allow for minimization of the area footprint of the integrated circuit.

[0008] In this regard, the examples of the present disclosure may provide integrated circuits with higher memory per unit area and increased computational processing (e.g., Tera operations per second (TOPS)). For example, in some examples, the integrated circuit architecture in the examples of the present disclosure may increase TOPS by at least four times (e.g., by utilizing a three-dimensional (3D) topology / configuration), and in some examples, may increase memory (e.g., static random-access memory (SRAM)) capacity by eight to ten times. In addition, the examples of the present disclosure may improve the latency and power efficiency of the integrated circuit system between core particles or chips. For example, by introducing another dimension as a degree of freedom, the communication network in such an architecture may provide lower latency than a traditional 2D topology.

[0009] In one exemplary aspect of the present disclosure, an integrated circuit (IC) is provided. The integrated circuit may include an interposer. The integrated circuit may also include: a plurality of random access memory core particles, the plurality of random access memory core particles stacked on top of the interposer; and a plurality of computing core particles. The plurality of computing core particles may be stacked on top of corresponding random access memory core particles in the plurality of random access memory core particles, so that the plurality of computing core particles may be in electrical communication with corresponding random access memory core particles in the plurality of random access memory core particles.

[0010] In another example aspect of the present disclosure, a method is provided. The method may include: sending at least one electrical signal from a computing core particle. The method may also include: transmitting the at least one electrical signal to a random access memory core particle. The computing core particle may be stacked on top of the random access memory core particle to form a three-dimensional stacked integrated circuit.

[0011] In another exemplary aspect of the present disclosure, a computer program product is provided. The computer program product may include at least one non-transitory computer-readable medium, the at least one non-transitory computer-readable medium including computer executable program code instructions stored therein. The computer executable program code instructions may include program code instructions configured to send at least one electrical signal from a computing core particle. The computer program product may also include program code instructions configured to transmit the at least one electrical signal to a random access memory core particle. The computing core particle may be stacked on top of the random access memory core particle to form a three-dimensional stacked integrated circuit.

[0012] In some examples, the plurality of random access memory core particles may include static random access memory (SRAM) core particles. In some examples, the plurality of computing core particles may include a plurality of processing elements (PEs). In some examples, the IC may include a plurality of high bandwidth memories (HBMs) stacked on top of the interposer. In some examples, the IC may include a set of core particles (e.g., network core particles) stacked on top of the interposer. The core particles may include, for example, functions including, but not limited to, networking, input / output (I / O), and / or a network interface card or a network interface controller (NIC), etc.

[0013] In some examples, the plurality of random access memory cores are configured to electrically communicate with each other via an interposer. In some examples, more than one of the plurality of computing cores are stacked on top of a random access memory core of the plurality of random access memory cores. In some examples, one or more of the plurality of random access memory cores are configured to electrically communicate with other random access memory cores of the plurality of random access memory cores via an interposer.

[0014] In some examples, the IC may further include: a substrate layer, wherein the interposer is stacked on top of the substrate layer; and at least one main central processing unit (CPU) stacked on top of the substrate layer, wherein the at least one main CPU is in electrical communication with the interposer via the substrate layer. In some examples, the at least one main CPU includes two main CPUs.

[0015] In some examples, the IC may also include a set of networks and CPU cores, wherein the set of networks and CPU cores are stacked on top of the interposer. In some examples, the IC may also include a CPU, which is stacked on top of the interposer. In some examples, the IC may also include: another random access memory, which is stacked on top of the interposer; and a main CPU, which is stacked on top of the other random access memory, wherein the main CPU is in electrical communication with the other random access memory. In some examples, the other random access memory is configured to electrically communicate with the plurality of random access memory cores via the interposer.

[0016] There has thus been outlined, rather broadly, certain embodiments of the disclosure in order that the detailed description of those embodiments may be better understood, and in order that the present contribution to the art may be better appreciated.

[0017] Additional advantages will be partially described in the following description or can be learned through practice. These advantages will be realized and obtained through the elements and combinations particularly pointed out in the appended claims. It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and not restrictive, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to facilitate a more complete understanding of the present application, reference is now made to the accompanying drawings, in which like elements are designated by like numerals. These drawings should not be construed as limiting the present application and are intended for illustration only.

[0019] Figure 1 A conventional chip or die is depicted.

[0020] Figure 2 A chip or die implementing a three-dimensional architecture according to an example of the present disclosure is depicted.

[0021] Figure 3 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0022] Figure 4 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0023] Figure 5 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0024] Figure 6 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0025] Figure 7 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0026] Figure 8 A chip or die implementing a three-dimensional architecture according to another example of the present disclosure is depicted.

[0027] Fig. 9 A process according to an example of the present disclosure is depicted.

[0028] Fig.10 A device capable of implementing a chip or a die according to examples of the present disclosure is depicted. DETAILED DESCRIPTION

[0029] A detailed description of various illustrative embodiments will be discussed with reference to the various figures, embodiments and aspects herein. Although this description provides detailed examples of possible implementations, it should be understood that the details are intended to be exemplary and therefore do not limit the scope of this application.

[0030] References in this specification to "one embodiment," "an embodiment," "one or more embodiments," or "an aspect," etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, the term "embodiment" in various places in this specification does not necessarily refer to the same embodiment. That is, various features are described that may be exhibited by some embodiments but not by other embodiments.

[0031] It should be understood that any or all of the systems, methods, and processes described herein may be implemented in the form of computer-executable instructions (e.g., program code) stored on a computer-readable storage medium, which, when executed by a machine such as a computer, server, or transmission device, executes and / or implements the systems, methods, and processes described herein. Specifically, any of the above steps, operations, or functions may be implemented in the form of such computer-executable instructions. Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, but such computer-readable storage media do not include signals. Computer-readable storage media may include, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other physical medium that can be used to store the desired information and that can be accessed by a computer.

[0032] As defined herein, “computer-readable storage media” referring to non-transitory physical or tangible storage media (eg, volatile or non-volatile memory devices) may be distinguished from “computer-readable transmission media” referring to electromagnetic signals.

[0033] Some manufacturers may try to maximize the processing power and storage capacity of an application specific integrated circuit (ASIC) by including more processing components / storage components on a given chip. This may also have cost advantages because a smaller chip size can provide more die cut or etched from a single wafer. However, ASIC size is usually limited based on reticle limits, which are the maximum area of ​​a chip that can be manufactured. Manufacturers may not be able to overcome reticle limits by increasing the width and / or length dimensions of the chip. These larger full reticle size chips may be prone to defects. This may result in lower yields and increase chip costs. However, these problems can be solved by using smaller chip sizes in specific technologies (e.g., microelectronics). According to the present disclosure, a chip may include a three-dimensional architecture. The chip may include computing cores configured to perform various processing functions. These computing cores may be stacked on top of random access memory cores. Similarly, other components of the chip may be stacked on an interposer or may also be stacked on a memory to enable communication between non-stacked entities. The stack can facilitate high-speed, low-latency communication between memory and computing cores, which can enable more powerful processing capabilities for the chip.

[0034] Figure 1 A conventional chip 100 is depicted. The chip 100 may include: a computing core 105 capable of performing various processes; a network (NW) core 110 capable of managing communications between internal entities of the chip 100 and external entities; and a high bandwidth memory (HBM) core 115 configured to store data (e.g., store data as multiple bits). These components may be placed on an interposer 120. The interposer 120 may facilitate electrical communication between various components on the interposer 120. This configuration of various components that electrically communicate with each other via an interposer is generally referred to as a 2.5-dimensional (2.5D) configuration.

[0035] Chips that include 2.5D configurations are often limited in capability due in part to the communication paths imposed by the configuration. Each component positioned on an interposer may transmit communications to other components on the interposer via the interposer. The communication path length and the material of the interposer may cause communication delays and communication attenuation. Such lags may also impose limitations on the processing capabilities of the chip, especially in examples where multiple components may need to communicate or collaborate with each other to complete a task.

[0036] Furthermore, in examples where the chip 100 is also an integrated circuit, a main CPU 125 may also be included in the chip 100. However, the main CPU 125 cannot typically be placed on top of the interposer 120, and therefore an additional substrate layer 130 (e.g., a printed circuit board (PCB) layer) may be implemented, wherein the main CPU 125 and the interposer 120 are placed on top of the substrate layer 130. This may further result in communication latency, as the main CPU 125 communicates with various components of the interposer 120 by sending communications to the substrate layer 130, which travel to the interposer 120 and then to specific components (e.g., the computing core 105).

[0037] Figure 2 Depicted is a chip 200 that implements a 3D configuration according to an example of the present disclosure. In some examples, the chip 200 may be a core particle that may be configured to operate with other core particles (not shown) to form a chip. In some examples, the chip 200 may be an ASIC. In some examples, the chip 200 may be configured to perform a machine learning (ML) process and / or an artificial intelligence (AI) process. In some other examples, the chip 200 may be configured to perform other applications (e.g., video transcoding, etc.).

[0038] Chip 200 may include substrate 205. Substrate 205 may be a portion of semiconductor material (e.g., a layer) that may support other components of chip 200. For example, substrate 205 may be composed of silicon. Substrate 205 may form a plane in which substrate 205 may include a length and a width that are substantially greater than the thickness of the substrate. Substrate 205 may be configured to accommodate, include, or contain one or more circuit components along a given surface.

[0039] The chip 200 may also include an interposer 210. The interposer 210 may be disposed on top of the substrate 205. The interposer 210 may facilitate electrical communication from the substrate 205 to components on the interposer 210, or facilitate electrical communication between different components on the interposer 210. The interposer 210 may be composed of a semiconductor material (e.g., silicon) and may include electrical connections (e.g., on a top surface) that are capable of carrying electrical connections to and from different components on the top of the interposer 210. The interposer 210 may form a plane in which the interposer 210 may include a width and a length that are substantially greater than the thickness of the interposer. In addition, the interposer plane may be substantially parallel to the substrate plane. In some examples, the interposer length, width, or both may be less than the length and / or the corresponding width of the substrate 205.

[0040] One or more bottom cores (e.g., random access memory cores 215) may be disposed on top of the interposer 210. The random access memory core 215 may be electrically connected to the interposer 210 (e.g., via the interposer top surface and the memory bottom surface), such that the random access memory core 215 is configured to send electrical communications to other components on the interposer 210, other components on the substrate 205, or both, via the interposer 210, and receive electrical communications from other components on the interposer, other components on the substrate, or both. In some examples, the random access memory core 215 may be a static random access memory (SRAM), such that data stored by the SRAM is statically maintained. In some cases, the random access memory core 215 may be connected to a DRAM, and may include in-memory compute, near memory, and / or network-on-chip, etc.

[0041] The chip 200 may also include one or more computing cores 220. The computing core 220 may be disposed on top of the random access memory core 215. The computing core 220 may be in electrical communication with the random access memory core 215 on which the computing core is disposed. For example, the computing core 220 may include electrical connections on its bottom surface that may be coupled to electrical connections on the top surface of the corresponding random access memory core 215. Thus, the computing core 220 may be configured to be in electrical communication with its corresponding random access memory core 215. In some examples, the computing core 220 may be configured to be in electrical communication with the following components: other components on the intermediary 210, such as other computing cores 220 (e.g., electrical communication is transferred from the computing core 220 to its corresponding random access memory core 215, to the intermediary 210, to another random access memory core 215, and to another computing core 220); and / or other components on the substrate 205 (e.g., a CPU), etc. In some examples, the electrical connection between the computing core 220 and the corresponding random access memory core 215 can be direct, such as through bump bonds or electrical pins. In some examples, the electrical connection can be indirect, such as by implementing electrical leads between the computing core 220 and the corresponding random access memory core 215.

[0042] Each computing core 220 may be configured to include one or more processing elements 221. The processing element 221 may be configured to receive one or more data sets and perform different processing operations on the one or more data sets. For example, the processing element 221 may be configured to perform arithmetic functions (e.g., multiplication, derivation, and / or addition, etc.) on one or more data sets. In some examples, the processing element 221 may be configured to perform logical functions (e.g., and, or, and / or or not (nor), etc.) on one or more data sets. In some examples, the processing element 221 may include functions specific to the processing element (e.g., each processing element may be different from each other). In some examples, the processing element 221 may receive one or more data sets from a specific circuit component (e.g., another processing element), process the data, and output the processing results to another specific circuit component (e.g., another specific circuit element) to form a processing pipeline. In some examples, the computing core 220 may include a predetermined number of processing elements 221 (e.g., 32 processing elements, 16 processing elements, etc.).

[0043] More than one computing core 220 may be stacked on top of a given random access memory core 215. For example, Figure 2 As shown, a random access memory core 215 may include two or more computing cores 220 stacked on the random access memory core 215. In some examples, each computing core 220 on a corresponding random access memory core 215 may directly communicate electrically with another computing core 220 on the random access memory core 215 via the corresponding random access memory core 215, so that the electrical communication may not be forwarded through the intermediary 210.

[0044] The chip 200 may also include one or more high bandwidth memory (HBM) cores 225. In some examples of the present disclosure, the HBM core 225 may be referred to herein as HBM 225. The HBM 225 may provide additional storage capacity of the chip 200, for example, for AI model / inference training, etc. The HBM 225 may be disposed on the interposer 210. For example, the HBM 225 may be in direct contact with the interposer 210, so that the bottom surface of the HBM 225 may contact the top surface of the interposer 210. The HBM 225 may be in electrical communication with the interposer 210. For example, the bottom surface of the HBM 225 may include electrical connections that may be coupled to corresponding electrical connections of the top surface of the interposer 210. In some examples, these electrical connections may include bump bonding and / or electrical pins, etc. In some examples, HBM 225 may include second generation of high bandwidth memory (HBM2), second generation evolutionary high bandwidth memory (HBM2E), third generation of high bandwidth memory (HBM3), fourth generation of high bandwidth memory (HBM4), and / or HBM with in-memory processing, etc.

[0045] The chip 200 may also include one or more core particles 230. The core particles 230 may include, for example, functions including, but not limited to, networking, input / output (I / O), and / or a network interface card or network interface controller (NIC), etc. The core particles 230 may be disposed on the intermediary 210. For example, the core particles 230 may be in direct contact with the intermediary 210, so that the bottom surface of the core particles 230 may contact the top surface of the intermediary 210. The core particles 230 may be in electrical communication with the intermediary 210. For example, the bottom surface of the core particles 230 may include electrical connections that may be coupled to corresponding electrical connections on the top surface of the intermediary 210. In some examples, these electrical connections may include bump bonding and / or electrical pins, etc. The core particles 230 may be configured to facilitate communication between various components of the chip 200. For example, in some examples, the core particles 230 may include on-chip network logic. For example, the core particles 230 may manage the processing pipeline of the processing elements within the computing core particles 220 or between the computing core particles 220. In some examples, cored-in 230 may be configured to facilitate communication between chip 200 and external components.

[0046] The chip may also include one or more main CPUs 235. The main CPUs 235 may be disposed on the substrate 205. For example, the main CPUs 235 may be in direct contact with the substrate 205, such that the bottom surface of the main CPUs 235 may contact the top surface of the substrate. The main CPUs 235 may be in electrical communication with the substrate 205. For example, the bottom surface of one or more main CPUs 235 may include electrical connections that may be coupled to corresponding electrical connections on the top surface of the substrate 205. In some examples, these electrical connections may include bump bonds and / or electrical pins, etc. The main CPUs 235 may include logic for managing various other components of the chip 200. For example, the main CPUs 235 may be configured to perform artificial intelligence, machine learning, and / or video processing, etc.

[0047] The chip 200 may utilize a 3D architecture, at least in relation to the stacking of compute cores 220 on random access memory cores 215, and similarly in relation to the stacking of random access memory cores 215 on interposer 210. The stacking of compute cores 220 on top of random access memory cores 215 may allow for very low latency communications between compute cores 220 on random access memory cores 215, which may enhance the processing capabilities of the chip 200. Additionally, the implementation of various components on interposer 210 (e.g., in a 2.5D architecture) may further enhance the low latency on the chip 200. For example, the various components may include embedded silicon bridges, embedded metal connectors, passive components, capacitors, and / or core-to-core physical layers, etc.

[0048] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Various other examples of chips implementing 3D architectures according to the present disclosure are depicted. For example, Figure 3 Describes the Figure 2 200 in 3D configuration, although the chip has two main CPUs 235 disposed on substrate 205. Each main CPU 235 can be in electrical communication with other entities of chip 300 (e.g., via substrate 205). Thus, each main CPU 235 can share logical instructions (e.g., for the same program / application), or each main CPU 235 can be different from each other (e.g., hosting different programs / applications for execution).

[0049] Figure 4 A chip 400 implementing a 3D architecture according to an example of the present disclosure is depicted. The chip 400 may have Figure 2 and Figure 3The chip 200 and the chip 300 are similar in 3D configuration to those depicted in FIG. 400 include a network and a main CPU 440. The chip and the main CPU 440 may be included in the reference Figure 2 and Figure 3 The combination of hardware and logic in the described core particle 230 and main CPU 235. The core particle and main CPU 440 can manage or facilitate communication between various entities of the chip 400 (for example, managing the processing pipeline within the computing core particle 220 and between each computing core particle), and communication between the chip 400 and external entities. The core particle and main CPU 440 can also include main processing logic (for example, one or more executable programs / one or more applications), and can instruct or manage other entities of the chip 400 to execute the logic. The core particle and main CPU 440 can be set at the intermediary 210 and can communicate electrically with the intermediary 210. Therefore, the core particle and main CPU 440 can communicate electrically with other entities of the chip 400 via the intermediary 210.

[0050] Figure 5 A chip 500 implementing a 3D architecture according to an example of the present disclosure is depicted. The chip 500 may have the same Figure 2 However, chip 500 may include a chip 200 disposed on interposer 210 instead of Figure 2 The main CPU core 235 (also referred to herein as the main CPU 235) on the substrate layer is depicted. The main CPU 235 can be in electrical communication with the intermediary 210 so that the main CPU 235 can communicate with other entities of the chip 500 via the intermediary 210. The chip 500 can also include a double data rate (DDR) memory 545. The DDR memory 545 can be disposed on top of the intermediary 210 so that the DDR memory 545 is in electrical communication with the intermediary 210. The DDR memory 545 can be configured to be in electrical communication with other entities of the chip 500 (e.g., the main CPU 235). The DDR memory 545 can include a volatile memory that can be configured to read data based on a memory clock signal. In some examples, the DDR memory 545 can include a Double Data Rate 2 (DDR2) memory, a Double Data Rate 3 (DDR3) memory, a Double Data Rate 4 (DDR4) memory, a Double Data Rate 5 (DDR5) memory, and / or a Low-Power Double Data Rate (LPDDR), etc. The DDR memory 545 can facilitate the overall system storage of the chip 500.

[0051] Figure 6 A chip 600 implementing a 3D architecture according to an example of the present disclosure is depicted. The chip 600 may have the same Figure 5 600. However, the chip 600 may also include a main CPU 235 disposed on the RAM core 215. The main CPU 235 may be in electrical communication with a corresponding RAM core 215 (e.g., via a bottom surface of the main CPU 235 and a top surface of the RAM core 215), and similarly, the RAM core 215 may be in electrical communication with the interposer 210 (e.g., via a bottom surface of the RAM core 215 and a top surface of the interposer 210). Thus, the main CPU 235 may be configured to be in electrical communication with other entities of the chip 600 (e.g., an electrical signal from the main CPU 235 may be sent to the RAM core 215, to the interposer 210, and then to another entity of the chip 600).

[0052] Figure 7 A chip 700 implementing a 3D architecture according to an example of the present disclosure is depicted. The chip 700 may have the same Figure 5 The chip 500 described above may be configured similarly. The chip may include two (or more) main CPUs 235 disposed on an intermediary 210. Each main CPU 235 may be in electrical communication with other entities of the chip 700 (e.g., via the intermediary 210). Thus, each main CPU 235 may share logic instructions (e.g., for the same program), or each main CPU may be different from each other (e.g., hosting different programs for execution).

[0053] Figure 8 Depicted is a chip 800 implementing a 3D architecture according to an example of the present disclosure. The chip 800 may have the same Figure 7The chip 800 may also include a main CPU 235 disposed on a corresponding random access memory core 215. The main CPU 235 may be in electrical communication with the corresponding random access memory core 215 (e.g., via a bottom surface of the main CPU 235 and a top surface of the random access memory core 215), and similarly, the random access memory core 215 may be in electrical communication with the intermediary 210 (e.g., via a bottom surface of the random access memory core 215 and a top surface of the intermediary 210). Thus, the main CPU 235 may be configured to communicate electrically with other entities of the chip 800 (e.g., an electrical signal from the main CPU 235 may be sent to the random access memory core 215, to the intermediary 210, and then to another entity of the chip 800). Thus, each main CPU 235 may share logical instructions (e.g., for the same program / application), or each main CPU may be different from each other (e.g., hosting different programs / applications for execution).

[0054] Although reference Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The various chips described provide specific examples, but the disclosure provided herein is not limited to these examples. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Various numbers of chip components are depicted, but in other examples, a chip may include fewer or more of those components that implement the architecture described herein. For example, consider Figure 2 , the chip 200 may include fewer or more HBM3 cores 225 than the 12 HBM3 cores 225 depicted. The 3D stacking architecture can enable the integration of different functions (e.g., cryptographic technology, and / or secure input / output (IO), etc.) while achieving stronger performance. The 3D stacking architecture can also increase the memory capacity and / or processing power of the chip. In addition, in some examples, the various chip components of the chip may include Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The positions shown in FIG. 1 are different than those shown in FIG.

[0055] Fig. 9The process 900 according to an example of the present disclosure is depicted. The process 900 may be implemented by a chip, for example, a chip that is respectively Figures 2 to 8 200, chip 300, chip 400, chip 500, chip 600, chip 700, chip 800 in. In step 905, at least one electrical signal from a computing core (e.g., computing core 220) may be sent. In step 910, the at least one electrical signal may be transmitted or sent from the computing core to a random access memory core (e.g., random access memory core 215), wherein the computing core may be stacked on top of the random access memory core to form a three-dimensional stacked integrated circuit. In some examples, the bottom surface of the computing core may contact the top surface of the random access memory core. In some examples, the bottom surface of the computing core may include electrical connections that are coupled to corresponding electrical connections on the top surface of the random access memory core. In some examples, the three-dimensional stacking may include placing the computing core on the random access memory core (or vice versa) so that the width dimension / length dimension of the computing core may be configured / extended in parallel with the width dimension / length dimension of the random access memory core. In some other examples, the at least one electrical signal transmission may be transmitted or sent from the random access memory to another component of the integrated circuit via the interposer. For example, the bottom surface of the random access memory core may include electrical connections that are coupled to corresponding electrical connections on the top surface of the interposer. In some examples, the other component may be stacked on the interposer. In some examples, the other component of the integrated circuit may be referred to as a second component of the integrated circuit in this article. In some examples, the other component may include another random access memory core, a main CPU, a networking core, or a high bandwidth memory core. In some examples, another random access memory core may be referred to as a second random access memory core in this article.

[0056] Fig.10 is a block diagram of an exemplary computing device 30 that can incorporate the chips described herein, such as in Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The chips 200, 300, 400, 500, 600, 700 and 800 in FIG. In an example, the computing device 30 may be a server or a communication device configured to provide AI functions and / or ML functions.

[0057] like Fig.10As shown, computing device 30 may include chip 32, non-removable memory 44, removable memory 46, speaker / microphone 38, keypad 40, camera 54, display / touchpad / pointer 42, power supply 48, global positioning system (GPS) chipset 50, and other peripherals 52. Computing device 30 may also include communication circuitry, such as transceiver 34 and transmit / receive element 36. It will be appreciated that computing device 30 may include any sub-combination of the foregoing elements while remaining consistent with an embodiment.

[0058] The chip 32 may be an integrated circuit, such as an ASIC. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 200, chip 300, chip 400, chip 500, chip 600, chip 700, chip 800 in the example. Chip 32 may have various functions designed for computing device 30. For example, chip 32 may be configured to perform AI training and / or ML training, process output from an AI model / ML model, and / or inference and video processing, etc. In other examples, chip 32 may perform other functions or tasks.

[0059] In some examples, the chip 32 can execute computer executable instructions stored in a memory (e.g., non-removable memory 44 and / or removable memory 46) of the computing device 30 to perform various desired functions of the computing device 30. For example, the chip 32 can perform signal encoding, data processing, power control, input / output processing, and / or any other function that enables the computing device 30 to operate in a wireless or wired environment. In some examples, the chip 32 can run application layer programs (e.g., browsers) and / or radio access layer (radio access-layer, RAN) programs and / or other communication programs. In some examples, the chip 32 can also perform security operations, such as authentication, security key protocols, and / or cryptographic operations, etc., at the access layer and / or application layer, for example.

[0060] Chip 32 may be coupled to communication circuitry (eg, transceiver 34 and transmit / receive element 36). In some examples, chip 32 may control the communication circuitry by executing computer-executable instructions to enable computing device 30 to communicate with other computing devices via a network to which it is connected.

[0061] The send / receive element 36 can be configured to send signals to other computing devices or network devices, or receive signals from other computing devices or network devices. For example, in one embodiment, the send / receive element 36 can be an antenna configured to send and / or receive radio frequency (RF) signals. The send / receive element 36 can support various networks and air interfaces, such as wireless local area network (WLAN), wireless personal area network (WPAN) and cellular, etc. In another embodiment, the send / receive element 36 can be configured to send and receive both RF signals and optical signals. It will be understood that the send / receive element 36 can be configured to send and / or receive any combination of wireless signals or wired signals.

[0062] The transceiver 34 may be configured to modulate signals to be transmitted by the transmit / receive element 36 and to demodulate signals received by the transmit / receive element 36. As mentioned above, the computing device 30 may have multi-mode capabilities. Thus, the transceiver 34 may include multiple transceivers to enable the computing device 30 to communicate via multiple radio access technologies (RATs), such as universal terrestrial radio access (UTRA) and Institute of Electrical and Electronics Engineers (IEEE) 802.11.

[0063] The chip 32 can access information from any type of suitable memory (e.g., non-removable memory 44 and / or removable memory 46) and store data in any type of suitable memory. For example, as described above, the chip 32 can store session context in its memory. The non-removable memory 44 may include RAM, ROM, a hard disk, or any other type of memory storage device. The removable memory 46 may include a subscriber identity module (SIM) card, a memory stick, and a secure digital (SD) memory card, etc. In other embodiments, the chip 32 can access information from a memory that is not physically located on the computing device 30 (e.g., on a server or a home computer) and store data in the memory.

[0064] The chip 32 may receive power from the power supply 48 and may be configured to distribute and / or control the power to other components in the computing device 30. The power supply 48 may be any suitable device for powering the computing device 30. For example, the power supply 48 may include one or more dry cell batteries (e.g., nickel-cadmium (NiCd), nickel-zinc (NiZn), nickel metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, fuel cells, etc.

[0065] Chip 32 may also be coupled to a GPS chipset 50, which may be configured to provide location information (e.g., longitude and latitude) regarding the current location of computing device 30. It will be appreciated that computing device 30 may acquire location information by any suitable location determination method while remaining consistent with exemplary embodiments.

[0066] The foregoing description of exemplary aspects of the present disclosure has been presented for illustrative purposes. This description is not intended to be exhaustive, nor is it intended to limit the patent rights to the precise form disclosed. It will be appreciated by those skilled in the relevant art that many modifications and variations are possible based on the above disclosure.

[0067] Some parts of this description describe exemplary aspects of the present disclosure in terms of applications and / or symbolic representations that operate on information. These application descriptions and representations are typically used by technicians in the field of data processing to effectively convey the substance of their work to other technicians in the field. Although these operations are described functionally, computationally, or logically, these operations are understood to be implemented by computer programs or equivalent circuits and microcodes, etc. In addition, it has been proven that, without loss of generality, it is convenient to refer to the arrangement of these operations as components. The described operations and their associated components can be implemented in software, firmware, hardware, or any combination thereof.

[0068] One or more hardware components or software components may be used to perform or implement any of the steps, operations, or processes described herein, either alone or in combination with other devices. In an exemplary aspect of the present disclosure, the software components may be implemented using a computer program product including a computer-readable medium, the computer-readable medium containing computer program code, which may be executed by a computer processor to perform any or all of the steps, operations, or processes described.

[0069] Some exemplary aspects of the present disclosure may also relate to a device for performing the operations herein. The device may be specially constructed for the desired purpose, or the device may include a computing device that is selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a non-transitory tangible computer-readable storage medium, or in any type of medium suitable for storing electronic instructions that may be coupled to a computer system bus. In addition, any computing system mentioned in this specification may include a single processor, or may be an architecture that uses a multi-processor design to increase computing power.

[0070] Some exemplary aspects of the present disclosure may also relate to products produced by the computing process described herein. Such products may include information obtained from the computing process, wherein the information is stored on a non-transitory tangible computer-readable storage medium and may include any exemplary aspects of the computer program product or other data combination described herein.

[0071] The terms used in this specification are selected primarily for readability and instructional purposes, and may not be selected to describe or limit the subject matter of the present invention. Therefore, the scope of the patent rights is not intended to be limited by this specific embodiment, but by any claims published on the application based on this document. Therefore, the disclosure of the exemplary aspects is intended to illustrate rather than limit the scope of the patent rights, which is set forth in the following claims.

Claims

1. An integrated circuit, comprising: Intermediary layer; a plurality of random access memory chips stacked on top of the interposer; as well as A plurality of computing cores, wherein the plurality of computing cores are stacked on top of corresponding ones of the plurality of random access memory cores such that the plurality of computing cores are in electrical communication with corresponding ones of the plurality of random access memory cores.

2. The integrated circuit according to claim 1, wherein: The plurality of random access memory chips include static random access memory (SRAM) chips.

3. The integrated circuit according to claim 1, wherein: The plurality of computing cores include a plurality of processing elements PE.

4. The integrated circuit of claim 1 , further comprising: A plurality of high bandwidth memory HBM cores are stacked on top of the interposer.

5. The integrated circuit of claim 1 , further comprising: A set of core particles are stacked on top of the interposer.

6. The integrated circuit of claim 1, wherein: The plurality of random access memory cores are configured to electrically communicate with each other via the interposer.

7. The integrated circuit according to claim 1, wherein: More than one computing core of the plurality of computing cores are stacked on top of a random access memory core of the plurality of random access memory cores.

8. The integrated circuit of claim 1, wherein: One or more of the plurality of random access memory cores are configured to electrically communicate with other random access memory cores of the plurality of random access memory cores via the interposer.

9. The integrated circuit of claim 1 , further comprising: a substrate layer, wherein the interposer is stacked on top of the substrate layer; and At least one main central processing unit (CPU) is stacked on top of the substrate layer, wherein the at least one main CPU is in electrical communication with the interposer layer via the substrate layer.

10. The integrated circuit of claim 9, wherein: The at least one main CPU includes two main CPUs.

11. The integrated circuit of claim 1 , further comprising: A set of network and main central processing unit CPU chips are stacked on top of the interposer.

12. The integrated circuit of claim 1 , further comprising: A main central processing unit (CPU) is stacked on top of the interposer.

13. The integrated circuit of claim 1 , further comprising: another random access memory, the another random access memory stacked on top of the interposer; as well as A main central processing unit (CPU) is stacked on top of the other random access memory, wherein the main CPU is in electrical communication with the other random access memory.

14. The integrated circuit of claim 13, wherein: The another random access memory is configured to electrically communicate with the plurality of random access memory chips via the interposer.

15. The integrated circuit of claim 1 , further comprising: One or more double data rate (DDR) memory chips are stacked on top of the interposer.

16. The integrated circuit of claim 1, wherein: The integrated circuit is configured to perform artificial intelligence AI functions or machine learning ML functions.

17. A method comprising: sending at least one electrical signal from the computing core particle; as well as The at least one electrical signal is transmitted to a random access memory chip, wherein the computing chip is stacked on top of the random access memory chip to form a three-dimensional stacked integrated circuit.

18. The method according to claim 17, further comprising: The at least one electrical signal is sent from the random access memory die to another component of the integrated circuit via an interposer of the integrated circuit.

19. The method according to claim 18, wherein: The another component is stacked on top of the interposer.

20. A non-transitory computer readable medium storing instructions which, when executed, cause: sending at least one electrical signal from the computing core; and transmitting the at least one electrical signal to a random access memory chip, wherein: The compute core is stacked on top of the random access memory core to form a three-dimensional stacked integrated circuit.

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