Shield gate groove type MOSFET device and preparation method thereof

Abstract

The invention provides a shield gate trench type MOSFET device and a preparation method thereof, and the method at least comprises the steps: forming a first trench unit and a second trench unit on a substrate with an epitaxial layer, forming a first dielectric layer and first polycrystalline silicon in the first trench unit, and forming a second dielectric layer in the second trench unit, and forming a combined gate dielectric layer on the inner wall of the second trench unit and filling second polycrystalline silicon, the combined gate dielectric layer being formed by stacking inner silicon oxide, silicon nitride and outer silicon oxide, and then forming a body region, a source region and an upper metal layer. The thickness of inner silicon oxide is reduced, and stress concentration between silicon oxide and polycrystalline silicon on the two sides of the inner wall of the second groove unit is reduced; meanwhile, the combined gate dielectric layer effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the inner wall interface of the groove, and reduces the risk of wafer warping. And finally, the combined gate dielectric layer has a higher dielectric constant, so that the device has higher gate voltage endurance capability under low threshold voltage, the gate electric leakage is improved, and the performance of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a shielded gate trench type MOSFET device and a preparation method thereof. Background Art

[0002] Shielded-Gate Trench MOSFET (SGT MOSFET) uses the principle of two-dimensional charge balance to break through the performance limit of traditional power MOSFET. Compared with traditional trench MOSFET, SGT MOSFET realizes the role of internal field plate by setting a shield gate in the drift region, effectively reducing the on-resistance and improving the energy efficiency of the system. In addition, the design of SGT MOSFET also considers reducing the gate-drain capacitance, thereby improving the switching performance of the device.

[0003] The left-right structure shielded gate trench MOSFET technology is an advanced power semiconductor device that optimizes the electric field distribution by introducing a shielded gate in the trench, thereby improving the on-resistance, switching speed and reliability of the device. This technology is mainly used in medium and low voltage fields, such as power management, motor drive, DC / DC and AC / DC subsystem current switching. However, in the manufacturing process of the left-right structure shielded gate trench, especially in the manufacturing of the gate trench structure, wafer warpage is a common problem. This is mainly due to the uneven mechanical stress inside the wafer and a large amount of thermal stress when etching the trench. For example, in the preparation of the shallow trench isolation structure, it is usually first etched in the shielded gate dielectric layer to form a trench, and then thermally oxidized on its surface to form a dense gate oxide layer, and the gate oxide layer is mostly silicon oxide formed by a thermal oxidation process. When the thickness of silicon oxide is too large, the oxygen in the thermal oxidation process will continue to accumulate at the interface between polysilicon and silicon oxide, and the density of silicon oxide generated in the thermal oxidation process will continue to increase, thereby causing extrusion stress on the polysilicon and substrate on both sides of the trench at the microscopic level, which is manifested in the warpage of the wafer at the macroscopic level. In addition, when polysilicon is subsequently filled inside the gate trench, the high-temperature thermal process in the subsequent semiconductor manufacturing process will still cause oxygen to penetrate the oxide layer and enter the interface between polysilicon and silicon oxide to react, causing continuous thermal stress on both sides of the trench and the substrate.

[0004] Therefore, how to provide a shielded gate trench MOSFET device and a preparation method thereof to reduce the probability of wafer warping generated during the manufacturing process of the left and right structure shielded gate trench and improve the yield has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a shielded gate trench MOSFET device and a preparation method thereof, which are used to solve the wafer warping problem in the manufacturing process of left-right structure SGT-MOSFET devices, thereby further improving the gate voltage resistance.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a shielded gate trench MOSFET device, the preparation method at least comprising:

[0008] Providing a semiconductor substrate having an epitaxial layer, and forming a hard mask layer on a surface of the epitaxial layer;

[0009] Patterning the hard mask layer, and etching the epitaxial layer, forming a plurality of first trench units in the epitaxial layer and removing the hard mask layer;

[0010] forming a first dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer;

[0011] forming a first polysilicon filling the first trench unit on the first dielectric layer, and removing the first dielectric layer and the first polysilicon located on the surface of the epitaxial layer;

[0012] forming a second trench unit in the first dielectric layer, wherein the second trench unit is distributed on both sides of the first polysilicon layer, and the second trench unit exposes the sidewall of the first polysilicon layer and the sidewall of the epitaxial layer;

[0013] forming a combined gate dielectric layer, wherein the combined gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked; the combined gate dielectric layer covers the surface of the second trench unit, the surface of the first polysilicon, the surface of the first dielectric layer and the surface of the epitaxial layer; the inner silicon oxide is prepared by a thermal oxidation process; forming a second polysilicon covering the combined gate dielectric layer and filling the second trench unit;

[0014] forming a body region in the epitaxial layer at the side of the first trench unit, and forming a source region in the body region;

[0015] forming an interlayer dielectric layer on the combined gate dielectric layer, wherein the interlayer dielectric layer has a first connection hole exposing the body region and a second connection hole exposing the first polysilicon;

[0016] An upper metal structure filling the first connection hole and the second connection hole is formed.

[0017] Optionally, the combined gate dielectric layer includes a first combined gate dielectric layer and a second combined gate dielectric layer; the first combined gate dielectric layer is located close to the first polysilicon sidewall, the second combined gate dielectric layer is located close to the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer.

[0018] Optionally, the thickness of the inner silicon oxide of the first combined gate dielectric layer is The thickness of the silicon nitride in the first combined gate dielectric layer is The thickness of the inner silicon oxide of the second combined gate dielectric layer is The thickness of the silicon nitride in the second combined gate dielectric layer is

[0019] Optionally, the surface of the formed second polysilicon is lower than the surface of the combined gate dielectric layer.

[0020] Optionally, forming the upper metal structure comprises the following steps:

[0021] forming an interlayer dielectric layer covering the epitaxial layer;

[0022] Etching a contact hole in the interlayer dielectric layer and forming an implantation region, forming a first connection hole penetrating the interlayer dielectric layer and the body region and a second connection hole penetrating the interlayer dielectric layer and the first polysilicon;

[0023] A metal connection layer is formed in the first connection hole and the second connection hole, and a front metal layer is formed on the surface of the interlayer dielectric layer.

[0024] Optionally, the interlayer dielectric layer includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer.

[0025] In addition, the present invention also provides a shielded gate trench MOSFET device, the shielded gate trench MOSFET device at least comprising:

[0026] A semiconductor substrate having an epitaxial layer;

[0027] A first trench unit is located in the epitaxial layer;

[0028] A first dielectric layer, located on the inner wall of the first trench unit;

[0029] A first polysilicon layer is located on the first dielectric layer and fills the first trench unit;

[0030] A second trench unit is located in the first dielectric layer, the second trench unit is distributed on both sides of the first polysilicon, and the second trench unit exposes the sidewall of the first polysilicon and the sidewall of the epitaxial layer;

[0031] A combined gate dielectric layer, wherein the combined gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked together; the combined gate dielectric layer covers the inner wall of the second trench unit, the surface of the first polysilicon and the surface of the semiconductor substrate;

[0032] second polysilicon, covering the combined gate dielectric layer and filling the second trench unit;

[0033] A body region located in the epitaxial layer at a side of the first trench unit;

[0034] a source region, the source region being located in the body region;

[0035] an interlayer dielectric layer, located on the combined gate dielectric layer, and having a first connection hole exposing the body region and a second connection hole exposing the first polysilicon;

[0036] The upper metal structure is filled with the first connection hole and the second connection hole. Optionally, the combined gate dielectric layer includes a first combined gate dielectric layer and a second combined gate dielectric layer; wherein the first combined gate dielectric layer is located near the first polysilicon sidewall, the second combined gate dielectric layer is located near the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer; the thickness of the inner silicon oxide in the first combined gate dielectric layer is The thickness of the silicon nitride in the first combined gate dielectric layer is The thickness of the outer silicon oxide of the second combined gate dielectric layer is The thickness of the silicon nitride in the second combined gate dielectric layer is Optionally, the surface of the formed second polysilicon is lower than the surface of the combined gate dielectric layer.

[0037] Optionally, the shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

[0038] As described above, the shielded gate trench MOSFET device and its preparation method of the present invention at least include: forming a first trench unit and a second trench unit on a substrate having an epitaxial layer, forming a first dielectric layer and a first polysilicon in the first trench unit, forming a combined gate dielectric layer on the inner wall of the second trench unit and filling the second polysilicon, the combined gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked, and forming a body region, a source region and an upper metal layer on the surface of the combined gate dielectric layer and the second polysilicon. The thickness of the inner silicon oxide is reduced, which reduces the stress concentration between the inner silicon oxide and the polysilicon on both sides of the inner wall of the second trench unit; at the same time, the combined gate dielectric layer effectively reduces the influence of subsequent high-temperature processes on the stress concentration of the inner wall of the trench; in addition, due to the surface integrity of the combined gate dielectric layer, the influence of subsequent semiconductor high-temperature processes on the stress concentration of various positions of the wafer is effectively reduced, and the risk of wafer warping is reduced. Finally, the combined gate dielectric layer has a higher dielectric constant, so that the device has a higher gate withstand voltage capability at a low threshold voltage, improves gate leakage and improves device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shown is a schematic flow chart of a method for preparing a shielded gate trench MOSFET device of the present invention.

[0040] Figure 2 It is a schematic structural diagram showing the present invention after a hard mask layer is formed on the surface of the epitaxial layer of the semiconductor substrate.

[0041] Figure 3 It is a schematic structural diagram of the present invention after forming a first trench unit in the epitaxial layer.

[0042] Figure 4 It is a schematic structural diagram showing the present invention after a first dielectric layer is formed on the sidewall of the first trench unit and the surface of the epitaxial layer.

[0043] Figure 5a It is a schematic diagram of the structure after the first trench unit is filled with the first polysilicon in the present invention.

[0044] Figure 5b It is a schematic diagram of the structure after the first polysilicon and the first dielectric layer on the surface of the epitaxial layer are removed in the present invention.

[0045] Figure 6 It is a schematic structural diagram showing the second trench unit formed in the first medium in the present invention.

[0046] Figure 7 It is a schematic diagram of the structure after forming a combined gate dielectric layer in the present invention.

[0047] Figure 8Shown is a schematic diagram of a local enlarged structure of the combined gate dielectric layer described in the present invention.

[0048] Fig. 9 It is a schematic diagram of the structure after the second polysilicon is formed in the present invention.

[0049] Fig.10 It is a schematic diagram of the structure after the body region and the source region are formed in the present invention.

[0050] Fig.11a It is a schematic diagram of the structure after the interlayer dielectric layer is formed in the present invention.

[0051] Fig.11b It is a schematic diagram of the structure after the first connection hole, the second connection hole, the first injection region and the second injection region are formed in the present invention.

[0052] Fig.12a It is a schematic diagram of the structure after a barrier layer is formed on the sidewall of the first connection hole and the sidewall of the second connection hole in the present invention.

[0053] Figure 12b It is a schematic structural diagram showing the structure after metal connection columns are formed in the first connection hole and the second connection hole in the present invention.

[0054] Fig.12c It is a schematic diagram of the structure after the front metal layer is formed in the present invention.

[0055] Description of Reference Numerals

[0056] 100 Semiconductor Substrate

[0057] 110 Epitaxial layer

[0058] 120 Hard mask layer

[0059] 200 First trench unit

[0060] 210 First dielectric layer

[0061] 220 First Polysilicon

[0062] 300 Second trench unit

[0063] 310 Combined gate dielectric layer

[0064] 320 first combined gate dielectric layer

[0065] 321 First Silicon Oxide

[0066] 322 First Silicon Nitride

[0067] 323 Second Silicon Oxide

[0068] 330 second combined gate dielectric layer

[0069] 331 Third Silicon Oxide

[0070] 332 Second Silicon Nitride

[0071] 333 Fourth Silicon Oxide

[0072] 340 Second Polysilicon

[0073] 610 Body Area

[0074] 620 Source Area

[0075] 400 Interlayer dielectric layer

[0076] 410 Dielectric silicon oxide layer

[0077] 420 Silicon phosphate glass layer

[0078] 510 Barrier layer

[0079] 520 Metal connecting column

[0080] 530 Front metal layer

[0081] 540 First connection hole

[0082] 550 Second connection hole

[0083] 630 Injection Area

[0084] 631 Second injection area

[0085] 632 First injection area DETAILED DESCRIPTION

[0086] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0088] Embodiment 1

[0089] This embodiment provides a method for manufacturing a shielded gate trench MOSFET device. Since the shielded gate trench MOSFET device structure can be an N-type device or a P-type device, this embodiment takes an N-type device as an example. Figure 1 , which is a flowchart showing a method for manufacturing the shielded gate trench MOSFET device, comprising the following steps:

[0090] First, execute step S1, see Figure 1 and Figure 2 , a semiconductor substrate 100 having an epitaxial layer 110 is provided, and a hard mask layer 120 is formed on a surface of the epitaxial layer 110 .

[0091] Specifically, the epitaxial layer 110 may be an N++ type doped silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc. In this embodiment, the substrate 100 is an N++ type doped silicon substrate, and the epitaxial layer 110 is an N-type single crystal silicon epitaxial layer.

[0092] Furthermore, the structure of the hard mask layer 120 can be a single silicon oxide layer with a certain thickness, or it can include a combination layer of silicon oxide-silicon nitride-silicon oxide stacked from bottom to top. Preferably, in this embodiment, the hard mask layer 120 adopts a combination layer of silicon oxide-silicon nitride-silicon oxide.

[0093] Next, execute step S2, see Figure 1 and Figure 3 , patterning the hard mask layer 120 , and etching the epitaxial layer 110 , forming a plurality of first trench units 200 in the epitaxial layer 110 and removing the hard mask layer 120 .

[0094] Specifically, the hard mask layer 120 is used to define the region position of the first trench unit 200 to be prepared through a photolithography process, thereby etching the required first trench unit 200. The specific implementation of the photolithography and etching process can be implemented by conventional means known to those skilled in the art, and is not specifically limited here.

[0095] Next, execute step S3, see Figure 1 and Figure 4 , a first dielectric layer 210 is formed on the inner wall of the first trench unit 200 and the surface of the epitaxial layer 110 .

[0096] Specifically, the first dielectric layer 210 is usually formed by using a furnace tube and a CVD process to grow a certain thickness of the first dielectric layer 210 on the surface of the epitaxial layer 110 and the sidewall of the first trench unit 200. Preferably, the material of the first dielectric layer 210 in this embodiment includes silicon oxide.

[0097] Furthermore, the epitaxial layer 110 constitutes a drift region, and when the shielded gate MOSFET is in a reverse bias state, the subsequent first polysilicon 220 laterally depletes the drift region through the first dielectric layer 210 and improves the voltage withstand capability of the shielded gate MOSFET device.

[0098] Next, execute step S4, see Figure 1 and Figure 5a-5b , forming the first polysilicon 220 filling the first trench unit 200 on the first dielectric layer 210 , and removing the first dielectric layer 210 and the first polysilicon 220 located on the surface of the epitaxial layer 110 .

[0099] Specifically, the first polysilicon 220 may be planarized to expose the surface of the first dielectric layer 210, and then the first polysilicon 220 and the first dielectric layer 210 may be planarized until the surface of the epitaxial layer 110 is exposed. The planarization process may include mechanical grinding or CMP, which is not excessively limited here.

[0100] Next, execute step S5, refer to Figure 1 and Figure 6 , a second trench unit 300 is formed in the first dielectric layer 210 , the second trench unit 300 is distributed on both sides of the first polysilicon 220 , and the second trench unit 300 exposes the sidewall of the first polysilicon 220 and the sidewall of the epitaxial layer 110 .

[0101] Next, execute step S6, refer to Figure 1 and Figure 7 A combined gate dielectric layer 310 is formed on the surface of the epitaxial layer 110, and the combined gate dielectric layer 310 is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked together; the combined gate dielectric layer 310 covers the inner wall of the second trench unit 300, the surface of the first polysilicon 220 and the surface of the epitaxial layer 110; the inner silicon oxide is prepared by a thermal oxidation process.

[0102] Specifically, in order to ensure that the sidewalls and bottom of the second trench unit 300 are clean and pollution-free, the second trench unit 300 is usually formed by etching the upper layer of the first dielectric layer 210, and then the metal impurities of the second trench unit 300 are cleaned and removed, and then a thermal oxidation process is performed in a high-temperature thermal oxygen environment to form high-quality inner silicon oxide, thereby ensuring the uniformity and density of the inner silicon oxide.

[0103] Furthermore, a layer of silicon nitride is deposited on the inner silicon oxide surface by chemical vapor deposition, and then an outer silicon oxide layer is grown on the silicon nitride surface.

[0104] For further information, see Figure 8 The combined gate dielectric layer 310 includes a first combined gate dielectric layer 320 and a second combined gate dielectric layer 330 located in the first trench unit 200; the first combined gate dielectric layer 320 is located close to the side wall of the first polysilicon 220; the second combined gate dielectric layer 330 is located close to the side wall of the epitaxial layer 110.

[0105] As an example, the inner silicon oxide in the first combined gate dielectric layer 320 is the first silicon oxide 321, and the thickness of the first silicon oxide 321 is like The silicon nitride in the first combined gate dielectric layer 320 is a first silicon nitride 322, and the thickness of the first silicon nitride 322 is like The outer silicon oxide in the first combined gate dielectric layer 320 is the second silicon oxide 323, which is not limited here and is defined according to actual needs.

[0106] As an example, the inner silicon oxide of the second combined gate dielectric layer 330 is a third silicon oxide 331, and the thickness of the third silicon oxide 331 is like The silicon nitride of the second combined gate dielectric layer 330 is a second silicon nitride 332, and the thickness of the second silicon nitride 332 is like The outer silicon oxide in the second combined gate dielectric layer 330 is the fourth silicon oxide 333, which is not limited here and is defined according to actual needs.

[0107] Furthermore, the first silicon oxide 321 and the third silicon oxide 331 are formed synchronously. During the thermal oxidation process, due to the difference in the polysilicon composition of the left and right side walls of the second trench unit 300, the thickness of the inner silicon oxide formed on both sides of the second trench unit 300 is different. The first silicon nitride 322 and the second silicon nitride 332 are formed by chemical vapor deposition at the same time, so the thickness of the two is the same. Similarly, the second silicon oxide 323 in the first combined gate dielectric layer 320 and the fourth silicon oxide 333 in the second combined gate dielectric layer 330 are the same thickness. It is not limited here and is defined according to actual needs.

[0108] In this embodiment, compared with the prior art, the process time of the inner silicon oxide thermal oxidation process is reduced, and the thickness of the inner silicon oxide is reduced, so as to avoid stress concentration between the inner silicon oxide and the first polysilicon 220. At the same time. On this basis, a silicon nitride layer and an outer silicon oxide layer are added to form a combined gate dielectric layer 310, which effectively reduces the risk of stress concentration at the interface between the inner silicon oxide of the second trench unit 300 and the first polysilicon 220 in the subsequent high-temperature process; in addition, since the surfaces of the first polysilicon 220 and the semiconductor substrate 100 are covered with a three-layer structure of silicon oxide / silicon nitride / silicon oxide, in the subsequent semiconductor high-temperature process, the stress concentration at various positions of the wafer is effectively reduced, and the risk of wafer warping is reduced.

[0109] Next, execute step S7, refer to Figure 1 and Fig. 9 , the inner wall of the combined gate dielectric layer 310 in the second trench unit 300 is filled with second polysilicon 340 .

[0110] Specifically, the bottom and sides of the second polysilicon 340 are isolated from the first polysilicon 220 by the first combined gate dielectric layer 320 ; the second combined gate dielectric layer 330 is isolated between the second polysilicon 340 and the sidewall of the first trench unit 200 .

[0111] Specifically, the second polysilicon 340 is planarized to expose the surface of the combined dielectric layer 310 . Furthermore, the second polysilicon 340 is preferably etched to make the surface of the second polysilicon 340 lower than the surface of the combined gate dielectric layer 310 .

[0112] Furthermore, the etching process of the second polysilicon 340 may be dry etching or wet etching, which will not be described in detail here.

[0113] Next, execute step S8, see Figure 1 and Fig.10 , a body region 610 is formed in the epitaxial layer 110 on both sides of the first trench unit 200 , and a source region 620 is formed in the body region 610 .

[0114] Specifically, the source region 620 is located on the upper surface of the body region 610 . The body region 610 is adjacent to the sidewall of the first trench unit 200 , and the bottom surface of the body region 610 is higher than the bottom surface of the second polysilicon 340 .

[0115] As an example, the body region 610 includes a P-type body region, and the method of forming the body region 610 includes ion implantation, for example, ion implantation can be used to implant P-type impurities into the epitaxial layer 110. In other examples, photolithography is used to define the implantation region as needed.

[0116] As an example, the source region 620 includes an N+ type source region, and the method for forming the source region 620 includes: forming a mask layer on the surface of the epitaxial layer 110, the mask layer can be made of photoresist, forming a plurality of openings in the mask layer through photolithography steps such as exposure and development, thereby defining a plurality of ion implantation regions, and performing N-type ion implantation on the epitaxial layer 110 based on the plurality of ion implantation regions defined in the mask layer to form the source region 620 on the upper surface layer of the body region 610. Next, step S9 is performed, referring to Figures 11a-11b An interlayer dielectric layer 400 is formed on the combined gate dielectric layer 310 , and the interlayer dielectric layer 400 has a first connection hole 540 exposing the body region 610 and a second connection hole 550 exposing the first polysilicon 220 .

[0117] Next, execute step S10, refer to Figures 12a to 12c , forming an upper metal structure filling the first connection hole 540 and the second connection hole 550 .

[0118] Specifically, the step of forming the upper metal structure also includes:

[0119] S10-1, see Fig.12a , forming an interlayer dielectric layer 400 covering the epitaxial layer 110.

[0120] Specifically, the interlayer dielectric layer 400 includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer. In this embodiment, the interlayer dielectric layer 400 includes a stacked structure of a dielectric silicon oxide layer 410 and a silicon phosphate glass layer 420 .

[0121] S10-2, see Figure 12b , contact holes are etched in the interlayer dielectric layer 400 and an implantation region 630 is formed, forming a first connection hole 540 penetrating the interlayer dielectric layer 400 and the body region 610 and a second connection hole 550 penetrating the interlayer dielectric layer 400 and the first polysilicon 220.

[0122] Furthermore, the photoresist is exposed using masks with different critical sizes to define contact hole areas in the developed photoresist; the interlayer dielectric layer 400 is penetrated by a dry etching process to form contact holes with different critical sizes, including the first connection hole 540 and the second connection hole 550.

[0123] Furthermore, ion implantation is performed in the first connection hole 540 to form a first implantation region 632, and ion implantation is performed at the bottom of the second connection hole 550 to form a second implantation region 631, and the implanted ions enter the bottom of the contact hole to a predetermined depth. As an example, the ion implantation uses P-type ion implantation.

[0124] S10-3, see Fig.12c , a metal connection layer is formed in the first connection hole 540 and the second connection hole 550 , and a front metal layer 530 is formed on the surface of the interlayer dielectric layer 400 .

[0125] Specifically, in order to ensure good metal connection between the first connection hole 540 and the second connection hole 550, the present embodiment uses metal W to fill the contact hole and thin it to form a metal connection column 520. In order to avoid polysilicon metallization, chemical vapor deposition is used in the example to form a barrier layer 510 covering the inner walls of the first connection hole 540 and the second connection hole 550. Preferably, the material of the barrier layer 510 includes Ti / TiN.

[0126] Furthermore, the front metal layer 530 is formed on the surface of the interlayer dielectric layer 400 and connected to the metal connection column 520 .

[0127] Furthermore, the front metal layer 530 contacts the source region 620 through the first connection hole 540 to lead out the source, and the body region 610 is short-circuited with the source. A drain region can be formed on the back of the semiconductor substrate 100, forming a back metal layer and leading out the drain through the back metal layer. To distinguish the gate, the first polysilicon 220 is connected to the source through the second connection hole 550 to form a shielding gate, and the second polysilicon 340 is connected to the gate metal at other places to form a control gate. Since there is a large potential difference between the shielding gate and the drift region formed by the epitaxial layer 110, the first dielectric layer 210 has a relatively thick thickness. The first gate that is always connected to a low potential acts as a constant companion, introduces the RESURF (Refuced Surface Fielded) effect of the dielectric layer, assists in depleting the N-type impurities in the drift region in the off state and optimizes the electric field distribution, thereby allowing the drift region to adopt a higher doping concentration while keeping the breakdown voltage unchanged or even optimized, reducing the on-resistance of the device and achieving low static loss.

[0128] As an example, this example takes an N-type device as an example, and provides a method for preparing a shielded gate trench MOSFET device, wherein the semiconductor epitaxial layer 110 and the source region 620 are doped with N-type conductive ions, and the body region 610 and the injection region 630 are doped with P-type conductive ions. In some other embodiments, a method for preparing a shielded gate trench MOSFET device taking a P-type device as an example can also be provided, wherein the epitaxial layer 110 and the source region 620 are doped with P-type conductive ions, and the body region 610 and the injection region 630 are doped with N-type conductive ions. No further details are given here.

[0129] The preparation method of the shielded gate trench MOSFET device proposed in this embodiment reduces the thickness of the inner silicon oxide and reduces the stress concentration between the silicon oxide and polysilicon on both sides of the inner wall of the second trench unit 300; at the same time, the formation of the combined gate dielectric layer 310 covering the first polysilicon 220, the epitaxial layer 110 and the second trench unit 300 effectively reduces the impact of subsequent high-temperature processes on the stress concentration of the inner wall interface of the trench, and also reduces the stress concentration problem of subsequent high-temperature processes on various positions of the wafer, reducing the risk of wafer warping. Finally, the combined gate dielectric layer 310 has a higher dielectric constant, so that the device has a higher gate withstand voltage capability at a low threshold voltage, improves gate leakage and improves device performance.

[0130] Embodiment 2

[0131] This embodiment also provides a shielded gate trench MOSFET device, which is manufactured by the manufacturing method described in the first embodiment or other suitable similar methods. The manufacturing method, material and structure of the shielded gate trench MOSFET device can all be referred to the first embodiment. Fig.12c , which is a schematic diagram of the structure of the shielded gate trench MOSFET device, wherein the shielded gate trench MOSFET device includes:

[0132] A semiconductor substrate 100 having an epitaxial layer 110;

[0133] A first trench unit 200 is located in the epitaxial layer 110;

[0134] A first polysilicon 220, located on the first dielectric layer 210 and filling the first trench unit 200;

[0135] The second trench unit 300 is located in the first dielectric layer 210 . The second trench unit 300 is distributed on both sides of the first polysilicon 220 , and the second trench unit 300 exposes the sidewalls of the first polysilicon 220 and the sidewalls of the epitaxial layer 110 .

[0136] A combined gate dielectric layer 310, wherein the combined gate dielectric layer 310 is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked together; the combined gate dielectric layer 310 covers the inner wall of the second trench unit 300, the surface of the first polysilicon 220 and the surface of the epitaxial layer 110; the inner silicon oxide is prepared by a thermal oxidation process;

[0137] A second polysilicon 340 covering the combined gate dielectric layer 310 and filling the second trench unit 300;

[0138] A body region 610 located in the epitaxial layer 110 on the side of the first trench unit 200;

[0139] A source region 620 located in the body region 610;

[0140] An interlayer dielectric layer 400 is located on the combined gate dielectric layer 310 , and has a first connection hole 540 exposing the body region and a second connection hole 550 exposing the first polysilicon 220 ;

[0141] The upper metal structure fills the first connection hole 540 and the second connection hole 550 .

[0142] As an example, the combined gate dielectric layer 310 includes a first combined gate dielectric layer 320 and a second combined gate dielectric layer 330; the first combined gate dielectric layer 320 is located between the sidewall of the first polysilicon 220 and the sidewall of the second polysilicon 340; the second combined gate dielectric layer 330 is located between the sidewall of the second polysilicon 340 and the sidewall of the epitaxial layer 110;

[0143] As an example, the inner silicon oxide in the first combined gate dielectric layer 320 is the first silicon oxide 321, and the thickness of the first silicon oxide 321 is like The silicon nitride in the first combined gate dielectric layer 320 is a first silicon nitride 322, and the thickness of the first silicon nitride 322 is like The outer silicon oxide in the first combined gate dielectric layer 320 is the second silicon oxide 323, which is not limited here and is defined according to actual needs.

[0144] As an example, the inner silicon oxide of the second combined gate dielectric layer 330 is a third silicon oxide 331, and the thickness of the third silicon oxide 331 is like The silicon nitride of the second combined gate dielectric layer 330 is a second silicon nitride 332, and the thickness of the second silicon nitride 332 is like The outer silicon oxide in the second combined gate dielectric layer 330 is the fourth silicon oxide 333, which is not limited here and is defined according to actual needs.

[0145] In the structure of the shielded gate trench MOSFET device in the second embodiment, the thickness of the inner silicon oxide is reduced, so that the compressive stress at the interface between the inner silicon oxide and the first polysilicon 220 in the second trench unit 300 is reduced. At the same time, on the basis of the inner silicon oxide, a silicon nitride layer and an outer silicon oxide layer are added to form the combined gate dielectric layer 310, which effectively avoids the risk of stress concentration on the inner interface of the trench in the subsequent high-temperature process; in addition, since the first polysilicon 220 and the surface of the semiconductor substrate 100 are covered with a three-layer structure of silicon oxide / silicon nitride / silicon oxide, the stress concentration at various positions of the wafer is effectively reduced, and the risk of wafer warping is reduced.

[0146] As an example, the surface of the formed second polysilicon 340 is lower than the surface of the combined gate dielectric layer 310. Further, the upper metal structure further includes:

[0147] A first connection hole 540 and a first injection region 632 , wherein the first connection hole 540 penetrates the interlayer dielectric layer 400 and the body region 610 ;

[0148] A second connection hole 550 and a second implantation region 631, wherein the second connection hole 550 penetrates the interlayer dielectric layer 400 and the first polysilicon 220;

[0149] A metal connection layer and a front metal layer 530 , wherein the metal connection layer passes through the first connection hole 540 and the second connection hole 550 , and the front metal layer 530 covers the surface of the interlayer dielectric layer 400 and is electrically connected to the metal connection layer.

[0150] Specifically, the interlayer dielectric layer 400 includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer. In this embodiment, the interlayer dielectric layer 400 includes a stacked structure of a dielectric silicon oxide layer 410 and a silicon phosphate glass layer 420 .

[0151] Specifically, the metal connection layer includes a barrier layer 510 and a metal connection column 520 , and the material of the barrier layer 510 includes Ti / TiN.

[0152] Furthermore, the front metal layer 530 contacts the source region 620 through the first connection hole 540 to lead out the source, and the body region 610 is short-circuited with the source, and a drain region can be formed on the back side of the semiconductor substrate 100, forming a back metal layer and leading out the drain through the back metal layer. To distinguish the gate, the first polysilicon 220 is connected to the source through the second connection hole 550 to form a shielding gate, and the second polysilicon 340 is connected to the gate metal at other places to form a control gate.

[0153] Furthermore, the epitaxial layer 110 and the source region 620 are doped with ions of a first conductivity type, and the body region 620 and the implantation region 630 are doped with ions of a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types to each other.

[0154] In summary, the preparation method of the shielded gate trench MOSFET device of the present invention at least includes: forming a first trench unit and a second trench unit on a substrate having an epitaxial layer, forming a first dielectric layer and a first polysilicon in the first trench unit, forming a combined gate dielectric layer on the inner wall of the second trench unit and filling the second polysilicon, the combined gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked, and then forming a body region, a source region and an upper metal layer. The thickness of the inner silicon oxide is reduced, which reduces the stress concentration between the inner silicon oxide and the polysilicon on both sides of the inner wall of the second trench unit; at the same time, the combined gate dielectric layer effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the inner wall interface of the trench; in addition, due to the overall distribution of the combined gate dielectric layer, the stress concentration at each position of the wafer is improved as a whole, thereby reducing the risk of wafer warping. Finally, the combined gate dielectric layer has a higher dielectric constant, and the MOSFET device can have a higher gate withstand voltage capability at a low threshold voltage, improve gate leakage and improve device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0155] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a shielded gate trench MOSFET device, characterized in that: The following steps are involved: Providing a semiconductor substrate having an epitaxial layer, and forming a hard mask layer on a surface of the epitaxial layer; Patterning the hard mask layer, etching the epitaxial layer, forming a plurality of first trench units in the epitaxial layer, and removing the hard mask layer; forming a first dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer; Forming first polysilicon filling the first trench unit on the first dielectric layer, and removing the first dielectric layer and the first polysilicon located on the surface of the epitaxial layer; forming a second trench unit in the first dielectric layer, wherein the second trench unit is distributed on both sides of the first polysilicon layer, and the second trench unit exposes the sidewall of the first polysilicon layer and the sidewall of the epitaxial layer; forming a composite gate dielectric layer, wherein the composite gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked together; the composite gate dielectric layer covers the inner wall of the second trench unit, the surface of the first polysilicon and the surface of the epitaxial layer; the inner silicon oxide is prepared by a thermal oxidation process; forming a second polysilicon covering the combined gate dielectric layer and filling the second trench unit; forming a body region in the epitaxial layer at the side of the first trench unit, and forming a source region in the body region; An interlayer dielectric layer is formed on the combined gate dielectric layer, wherein the interlayer dielectric layer has a first connection hole exposing the body region and a second connection hole exposing the first polysilicon; and an upper metal structure is formed to fill the first connection hole and the second connection hole.

2. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: The combined gate dielectric layer includes a first combined gate dielectric layer and a second combined gate dielectric layer, wherein the first combined gate dielectric layer is located close to the first polysilicon sidewall, the second combined gate dielectric layer is located close to the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer.

3. The method for preparing a shielded gate trench MOSFET device according to claim 2, characterized in that: The thickness of the inner silicon oxide in the first combined gate dielectric layer is The thickness of the silicon nitride in the first combined gate dielectric layer is The thickness of the outer silicon oxide of the second combined gate dielectric layer is The thickness of the silicon nitride in the second combined gate dielectric layer is 4. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: The surface of the formed second polysilicon is lower than the surface of the combined gate dielectric layer.

5. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: Forming the upper metal structure comprises the following steps: forming an interlayer dielectric layer covering the epitaxial layer; Etching a contact hole in the interlayer dielectric layer and forming an implantation region, forming a first connection hole penetrating the interlayer dielectric layer and the body region and a second connection hole penetrating the interlayer dielectric layer and the first polysilicon; A metal connection layer is formed in the first connection hole and the second connection hole, and a front metal layer is formed on the surface of the interlayer dielectric layer.

6. The method for preparing a shielded gate trench MOSFET device according to claim 5, characterized in that: The interlayer dielectric layer includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer.

7. A shielded gate trench MOSFET device, characterized in that: include: A semiconductor substrate having an epitaxial layer; A first trench unit is located in the epitaxial layer; A first dielectric layer, located on the inner wall of the first trench unit; A first polysilicon layer is located on the first dielectric layer and fills the first trench unit; A second trench unit is located in the first dielectric layer, the second trench unit is distributed on both sides of the first polysilicon, and the second trench unit exposes the sidewall of the first polysilicon and the sidewall of the epitaxial layer; A combined gate dielectric layer, wherein the combined gate dielectric layer is composed of inner silicon oxide, silicon nitride and outer silicon oxide stacked together; the combined gate dielectric layer covers the inner wall of the second trench unit, the surface of the first polysilicon and the surface of the epitaxial layer; the inner silicon oxide is prepared by a thermal oxidation process; second polysilicon, covering the combined gate dielectric layer and filling the second trench unit; A body region located in the epitaxial layer at a side of the first trench unit; a source region located in the body region; an interlayer dielectric layer, located on the combined gate dielectric layer, and having a first connection hole exposing the body region and a second connection hole exposing the first polysilicon; The upper metal structure fills the first connection hole and the second connection hole.

8. The shielded gate trench MOSFET device according to claim 7, characterized in that: The combined gate dielectric layer comprises a first combined gate dielectric layer and a second combined gate dielectric layer; wherein the first combined gate dielectric layer is located near the first polysilicon sidewall, the second combined gate dielectric layer is located near the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer; the thickness of the inner silicon oxide in the first combined gate dielectric layer is The thickness of the inner silicon oxide in the first combined gate dielectric layer is The thickness of the outer silicon oxide of the second combined gate dielectric layer is The thickness of the outer silicon oxide in the second combined gate dielectric layer is 9. The shielded gate trench MOSFET device according to claim 7, characterized in that: The surface of the formed second polysilicon is lower than the surface of the combined gate dielectric layer.

10. The shielded gate trench MOSFET device according to claim 7, characterized in that: The shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

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