Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: forming a substrate structure, the substrate structure comprising a drain doping region and a drift region located on the drain doping region, the substrate structure comprising adjacent first and second regions, the first and second regions being arranged in a direction parallel to a first surface or a second surface; forming a first body region in the drift region of the first region, the first body region extending from the first surface toward the second surface, the conductivity type of the first body region being different from the conductivity type of the drift region; forming a plurality of columnar regions in the drift region of the second region, each columnar region extending from the first surface toward the second surface, the conductivity type of the plurality of columnar regions being different from the conductivity type of the drift region; forming a first gate structure on the first surface, with a portion of the first gate structure located on the first region and another portion of the first gate structure also located on the second region; and forming a first source doping region in the first body region on one side of the first gate structure, thereby facilitating improving the breakdown voltage of the formed device and reducing the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Vertical double-diffused metal oxide semiconductor (VDMOS) is used in ultra-large-scale integrated circuit devices for power devices and has the advantages of low switching loss, high input impedance, low driving power, and good frequency characteristics.

[0003] In order to improve the breakdown voltage of the device, a superjunction structure is introduced on the basis of the VDMOS device to form a superjunction VDMOS device. That is, alternating P pillars and N pillars are used to replace a single conductive type material as the drift region, and a lateral electric field is introduced in the drift region, so that the drift region of the device is completely depleted at a smaller turn-off voltage.

[0004] However, the performance of existing superjunction VDMOS devices still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate structure, the substrate structure including a drain-doped region and a drift region located on the drain-doped region, the substrate structure having a first surface and a second surface opposite to each other, the first surface exposing the surface of the drift region, the second surface exposing the surface of the drain-doped region, the drift region and the drain-doped region having the same conductivity type, and the doping concentration of the drift region being lower than the doping concentration of the drain-doped region, the substrate structure including adjacent first and second regions, the first and second regions being arranged in a direction parallel to the first surface or the second surface; a first body region located in the drift region of the first region, the first body region extending from the first surface toward the second surface, the conductivity type of the first body region being different from the conductivity type of the drift region; a plurality of columnar regions located in the drift region of the second region, each of the columnar regions extending from the first surface toward the second surface, the conductivity type of the plurality of columnar regions being different from the conductivity type of the drift region; a first gate structure located on the first surface, a portion of the first gate structure being located on the first region, and another portion of the first gate structure also being located on the second region; and a first source doped region located in the first body region on one side of the first gate structure.

[0007] Optionally, it also includes: a plurality of grooves located in the drift region of the second region, and a plurality of columnar regions located in the plurality of grooves; the material of the plurality of columnar regions includes semiconductor material, and the semiconductor material includes a multi-element semiconductor material composed of silicon, silicon carbide, silicon germanium, and III-V group elements.

[0008] Optionally, the first gate structure includes a first gate oxide layer and a first gate layer located on a surface of the first gate oxide layer.

[0009] Optionally, the substrate structure also includes: a third region adjacent to the second region, the second region being located between the first region and the third region; and also includes: a second body region located in the drift region of the third region, the second body region extending from the first surface toward the second surface, the conductivity type of the second body region being different from the conductivity type of the drift region.

[0010] Optionally, part of the first gate structure is located on the third region; and further comprising: a second source doping region located in the second body region on the other side of the first gate structure.

[0011] Optionally, it also includes: a second gate structure located on the first surface, part of the second gate structure is located on the third region, and another part of the second gate structure is also located on the second region; a second source doping region located in the second body region on one side of the second gate structure.

[0012] Optionally, it also includes: a first source contact layer located on a surface of part of the first source doping region, the first source contact layer and the first gate structure being separate from each other; a first gate contact layer located on a surface of the first gate structure; and a drain contact layer located on the second surface.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: forming a substrate structure, the substrate structure comprising a drain doping region and a drift region located on the drain doping region, the substrate structure having a first surface and a second surface relative to each other, the first surface exposing the drift region, the second surface exposing the drain doping region, the drift region and the drain doping region having the same conductivity type, and the doping concentration of the drift region being lower than the doping concentration of the drain doping region, the substrate structure comprising adjacent first and second regions, the first region and the second region being arranged in a direction parallel to the first surface or the second surface; forming a first body region in the drift region of the first region, the first body region extending from the first surface toward the second surface, the conductivity type of the first body region being different from the conductivity type of the drift region; forming a plurality of columnar regions in the drift region of the second region, each of the columnar regions extending from the first surface toward the second surface, the conductivity type of the plurality of columnar regions being different from the conductivity type of the drift region; forming a first gate structure on the first surface, wherein a portion of the first gate structure is located on the first region, and another portion of the first gate structure is also located on the second region; and forming a first source doping region in the first body region on one side of the first gate structure.

[0014] Optionally, the method for forming several columnar regions includes: forming a first mask layer on the first surface, the first mask layer exposing a portion of the second region; etching the drift region using the first mask layer as a mask; forming several grooves in the drift region; and forming several columnar regions in the grooves.

[0015] Optionally, materials of some of the columnar regions include semiconductor materials, and the semiconductor materials include multi-component semiconductor materials composed of silicon, silicon carbide, silicon germanium, and group III-V elements.

[0016] Optionally, the method for forming the first mask layer includes: forming a patterned photoresist layer on the surface of the drift region; and forming the first mask layer on the surface of the drift region exposed by the photoresist layer using a selective growth process.

[0017] Optionally, the method of forming the plurality of columnar regions in the plurality of grooves includes: forming a semiconductor material layer in the plurality of grooves and on the surface of the first mask layer; and planarizing the semiconductor material layer and the first mask layer until the first surface is exposed.

[0018] Optionally, the method for forming the substrate structure includes: providing a substrate, using the substrate as the drain doping region; forming an epitaxial layer on a surface of the substrate, using the epitaxial layer as the drift region.

[0019] Optionally, the method for forming the first body region includes: forming a second mask layer on the first surface, the second mask layer exposing the first surface of the first region; using the second mask layer as a mask, injecting dopant ions into the first surface to form the first body region.

[0020] Optionally, before forming the second mask layer, a protective layer is also formed on the first surface; the material of the protective layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

[0021] Optionally, the first gate structure includes a first gate oxide layer and a first gate layer located on the surface of the first gate oxide layer; the method for forming the first gate structure includes: forming a gate oxide material layer on the first surface; forming a gate material layer on the surface of the gate oxide material layer; patterning the gate material layer and the gate oxide material layer, forming a first gate layer with the gate material layer, and forming the first gate oxide layer with the gate oxide material layer.

[0022] Optionally, the substrate structure also includes: a third region adjacent to the second region, the second region being located between the first region and the third region; the method also includes: while forming the first body region, forming a second body region in the drift region of the third region, the second body region extending from the first surface toward the second surface, and the conductivity type of the second body region is different from the conductivity type of the drift region.

[0023] Optionally, part of the first gate structure is located on the third region; the method further includes: forming a second source doping region in the second body region on the other side of the first gate structure while forming the first source doping region.

[0024] Optionally, it also includes: forming a second gate structure on the first surface while forming the first gate structure, part of the second gate structure is located on the third region, and another part of the second gate structure is also located on the second region; and forming a second source doping region in the second body region on one side of the second gate structure while forming the first source doping region.

[0025] Optionally, the method further includes: forming a first source contact layer on a portion of the surface of the first source doping region, the first source contact layer and the first gate structure being separate from each other; forming a first gate contact layer on the surface of the first gate structure; and forming a drain contact layer on the second surface.

[0026] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first body region is formed in the drift region of the first region, and a plurality of columnar regions are formed in the drift region of the second region, each of the columnar regions extends from the first surface toward the second surface, and the conductivity type of the plurality of columnar regions is different from the conductivity type of the drift region. The plurality of columnar regions and the drift region form a superjunction structure, which is beneficial to improving the breakdown voltage of the formed device. At the same time, compared with setting the columnar region between the drain doping region and the first body region, the setting position of the plurality of columnar regions increases the current path between the first source doping region and the drain doping region, and the PN junction resistance formed between the columnar region and the drift region has less influence on the current path, which is beneficial to reducing the on-resistance of the device, thereby improving the performance of the device as a whole.

[0028] Furthermore, the plurality of columnar regions are formed by first forming the grooves and then filling them. Compared with the super junction structure formed by ion implantation, this is beneficial to improving the uniformity of doping concentration distribution and reducing process difficulty and complexity.

[0029] In the semiconductor structure provided by the technical solution of the present invention, a first body region is located in the drift region of the first region, and several columnar regions are located in the drift region of the second region. Each of the columnar regions extends from the first surface toward the second surface. The conductivity type of several of the columnar regions is different from the conductivity type of the drift region. Several columnar regions and the drift region form a super junction structure, which is beneficial to improving the breakdown voltage of the formed device. At the same time, compared with setting the columnar region between the drain doping region and the first body region, the setting position of the several columnar regions increases the current path between the first source doping region and the drain doping region, and the PN junction resistance formed between the columnar region and the drift region has less influence on the current path, which is beneficial to reducing the on-resistance of the device, thereby improving the performance of the device as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the structure of a super junction VDMOS device;

[0031] Figures 2 to 16 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 17 to 20 1 is a structural schematic diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0033] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0034] As described in the background art, the performance of existing superjunction VDMOS devices still needs to be improved. An example of a VDMOS device will now be described and analyzed.

[0035] Figure 1 It is a structural diagram of a VDMOS device.

[0036] Please refer to Figure 1 The VDMOS device includes: an N+ substrate 100, the N+ substrate 100 having a first surface (not shown in the figure) and a second surface (not shown in the figure) opposite to each other; a drain contact layer 101 located on the second surface; an N-drift region 102 and a doped region located on the first surface, the doped region being located on both sides of the drift region 102, the doped region including a P column 103, a P well 104 located on the P column 103, and a source doped region 105 located within the P well 104; a gate structure located on a surface of the N-drift region 102 and extending to a portion of the surface of the P well 104 and the source doped region 105, the gate structure including a gate oxide layer 106 and a gate layer 107 located on a surface of the gate oxide layer 106; a source contact layer 108 located on a portion of the surface of the P well 104 and a portion of the surface of the source doped region 105, the source contact layer 108 and the gate structure being separate from each other.

[0037] In the above VDMOS device, the N+ substrate 100 serves as a drain doping region, and the drift region of the VDMOS device is a super junction structure formed by the P column 103 and the N− drift region 102 , which is beneficial to improving the breakdown voltage of the VDMOS device.

[0038] However, in the process of manufacturing the above-mentioned superjunction structure, the width of the P column 103 is difficult to reduce due to the limitation of the lithography capability of the ion implantation mask. Moreover, the P column 103 is located between the P well 104 and the drain doping region. The large volume of the P column 103 not only occupies a large amount of the drift region carrier path, but also causes P-type diffusion phenomenon during device heat dissipation during operation, further increasing the on-resistance.

[0039] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, in which a plurality of columnar regions and the drift region form a superjunction structure, which is beneficial to improving the breakdown voltage of the formed device. At the same time, compared with setting the columnar region between the drain doping region and the first body region, the setting position of the plurality of columnar regions increases the current path between the source doping region and the drain doping region, and the PN junction resistance formed between the columnar region and the drift region has less influence on the current path, which is beneficial to reducing the on-resistance of the device, thereby improving the performance of the device as a whole.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 16 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 2 and Figure 3 , Figure 2 for Figure 3 Schematic diagram of the top view of the structure, Figure 3 for Figure 2 The cross-sectional structural schematic diagram along the EE1 direction forms a substrate structure, wherein the substrate structure includes a drain-doped region 201 and a drift region 202 located on the drain-doped region 201, and the substrate structure has a first surface 200a and a second surface 200b relative to each other, wherein the first surface 200a exposes the surface of the drift region 202, and the second surface 200b exposes the surface of the drain-doped region 201, the drift region 202 and the drain-doped region 201 have the same conductivity type, and the doping concentration of the drift region 202 is lower than the doping concentration of the drain-doped region 201, and the substrate structure includes adjacent first regions I and second regions II, and the first regions I and the second regions II are arranged in a direction parallel to the first surface 200a or the second surface 200b.

[0043] In this embodiment, the substrate structure further includes: a third region III adjacent to the second region II, and the second region II is located between the first region I and the third region III. In another embodiment, the substrate structure may include only the first region and the second region, but not the third region.

[0044] In this embodiment, the method for forming the substrate structure includes: providing a substrate, using the substrate as the drain doping region 201 ; forming an epitaxial layer on a surface of the substrate, using the epitaxial layer as the drift region 202 .

[0045] In other embodiments, the substrate structure may be formed by first forming an epitaxial layer and then doping, or by directly doping the substrate, etc., which is not limited here.

[0046] In this embodiment, the conductivity type of the drain doping region 201 and the drift region 202 is N-type, and is used to form an NMOS device.

[0047] In another embodiment, the conductivity type of the drain doping region and the drift region may be P-type, so as to form a PMOS device.

[0048] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 Schematic diagram of the top view of the structure, Figure 5for Figure 4 In the schematic diagram of the cross-sectional structure along the EE1 direction, a first body region 205 is formed in the drift region 202 of the first region I, and the first body region 205 extends from the first surface 200a to the second surface 200b. The conductivity type of the first body region 205 is different from the conductivity type of the drift region 202.

[0049] In this embodiment, the conductivity type of the first body region 205 is P-type. In another embodiment, the conductivity type of the first body region may be N-type.

[0050] In this embodiment, the method for forming the first body region 205 includes: forming a second mask layer 203 on the first surface 200a, the second mask layer 203 exposing the first surface 200a of the first region I; using the second mask layer 203 as a mask, injecting dopant ions into the first surface 200a to form the first body region 205.

[0051] In this embodiment, a protective layer 204 is formed on the first surface 200a before forming the second mask layer 203. The protective layer 204 protects the first surface 200a and reduces damage to the first surface 200a when dopant ions are implanted into the first surface 200a. In another embodiment, the protective layer may not be formed.

[0052] The material of the protective layer 204 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the protective layer 204 is silicon oxide.

[0053] In this embodiment, while forming the first body region 205, the second body region 206 is also formed in the drift region 202 of the third region III. The second body region 206 extends from the first surface 200a toward the second surface 200b. The conductivity type of the second body region 206 is different from the conductivity type of the drift region 202.

[0054] Specifically, the second mask layer 203 further exposes the first surface 200 a of the third region III, and the dopant ions are further implanted into the drift region 202 of the third region III to form the second body region 206 .

[0055] In this embodiment, after the first body region 205 and the second body region 206 are formed, the second mask layer 203 and the protection layer 204 are further removed.

[0056] The material of the second mask layer 203 includes a photoresist material.

[0057] Subsequently, a plurality of columnar regions are formed in the drift region 202 of the second region II. Each of the columnar regions extends from the first surface 200a to the second surface 200b. The conductivity type of the plurality of columnar regions is different from that of the drift region 202. In this embodiment, the method for forming the plurality of columnar regions is described in detail. Figures 6 to 9 .

[0058] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Schematic diagram of the top view of the structure, Figure 7 for Figure 6 In the schematic cross-sectional structure diagram along the EE1 direction, a first mask layer 207 is formed on the first surface 200a, and the first mask layer 207 exposes a portion of the second region II; the drift region 202 is etched using the first mask layer 207 as a mask; and a plurality of grooves 208 are formed in the drift region 202.

[0059] The material of the first mask layer 207 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first mask layer 207 is silicon oxide.

[0060] The formation process of the plurality of grooves 208 includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the formation process of the plurality of grooves 208 is a dry etching process, which is conducive to improving the morphology performance of the formed grooves 208.

[0061] Please refer to Figure 8 and Figure 9 , Figure 8 for Figure 9 Schematic diagram of the top view of the structure, Figure 9 for Figure 8 In the schematic cross-sectional structure diagram along the EE1 direction, a plurality of columnar regions 209 are formed in the plurality of grooves 208, and each of the columnar regions 209 extends from the first surface 200a toward the second surface 200b, and the conductivity type of the plurality of columnar regions 209 is different from the conductivity type of the drift region 202.

[0062] At this point, several columnar regions 209 and the drift region 202 form a super junction structure, which is beneficial to improving the breakdown voltage of the formed device. At the same time, compared with setting the columnar region 209 between the drain doping region 201 and the first body region 205, the setting position of several columnar regions 209 increases the current path between the first source doping region 216 and the drain doping region 201, and the PN junction resistance formed between the columnar region 209 and the drift region 202 has less influence on the current path, which is beneficial to reducing the on-resistance of the device, thereby improving the performance of the device as a whole.

[0063] Furthermore, the plurality of columnar regions 209 are formed by first forming the grooves 208 and then filling them. Compared with the super junction structure formed by ion implantation, this method is beneficial to improving the uniformity of doping concentration distribution and reducing process difficulty and complexity.

[0064] It should be noted that, in order to improve the performance of the super junction structure, the number and depth of the columnar regions 209 , the size of a single columnar region 209 , etc., can be adjusted according to the doping concentration of the drift region 202 , etc.

[0065] In other embodiments, a method for forming several columnar regions may also be adopted: a graphic mask layer is formed on the surface of the drift region, and doping ions are injected into the drift region using the graphic mask layer as a mask. However, the uniformity of the doping concentration of the columnar region formed by ion injection is difficult to control, and the performance is not as good as the performance of the columnar region in the technical solution of this embodiment.

[0066] In this embodiment, the conductivity type of the pillar regions 209 is P-type. In another embodiment, the conductivity type of the pillar regions may be N-type.

[0067] The materials of the columnar regions 209 include semiconductor materials, and the semiconductor materials include silicon, silicon carbide, silicon germanium, and multi-element semiconductor materials composed of group III-V elements.

[0068] In this embodiment, the material of the plurality of columnar regions 209 is silicon. Specifically, the material of the plurality of columnar regions 209 is polysilicon.

[0069] In this embodiment, the method for forming the plurality of columnar regions 209 in the plurality of grooves 208 includes: forming a semiconductor material layer (not shown in the figure) in the plurality of grooves 208 and on the surface of the first mask layer 207; and flattening the semiconductor material layer and the first mask layer 207 until the first surface 200a is exposed.

[0070] Subsequently, a first gate structure is formed on the first surface 200 a , wherein a portion of the first gate structure is located on the first region I, and another portion of the first gate structure is also located on the second region II.

[0071] In this embodiment, while forming the first gate structure, a second gate structure is also formed on the first surface 200a. Part of the second gate structure is located on the third region III, and another part of the second gate structure is also located on the second region II. In another embodiment, another part of the first gate structure is also located on the third region.

[0072] In this embodiment, the method for forming the first gate structure and the second gate structure can be referred to Figures 10 to 12 .

[0073] Please refer to Figure 10 , Figure 10 The viewing direction is the same as Figure 9 , a gate oxide material layer 210 is formed on the first surface 200 a ; and a gate material layer 211 is formed on the surface of the gate oxide material layer 210 .

[0074] In this embodiment, the gate oxide material layer 210 is made of silicon oxide; and the gate material layer 211 is made of polysilicon.

[0075] Please refer to Figure 11 and Figure 12 , Figure 11 for Figure 12 Schematic diagram of the top view of the structure, Figure 12 for Figure 11 In the schematic cross-sectional structure diagram along the EE1 direction, the gate material layer 211 and the gate oxide material layer 210 are graphed, the gate material layer 211 is used to form a first gate layer 212, and the gate oxide material layer 210 is used to form the first gate oxide layer 213, and the first gate structure includes the first gate oxide layer 213 and the first gate layer 212.

[0076] In this embodiment, the gate material layer 211 is used to form a second gate layer 214 , and the gate oxide material layer 210 is used to form the second gate oxide layer 215 . The second gate structure includes the second gate oxide layer 215 and the second gate layer 214 .

[0077] In another embodiment, a portion of the first gate structure is located on the third region.

[0078] Please refer to Figure 13 and Figure 14 , Figure 13 for Figure 14 Schematic diagram of the top view of the structure, Figure 14 for Figure 13 In the cross-sectional structural diagram along the EE1 direction, a first source doping region 216 is formed in the first body region 205 on one side of the first gate structure.

[0079] The conductivity type of the first source doping region 216 is the same as the conductivity type of the drain doping region 201. In this embodiment, the conductivity type of the first source doping region 216 is N-type.

[0080] In another embodiment, the conductivity type of the first source doping region may be P-type.

[0081] In this embodiment, while forming the first source doping region 216 , a second source doping region 217 is also formed in the second body region 206 on one side of the second gate structure.

[0082] In another embodiment, while forming the first source doping region, a second source doping region is also formed in the second body region on the other side of the first gate structure.

[0083] Please refer to Figure 15 and Figure 16 , Figure 15 for Figure 16 Schematic diagram of the top view of the structure, Figure 17 for Figure 16 In the schematic cross-sectional structure diagram along the EE1 direction, a first source contact layer 218 is formed on a portion of the surface of the first source doping region 216, and the first source contact layer 218 and the first gate structure are separate from each other; a first gate contact layer 219 is formed on the surface of the first gate structure; and a drain contact layer 220 is formed on the second surface 200b.

[0084] In this embodiment, a second source contact layer 221 is further formed on a portion of the surface of the second source doping region 206 , and the second source contact layer 221 and the second gate structure are separated from each other.

[0085] In this embodiment, a second gate contact layer 222 is further formed on the surface of the second gate structure.

[0086] Here, the materials of the first source contact layer 218 , the second source contact layer 221 , the first gate contact layer 219 , the second gate contact layer 222 , and the drain contact layer 220 include metal silicide materials to reduce contact resistance.

[0087] In another embodiment, the first source contact layer, the second source contact layer, the first gate contact layer, the second gate contact layer, and the drain contact layer may not be formed.

[0088] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 15 and Figure 16, comprising: a substrate structure, the substrate structure comprising a drain-doped region 201 and a drift region 202 located on the drain-doped region 201, the substrate structure having a first surface 200a and a second surface 200b opposite to each other, the first surface 200a exposing the drift region 202, the second surface 200b exposing the drain-doped region 200b, the drift region 202 and the drain-doped region 201 having the same conductivity type, and the doping concentration of the drift region 202 being lower than the doping concentration of the drain-doped region 201, the substrate structure comprising adjacent first regions I and second regions II, the first regions I and the second regions II being arranged in a direction parallel to the first surface 200a or the second surface 200b; a first body region 202 located in the drift region 202 of the first region I 05, the first body region 205 extends from the first surface 200a toward the second surface 200b, and the conductivity type of the first body region 205 is different from the conductivity type of the drift region 202; a plurality of columnar regions 209 located in the drift region 202 of the second region II, each of the columnar regions 209 extending from the first surface 200a toward the second surface 200b, and the conductivity type of several of the columnar regions 209 is different from the conductivity type of the drift region 202; a first gate structure located on the first surface 200a, part of the first gate structure is located on the first region I, and another part of the first gate structure is also located on the second region II; a first source doping region 216 located in the first body region 205 on one side of the first gate structure.

[0089] At this point, several columnar regions 209 and the drift region 202 form a super junction structure, which is beneficial to improving the breakdown voltage of the formed device. At the same time, compared with setting the columnar region 209 between the drain doping region 201 and the first body region 205, the setting position of several columnar regions 209 increases the current path between the first source doping region 216 and the drain doping region 201, and the PN junction resistance formed between the columnar region 209 and the drift region 202 has less influence on the current path, which is beneficial to reducing the on-resistance of the device, thereby improving the performance of the device as a whole.

[0090] In this embodiment, the semiconductor structure further includes: a plurality of grooves 208 (such as Figure 6 and Figure 7 As shown), the plurality of columnar regions 209 are located within the plurality of grooves 208 .

[0091] The material of the columnar regions 209 includes semiconductor materials, including silicon, silicon carbide, silicon germanium, and multi-component semiconductor materials composed of Group III-V elements. In this embodiment, the material of the columnar regions 209 is polysilicon.

[0092] In this embodiment, the first gate structure includes a first gate oxide layer 213 and a first gate layer 212 located on a surface of the first gate oxide layer 213 .

[0093] In this embodiment, the substrate structure further includes: a third region III adjacent to the second region II, and the second region II is located between the first region I and the third region III.

[0094] In this embodiment, the semiconductor structure further includes: a second body region 206 located in the drift region 202 of the third region III, the second body region 206 extending from the first surface 200a toward the second surface 200b, and the conductivity type of the second body region 206 is different from the conductivity type of the drift region 202.

[0095] In this embodiment, the semiconductor structure also includes: a second gate structure located on the first surface 200a, part of the second gate structure is located on the third region III, and another part of the second gate structure is also located on the second region II; a second source doping region 217 located in the second body region 206 on one side of the second gate structure.

[0096] In this embodiment, the semiconductor structure also includes: a first source contact layer 218 located on a surface of a portion of the first source doping region 216, the first source contact layer 218 and the first gate structure being separate from each other; a first gate contact layer 219 located on the surface of the first gate structure; and a drain contact layer 220 located on the second surface 200b.

[0097] In this embodiment, the semiconductor structure further includes: a second source contact layer 221 located on a surface of a portion of the second source doping region 206 , the second source contact layer 221 and the second gate structure being separate from each other; and a second gate contact layer 222 located on a surface of the second gate structure.

[0098] Figures 17 to 20 1 is a structural schematic diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0099] The main differences between this embodiment and the previous embodiment are:

[0100] In the previous embodiment, the first gate structure and the second gate structure are separate from each other;

[0101] In this embodiment, part of the first gate structure is located on the third region, that is, two adjacent devices share the first gate structure.

[0102] Please Figures 2 to 10 Based on the reference Figure 17 and Figure 18, patterning the gate material layer 211 and the gate oxide material layer 210, forming a first gate layer 301 with the gate material layer 211, and forming the first gate oxide layer 302 with the gate oxide material layer 210, the first gate structure includes the first gate oxide layer 302 and the first gate layer 301.

[0103] In this embodiment, a portion of the first gate structure is also located on the third region III.

[0104] Please refer to Figure 19 and Figure 20 , a first source doping region 303 is formed in the first body region 205 on one side of the first gate structure.

[0105] While forming the first source doping region 303 , a second source doping region 304 is also formed in the second body region 206 on the other side of the first gate structure.

[0106] Please continue to refer to Figure 19 and Figure 20 A first source contact layer 305 is formed on a portion of the surface of the first source doping region 303, and the first source contact layer 305 and the first gate structure are separated from each other; a first gate contact layer 306 is formed on the surface of the first gate structure; and a drain contact layer 307 is formed on the second surface 200b.

[0107] In this embodiment, a second source contact layer 308 is further formed on a portion of the surface of the second source doping region 304 , and the second source contact layer 308 and the second gate structure are separated from each other.

[0108] In this embodiment, a second gate contact layer 309 is further formed on the surface of the second gate structure.

[0109] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 19 and Figure 20 .

[0110] The main differences between this embodiment and the previous embodiment are:

[0111] In the previous embodiment, the first gate structure and the second gate structure are separate from each other;

[0112] In this embodiment, part of the first gate structure is located on the third region III, that is, two adjacent devices share the first gate structure.

[0113] In this embodiment, the semiconductor structure further includes a second source doping region 217 located in the second body region 206 on the other side of the first gate structure.

[0114] In this embodiment, for the description of other parts of the semiconductor structure, please refer to the previous embodiment and will not be repeated here.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate structure comprising a drain-doped region and a drift region located on the drain-doped region, the substrate structure having a first surface and a second surface opposite each other, the first surface exposing a surface of the drift region, the second surface exposing a surface of the drain-doped region, the drift region and the drain-doped region having the same conductivity type, and a doping concentration of the drift region being lower than a doping concentration of the drain-doped region, the substrate structure comprising adjacent first and second regions, the first region and the second region being arranged in a direction parallel to the first surface or the second surface; a first body region located in the drift region of the first area, the first body region extending from the first surface toward the second surface, the first body region having a conductivity type different from that of the drift region; a plurality of columnar regions located in the drift region of the second region, wherein the plurality of columnar regions extend from the first surface toward the second surface, the conductivity type of the plurality of columnar regions is different from the conductivity type of the drift region, and the plurality of columnar regions are not disposed between the first body region and the drain doped region; a first gate structure located on the first surface, wherein a portion of the first gate structure is located on the first region, and another portion of the first gate structure is also located on the second region; A first source doping region is located in the first body region on one side of the first gate structure.

2. The semiconductor structure according to claim 1, wherein Also includes: Several grooves are located in the drift region of the second region, and several columnar regions are located in the grooves; the material of the columnar regions includes semiconductor material, and the semiconductor material includes silicon, silicon carbide, silicon germanium, and a multi-element semiconductor material composed of III-V group elements.

3. The semiconductor structure according to claim 1, wherein: The first gate structure includes a first gate oxide layer and a first gate layer located on a surface of the first gate oxide layer.

4. The semiconductor structure according to claim 1, wherein: The substrate structure also includes: a third region adjacent to the second region, the second region being located between the first region and the third region; and also includes: a second body region located in the drift region of the third region, the second body region extending from the first surface toward the second surface, the conductivity type of the second body region being different from the conductivity type of the drift region.

5. The semiconductor structure according to claim 4, wherein: A portion of the first gate structure is located on the third region; and further comprising: a second source doping region located in the second body region on the other side of the first gate structure.

6. The semiconductor structure according to claim 4, wherein: Also includes: A second gate structure is located on the first surface, part of the second gate structure is located on the third region, and another part of the second gate structure is also located on the second region; a second source doping region is located in the second body region on one side of the second gate structure.

7. The semiconductor structure according to claim 4, wherein: Also includes: a first source contact layer located on a surface of a portion of the first source doping region, the first source contact layer and the first gate structure being separate from each other; and a first gate contact layer located on a surface of the first gate structure; A drain contact layer is located on the second surface.

8. A method for forming a semiconductor structure, characterized in that: include: forming a substrate structure, the substrate structure including a drain-doped region and a drift region located on the drain-doped region, the substrate structure having a first surface and a second surface opposite each other, the first surface exposing the drift region, the second surface exposing the drain-doped region, the drift region and the drain-doped region having the same conductivity type, and a doping concentration of the drift region being lower than a doping concentration of the drain-doped region, the substrate structure including adjacent first and second regions, the first region and the second region being arranged in a direction parallel to the first surface or the second surface; forming a first body region in the drift region of the first area, the first body region extending from the first surface toward the second surface, the first body region having a conductivity type different from that of the drift region; forming a plurality of columnar regions in the drift region of the second region, wherein the plurality of columnar regions extend from the first surface toward the second surface, the conductivity type of the plurality of columnar regions is different from the conductivity type of the drift region, and the plurality of columnar regions are not disposed between the first body region and the drain doped region; forming a first gate structure on the first surface, wherein a portion of the first gate structure is located on the first region, and another portion of the first gate structure is also located on the second region; A first source doping region is formed in the first body region on one side of the first gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming a plurality of columnar regions includes: forming a first mask layer on a first surface, wherein the first mask layer exposes a portion of the second region; etching the drift region using the first mask layer as a mask; forming a plurality of grooves in the drift region; and forming a plurality of the columnar regions in the plurality of grooves.

10. The method for forming a semiconductor structure according to claim 9, wherein: The materials of the columnar regions include semiconductor materials, and the semiconductor materials include silicon, silicon carbide, silicon germanium, and multi-element semiconductor materials composed of III-V group elements.

11. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the first mask layer includes: forming a patterned photoresist layer on the surface of the drift region; and forming the first mask layer on the surface of the drift region exposed by the photoresist layer using a selective growth process.

12. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the plurality of columnar regions in the plurality of grooves includes: forming a semiconductor material layer in the plurality of grooves and on the surface of the first mask layer; and planarizing the semiconductor material layer and the first mask layer until the first surface is exposed.

13. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the substrate structure includes: providing a substrate, using the substrate as the drain doping region; forming an epitaxial layer on the surface of the substrate, using the epitaxial layer as the drift region.

14. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first body region includes: forming a second mask layer on the first surface, the second mask layer exposing the first surface of the first region; and using the second mask layer as a mask to implant dopant ions into the first surface to form the first body region.

15. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the second mask layer, a protective layer is also formed on the first surface; the material of the protective layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

16. The method for forming a semiconductor structure according to claim 8, wherein: The first gate structure includes a first gate oxide layer and a first gate layer located on a surface of the first gate oxide layer; The method for forming the first gate structure includes: forming a gate oxide material layer on the first surface; forming a gate material layer on the surface of the gate oxide material layer; patterning the gate material layer and the gate oxide material layer, forming a first gate layer with the gate material layer, and forming the first gate oxide layer with the gate oxide material layer.

17. The method for forming a semiconductor structure according to claim 8, wherein: The substrate structure also includes: a third region adjacent to the second region, and the second region is located between the first region and the third region; the method also includes: while forming the first body region, forming a second body region in the drift region of the third region, the second body region extends from the first surface toward the second surface, and the conductivity type of the second body region is different from the conductivity type of the drift region.

18. The method for forming a semiconductor structure according to claim 17, wherein: A portion of the first gate structure is located on the third region; the method further includes: forming a second source doping region in the second body region on the other side of the first gate structure while forming the first source doping region.

19. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: While forming the first gate structure, a second gate structure is formed on the first surface, part of the second gate structure is located on the third region, and another part of the second gate structure is also located on the second region; while forming the first source doping region, a second source doping region is formed in the second body region on one side of the second gate structure.

20. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: A first source contact layer is formed on a portion of the surface of the first source doping region, the first source contact layer and the first gate structure being separate from each other; a first gate contact layer is formed on the surface of the first gate structure; and a drain contact layer is formed on the second surface.

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