Vertical gallium oxide UMOSFET device and preparation method thereof

Abstract

The invention discloses a vertical gallium oxide UMOSFET device and a preparation method thereof, and belongs to the technical field of semiconductors, the device comprises an N + type gallium oxide substrate, an N type gallium oxide drift region, a P well, an N + type source region, a gate dielectric layer, a polycrystalline silicon layer, a source electrode ohmic contact, a drain electrode ohmic contact, a gate contact layer, a source electrode and a drain electrode; wherein the N type gallium oxide drift region comprises a first drift region located on the upper surface of the N + type gallium oxide substrate and a second drift region located on the upper surface of the first drift region; a groove is etched in the first drift region; the groove is filled with a dielectric layer, and the bottom and the side wall of the groove are covered with a P-type charge balance regulation and control layer to form a super junction structure. According to the design, a gallium oxide-based vertical super junction device is realized by utilizing etching and heterogeneous backfill technologies, and the problems that an effective vertical super junction structure device is difficult to form and a terminal is difficult to design due to the fact that effective P-type ion implantation cannot be carried out on gallium oxide are solved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a vertical gallium oxide UMOSFET device and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) has a very promising application prospect in MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor) power devices, mainly due to its excellent material properties and ability to be suitable for high-power and high-frequency applications. The wide bandgap characteristics of gallium oxide give it an extremely high breakdown voltage, which can theoretically reach several thousand volts, making it suitable for applications in fields such as high-voltage power supplies and electric vehicles. Due to its unique crystal structure and doping characteristics, gallium oxide MOSFET has a lower on-resistance in the on state, thereby reducing power consumption and improving energy conversion efficiency. Gallium oxide MOSFET has a faster switching speed than traditional silicon (Si)-based and silicon carbide (SiC)-based devices, and is suitable for high-frequency applications such as switching power supplies and radio frequency amplifiers. As the global demand for high-efficiency power electronic devices increases, the market potential of gallium oxide MOSFET is huge and is expected to promote the development of related technologies and applications.

[0003] As a representative device for 1200V applications, superjunction UMOSFET (U-shaped gate trench structure MOSFET) is expected to break the one-dimensional limit of the material and further improve the performance of the device. However, superjunction devices require a deep P junction to balance the electric field, and gallium oxide cannot be effectively implanted with P-type ions, making it difficult to form an effective vertical superjunction structure device; and the device terminal area usually also requires P-type ion implantation, which also makes it impossible for gallium oxide devices to perform effective terminal design, which greatly limits the development of gallium oxide-based power semiconductor devices. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a vertical gallium oxide UMOSFET device and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions: In a first aspect, the present invention provides a vertical gallium oxide UMOSFET device, comprising: N+ type gallium oxide substrate; An N-type gallium oxide drift region comprises a first drift region located on an upper surface of an N+-type gallium oxide substrate and a second drift region located on an upper surface of the first drift region; a groove is etched in the first drift region; A P-type charge balance control layer covers the bottom and sidewalls of the trench to form a P column of a super junction structure; A dielectric layer is filled in the trench; A P well is disposed in the second drift region and is located directly above the trench; N+ type source region, located in the P well; A gate dielectric layer and a polysilicon layer are stacked on the upper surface of the second drift region and are etched to form a gate structure of the device; A dielectric isolation layer is disposed on the polysilicon layer and has a window to expose the N+ type source region and a portion of the polysilicon layer; A source ohmic contact is provided on the surface of the exposed N+ type source region; A drain ohmic contact is arranged on the lower surface of the N+ type gallium oxide substrate; A gate contact layer is disposed on the exposed polysilicon layer; A source electrode is arranged on the front side of the entire device; The drain electrode is arranged on the lower surface of the drain ohmic contact.

[0005] In a second aspect, the present invention provides a method for preparing a vertical gallium oxide UMOSFET device, comprising: epitaxially growing N-type gallium oxide on an N+-type gallium oxide substrate to form a first drift region; Etching the first drift region to form a groove required for the super junction structure P column; A P-type charge balance regulating layer is grown on the bottom and sidewalls of the trench, and a dielectric layer is filled in the trench to form a super junction structure; epitaxially growing a second drift region on the surface of the first drift region to form a complete N-type gallium oxide drift region; A P-well is fabricated in the second drift region, and ion implantation is performed on the P-well to form an N+ type source region in the P-well; A gate dielectric layer and a polysilicon layer are sequentially deposited on the upper surface of the second drift region, and a gate structure of the device is formed by etching; A dielectric isolation layer is deposited on the surface of the device obtained in the previous step, and a window is opened in the source region to expose the N+ type source region; Depositing metal on the N+ type source region and the lower surface of the N+ type gallium oxide substrate to form a source ohmic contact and a drain ohmic contact; Opening a hole in the dielectric isolation layer and depositing metal to form a gate contact layer; Metal is deposited across the front and back sides of the device to form the source and drain electrodes of the device.

[0006] Beneficial effects of the present invention: A vertical gallium oxide UMOSFET device provided by the present invention includes an N+ type gallium oxide substrate, an N-type gallium oxide drift region, a P-type charge balance control layer, a gate structure and a source-drain electrode; wherein the N-type gallium oxide drift region includes a first drift region located on the upper surface of the N+ type gallium oxide substrate and a second drift region located on the upper surface of the first drift region; a groove is etched in the first drift region; the groove is filled with a dielectric layer, and the P-type charge balance control layer covers the bottom and sidewalls of the groove to form a vertical super junction structure gallium oxide UMOSFET device. This design uses etching and heterogeneous backfilling technology to realize a gallium oxide-based vertical super junction device, solving the problem of difficulty in forming an effective vertical super junction structure device and difficulty in terminal design due to the inability to effectively perform P-type ion implantation on gallium oxide; and the vertical UMOSFET enables gallium oxide-based power devices to break through the traditional one-dimensional limit, achieve lower on-resistance, and greatly improve the performance of the device.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a structural schematic diagram of a vertical gallium oxide UMOSFET device provided by an embodiment of the present invention; Figure 2 It is a schematic flow chart of a method for preparing a vertical gallium oxide UMOSFET device provided by an embodiment of the present invention; Figure 3a-3m It is a schematic diagram of a process for preparing a vertical gallium oxide UMOSFET device provided in an embodiment of the present invention.

[0009] Description of reference numerals: 1-N+ type gallium oxide substrate, 2-N type gallium oxide drift region, 2A-first drift region, 2A1-trench, 2B-second drift region, 3-P type charge balance control layer, 4-dielectric layer, 5-P well, 6-N+ type source region, 7-gate dielectric layer, 8-polysilicon layer, 9-dielectric isolation layer, 10-source ohmic contact, 11-drain ohmic contact, 12-gate contact layer, 13-source electrode, 14-drain electrode. DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0011] The first aspect of the present invention provides a vertical gallium oxide UUMOSFET device. Figure 1 , Figure 1 1 is a schematic diagram of the structure of a vertical gallium oxide UMOSFET device provided by an embodiment of the present invention. The device includes: N+ type gallium oxide substrate 1; The N-type gallium oxide drift region 2 comprises a first drift region 2A located on the upper surface of the N+ type gallium oxide substrate 1 and a second drift region 2B located on the upper surface of the first drift region 2A; a groove 2A1 is etched in the first drift region 2A; A P-type charge balance regulating layer 3 covers the bottom and sidewalls of the trench 2A1 to form a P column of a super junction structure; A dielectric layer 4 is filled in the trench 2A1; A P well 5 is provided in the second drift region 2B and is located directly above the trench 2A1; N+ type source region 6, located in the P well 5; A gate dielectric layer 7 and a polysilicon layer 8 are stacked on the upper surface of the second drift region 2B and are etched to form a gate structure of the device; A dielectric isolation layer 9 is disposed on the polysilicon layer 8 and has a window opening to expose the N+ type source region 6 and a portion of the polysilicon layer 8; A source ohmic contact 10 is disposed on the surface of the exposed N+ type source region 6; A drain ohmic contact 11 is provided on the lower surface of the N+ type gallium oxide substrate 1; A gate contact layer 12 is disposed on the exposed polysilicon layer 8; A source electrode 13 is provided on the front side of the entire device; The drain electrode 14 is disposed on the lower surface of the drain ohmic contact 11 .

[0012] Optionally, in this embodiment, the material of the N+ type gallium oxide substrate 1 is a heavily doped N type β -Ga2O3, doping concentration 5E18cm -3 -1E19cm -3 , with a thickness of 100μm-300μm. The material of the N-type gallium oxide drift region 2 is N-type β -Ga2O3, doping concentration 6E16cm -3 -1E17cm -3 , the doping element is one of Sn, Si, and Ge; wherein the thickness of the first drift region 2A is 10 μm, and the thickness of the second drift region 2B is 2 μm.

[0013] In this embodiment, the number of the grooves 2A1 is 2, and the dielectric layer 4 filled therein is preferably SiO2. The material of the P-type charge balance control layer 3 covering the bottom and sidewall of the groove 2A1 is P-type NiO, with a thickness of 200nm and a doping concentration of 1E17cm -3 -5E17cm -3 , the doping element is Mg.

[0014] In this embodiment, a vertical super junction structure is formed by etching a trench 2A1 in the first drift region 2A, performing heterogeneous filling on the trench 2A1, and covering the bottom and sidewalls of the trench with P-type NiO. The electric field can be regulated by covering the sidewalls of the trench with P-type NiO, so that the electric field presents a rectangular distribution and the breakdown is delayed. Together with Ga2O3, it can bring about a lower resistance in the drift region of the device, thereby reducing the on-resistance of the device.

[0015] It is understandable that the groove 2A1 in the first drift region 2A reserves a certain space from the bottom of the first drift region 2A. The depth of the groove 2A1 is related to the P-type charge balance control layer 3 to be designed, and is specifically determined by the withstand voltage level of the device. Generally speaking, when the withstand voltage performance of the device increases between 650V-3300V, the corresponding depth of the groove 2A1 also increases between 5μm-25μm.

[0016] For further information, please see Figure 1 , wherein the two P-wells 5 are respectively located in the second drift region 2B directly above the two trenches 2A1 , and the width of the P-well 5 is greater than the width of the trench 2A1 , and the depth is consistent with the thickness of the second drift region 2B.

[0017] Optionally, the material of the P well 5 is NiO, and the doping concentration is 1E17cm -3 -5E17cm -3 Specifically, a groove required for the P well can be etched on the second drift region 2B first, and then NiO can be epitaxially grown in the groove to form the P well 5 .

[0018] For further information, please see Figure 1 Each P well 5 is provided with two N+ source regions 6, with a width of 1 μm, a depth of 2 μm, and a doping concentration of 1E18 cm -3 -5E18cm -3 , the doping element is one of Sn, Si, and Ge.

[0019] Optionally, regarding the setting of the device gate structure, source structure and drain structure, this embodiment adopts the structural design of the existing UMOSFET device, such as Figure 1As shown, the gate dielectric layer 7 is made of Al2O3 with a thickness of 50nm; the polysilicon layer 8 is 1μm thick; the dielectric isolation layer 9 is made of SiO2 with a thickness of 1μm. The source ohmic contact 10 is made of a Ti / Au metal combination with a thickness of 50nm / 100nm; the drain ohmic contact 11 is made of a Ti / Au metal combination with a thickness of 50nm / 100nm; the gate contact layer 12 is made of Ti with a thickness of 20nm; the source electrode 13 is made of Al with a thickness of 4μm; the drain electrode 14 is made of a Ti / Ni / Ag metal combination with a thickness of 200nm / 4000nm / 10000nm.

[0020] A vertical gallium oxide UMOSFET device provided by the present invention includes an N+ type gallium oxide substrate, an N-type gallium oxide drift region, a P-type charge balance control layer, a gate structure and a source-drain electrode; wherein the N-type gallium oxide drift region includes a first drift region located on the upper surface of the N+ type gallium oxide substrate and a second drift region located on the upper surface of the first drift region; a groove is etched in the first drift region; the groove is filled with a dielectric layer, and the P-type charge balance control layer covers the bottom and sidewalls of the groove to form a vertical super junction structure gallium oxide UMOSFET device. This design uses etching and heterogeneous backfilling technology to realize a gallium oxide-based vertical super junction device, solving the problem of difficulty in forming an effective vertical super junction structure device and difficulty in terminal design due to the inability to effectively perform P-type ion implantation on gallium oxide; and the vertical UMOSFET enables gallium oxide-based power devices to break through the traditional one-dimensional limit, achieve lower on-resistance, and greatly improve the performance of the device.

[0021] Based on the same inventive concept, the second aspect of the present invention provides a method for preparing a vertical gallium oxide UMOSFET device. The preparation method provided by the present invention is described in detail below in conjunction with the accompanying drawings.

[0022] Please see the joint Figure 2 and Figure 3a-3m , Figure 2 It is a schematic flow chart of a method for preparing a vertical gallium oxide UMOSFET device provided by an embodiment of the present invention; Figure 3a-3m 1 is a schematic diagram of a process for preparing a vertical gallium oxide UMOSFET device provided by an embodiment of the present invention. The method specifically comprises the following steps: Step 1: epitaxially grow N-type gallium oxide on an N+ type gallium oxide substrate 1 to form a first drift region 2A.

[0023] Specifically, select heavily doped N-type β -Ga2O3 is used as the N+ type gallium oxide substrate 1, and high-quality N-type β-Ga2O3, forming an N-type first drift region 2A, such as Figure 3a shown.

[0024] Step 2: Etch the first drift region 2A to form the trench 2A1 required for the super junction structure P column.

[0025] Specifically, the trench 2A1 required for the super junction structure P column can be etched on the N-type first drift region 2A by using photolithography and dry etching processes, such as Figure 3b shown.

[0026] Step 3: grow a P-type charge balance control layer 3 at the bottom and sidewall of the trench 2A1, and fill the trench 2A1 with a dielectric layer 4 to form a super junction structure.

[0027] First, NiO is grown on the bottom and sidewalls of the trench 2A1 using a CVD (Chemical Vapor Deposition) method and an oxide layer self-alignment process to form a P-type charge balance control layer 3. Figure 3c shown.

[0028] Then, the groove 2A1 is filled with SiO2, and the surface is planarized by photolithography and etching processes, and finally a dielectric layer 4 is formed. Figure 3d shown.

[0029] Step 4: epitaxially grow the second drift region 2B on the surface of the first drift region 2A to form a complete N-type gallium oxide drift region 2 .

[0030] Specifically, based on step 3, continue to epitaxially grow high-quality N-type β -Ga2O3, forming the second drift region 2B, such as Figure 3e shown.

[0031] Step 5: a P-well 5 is fabricated in the second drift region 2B, and ion implantation is performed on the P-well 5 to form an N+ type source region 6 in the P-well 5 .

[0032] First, use photolithography and etching processes to etch out the grooves required for the P well 5, such as Figure 3f shown.

[0033] Then, P-type NiO is epitaxially grown by a silicon dioxide self-aligned process to form a P well 5, as shown in FIG. Figure 3g shown.

[0034] Finally, N-type epitaxial growth is achieved through photolithography and silicon dioxide self-alignment process. β -Ga2O3, and then N-type ion implantation is performed to form an N+ source region 6, such as Figure 3h shown.

[0035] Step 6: A gate dielectric layer 7 and a polysilicon layer 8 are sequentially deposited on the upper surface of the second drift region 2B, and the gate structure of the device is formed by etching.

[0036] Specifically, Al2O3 is first deposited as a gate dielectric layer 7 using an ALD (Atomic layer deposition) process, and then Poly Si is deposited by an LPCVD (Low Pressure Chemical Vapor Deposition) process to form a polysilicon layer 8; finally, a gate structure of the device is formed by an etching process, such as Figure 3i shown.

[0037] Step 7: Deposit a dielectric isolation layer 9 on the surface of the device obtained in the previous step, and open a window in the source region to expose the N+ type source region 6.

[0038] Specifically, ILD SiO2 is deposited on the surface of the device obtained in step 6 to form a dielectric isolation layer 9, and a photolithography wet etching process is used to open a window in the source region to expose the N+ type source region 6, such as Figure 3j shown.

[0039] Step 8: Deposit metal on the N+ type source region 6 and the lower surface of the N+ type gallium oxide substrate 1 to form a source ohmic contact 10 and a drain ohmic contact 11 .

[0040] Specifically, on the basis of step 7, Ti / Au metal is deposited on the front and back sides of the device respectively by electron beam evaporation process, and then the source ohmic contact 10 and the drain ohmic contact 11 are formed by metal self-alignment process, as shown in FIG. Figure 3k shown.

[0041] Step 9: Open a hole in the dielectric isolation layer 9 and deposit metal to form a gate contact layer 12.

[0042] Specifically, on the basis of step 8, a hole is opened on the dielectric isolation layer 9 by using photolithography and electron beam evaporation process, and Ti metal is deposited, and then a wet etching process is used to form a gate contact layer 12, such as Figure 3l shown.

[0043] Step 10: Deposit metal on the front and back sides of the entire device to form the source electrode 13 and the drain electrode 14 of the device.

[0044] Specifically, on the basis of step 9, Al metal is deposited on the front side using photolithography and electron beam evaporation process, and a front source electrode 13 is formed using a wet etching process, and then Ti / Ni / Ag is deposited on the back side as a back drain electrode 14, as shown in FIG. Figure 3m shown.

[0045] At this point, the preparation of the vertical gallium oxide UMOSFET device has been completed.

[0046] It should be noted that the epitaxial growth process, photolithography process, dry etching process, wet etching process, CVD process, ion implantation process, silicon dioxide self-alignment process, ALD process, LPCVD process, electron beam evaporation process, etc. used in the process of preparing the vertical gallium oxide UMOSFET device in this embodiment are all existing mature processes, and the relevant parameter settings can be implemented by referring to the existing relevant technologies.

[0047] The preparation method provided in the second aspect of the present invention can be used to prepare the vertical gallium oxide UMOSFET device provided in the first aspect, and therefore has similar beneficial effects as the device embodiment of the first aspect. The method uses etching and heterogeneous backfilling technology to realize a gallium oxide-based vertical super junction device, solving the problem of difficulty in forming an effective vertical super junction structure device and difficulty in terminal design due to the inability to effectively perform P-type ion implantation of gallium oxide; and the vertical UMOSFET enables gallium oxide-based power devices to break through the traditional one-dimensional limit, achieve lower on-resistance, and greatly improve the performance of the device. For technical details not disclosed in the embodiment of the preparation method of the present invention, they can be understood by referring to the description of the device embodiment.

[0048] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0050] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0051] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0052] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A vertical gallium oxide UMOSFET device, characterized in that: include: N+ type gallium oxide substrate (1); An N-type gallium oxide drift region (2), comprising a first drift region (2A) located on the upper surface of the N+ type gallium oxide substrate (1) and a second drift region (2B) located on the upper surface of the first drift region (2A); a groove (2A1) is etched in the first drift region (2A); A P-type charge balance regulating layer (3) covering the bottom and sidewalls of the trench (2A1) to form a P column of a super junction structure; A dielectric layer (4) filled in the groove (2A1); A P well (5) is arranged in the second drift region (2B) and is located directly above the trench (2A1); An N+ type source region (6), located in the P well (5); A gate dielectric layer (7) and a polysilicon layer (8) are stacked on the upper surface of the second drift region (2B) and are etched to form a gate structure of the device; A dielectric isolation layer (9) is disposed on the polysilicon layer (8) and exposes the N+ type source region (6) and a portion of the polysilicon layer (8) through a window; A source ohmic contact (10) is arranged on the exposed surface of the N+ type source region (6); A drain ohmic contact (11) is arranged on the lower surface of the N+ type gallium oxide substrate (1); A gate contact layer (12) is disposed on the exposed polysilicon layer (8); A source electrode (13) is arranged on the front side of the entire device; A drain electrode (14) is arranged on the lower surface of the drain ohmic contact (11).

2. A vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the N+ type gallium oxide substrate (1) is a heavily doped N-type β -Ga2O3, doping concentration 5E18cm -3 -1E19cm -3 , thickness is 100μm-300μm.

3. A vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the N-type gallium oxide drift region (2) is N-type β -Ga2O3, doping concentration 6E16cm -3 -1E17cm -3 , the doping element is one of Sn, Si, and Ge; the thickness of the first drift region (2A) is 10 μm, and the thickness of the second drift region (2B) is 2 μm.

4. A vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the P-type charge balance regulating layer (3) is P-type NiO, with a thickness of 200 nm and a doping concentration of 1E17 cm -3 -5E17cm -3 , the doping element is Mg.

5. The vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the dielectric layer (4) is SiO2.

6. A vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the P well (5) is NiO, and the doping concentration is 1E17cm -3 -5E17cm -3 , the doping element is Mg.

7. The vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The width of the N+ type source region (6) is 1 μm, the depth is 2 μm, and the doping concentration is 1E18 cm -3 -5E18cm -3 , the doping element is one of Sn, Si, and Ge.

8. The vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The gate dielectric layer (7) is made of Al2O3 and has a thickness of 50 nm; The thickness of the polysilicon layer (8) is 1 μm; The material of the dielectric isolation layer (9) is SiO2 and has a thickness of 1 μm.

9. The vertical gallium oxide UMOSFET device according to claim 1, characterized in that: The material of the source ohmic contact (10) is a Ti / Au metal combination with a thickness of 50nm / 100nm respectively; The material of the drain ohmic contact (11) is a Ti / Au metal combination with a thickness of 50nm / 100nm respectively; The gate contact layer (12) is made of Ti and has a thickness of 20 nm; The source electrode (13) is made of Al and has a thickness of 4 μm; The material of the drain electrode (14) is a metal combination of Ti / Ni / Ag, and the thicknesses are 200nm / 4000nm / 10000nm respectively.

10. A method for preparing a vertical gallium oxide UMOSFET device, characterized in that: include: epitaxially growing N-type gallium oxide on an N+-type gallium oxide substrate to form a first drift region; Etching the first drift region to form a groove required for a super junction structure P column; Growing a P-type charge balance regulating layer at the bottom and sidewalls of the trench, and filling a dielectric layer in the trench to form a super junction structure; epitaxially growing a second drift region on the surface of the first drift region to form a complete N-type gallium oxide drift region; Fabricating a P-well in the second drift region, and performing ion implantation on the P-well to form an N+ type source region in the P-well; Depositing a gate dielectric layer and a polysilicon layer in sequence on the upper surface of the second drift region, and etching to form a gate structure of the device; Depositing a dielectric isolation layer on the surface of the device obtained in the previous step, and opening a window in the source region to expose the N+ type source region; Depositing metal on the upper surface of the N+ type source region and the lower surface of the N+ type gallium oxide substrate to form a source ohmic contact and a drain ohmic contact; Opening a hole on the dielectric isolation layer and depositing metal to form a gate contact layer; Metal is deposited across the front and back sides of the device to form the source and drain electrodes of the device.

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