Method for manufacturing stacked transistors, stacked transistors, and semiconductor devices

Abstract

The present application provides a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device. The method includes: forming a stacked structure by one-time etching on a semiconductor substrate, the stacked structure including a first active structure and a second active structure; forming an oxide layer covering the stacked structure on the semiconductor substrate; forming a dummy gate structure covering the oxide layer; the dummy gate structure includes a first dummy gate structure and a second dummy gate structure; forming a first transistor based on the first active structure covered with the oxide layer; flipping the wafer and removing the semiconductor substrate; forming a second transistor based on the second active structure covered with the oxide layer; performing an oxidation process on a first portion of the first dummy gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or performing an oxidation process on a first portion of the second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and particularly to a method for manufacturing stacked transistors, a stacked transistor, and a semiconductor device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can achieve further improvement in transistor integration density, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some solutions for manufacturing stacked transistors, the active regions of upper and lower layers of homologous transistors are formed by etching, and the stacked transistors are fabricated on the front and back sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip transistor" solution. However, in the "self-aligned flip transistor" solution, deep high-aspect-ratio processes need to be used multiple times, and it is difficult to control the etching height during the process of forming the gate isolation structure between the upper and lower gate structures. Therefore, there is a certain room for optimization in the "self-aligned flip transistor" solution. Summary of the Invention

[0004] This application provides a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device to optimize the manufacturing process of the gate isolation structure in the "self-aligned flip transistor" solution.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor, including: etching a stacked structure on a semiconductor substrate at one time, where the stacked structure includes: a first active structure and a second active structure; the first active structure and the second active structure are stacked in sequence in a first direction, the first active structure is farther from the semiconductor substrate than the second active structure, and the first direction is a direction perpendicular to the semiconductor substrate; forming an oxide layer covering the stacked structure on the semiconductor substrate; forming a dummy gate structure covering the oxide layer in the gate region of the stacked transistor; the dummy gate structure includes a first dummy gate structure and a second dummy gate structure; forming a first transistor based on the first active structure covered with the oxide layer, where the first transistor includes: a first gate structure, and the first gate structure is formed based on the first dummy gate structure; flipping the wafer and removing the semiconductor substrate; forming a second transistor based on the second active structure covered with the oxide layer, where the second transistor includes: a second gate structure, and the second gate structure is formed based on the second dummy gate structure; oxidizing a first portion of the first dummy gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or oxidizing a first portion of the second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure; where the first portion of the first dummy gate structure is a portion of the first dummy gate structure close to the second dummy gate structure, the first portion of the second dummy gate structure is a portion of the second dummy gate structure close to the first dummy gate structure, and the oxide layer protects the stacked structure during the oxidation process.

[0006] In some possible implementation manners, when forming a first gate isolation structure between the first gate structure and the second gate structure, forming the first transistor based on the first active structure covered with the oxide layer includes: forming a first source / drain structure in the source / drain region of the stacked transistor based on the first active structure covered with the oxide layer; forming a first gate structure above the first gate isolation structure, and the first gate structure and the first source / drain structure together form the first transistor.

[0007] In some possible implementation manners, forming the first gate structure above the first gate isolation structure includes: depositing a gate dielectric material on the exposed first active structure to form a first gate dielectric layer covering the first active structure; depositing a metal material above the first gate dielectric layer to form a first gate electrode layer, and the first gate dielectric layer and the first gate electrode layer together form the first gate structure.

[0008] In some possible implementation manners, forming the first source / drain structure based on the first active structure covered with the oxide layer includes: removing the oxide layer not covered by the dummy gate structure; etching the stacked structure not covered by the dummy gate structure to form a first deep trench; epitaxially growing a first source / drain structure inside and outside the first deep trench based on the first active structure in the gate region.

[0009] In some possible embodiments, the stacked structure further includes: a first sacrificial layer located between the first active structure and the second active structure; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: removing the first sacrificial layer; depositing an insulating material at the position where the first sacrificial layer is removed to form an isolation structure.

[0010] In some possible embodiments, when the stacked transistor is a fully surrounding gate field effect transistor, both the first active structure and the second active structure are formed by alternately stacking a channel layer and a sacrificial layer; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: laterally etching the sacrificial layer in the first active structure within the gate region to a preset depth; depositing an insulating material at the position where the sacrificial layer is etched to form an inner sidewall.

[0011] In some possible embodiments, before epitaxially growing a first source / drain structure inside and outside the first deep trench based on the first active structure within the gate region, the method further includes: depositing an oxide material in the first deep trench to form a first filling structure, the height of the first filling structure being less than the height of the first active structure and greater than the height of the second active structure; depositing an insulating material on the first filling structure to form an isolation layer for isolating the first source / drain structure and the second source / drain structure.

[0012] In some possible embodiments, forming the stacked structure by one-time etching on a semiconductor substrate includes: forming an initial stacked structure and an initial barrier layer on the semiconductor substrate, where the initial barrier layer is located between the initial stacked structure and the semiconductor substrate; etching the initial stacked structure and the initial barrier layer at one time to form a stacked structure and a barrier layer; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: etching the barrier layer at the bottom of the first deep trench to form an etched barrier layer, where the etched barrier layer is located in the gate region; flipping the wafer and removing the semiconductor substrate, including: flipping the wafer and removing the semiconductor substrate to expose the etched barrier layer; before forming a second transistor based on the second active structure covered with an oxide layer, the method further includes: etching the first filling structure not covered by the etched barrier layer until the isolation layer is exposed.

[0013] In some possible embodiments, in the case of forming the second gate isolation structure between the first gate structure and the second gate structure, forming a second transistor based on the second active structure covered with an oxide layer includes: forming a second source / drain structure in the source / drain region of the stacked transistor based on the second active structure covered with an oxide layer; forming a second gate structure on the second gate isolation structure, the second gate structure and the second source / drain structure together constituting the second transistor.

[0014] In some possible embodiments, the method further includes: after forming the first gate structure, removing the third gate structure in the first gate structure by using a gate cutting process, and depositing an insulating material at the position where the third gate structure is removed to form a first gate isolation structure; wherein, in the second direction, the third gate structure is located at both ends of the first gate structure; the second direction is perpendicular to the first direction; and / or, after forming the second gate structure, removing the fourth gate structure in the second gate structure by using a gate cutting process, and depositing an insulating material at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

[0015] In some possible embodiments, the first transistor or the second transistor is any one of the following: fin field effect transistor, gate-all-around field effect transistor, vertical field effect transistor, complementary field effect transistor, crossbar transistor, and planar field effect transistor.

[0016] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a first transistor; a second transistor, the first transistor and the second transistor are arranged back to back, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned; the first gate structure is formed based on a first dummy gate structure; the second gate structure is formed based on a second dummy gate structure; wherein, a gate isolation structure is formed between the first gate structure and the second gate structure, and the gate isolation structure is obtained by oxidizing a first part of the first dummy gate structure and / or a first part of the second dummy gate structure, the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, and the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure.

[0017] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor as described in the above embodiment.

[0018] In the embodiments of the present disclosure, by etching once on a semiconductor substrate to form a stacked structure, the active regions of the first transistor and the second transistor in the stacked transistor can be self-aligned. Subsequently, a common dummy gate structure for the first transistor and the second transistor is formed. During the process of forming the front transistor and / or the back transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is oxidized to form a gate isolation structure in the stacked transistor by using the dummy gate structure. Subsequently, a self-aligned gate structure can be formed based on the active structure, and finally, the complete self-alignment of the first transistor and the second transistor is achieved.

[0019] In this way, on the one hand, fewer processes with high aspect ratios can be adopted, and the fully self-aligned flip-chip stacking of various types of transistors can be more compatible, realizing further optimization of the "self-aligned flip-chip transistor" solution; on the other hand, by oxidizing the pseudo-gate structure to form a gate isolation structure between the front and back transistors, the process difficulty can be reduced to a certain extent, and the quality of the gate isolation structure can be improved.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. Brief Description of the Drawings

[0021] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0022] Figure 1 It is a schematic flowchart of an implementation process of a method for manufacturing a stacked transistor according to an embodiment of this application;

[0023] Figure 2 It is a top view of a stacked transistor according to an embodiment of this application;

[0024] Figures 3 to 37 It is a schematic diagram of the manufacturing process of the first stacked transistor according to an embodiment of this application;

[0025] Figures 38 to 55 It is a schematic diagram of the manufacturing process of the second stacked transistor according to an embodiment of this application.

[0026] In the above figures: 10, stacked transistors; 11, first transistor; 12, second transistor; 112, first source / drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source / drain metal; 116, first metal interconnect layer; 122, second source / drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source / drain metal; 126, second metal interconnect layer; 20, semiconductor substrate; 21, initial stacked structure; 22, initial barrier layer; 23, stacked structure; 24, barrier layer; 25, shallow trench isolation structure; 26, dummy gate structure; 27, dummy gate sidewall; 29, first active structure; 30, first sacrificial layer; 31, second active structure; 32, second sacrificial layer; 33, isolation structure; 34, sacrificial layer; 35, channel layer; 36, inner sidewall; 37, filling structure; 37a, first filling structure; 37b, second filling structure; 38, isolation layer; 41, first isolation structure; 42, first dielectric layer; 43, insulating layer; 44, carrier wafer; 45, polysilicon structure; 46, second dielectric layer; 47, second isolation structure; 48, first deep trench; 50, oxide layer; 51, first dummy gate structure; 511, first part of the first dummy gate structure; 512, second part of the first dummy gate structure; 52, second dummy gate structure; 521, first part of the second dummy gate structure; 522, second part of the second dummy gate structure; 53, first gate isolation structure; 54, second gate isolation structure. Detailed Description of the Embodiments

[0027] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0028] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in the vertical space through three-dimensional transistor stacking, which helps to further improve the transistor integration density and circuit performance, and is considered one of the important technologies to continue the miniaturization of integrated circuit size.

[0029] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is the monolithic scheme, and the second is the sequential scheme.

[0030] In the first solution, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this solution is better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and a large amount of process technology development and optimization are required; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0031] In the second solution, it is based on wafer bonding and layer-by-layer processing. Specifically, the upper layer transistors are prepared by bonding a wafer on top of the previously fabricated lower layer transistors, stacking the two transistors vertically. However, during the thermal process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and interconnect lines. The advantage of this solution is that thanks to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matching device performance.

[0032] To solve the technical problems existing in the above two solutions, a flip-chip solution for realizing self-aligned stacked transistors is proposed. This flip-chip solution forms the active regions of the upper and lower layer homologous transistors by etching, and realizes the fabrication of stacked transistors on the front and back sides of the wafer by flipping the wafer, so as to overcome the disadvantages of the above two solutions. This can also be called the "self-aligned flip-chip transistor" solution.

[0033] However, in the "self-aligned flip-chip transistor" solution, deep high-aspect-ratio processes need to be used multiple times, and it is difficult to control the etching height during the process of forming the gate isolation structure between the upper and lower layer gate structures. Therefore, there is a certain room for optimization in the "self-aligned flip-chip transistor" solution.

[0034] To solve the above technical problems, an embodiment of the present application provides a method for fabricating stacked transistors to optimize the "self-aligned flip-chip transistor" solution.

[0035] Figure 1 For the implementation flow schematic diagram of a method for fabricating stacked transistors shown in an embodiment of the present application, see Figure 1 As shown, the method for fabricating stacked transistors may include:

[0036] Step S101: A stacked structure is etched on a semiconductor substrate at one time. The stacked structure includes: a first active structure and a second active structure; the first active structure and the second active structure are stacked in sequence in a first direction, the first active structure is farther from the semiconductor substrate than the second active structure, and the first direction is the direction perpendicular to the semiconductor substrate;

[0037] Step S102: An oxide layer covering the stacked structure is formed on the semiconductor substrate;

[0038] Step S103: In the gate region of the stacked transistor, a dummy gate structure covering the oxide layer is formed; the dummy gate structure includes a first dummy gate structure and a second dummy gate structure;

[0039] Step S104: Based on the first active structure covered with the oxide layer, a first transistor is formed. The first transistor includes: a first gate structure, and the first gate structure is formed based on the first dummy gate structure;

[0040] Step S105: The wafer is flipped and the semiconductor substrate is removed;

[0041] Step S106: Based on the second active structure covered with the oxide layer, a second transistor is formed. The second transistor includes: a second gate structure, and the second gate structure is formed based on the second dummy gate structure;

[0042] Step S107: The first part of the first dummy gate structure is oxidized to form a first gate isolation structure between the first gate structure and the second gate structure; and / or, the first part of the second dummy gate structure is oxidized to form a second gate isolation structure between the first gate structure and the second gate structure;

[0043] Wherein, the first part of the first dummy gate structure is the part of the first dummy gate structure close to the second dummy gate structure, the first part of the second dummy gate structure is the part of the second dummy gate structure close to the first dummy gate structure, and the oxide layer protects the stacked structure during the oxidation process.

[0044] It can be understood that the first direction in the embodiments of the present application may be the direction perpendicular to the substrate, the third direction may be the direction parallel to the surface of the substrate, for example, the width direction of the gate structure. The second direction may be the direction perpendicular to the third direction, for example, the length direction of the gate structure. In the third direction, the gate regions and the source / drain regions of the stacked transistors are alternately arranged in sequence, and the gate structures and the source / drain structures of the stacked transistors are alternately arranged in sequence.

[0045] In some embodiments, the material for forming the dummy gate structure may be polysilicon.

[0046] It should be noted that, Figure 1The steps shown are not exclusive, and other steps may be performed before, after, or between any of the shown operations; Figure 1 The steps shown can be adjusted in order according to actual requirements.

[0047] It can be understood that by etching a stacked structure on a semiconductor substrate at one time, the active regions of the first transistor and the second transistor in the stacked transistors can be self-aligned. Subsequently, a dummy gate structure shared by the first transistor and the second transistor is formed. During the formation of the front transistor and / or the back transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is oxidized to form a gate isolation structure in the stacked transistors using the dummy gate structure. Subsequently, a self-aligned gate structure can be formed based on the active structure, and finally, the complete self-alignment of the first transistor and the second transistor is achieved.

[0048] In this way, on the one hand, fewer high aspect ratio processes can be adopted, which is more compatible with the complete self-alignment flip-chip stacking of various types of transistors, realizing the further optimization of the "self-aligned flip transistor" solution; on the other hand, by oxidizing the dummy gate structure to form a gate isolation structure between the front and back transistors, the process difficulty can be reduced to a certain extent, and the quality of the gate isolation structure can be improved.

[0049] Figure 2 FIG. is a top view of a stacked transistor according to an embodiment of the present application. Refer to Figure 2 As shown, only the nanosheet structure, gate structure, and source / drain structure of the stacked transistor 10 are shown in the top view.

[0050] In one embodiment, the stacked transistor 10 includes a first transistor and a second transistor, and the first transistor and the second transistor are self-aligned, that is, the first source / drain structure of the first transistor and the second source / drain structure of the second transistor are self-aligned, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0051] In one embodiment, the first transistor and the second transistor can be the same type of transistor. For example, both the first transistor and the second transistor can be fin field effect transistors.

[0052] In one embodiment, according to the type of the stacked transistor, the active structure in the stacked transistor 10 can be different. In one example, when the stacked transistor 10 is a fin field effect transistor, the active structure can be a fin structure. When the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet) field effect transistor, the active structure can be a nanosheet structure; wherein, the nanosheet structure can be formed by alternately depositing silicon layers and silicon germanium layers. When the stacked transistor 10 is a planar transistor, the active structure can be a bulk structure.

[0053] In one embodiment, Figure 2 the stacked transistor 10 shown is a fully surrounding gate field effect transistor, and its active structure is a nanosheet structure.

[0054] Figures 3 to 37 FIG. is a schematic diagram of the manufacturing process of the first stacked transistor shown according to an embodiment of the present application. For ease of understanding, Figures 3 to 37 (a) in shows a cross-sectional view along the Figure 2 dashed line A-A' direction in Figures 3 to 37 (b) in shows a cross-sectional view along the Figure 2 dashed line B-B' direction in Figures 3 to 37 (c) in shows a cross-sectional view along the Figure 2 dashed line C-C' direction in. Below, the manufacturing method of the stacked transistor provided by the embodiment of the present application and the obtained stacked transistor 10 will be described by way of example in conjunction with Figures 1 to 37 .

[0055] In step S101, a stacked structure 23 is formed by one-time etching on the semiconductor substrate 20. Refer to Figure 5 shown.

[0056] It can be understood that, on the semiconductor substrate 20, processes such as material layer deposition, epitaxial growth, and lithography can be performed to form multiple material layers. Subsequently, the multiple material layers can be etched using the lithography process to form the stacked structure 23 at one time.

[0057] In one embodiment, the steps of the lithography process in the embodiment of the present application may include: depositing a photoresist material, exposing and developing the photoresist material, removing a part of the photoresist material, etching to remove the material layer corresponding to the part of the photoresist material, etc.

[0058] In one embodiment, the stacked structure 23 includes a first active structure 29 and a second active structure 31. The first active structure 29 and the second active structure 31 are stacked in sequence in a first direction. The first active structure 29 is farther from the semiconductor substrate 20 than the second active structure 31. The first direction is a direction perpendicular to the semiconductor substrate 20.

[0059] It can be understood that the stacked structure 23 includes a first active structure 29 and a second active structure 31. The first active structure 29 is used to form the active region of the first transistor 11 (front transistor) of the stacked transistor 10; the second active structure 31 stacked with the first active structure 29 in the first direction is used to form the active region of the second transistor 12 (back transistor) of the stacked transistor 10.

[0060] In one example, the first active structure 29 and the second active structure 31 are nanosheet structures, and both the first active structure 29 and the second active structure 31 can be formed by alternately depositing silicon layers and silicon germanium layers.

[0061] In some embodiments, when forming the first active structure 29 and the second active structure 31 by lithography, a relatively large etching depth can be adopted. For example, the height of the obtained nanosheet structure (which can also be a fin structure or a bulk structure) can be greater than 100 nm. It should be noted that the height of the nanosheet structure can be set according to the actual situation, and the embodiments of the present application do not limit this.

[0062] In some embodiments, after forming the first active structure 29 and the second active structure 31 by lithography, ion implantation can be performed in the middle part between the first active structure 29 and the second active structure 31 to electrically isolate the first active structure 29 and the second active structure 31.

[0063] In one embodiment, the ions implanted in the middle part between the first active structure 29 and the second active structure 31 include P-type ions, N-type ions or oxygen ions. Among them, the P-type ions include one or more of boron ions, gallium ions and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0064] In some embodiments, the stacked structures 23 in the two side regions of the stacked transistor 10 can be removed through a fin cutting process, so that the active structures of multiple standard transistor units are disconnected from each other, and the isolation between adjacent transistor units is completed.

[0065] In some embodiments, step S101 includes: forming an initial stacked structure 21 and an initial barrier layer 22 on the semiconductor substrate 20, where the initial barrier layer 22 is located between the initial stacked structure 21 and the semiconductor substrate 20; etching the initial stacked structure 21 and the initial barrier layer 22 once to form a stacked structure 23 and a barrier layer 24; depositing an oxide material on the semiconductor substrate 20 to form a shallow trench isolation structure 25, and the shallow trench isolation structure 25 wraps the barrier layer 24.

[0066] It can be understood that the initial barrier layer 22 can be deposited and formed on the semiconductor substrate 20, and the initial stacked structure 21 can be deposited and formed on the initial barrier layer 22. After the initial barrier layer 22 and the initial stacked structure 21 are formed, the initial stacked structure 21 and the initial barrier layer 22 can be lithographed once from top to bottom to form the stacked structure 23 and the barrier layer 24 at one time. At this time, the barrier layer 24 is located between the stacked structure 23 and the semiconductor substrate 20. When depositing an oxide material on the semiconductor substrate 20, the shallow trench isolation structure 25 formed by the oxide material can wrap the barrier layer 24, and the stacked structure 23 is exposed outside the shallow trench isolation structure 25.

[0067] It can be understood that the barrier layer 24 and the stacked structure 23 are formed by a single etching process, and the positions of the barrier layer 24 and the stacked structure 23 are opposite to each other. After flipping the wafer, the position of the active structure can be obtained according to the position of the barrier layer 24, which is beneficial to the alignment of the front and back sides of the stacked transistor 10.

[0068] In one embodiment, the material of the formed barrier layer 24 can have a certain hardness. In one example, the material of the formed barrier layer 24 can be silicon germanium. In one example, the silicon germanium forming the barrier layer 24 is different from the silicon germanium forming the nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium can be different.

[0069] In one embodiment, the oxide forming the shallow trench isolation structure 25 can be: silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2), etc.

[0070] In step S102, an oxide layer 50 covering the stacked structure 23 is formed on the semiconductor substrate 20, as shown in Figure 6 shown.

[0071] It can be understood that by depositing a semiconductor material on the semiconductor structure formed in step S101 and performing a thermal oxidation treatment on the semiconductor material, the oxide layer 50 can be formed. The oxide layer 50 covers the surface of the semiconductor substrate 20 and the surface of the stacked structure 23.

[0072] It can be understood that the oxide layer 50 is used to protect the stacked structure 23 from the influence of high temperature.

[0073] In some embodiments, the semiconductor material for forming the oxide layer 50 can be set according to actual needs, and the embodiments of the present application do not limit this. In one example, the semiconductor material for forming the oxide layer 50 can be silicon.

[0074] In step S103, a dummy gate structure 26 covering the oxide layer 50 is formed within the gate region of the stacked transistor 10, as shown in Figure 7 shown.

[0075] It can be understood that based on the semiconductor structure formed in step S102, a dummy gate structure 26 can be formed within the gate region of the stacked transistor 10 by using semiconductor manufacturing processes. The dummy gate structure 26 is located in the gate region of the stacked transistor 10, and the dummy gate structure 26 can cover the oxide layer 50.

[0076] In one embodiment, the dummy gate structure 26 is a dummy gate structure shared by the first active structure 29 and the second dummy gate structure. The dummy gate structure 26 includes a first dummy gate structure 51 and a second dummy gate structure 52. The first dummy gate structure 51 is the dummy gate structure of the first active structure 29, and the second dummy gate structure 52 is the dummy gate structure of the second active structure 31.

[0077] In some embodiments, after the dummy gate structure 26 is formed, a dummy gate sidewall 27 can be deposited and formed on the semiconductor substrate 20. In one embodiment, the dummy gate sidewall 27 covers the sidewalls of the dummy gate structure 26. In one embodiment, the dummy gate sidewall 27 covers the structures within the source / drain regions of the stacked transistor 10. For example, the dummy gate sidewall 27 can cover the oxide layer 50 within the source / drain regions.

[0078] In step S104, based on the first active structure 29 covered with the oxide layer 50, the first transistor 11 is formed, as shown in Figures 8 to 25 shown.

[0079] It can be understood that by removing the oxide layer 50 within the source / drain regions, the first active structure 29 within the source / drain regions can be exposed. Subsequently, based on the first active structure 29 within the source / drain regions, the first source / drain structure 112 can be formed. After the first source / drain structure 112 is formed, the first dummy gate structure 51 can be removed to form the first gate structure 114, thereby realizing the formation of the first transistor 11.

[0080] It should be noted that the manufacturing processes for forming the first source / drain structure 112 and the first gate structure 114 can be selected according to actual requirements.

[0081] In some embodiments, when the first gate isolation structure 53 is formed between the first gate structure 114 and the second gate structure 124, step S107 can be executed simultaneously with step S104. In one embodiment, within the source / drain regions of the stacked transistor 10, based on the first active structure 29 covered with the oxide layer 50, the first source / drain structure 112 is formed; the second part 512 of the first dummy gate structure is removed, and the first part 511 of the first dummy gate structure is retained to expose the first active structure 29; the first part 511 of the first dummy gate structure is oxidized to form the first gate isolation structure 53; the first gate structure 114 is formed on the first gate isolation structure 53, and the first gate structure 114 and the first source / drain structure 112 together constitute the first transistor 11.

[0082] It can be understood that, in the process of fabricating the first transistor 11, first, a first source / drain structure 112 can be formed within the source / drain regions of the stacked transistor 10 based on the first active structure 29 covered with the oxide layer 50. Subsequently, the second part 512 of the first dummy gate structure can be removed, and only the first part 511 of the first dummy gate structure is retained. Here, after removing the second part 512 of the first dummy gate structure, the first active structure 29 can be exposed. Subsequently, by oxidizing the retained first part 511 of the first dummy gate structure, a first gate isolation structure 53 can be formed. After the first gate isolation structure 53 is formed, the oxide layer 50 above the first active structure 29 can be removed, and a gate dielectric material and a metal material are sequentially deposited to form a first gate structure 114 covering the first active structure 29.

[0083] In some embodiments, the oxidation process can include a high-temperature oxidation process. In one embodiment, the dummy gate structure 26 can be a polysilicon structure formed of a polysilicon material. By performing high-temperature oxidation on the polysilicon structure, an oxidized polysilicon structure, i.e., the first gate isolation structure 53, can be obtained.

[0084] It can be understood that the first gate isolation structure 53 is an insulating structure, and the first gate isolation structure 53 is used to electrically isolate the first gate structure 114 and the second gate structure 124.

[0085] It can be understood that when oxidizing the first part 511 of the first dummy gate structure, the oxide layer 50 protects the first active structure 29 from being damaged.

[0086] In some embodiments, forming the first gate structure 114 above the first gate isolation structure 53 includes: depositing a gate dielectric material on the exposed first active structure 29 to form a first gate dielectric layer covering the first active structure 29; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer.

[0087] It can be understood that the first gate dielectric layer and the first gate electrode layer together constitute the first gate structure 114.

[0088] In one embodiment, after forming the first source / drain structure 112, a dielectric material can be deposited on the first source / drain structure 112 to form a first interlayer dielectric layer 113.

[0089] It can be understood that the first interlayer dielectric layer 113 wraps the first source / drain structure 112 and can electrically isolate the first source / drain structure 112 from other structures.

[0090] In some embodiments, when the stacked transistor 10 is a fully-depleted surround gate field-effect transistor, the method further includes: removing the sacrificial layer 34 in the first active structure 29 within the gate region and retaining the channel layer 35 in the first active structure 29, thereby completely exposing the channel layer 35 within the gate region.

[0091] In some embodiments, after the first active structure 29 within the gate region is exposed, a gate dielectric material may be deposited on the exposed first active structure 29 to form a first gate dielectric layer.

[0092] In one embodiment, the first gate dielectric layer is located between the gate electrode layer and the active structure (channel). The first gate dielectric layer is used to prevent gate current from directly flowing into the channel.

[0093] In one embodiment, the gate dielectric material for forming the first gate dielectric layer may be set according to actual requirements, and the embodiments of the present application do not limit this. In one example, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high dielectric constant (high-k), and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the first transistor 11. In one example, the gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0094] In one embodiment, the gate dielectric material for forming the gate electrode layer may be set according to actual requirements, and the embodiments of the present application do not limit this. In one embodiment, the gate electrode layer may be composed of multiple layers of electrode materials, and each layer of electrode material includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0095] In some embodiments, based on the first active structure 29 covered with the oxide layer 50, forming the first source / drain structure 112 includes: removing the oxide layer 50 not covered by the dummy gate structure 26; etching the stacked structure 23 not covered by the dummy gate structure 26 to form a first deep trench 48; and epitaxially growing the first source / drain structure 112 inside and outside the first deep trench 48 based on the first active structure 29 within the gate region.

[0096] It can be understood that the dummy gate structure 26 covers the oxide layer 50 within the gate region and does not cover the oxide layer 50 within the source / drain region. By removing the oxide layer 50 within the source / drain region, the stacked structure 23 within the source / drain region can be exposed.

[0097] It can be understood that the dummy gate structure 26 covers the stacked structure 23 within the gate region and does not cover the stacked structure 23 within the source / drain region. By etching the stacked structure 23 not covered by the dummy gate structure 26, a first deep trench 48 can be formed at the source / drain region between two adjacent gate regions.

[0098] In some embodiments, the sidewalls of the first deep trench 48 are formed by the stacked structure 23 within the gate region, and the bottom of the first deep trench 48 is formed by the structure located at the bottom of the stacked structure 23.

[0099] In some embodiments, the active structure further includes: a first sacrificial layer 30, and the first sacrificial layer 30 is located between the first active structure 29 and the second active structure 31.

[0100] It can be understood that the first sacrificial layer 30, the first active structure 29, and the second active structure 31 can be formed by the same etching process.

[0101] In some embodiments, the material for forming the first sacrificial layer 30 can be set according to actual requirements, and the embodiments of the present application do not limit this. In one embodiment, the material for forming the first sacrificial layer 30 can be silicon germanium. In one embodiment, the silicon germanium for forming the first sacrificial layer 30 is different from the silicon germanium for forming the nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium is different.

[0102] In some embodiments, the stacked structure 23 includes a second sacrificial layer 32, and the second sacrificial layer 32 is disposed between the active structure and the semiconductor substrate 20. The second sacrificial layer 32 can be removed in subsequent steps. After removal, the space originally occupied by the second sacrificial layer 32 is used to fill a metal material to form the second gate structure 124 of the second transistor 12.

[0103] In one embodiment, the second sacrificial layer 32 can be formed of a material different from that of the active structure; or, the second sacrificial layer 32 can be formed of the same material as the active structure; the embodiments of the present application do not limit this.

[0104] In some embodiments, after etching the stacked structure 23 not covered by the dummy gate structure 26 to form the first deep trench 48, the method further includes: removing the first sacrificial layer 30; depositing an insulating material at the position where the first sacrificial layer 30 is removed to form an isolation structure 33.

[0105] It can be understood that the stacked structure 23 in the source / drain region is not covered by the dummy gate structure 26. By sequentially etching the first active structure 29, the first sacrificial layer 30, the second active structure 31, and the second sacrificial layer 32 in the source / drain region, the first deep trench 48 can be formed. Here, after etching the first active structure 29 in the source / drain region, the first sacrificial layer 30 can be exposed; subsequently, by continuing to etch the first sacrificial layer 30 in the source / drain region, the second active structure 31 can be exposed. Subsequently, by etching the second active structure 31 in the source / drain region, the second sacrificial layer 32 can be exposed. Subsequently, by etching the second sacrificial layer 32 in the source / drain region, the first deep trench 48 can be formed.

[0106] It can be understood that by removing the first sacrificial layer 30 between the first active structure 29 and the second active structure 31 in the gate region, an unfilled space can be formed between the first active structure 29 and the second active structure 31 in the gate region. Subsequently, by filling the unfilled space with an insulating material, an isolation structure 33 can be formed.

[0107] In some embodiments, the isolation structure 33 is used to electrically isolate the first active structure 29 and the second active structure 31 in the gate region.

[0108] In some embodiments, before epitaxially growing the first source / drain structure 112 inside and outside the first deep trench 48 based on the first active structure 29 in the gate region, it includes: depositing an oxide material in the first deep trench 48 to form a first filling structure 37a. Depositing an insulating material on the first filling structure 37a to form an isolation layer 38.

[0109] It can be understood that the first active structure 29 and the second active structure 31 can be formed before and after flipping the wafer, respectively. Then, before forming the first active structure 29, an oxide material can be deposited in the first deep trench 48 to form a first filling structure 37a. The height of the first filling structure 37a is less than the height of the first active structure 29 and greater than the height of the second active structure 31. The first filling structure 37a completes the shielding of the second active structure 31 in the gate region, so as to ensure that only the first active structure 29 is formed in the source / drain region before flipping the wafer. Subsequently, by depositing an insulating material on the first filling structure 37a, an isolation layer 38 can be formed. The isolation layer 38 is used to isolate the subsequently generated first source / drain structure 112 and the second source / drain structure 122.

[0110] In some embodiments, when a barrier layer 24 is formed between the stacked structure 23 and the semiconductor substrate 20, after step S103, it includes: etching the barrier layer 24 located at the bottom of the first deep trench 48 to form an etched barrier layer 24. Depositing an oxide material at the position where the barrier layer 24 is etched to form a second filling structure 37b.

[0111] It can be understood that when a barrier layer 24 is formed on the semiconductor substrate 20, after forming the first deep trench 48, the barrier layer 24 (the barrier layer 24 in the source / drain region) at the bottom of the first deep trench 48 can be etched to form an etched barrier layer 24. The etched barrier layer 24 is located in the gate region. Subsequently, by depositing an oxide material at the position where the barrier layer 24 is etched, a second filling structure 37b can be formed.

[0112] In one embodiment, after flipping the wafer, according to the position of the etched barrier layer 24, the position of the gate region can be located, which is convenient for the stacked transistor 10 to achieve self-alignment.

[0113] In some embodiments, an oxide material is deposited in the first deep trench 48, and the first filling structure 37a and the second filling structure 37b can be formed simultaneously.

[0114] In some embodiments, when the stacked transistor 10 is a fully-depleted surround gate field-effect transistor, both the first active structure 29 and the second active structure 31 are formed by alternately stacking a channel layer 35 and a sacrificial layer 34. Step S104 includes: laterally etching the sacrificial layer 34 in the active structure within the gate region to a preset depth. An insulating material is deposited at the position where the sacrificial layer 34 is etched to form an inner sidewall 36.

[0115] It can be understood that when the stacked transistor 10 is a fully-depleted surround gate field-effect transistor, forming the first deep trench 48 can expose the active structure within the gate region. Subsequently, the sacrificial layer 34 in the exposed active structure can be etched until the preset depth. An insulating material can be deposited at the position where the sacrificial layer 34 is etched to form the inner sidewall 36 of the fully-depleted surround gate transistor.

[0116] In some embodiments, the inner sidewall 36 of the fully-depleted surround gate transistor is used to electrically isolate the source / drain structure and the gate structure, ensuring the stability of the transistor structure.

[0117] In some embodiments, the inner sidewall 36 includes a first inner sidewall and a second inner sidewall. The first inner sidewall faces the first active structure 29, and the second inner sidewall faces the second active structure 31.

[0118] It can be understood that after forming the first deep trench 48, the inner sidewall 36 in the first transistor 11 and the second transistor 12 can be formed simultaneously. The first inner sidewall of the first transistor 11 is used to isolate the first source / drain structure 112 and the first gate structure 114. The second inner sidewall of the second transistor 12 is used to isolate the second source / drain structure 122 and the second gate structure 124.

[0119] In one embodiment, the material for forming the inner sidewall 36 is the same as the material for forming the dummy gate sidewall 27.

[0120] In some embodiments, after forming the first deep trench 48, a first source / drain structure 112 can be epitaxially grown based on the first active structure 29 within the gate region. Here, the epitaxial growth direction is perpendicular to the first direction, and the epitaxial growth direction is from the gate region to the source / drain region. After the epitaxial growth is completed, a first source / drain structure 112 can be formed in the first deep trench 48.

[0121] In some embodiments, step S104 includes: depositing a dielectric material over the first gate structure 114 and the first interlayer dielectric layer 113 to form a first dielectric layer 42; etching the first dielectric layer 42 and the first interlayer dielectric layer 113 until the first source-drain structure 112 is exposed to form a first via; and depositing a metal material in the first via to form a first source-drain metal 115.

[0122] It can be understood that after the first gate structure 114 is formed, a first dielectric layer 42 can also be formed over the first gate structure 114 and the first interlayer dielectric layer 113. The first dielectric layer 42 is used to electrically isolate the source-drain metal from the gate oxide (such as the gate dielectric layer), thereby eliminating the adverse electrical effects caused by the direct contact between the source-drain metal and the gate oxide layer. After the first dielectric layer 42 is formed, the first dielectric layer 42 and the first interlayer dielectric layer 113 in the source-drain region can be etched to form a source-drain metal via. Subsequently, a metal material can be deposited in the source-drain metal via to form a first source-drain metal 115.

[0123] In some embodiments, step S104 includes: after the first gate structure 114 is formed, removing the third gate structure in the first gate structure 114 by using a gate cut process, and depositing an insulating material at the position where the third gate structure is removed to form a first isolation structure 41.

[0124] In one embodiment, in the second direction, the third gate structure is located at both ends of the first gate structure 114.

[0125] It can be understood that after the first gate structure 114 is formed, the third gate structure in the first gate structure 114 can be removed. The third gate structure is a structure located at both ends of the first gate structure 114 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the third gate structure is removed, an insulating material can be deposited at the position where the third gate structure is removed to form a first isolation structure 41.

[0126] In some embodiments, the insulating material for forming the first isolation structure 41 can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0127] In some embodiments, when removing the third gate structure in the first gate structure 114 by using a gate cut process, the third interlayer dielectric layer in the first interlayer dielectric layer 113 can be removed at the same time. The projection of the third interlayer dielectric layer in the third direction coincides with the projection of the third gate structure in the third direction. After the third interlayer dielectric layer is removed, an insulating material can also be deposited at the position where the third interlayer dielectric layer is removed to form a first isolation structure 41 that is continuous in the third direction.

[0128] In one embodiment, after the first gate structure 114 and the first source / drain metal 115 are formed, the first metal interconnect layer 116 can be formed on the first gate structure 114 and the first source / drain metal 115 by using standard back-end processes in semiconductor manufacturing (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.).

[0129] In some embodiments, after the first metal interconnect layer 116 is formed, the first transistor 11 can be formed.

[0130] It should be noted that, for ease of description, the first source / drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, etc. are all similar to the first source / drain groove, and the "source / drain" therein is an abbreviation for "source and / or drain".

[0131] Step S105, flip the wafer and remove the semiconductor substrate 20, as shown in Figures 26 to 28 shown.

[0132] It can be understood that after the first transistor 11 is obtained, the first transistor 11 can be flipped so that the prepared first transistor 11 is located at the bottom and the second active structure 31 of the second transistor 12 that is not yet prepared can be located at the upper part, which is convenient for subsequent preparation of the second transistor 12.

[0133] In one embodiment, after the back-end process of the first transistor 11 is completed, the first transistor 11 can be bonded to the carrier wafer 44. For example, an insulating material (such as silicon oxide) can be deposited on the first transistor 11 to form an insulating layer 43, and the insulating layer 43 can be bonded to the carrier wafer 44. Then, the wafer is flipped. After flipping, the first transistor 11 is located at the bottom.

[0134] In the embodiments of the present application, the bonded carrier wafer 44 can provide physical support for the flipped first transistor 11 after flipping, effectively preventing the first transistor 11 from being broken by external forces during the preparation process of the second transistor 12.

[0135] In some embodiments, when a barrier layer 24 is provided between the stacked structure 23 and the semiconductor substrate 20, step S105 includes: flipping the wafer and removing the semiconductor substrate 20 to expose the etched barrier layer 24 and the shallow trench isolation structure 25. Remove the shallow trench isolation structure 25 and retain the etched barrier layer 24.

[0136] It can be understood that after the wafer is reversed, processes such as polishing or chemical mechanical planarization can be used to remove the semiconductor substrate 20 to expose the etched barrier layer 24 and the shallow trench isolation structure 25. Subsequently, the shallow trench isolation structure 25 can be selectively etched to expose the etched barrier layer 24.

[0137] It can be understood that the etched barrier layer 24 is located within the gate region, so that the etched barrier layer 24 can protect the structures within the gate region from being affected by etching.

[0138] It can be understood that the gate region of the stacked transistor 10 can be located through the etched barrier layer 24, thereby realizing the self-alignment of the gate regions and source / drain regions of the front and back two layers of transistors.

[0139] Step S106, based on the second active structure 31 covered with the oxide layer 50, form the second transistor 12, see Figures 27 to 29 as shown.

[0140] It can be understood that after the wafer is reversed and the semiconductor substrate 20 is removed, the second active structure 31 covered with the oxide layer 50 can be exposed. Subsequently, based on the second active structure 31 covered with the oxide layer 50, the second transistor 12 can be formed.

[0141] In some embodiments, when the second gate isolation structure 54 is formed between the first gate structure 114 and the second gate structure 124, step S107 can be executed simultaneously with step S106. In one embodiment, within the source / drain regions of the stacked transistor 10, based on the second active structure 31 covered with the oxide layer 50, form the second source / drain structure 122; remove the second part 522 of the second dummy gate structure, and retain the first part 521 of the second dummy gate structure to expose the second active structure 31; perform an oxidation process on the first part 521 of the second dummy gate structure to form the second gate isolation structure 54; form the second gate structure 124 on the second gate isolation structure 54, and the second gate structure 124 and the second source / drain structure 122 together constitute the second transistor 12.

[0142] It can be understood that during the process of fabricating the second transistor 12, first, a second source / drain structure 122 can be formed within the source / drain regions of the stacked transistor 10 based on a second active structure 31 covered with an oxide layer 50. Subsequently, a second portion 522 of the second dummy gate structure can be removed, leaving only a first portion 521 of the second dummy gate structure. Here, after removing the second portion 522 of the second dummy gate structure, the second active structure 31 can be exposed. Subsequently, by oxidizing the remaining first portion 521 of the second dummy gate structure, a second gate isolation structure 54 can be formed. After the second gate isolation structure 54 is formed, the oxide layer 50 above the second active structure 31 can be removed, and a gate dielectric material and a metal material can be deposited in sequence to form a second gate structure 124 covering the second active structure 31.

[0143] Here, the steps of forming the second source / drain structure 122 are the same as those of forming the first source / drain structure 112. For the sake of brevity of the specification, they will not be elaborated here.

[0144] In some embodiments, during the process of fabricating the first transistor 11, if a first filling structure 37a is filled into the first deep trench 48, then before step S106, the method further includes: removing the first filling structure 37a within the first deep trench 48 to expose the second active structure 31 within the gate region.

[0145] It can be understood that by removing the first filling structure 37a within the first deep trench 48, the second active structure 31 within the gate region can be exposed, and thus, based on the exposed active structure, the second source / drain structure 122 can be formed.

[0146] In some embodiments, before step S106, it includes: etching the second filling structure 37b and the first filling structure 37a that are not covered by the etched barrier layer 24 in sequence until the isolation layer 38 is exposed.

[0147] It can be understood that the second filling structure 37b and the first filling structure 37a that are not covered by the etched barrier layer 24 can be etched during the etching process. During this process, the etched barrier layer 24 serves as a hard mask to protect the structures covered by the etched barrier layer 24.

[0148] In some embodiments, after the second active structure 31 within the gate region is exposed, a dielectric material can be deposited on the exposed second active structure 31 to form a second gate dielectric layer. A metal material is deposited on the second gate dielectric layer to form a second gate electrode layer.

[0149] In one embodiment, the second gate dielectric layer and the second gate electrode layer are jointly used to form the second gate structure 124. The second gate structure 124 is the gate structure in the second transistor 12.

[0150] In some embodiments, step S106 further includes: depositing a dielectric material over the second gate structure 124 and the second interlayer dielectric layer 123 to form a second dielectric layer 46; etching the second dielectric layer 46 and the second interlayer dielectric layer 123 until the second source / drain structure 122 is exposed to form a second via; and depositing a metal material in the second via to form a second source / drain metal 125.

[0151] It can be understood that after forming the second gate structure 124, a second dielectric layer 46 can also be formed over the second gate structure 124 and the second interlayer dielectric layer 123, and the function of the second dielectric layer 46 is the same as that of the first dielectric layer 42. After forming the second dielectric layer 46, the second dielectric layer 46 and the second interlayer dielectric layer 123 in the source / drain region can be etched to form source / drain metal vias. Subsequently, a metal material can be deposited in the source / drain metal vias to form a second source / drain metal 125.

[0152] In some embodiments, step S106 further includes: after forming the second gate structure 124, removing the fourth gate structure in the second gate structure 124 by a gate cut process, and depositing an insulating material at the position where the fourth gate structure is removed to form a second isolation structure 47.

[0153] In one embodiment, in the second direction, the fourth gate structure is located at both ends of the second gate structure 124.

[0154] It can be understood that after forming the second gate structure 124, the fourth gate structure in the second gate structure 124 can be removed. The fourth gate structure is a structure located at both ends of the second gate structure 124 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After removing the fourth gate structure, an insulating material can be deposited at the position where the fourth gate structure is removed to form a second isolation structure 47.

[0155] In some embodiments, the insulating material for forming the second isolation structure 47 can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0156] In some embodiments, when removing the fourth gate structure in the second gate structure 124 by a gate cut process, the fourth interlayer dielectric layer in the second interlayer dielectric layer 123 can be removed simultaneously, and the projection of the fourth interlayer dielectric layer in the third direction coincides with the projection of the fourth gate structure in the third direction. After removing the fourth interlayer dielectric layer, an insulating material can also be deposited at the position where the fourth interlayer dielectric layer is removed to form a second isolation structure 47 that is continuous in the third direction.

[0157] In some embodiments, the first isolation structure 41 and the second isolation structure 47 are oppositely arranged.

[0158] In one embodiment, after the second gate structure 124 and the second source / drain metal 125 are formed, a second metal interconnect layer 126 can be formed on the second gate structure 124 and the second source / drain metal 125 by using standard back-end processes in semiconductor fabrication (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.).

[0159] In some embodiments, after the second metal interconnect layer 126 is formed, the second transistor 12 can be formed.

[0160] Thus, the fabrication of the stacked transistors is completed. It should be noted that the first source / drain structure and the first gate structure together constitute the first transistor, and the second source / drain structure and the second gate structure together constitute the second transistor; the first transistor or the second transistor can be any one of the following: fin field-effect transistor, gate-all-around field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, crossbar transistor, and planar field-effect transistor, and the embodiments of the present application do not limit this.

[0161] In the embodiments of the present disclosure, by etching once on a semiconductor substrate to form a stacked structure, the active regions of the first transistor and the second transistor in the stacked transistors can be self-aligned. Subsequently, a dummy gate structure shared by the first transistor and the second transistor is formed. During the process of forming the front transistor and / or the back transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is oxidized to form a gate isolation structure in the stacked transistors by using the dummy gate structure. Subsequently, a self-aligned gate structure can be formed based on the active structure, and finally, the complete self-alignment of the first transistor and the second transistor is achieved.

[0162] In this way, on the one hand, fewer high aspect ratio processes can be used, which is more compatible with the complete self-alignment flip-chip stacking of various types of transistors, and further optimization of the "self-aligned flip-chip transistor" solution can be achieved; on the other hand, by oxidizing the dummy gate structure to form a gate isolation structure between the front and back transistors, the process difficulty can be reduced to a certain extent, and the quality of the gate isolation structure can be improved.

[0163] The following combines Figures 2 to 37 the fabrication process of the stacked transistors shown below to illustrate the fabrication method of the stacked transistors in the present application with a specific example.

[0164] In one example, the fabrication process of the stacked transistors can include the following steps:

[0165] The first step: Epitaxially grow silicon germanium and silicon on a semiconductor substrate 20 (formed of silicon) to form an initial stacked structure 21 and an initial barrier layer 22, obtaining asFigure 3 The structure shown.

[0166] It can be understood that the initial blocking layer 22 is located between the semiconductor substrate 20 and the initial stacked structure 21.

[0167] Here, the initial stacked structure 21 is formed by alternating arrangements of silicon-germanium layers and silicon layers.

[0168] The second step: Through photolithography, an etching is performed once to form the stacked structure 23 and the blocking layer 24, obtaining the structure as Figure 4 shown.

[0169] It can be understood that in the cross-sectional views in the A-A' direction and the B-B' direction, the portions on both sides of the initial stacked structure 21 are etched, thereby forming the stacked structure 23 for fabricating a fully-depleted surround-gate field-effect transistor.

[0170] In some embodiments, the material for forming the blocking layer 24 can have a certain hardness, such that the blocking layer 24 can serve as an etching stop layer after wafer flipping.

[0171] See Figure 4 shown, the stacked structure 23 includes a first active structure 29, a second active structure 31, a first sacrificial layer 30, and a second sacrificial layer 32.

[0172] The third step, deposit an oxide material on the semiconductor substrate 20 and etch the oxide material to a preset height to form the shallow trench isolation structure 25, obtaining the structure as Figure 5 shown.

[0173] Here, the shallow trench isolation structure 25 wraps the blocking layer 24, and the stacked structure 23 is exposed outside the shallow trench isolation structure 25.

[0174] The fourth step, form an oxide layer 50, obtaining the structure as Figure 6 shown.

[0175] It can be understood that the oxide layer 50 can be formed by depositing a silicon layer on the semiconductor substrate 20 and performing a thermal oxidation process on the silicon layer. The oxide layer 50 covers the upper surfaces of the stacked structure 23 and the semiconductor substrate 20.

[0176] The fifth step, form a dummy gate structure 26 that wraps the stacked structure 23. After the dummy gate structure 26 is formed, deposit and form a dummy gate sidewall 27, obtaining the structure as Figure 7 shown.

[0177] It can be understood that the dummy gate structure 26 is a dummy gate structure shared by the front and back two layers of crystals. The dummy gate structure 26 includes a first dummy gate structure 51 and a second dummy gate structure 52. When forming the dummy gate sidewall 27 by using an isotropic deposition process, the dummy gate sidewall 27 can cover the sidewalls of the dummy gate structure 26 within the gate region and the stacked structure 23 within the source / drain region.

[0178] The sixth step is to etch the dummy gate sidewall 27 until the first active structure 29 and the first sacrificial layer 30 in the stacked structure 23 within the source / drain region are exposed, obtaining the structure as Figure 8 shown.

[0179] It can be understood that an anisotropic etching process can be used to expose the first active structure 29 and the first sacrificial layer 30 covered by the oxide layer 50.

[0180] It should be noted that as Figure 7 shown, after the first active structure 29 and the first sacrificial layer 30 covered by the oxide layer 50 are exposed, in the cross-sectional view in the C-C' direction, a part of the dummy gate sidewall 27 remains on the sidewall of the dummy gate structure 26. This dummy gate sidewall 27 can be used as a hard mask in subsequent fabrication processes.

[0181] The seventh step is to etch the first active structure 29 within the source / drain region, obtaining the structure as Figure 9 shown.

[0182] It can be understood that by using the dummy gate structure 26 and the dummy gate sidewall 27 as hard masks, the first active structure 29 located within the source / drain region can be selectively etched.

[0183] The eighth step is to form an isolation structure 33 between the first active structure 29 and the second active structure 31 within the gate region, obtaining the structure as Figure 12 shown.

[0184] It can be understood that the isolation structure 33 is a middle dielectric isolation (MDI).

[0185] In one embodiment, forming the isolation structure 33 may include: selectively removing the first sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31, obtaining the structure as Figure 10 shown. Depositing an insulating material such as silicon nitride, and performing a planarization process on the isolation structure 33 formed of the silicon nitride material to obtain the structure as Figure 11 shown. Using an anisotropic etching process to remove the redundant isolation structure 33 and retain the isolation structure 33 between the first active structure 29 and the second active structure 31 within the gate region, obtaining the structure as Figure 12 shown.

[0186] Step 9: Horizontally etch the sacrificial layer 34 in the first active structure 29 to a certain depth. Deposit an insulating material such as silicon nitride at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the first transistor 11, obtaining the structure as shown in Figure 13 shown.

[0187] It can be understood that in this embodiment, the stacked transistor 10 is a fully surrounding gate field effect transistor. Therefore, it is necessary to form the inner sidewall 36. When the stacked transistor 10 is a fin field effect transistor, a planar field effect transistor, etc., there is no need to form the inner sidewall 36.

[0188] Step 10: Use an anisotropic etching process to etch the second active structure 31 in the source-drain region to form the first deep trench 48. Subsequently, use an anisotropic etching process to etch the second sacrificial layer 32 located at the bottom of the second active structure 31, obtaining the structure as shown in Figure 14 shown.

[0189] Step 11: Use an anisotropic etching process to etch the barrier layer 24 and the shallow trench isolation structure 25 in the source-drain region, obtaining the structure as shown in Figure 15 shown.

[0190] It can be understood that after using an anisotropic etching process to etch the barrier layer 24 in the source-drain region, the etched barrier layer 24 is formed. The etched barrier layer 24 is located in the gate region. After flipping the wafer, the position of the gate region can be obtained based on the etched barrier layer 24.

[0191] Step 12: Deposit a filling material in the source-drain region to form a filling structure 37, obtaining the structure as shown in Figure 16 shown.

[0192] In one embodiment, the filling structure 37 includes a first filling structure 37a and a second filling structure 37b. The first filling structure 37a is opposite to the position of the second active structure 31, and the second filling structure 37b is opposite to the position of the etched barrier layer 24.

[0193] In one embodiment, as shown in Figure 16 shown, the height of the top surface of the filling structure 37 is lower than the height of the top surface of the isolation structure 33 and higher than the height of the bottom surface of the isolation structure 33.

[0194] Step 13: Deposit an insulating material in the source-drain region and etch back the insulating material to a preset height to form an isolation layer 38, obtaining the structure as shown in Figure 17 shown.

[0195] It can be understood that the isolation layer 38 is used to electrically isolate the first source-drain structure 112 and the second source-drain structure 122.

[0196] The fourteenth step is to epitaxially form a first source / drain structure 112 inside and outside the source / drain region based on the first active structure 29 in the gate region, obtaining a structure as shown in Figure 18 the figure.

[0197] The fifteenth step is to deposit an interlayer gate dielectric material in the source / drain region to form a first interlayer dielectric layer 113, obtaining a structure as shown in Figure 19 the figure.

[0198] The sixteenth step is to remove the second part 512 of the first dummy gate structure and retain the first part 511 of the first dummy gate structure, obtaining a structure as shown in Figure 20 the figure.

[0199] The seventeenth step is to oxidize the first part 511 of the first dummy gate structure to form a first gate isolation structure 53, obtaining a structure as shown in Figure 21 the figure.

[0200] It should be noted that when oxidizing the first part 511 of the first dummy gate structure, the oxide layer 50 can protect the first active structure 29 from being damaged.

[0201] The eighteenth step is to remove the oxide layer 50 in the gate region and deposit a gate dielectric material and a metal material on the first active structure 29 to form a first gate structure 114, obtaining a structure as shown in Figure 22 the figure.

[0202] The nineteenth step is to form a first isolation structure 41, obtaining a structure as shown in Figure 23 the figure.

[0203] It can be understood that in the cross-sectional view in the A-A' direction and the cross-sectional view in the B-B' direction, the first isolation structure 41 is located on both sides.

[0204] The twentieth step is to deposit a dielectric material on the first interlayer dielectric layer 113 and the first gate structure 114 to form a first dielectric layer 42. Subsequently, the first dielectric layer 42 and the first interlayer dielectric layer 113 are etched according to the lithography pattern until the first source / drain structure 112 is exposed, and then a first source / drain metal 115 is deposited, obtaining a structure as shown in Figure 24 the figure.

[0205] The twenty-first step is to form a first metal interconnect layer 116, obtaining a structure as shown in Figure 25 the figure.

[0206] The twenty-second step is to deposit an insulating material (such as silicon oxide) on the first metal interconnect layer 116 to form an insulating layer 43, and bond the insulating layer 43 to the carrier wafer 44. Then, a wafer flip is performed. After the wafer flip, a structure as shown in Figure 26 the figure is obtained.

[0207] Step 23. Remove the semiconductor substrate 20 to obtain the structure as shown in Figure 27 .

[0208] It can be understood that after removing the semiconductor substrate 20, the etched barrier layer 24 and the filling structure 37 in the source-drain region can be exposed.

[0209] Step 24. Selectively etch the shallow trench isolation structure 25 wrapping the etched barrier layer to obtain the structure as shown in Figure 28 .

[0210] Step 25. Deposit polysilicon at the position where the shallow trench isolation structure 25 is removed to form a polysilicon structure 45, and obtain the structure as shown in Figure 29 .

[0211] Step 26. Remove the filling structure 37 in the source-drain region until the isolation layer 38 is exposed, and obtain the structure as shown in Figure 30 .

[0212] It can be understood that the etched barrier layer 24 is located in the gate region, and the position of the source-drain region can be determined according to the position of the etched barrier layer 24.

[0213] Step 27. Horizontally etch the sacrificial layer 34 in the second active structure 31 to a certain depth. Deposit an insulating material such as silicon nitride at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the second transistor 12, and obtain the structure as shown in Figure 31 .

[0214] Step 28. Based on the second active structure 31 in the gate region, epitaxially grow a second source-drain structure 122 inside and outside the source-drain region, and deposit a dielectric material above the second source-drain structure 122 to form a second interlayer dielectric layer 123, and obtain the structure as shown in Figure 32 .

[0215] Step 29. Using the etched barrier layer 24 as a hard mask, etch the second dummy gate structure 52 until the first gate isolation structure 53 is exposed, and obtain the structure as shown in Figure 33 .

[0216] Step 30. Remove the etched barrier layer 24 and the second sacrificial layer 32 to expose the second active structure 31. Subsequently, form a second gate structure 124 on the second active structure, and obtain the structure as shown in Figure 34 .

[0217] It can be understood that the second gate structure 124 includes a second gate dielectric layer and a second gate electrode layer.

[0218] Step 31. Form a second isolation structure 47 to obtain the structure as shown in Figure 35The structure shown.

[0219] It can be understood that in the cross-sectional view in the A-A' direction and the cross-sectional view in the B-B' direction, the second isolation structure 47 is located on both sides.

[0220] The thirty-second step is to deposit a dielectric material on the second interlayer dielectric layer 123 and the second gate structure 124 to form the second dielectric layer 46. Subsequently, the second dielectric layer 46 and the second interlayer dielectric layer 123 are etched until the second source / drain structure 122 is exposed, and then the second source / drain metal 125 is deposited to obtain the structure as shown in Figure 36 The structure shown.

[0221] The thirty-third step is to form the second metal interconnect layer 126 to obtain the structure as shown in Figure 37 The structure shown.

[0222] It can be understood that after the second metal interconnect layer 126 is formed, the stacked transistor 10 in the embodiment of the present application is fabricated.

[0223] In the embodiment of the present disclosure, by fabricating the first transistor before flipping the wafer and the second transistor after flipping the wafer, complementary flip-chip stacked transistors can be formed. The dummy gate structures of the first transistor and the second transistor are integrally formed, enabling the use of fewer high aspect ratio processes and more compatibly achieving complete self-alignment flip-chip stacking of various forms of transistors. Further, during the process of forming the front transistor, a part of the dummy gate structure is removed and the remaining dummy gate structure is oxidized, which reduces the process difficulty to a certain extent and forms a gate isolation structure with better quality.

[0224] Figures 38 to 55 FIG. is a schematic diagram of the fabrication process of the second stacked transistor shown according to the embodiment of the present application. For ease of understanding, Figures 38 to 55 in (a) shows a cross-sectional view along the dashed line A-A' direction in Figure 2 in FIG., Figures 38 to 55 in (b) shows a cross-sectional view along the dashed line B-B' direction in Figure 2 in FIG., Figures 38 to 55 in (c) shows a cross-sectional view along the dashed line C-C' direction in Figure 2 in FIG. The fabrication process of the stacked transistor shown in the following with reference to Figures 38 to 55 is used to illustrate the fabrication method of the stacked transistor in the present application with a specific example.

[0225] The first step is the same as the first to seventeenth steps in the above specific example, and reference can be made to the structure shown in Figures 3 to 19 FIG. For the sake of brevity of the specification, it will not be described in detail here.

[0226] The second step is to remove the first dummy gate structure 51 to obtain the structure as shown in Figure 38 The structure shown.

[0227] In the third step, the oxide layer 50 within the gate region is removed, and a gate dielectric material and a metal material are deposited on the first active structure 29 to form a first gate structure 114, obtaining a structure as shown in Figure 39 the figure.

[0228] In the fourth step, following steps 21 to 30 in the above specific example, a structure as shown in Figures 40 to 49 the figure can be obtained.

[0229] In the fifth step, using the etched barrier layer 24 as a hard mask, the second part 522 of the second dummy gate structure is etched, and the first part 521 of the second dummy gate structure is retained, obtaining a structure as shown in Figure 50 the figure.

[0230] In the sixth step, the first part 521 of the second dummy gate structure is oxidized to form a second gate isolation structure 55, obtaining a structure as shown in Figure 51 the figure.

[0231] In the seventh step, following steps 32 to 35 in the above specific example, a structure as shown in Figures 52 to 55 the figure can be obtained.

[0232] In the embodiments of the present disclosure, during the process of forming the back transistor, a part of the dummy gate structure is removed, and the remaining dummy gate structure is oxidized, which can reduce the process difficulty to a certain extent and form a gate isolation structure with better quality.

[0233] It should be noted that in the embodiments of the present disclosure, the gate isolation structure can also be formed by oxidizing the dummy gate structure during the processes of forming the front transistor and the back transistor. The specific process can refer to the description in the above specific example. For the sake of brevity of the specification, it will not be elaborated here.

[0234] In the embodiments of the present disclosure, a stacked transistor is provided, and this stacked transistor can be fabricated by using the method in Figure 1 one or more corresponding embodiments. As shown in Figure 37 and Figure 55 the figure, this stacked transistor 10 includes:

[0235] A first transistor 11 and a second transistor 12, the first transistor and the second transistor 12 are arranged back to back, the first active structure 29 of the first transistor 11 and the second active structure 31 of the second transistor 12 form an active structure; the first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure 124. The first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are self-aligned.

[0236] In some embodiments, a gate isolation structure is formed between the first gate structure 114 and the second gate structure 124. The gate isolation structure is obtained by oxidizing the first portion 511 of the first dummy gate structure and / or the first portion 521 of the second dummy gate structure. The first portion 511 of the first dummy gate structure is a portion of the first dummy gate structure 51 close to the second dummy gate structure 52, and the first portion 521 of the second dummy gate structure is a portion of the second dummy gate structure 52 close to the first dummy gate structure 51. The oxide layer 50 protects the stacked structure 23 during the oxidation process.

[0237] In some embodiments, the first transistor 11 or the second transistor 12 is any one of the following: fin field-effect transistor, gate-all-around field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, fork-sheet transistor, and planar field-effect transistor. The embodiments of the present application do not make any limitations in this regard.

[0238] It can be understood that the flip-chip stacked transistor solution in the embodiments of the present application has self-alignment. On the one hand, it solves the long-term problems such as complex processes and difficult alignment existing in the existing mainstream technical solutions of stacked transistors, and realizes the promotion of the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through the stacked transistors, greatly releasing the metal wiring resources.

[0239] Finally, the solution of realizing the upper and lower transistors through flip-chip is compatible with the existing mainstream device architectures, and can realize the front and back stacking of including planar transistors, FinFETs, GAA Nanosheets, Forksheet (fork-sheet transistors), and even vertical transistors (VTFETs), without the need for special process development for specific device architectures, with strong flexibility and strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicality and broad development prospects.

[0240] Embodiments of the present application provide a semiconductor device, including: a stacked transistor as described in the above embodiments. For the specific limitations of the stacked transistor, reference can be made to the stacked transistor shown in the above Figure 37 and Figure 55 and will not be elaborated herein.

[0241] Embodiments of the present application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned stacked transistor. For the specific limitations of the stacked transistor, reference can be made to the structure shown in the above Figure 37 and Figure 55 and will not be elaborated herein.

[0242] In the description of the present application, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expression of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0243] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a stacked transistor, characterized in that The method includes: Etching a stacked structure is formed on a semiconductor substrate at one time, wherein the stacked structure includes: a first active structure and a second active structure; the first active structure and the second active structure are stacked in sequence in a first direction, the first active structure is farther from the semiconductor substrate than the second active structure, and the first direction is a direction perpendicular to the semiconductor substrate; Forming an oxide layer covering the stacked structure on the semiconductor substrate; Forming a dummy gate structure covering the oxide layer in the gate region of the stacked transistor; the dummy gate structure includes a first dummy gate structure and a second dummy gate structure; Forming a first transistor based on the first active structure covered with the oxide layer, wherein the first transistor includes: a first gate structure, and the first gate structure is formed based on the first dummy gate structure; Flip the wafer and remove the semiconductor substrate; Forming a second transistor based on the second active structure covered with the oxide layer, wherein the second transistor includes: a second gate structure, and the second gate structure is formed based on the second dummy gate structure; Oxidizing a first part of the first dummy gate structure to form a first gate isolation structure between the first gate structure and the second gate structure; and / or, oxidizing a first part of the second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure; wherein the dummy gate structure is a polysilicon structure formed of a polysilicon material; performing high-temperature oxidation on the polysilicon structure to obtain an oxidized polysilicon structure, and the oxidized polysilicon structure is a gate isolation structure; the gate isolation structure includes the first gate isolation structure and the second gate isolation structure; Wherein, the first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure, and the oxide layer protects the stacked structure during the oxidation process.

2. The method according to claim 1, wherein In the case of forming the first gate isolation structure between the first gate structure and the second gate structure, the forming the first transistor based on the first active structure covered with the oxide layer includes: Forming a first source / drain structure based on the first active structure covered with the oxide layer in the source / drain region of the stacked transistor; Forming a first gate structure on the first gate isolation structure, and the first gate structure and the first source / drain structure together constitute the first transistor.

3. The method according to claim 2, wherein The forming the first gate structure on the first gate isolation structure includes: Depositing a gate dielectric material on the exposed first active structure to form a first gate dielectric layer covering the first active structure; Depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, and the first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

4. The method according to claim 2, wherein The forming the first source / drain structure based on the first active structure covered with the oxide layer includes: Remove the oxide layer not covered by the pseudo-gate structure; Etch the stacked structure not covered by the pseudo-gate structure to form a first deep trench; Based on the first active structure within the gate region, epitaxially grow the first source / drain structure inside and outside the first deep trench.

5. The method according to claim 4, characterized in that, The stacked structure further includes: a first sacrificial layer located between the first active structure and the second active structure; After etching the stacked structure not covered by the pseudo-gate structure to form a first deep trench, the method further includes: Remove the first sacrificial layer; Deposit an insulating material at the position where the first sacrificial layer is removed to form an isolation structure.

6. The preparation method according to claim 4, characterized in that, When the stacked transistor is a fully-depleted surround-gate field-effect transistor, both the first active structure and the second active structure are formed by alternately stacking a channel layer and a sacrificial layer; After etching the stacked structure not covered by the pseudo-gate structure to form a first deep trench, the method further includes: Laterally etch the sacrificial layer in the first active structure within the gate region to a preset depth; Deposit an insulating material at the position where the sacrificial layer is etched to form an inner sidewall.

7. The method according to claim 4, wherein Before epitaxially growing the first source / drain structure inside and outside the first deep trench based on the first active structure within the gate region, the method further includes: Deposit an oxide material in the first deep trench to form a first filling structure, the height of the first filling structure being less than the height of the first active structure and greater than the height of the second active structure; Deposit an insulating material on the first filling structure to form an isolation layer for isolating the first source / drain structure and the second source / drain structure.

8. The preparation method according to claim 7, wherein The forming of the stacked structure by one-time etching on the semiconductor substrate includes: Form an initial stacked structure and an initial barrier layer on the semiconductor substrate, where the initial barrier layer is located between the initial stacked structure and the semiconductor substrate; One-time etch the initial stacked structure and the initial barrier layer to form the stacked structure and the barrier layer; After etching the stacked structure not covered by the pseudo-gate structure to form a first deep trench, the method further includes: Etch the barrier layer at the bottom of the first deep trench to form an etched barrier layer, where the etched barrier layer is located in the gate region; The flipping the wafer and removing the semiconductor substrate includes: Flip the wafer and remove the semiconductor substrate to expose the etched barrier layer; Before forming a second transistor based on the second active structure covered with the oxide layer, the method further includes: Etch the first filling structure not covered by the etched barrier layer until the isolation layer is exposed.

9. The method according to any one of claims 1 to 8, characterized in that, In the case of forming a second gate isolation structure between the first gate structure and the second gate structure, forming a second transistor based on the second active structure covered with the oxide layer includes: In the source / drain region of the stacked transistor, form a second source / drain structure based on the second active structure covered with the oxide layer. A second gate structure is formed over the second gate isolation structure, and the second gate structure and the second source / drain structure together constitute the second transistor.

10. The preparation method according to claim 1, wherein, The method further includes: After the first gate structure is formed, a gate cut process is used to remove the third gate structure in the first gate structure, and an insulating material is deposited at the position where the third gate structure is removed to form a first gate isolation structure; wherein, in a second direction perpendicular to the first direction, the third gate structure is located at both ends of the first gate structure; and / or After the second gate structure is formed, a gate cut process is used to remove the fourth gate structure in the second gate structure, and an insulating material is deposited at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

11. The preparation method according to claim 1, characterized in that, The first transistor or the second transistor is any one of the following: Fin field-effect transistor, gate-all-around field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, crossbar transistor, and planar field-effect transistor.

12. A stacked transistor prepared by the preparation method according to any one of claims 1 to 11, characterized in that, Comprising: A first transistor; A second transistor, the first transistor and the second transistor are disposed back to back, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process; The first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned; the first gate structure is formed based on the first dummy gate structure; the second gate structure is formed based on the second dummy gate structure; Wherein, a gate isolation structure is formed between the first gate structure and the second gate structure, and the gate isolation structure is obtained by oxidizing a first part of the first dummy gate structure and / or a first part of the second dummy gate structure. The first part of the first dummy gate structure is a part of the first dummy gate structure close to the second dummy gate structure, and the first part of the second dummy gate structure is a part of the second dummy gate structure close to the first dummy gate structure.

13. A semiconductor device, characterized in that, Comprising: The stacked transistor according to claim 12.

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