A method for preparing a light-heat-isolated co-packaging structure and a co-packaging structure

Abstract

The present application provides a method for preparing a light-thermal isolation co-packaging structure and a co-packaging structure, which relate to the field of semiconductor technology, and include: obtaining a first adapter board required for packaging; determining a first position on the first adapter board where a heat-sensitive chip is to be placed, and preparing a heat-isolation structure around the first position, wherein the heat-isolation structure includes: a first through-hole structure and a second through-hole structure filled with polyparaxylene, wherein the distance between the first through-hole structure and the second through-hole structure is less than the first distance; defining a first interconnected metal electrode and a second interconnected metal electrode on a first surface of the first adapter board; burying a light-isolating chip in the first adapter board, and connecting the electrode of the light-isolating chip to the first interconnected metal electrode on the first surface; fixing the heat-sensitive chip at the first position, and connecting the heat-sensitive chip to the second interconnected metal electrode on the first surface by a wire bonding process, to obtain a heat-sensitive chip-light-isolating chip co-packaging structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a light-heat-isolated co-packaging structure and a co-packaging structure. Background Art

[0002] With the rapid development of high-speed optical communication technology, the miniaturization and high integration of optoelectronic devices have become key requirements, especially in the fields of optical fiber communication, data centers, 5G networks, etc. The efficient integration of optical emitting devices and optical detection devices is essential to achieve higher data transmission rates and more stable signal transmission. APD (Avalanche Photodiode) and VCSEL (Vertical-Cavity Surface-Emitting Laser) are common optoelectronic components and are widely used in high-speed optical communication and optical sensing systems.

[0003] However, light emitting devices and light detecting devices usually need to work in the same optical path system, which may cause optical interference (the laser emitted by the light emitting device may enter the light detecting device through scattering or reflection, generating optical noise, resulting in reduced detection accuracy of the light detecting device) and thermal interference (the heat generated by the light emitting device during operation is transferred to the light detecting device, causing the performance of the light detecting device to deteriorate), which in turn leads to the overall instability of the optical path system. Therefore, how to effectively integrate them and solve the problems of light and heat interference has become an important technical challenge facing the industry. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a method for preparing a light-heat-isolated co-packaging structure and a co-packaging structure, so as to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a method for preparing a light-heat-isolated co-packaging structure is provided, the method comprising:

[0006] Obtaining a first adapter plate required for packaging;

[0007] Determine a first position where the heat-sensitive chip is to be placed on the first adapter board, and prepare a thermal isolation structure around the first position, wherein the thermal isolation structure includes: a first through-hole structure and a second through-hole structure filled with polyparaxylene, wherein a distance between the first through-hole structure and the second through-hole structure is less than a first distance;

[0008] defining a first interconnect metal electrode and a second interconnect metal electrode on the first surface of the first interposer by photolithography-lift-off;

[0009] embedding an optical isolation chip in the first adapter plate, and connecting electrodes of the optical isolation chip to the first interconnecting metal electrodes on the first surface;

[0010] The heat sensitive chip is fixed at the first position, and the heat sensitive chip is connected to the second interconnected metal electrode on the first surface by a wire bonding process to obtain a heat sensitive chip-optical isolation chip co-packaging structure.

[0011] In a possible implementation manner, a thermal isolation structure is prepared around the first position, including:

[0012] Performing image etching around the first position on the first surface of the first adapter plate to obtain a first blind hole and a second blind hole, wherein the distance between the first blind hole and the second blind hole is less than the first distance; and the etching depth of the first blind hole and the second blind hole is greater than the thickness of the optical isolation chip;

[0013] Depositing polyparaxylene on the first surface of the first adapter plate so that the first blind hole and the second blind hole are completely filled with polyparaxylene;

[0014] Removing excess polyparaxylene on the first surface by oxygen plasma etching or chemical mechanical polishing;

[0015] The surface of the first adapter plate facing away from the first surface is thinned until the polyparaxylene in the first blind hole and the second blind hole is exposed, thereby obtaining the first through hole structure and the second through hole structure filled with polyparaxylene.

[0016] In a possible implementation, the method further includes:

[0017] The first adapter plate material between the first through-hole structure and the second through-hole structure is removed by etching.

[0018] In a possible implementation manner, embedding the optical isolation chip in the first adapter board includes:

[0019] Etching a chip embedding groove on the first surface of the first adapter plate, wherein the width of the chip embedding groove is 10-30 um greater than the width of the optical isolation chip;

[0020] embedding the optical isolation chip in the chip embedding groove;

[0021] The gap between the optical isolation chip and the chip buried groove is filled by depositing polyparaxylene or by dry film lamination process.

[0022] In a possible implementation, the method further includes:

[0023] Determine the position of the first interconnection metal electrode on the first surface; the position of the first interconnection metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the first interconnection metal electrode is farther from the heat-sensitive chip than the second through-hole structure;

[0024] The position of the second interconnected metal electrode on the first surface is determined; the position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the second interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure.

[0025] In a possible implementation manner, the first through-hole structure is at least 200 μm away from the thermal sensitive chip, and the second through-hole structure is farther away from the thermal sensitive chip than the first through-hole structure.

[0026] In a possible implementation, connecting the electrode of the optical isolation chip to the first interconnected metal electrode on the first surface includes:

[0027] The electrodes of the optical isolation chip are connected to the first interconnection metal electrodes on the first surface through a Damascene process.

[0028] The second aspect of the embodiment of the present application further provides a co-packaging structure, wherein the co-packaging structure is prepared by the method for preparing the light-heat-isolated co-packaging structure according to the first aspect of the embodiment of the present application;

[0029] The co-packaging structure comprises:

[0030] The first adapter board, the thermal sensitive chip and the optical isolation chip;

[0031] The heat sensitive chip is located at a first position on the first surface of the first adapter plate; a heat isolation structure is prepared around the heat sensitive chip, and the heat isolation structure includes: a first through hole structure and a second through hole structure filled with polyparaxylene, and the distance between the first through hole structure and the second through hole structure is less than the first distance;

[0032] The optical isolation chip is buried in the first adapter board;

[0033] The heat sensitive chip is connected to the second interconnected metal electrode on the first surface through a metal wire prepared by a wire bonding process, and the electrode of the optical isolation chip is connected to the first interconnected metal electrode on the first surface.

[0034] In a possible implementation manner, the position of the first interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; the first interconnected metal electrode is farther from the thermal sensitive chip than the second through-hole structure;

[0035] The position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; and the second interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure.

[0036] In a possible implementation manner, the first through-hole structure is at least 200 μm away from the thermal sensitive chip, and the second through-hole structure is farther away from the thermal sensitive chip than the first through-hole structure.

[0037] The embodiment of the present application provides a method for preparing a light-heat-isolation co-packaging structure, the method comprising: obtaining a first adapter board required for packaging; determining a first position on the first adapter board where a heat-sensitive chip is to be placed, and preparing a heat-isolation structure around the first position, the heat-isolation structure comprising: a first through-hole structure and a second through-hole structure filled with polyparaxylene, the distance between the first through-hole structure and the second through-hole structure being less than a first distance; defining a first interconnected metal electrode and a second interconnected metal electrode on the first surface of the first adapter board by photolithography-stripping; burying a light-isolation chip in the first adapter board, and connecting the electrode of the light-isolation chip to the first interconnected metal electrode on the first surface; fixing the heat-sensitive chip at the first position, and connecting the heat-sensitive chip to the second interconnected metal electrode on the first surface by a wire bonding process, to obtain a heat-sensitive chip-light-isolation chip co-packaging structure.

[0038] The present application provides a method for preparing a co-packaged structure of optical-thermal isolation. On the one hand, by preparing a thermal isolation structure (a first through-hole structure and a second through-hole structure filled with polyparaxylene, and the distance between the first through-hole structure and the second through-hole structure is less than the first distance) around the thermal sensitive chip, a double-layer polyparaxylene filling structure (the first through-hole structure and the second through-hole structure) is used to prevent the heat generated by the optical isolation chip from being conducted to the thermal sensitive chip; on the other hand, by burying the optical isolation chip in the first adapter plate (the chip embedding groove), the electrode of the optical isolation chip is connected to the first interconnected metal electrode on the first surface, thereby reducing the scattering or reflection of the laser emitted by the optical isolation chip and avoiding a decrease in detection accuracy. The embodiment of the present application realizes optical isolation and thermal isolation between the two chips while preparing a co-packaged structure of the optical isolation chip (light emitting device) and the thermal sensitive chip (light detection device), thereby reducing the impact of optical interference and thermal interference on system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 It is a flow chart of the steps of a method for preparing a light-heat-isolated co-packaging structure provided in an embodiment of the present application;

[0041] Figure 2 is a schematic structural diagram of a first adapter plate formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0042] Figure 3 is a schematic structural diagram of a thermal isolation structure formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0043] Figure 4 is a top view of a thermal isolation structure on a first adapter board provided in an embodiment of the present application;

[0044] Figure 5 is a schematic structural diagram of a blind hole formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0045] Figure 6 It is a schematic structural diagram of a blind hole filled with polyparaxylene material formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0046] Figure 7 is a structural schematic diagram of another thermal isolation structure provided in an embodiment of the present application;

[0047] Figure 8 is a schematic diagram of a photoresist formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0048] Fig. 9 is a schematic diagram of interconnected metal electrodes formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0049] Fig.10 It is a schematic structural diagram of a chip buried trench formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0050] Fig.11 is a schematic diagram of a first intermediate structure formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0051] Fig.12is a schematic diagram of a second intermediate structure formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0052] Fig.13 It is a schematic diagram of an optical isolation structure formed in a method for preparing a co-packaging structure provided in an embodiment of the present application;

[0053] Fig.14 This is a schematic diagram of a thermal sensitive chip-optical isolation chip co-packaging structure provided in an embodiment of the present application;

[0054] Description of the drawings: first adapter board 100, first through hole structure 101, second through hole structure 102, first blind hole 103, second blind hole 104, photoresist 105, first interconnected metal electrode 106, second interconnected metal electrode 107, chip buried groove 108, optical isolation chip 109, polyparaxylene layer 110, thermal sensitive chip 111. DETAILED DESCRIPTION

[0055] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0056] With the rapid development of high-speed optical communication technology, the miniaturization and high integration of optoelectronic devices have become key requirements, especially in the fields of optical fiber communication, data centers, 5G networks, etc. The efficient integration of optical emitting devices and optical detection devices is essential to achieve higher data transmission rates and more stable signal transmission. APD (avalanche photodiode) and VCSEL (vertical cavity surface emitting laser) are common optoelectronic components and are widely used in high-speed optical communication and optical sensing systems.

[0057] APD (Avalanche Photodiode) is a highly sensitive photodetector that can detect weak light signals. It has extremely high light sensitivity and gain, and can effectively detect signals in low light signal environments. Therefore, it is usually used in high-speed, long-distance fiber-optic communications. VCSEL (Vertical-Cavity Surface-Emitting Laser) is an efficient and compact light source that can emit lasers vertically. It is widely used in optical communication modules, optical interconnects, and sensing scenarios. The co-packaged structure of APD and VCSEL is used in high-speed optical communications to achieve efficient data transmission and reception.

[0058] At present, some packaging methods package APD and VCSEL separately, and then connect them through optical fiber or micro-optical path coupling. APD and VCSEL are each packaged in a separate module, and the optical signal is transmitted through optical fiber or optical waveguide components. However, the above discrete packaging scheme has the following problems: 1) Optical signal loss. Through optical fiber coupling, optical signals will be lost during transmission, especially under high-speed transmission conditions, signal attenuation will affect system performance. 2) Large system volume. The discrete packaging method increases the length of the optical path, and the overall volume of the system is large, which is not suitable for application scenarios that require miniaturization and high-density integration. 3) High packaging cost. Discrete packaging requires more optical coupling and debugging processes, resulting in higher manufacturing costs.

[0059] If a simple co-packaging solution is adopted to package the light emitting device (such as VCSEL) and the light detecting device (such as APD) in the same optical path system (the APD and VCSEL are co-packaged in one module, relying on the characteristics of the packaging material itself for simple physical isolation), there will be problems such as optical interference (the laser emitted by the light emitting device may generate optical noise by scattering or reflecting to the light receiving area of ​​the light detecting device, which will significantly affect the detection accuracy of the light detecting device, resulting in increased signal error or noise, and then causing the detection accuracy of the light detecting device to decrease) and thermal interference (the heat generated by the light emitting device during operation is transferred to the light detecting device, causing the performance of the light detecting device to decrease), which will lead to the overall performance of the optical path system being unstable. Therefore, how to effectively integrate them together and solve the problems of optical and thermal interference has become an important technical challenge facing the industry.

[0060] In view of the above problems, the embodiment of the present application proposes a method for preparing a co-packaging structure of optical-thermal isolation and a co-packaging structure, so as to achieve optical isolation and thermal isolation between the two chips while preparing a co-packaging structure of an optical isolation chip (light emitting device) and a thermal sensitive chip (light detection device), thereby reducing the impact of optical interference and thermal interference on system performance. In conjunction with the accompanying drawings, the method for preparing a co-packaging structure of optical-thermal isolation provided by the embodiment of the present application is described in detail through some embodiments and their application scenarios.

[0061] The first aspect of the present application provides a method for preparing a light-heat-isolated co-packaging structure, referring to Figure 1 , Figure 1 A flow chart of the steps of a method for preparing a light-heat-isolated co-packaging structure provided in an embodiment of the present application, such as Figure 1 As shown, the method includes:

[0062] Step S101, obtaining a first adapter plate required for packaging.

[0063] Specifically, first prepare the sheet, and select a transfer board substrate with a suitable material and size as the first transfer board according to the packaging requirements in the actual application process. Figure 2 , Figure 2 A schematic structural diagram of a first transfer board formed in a method for preparing a co-packaging structure is shown. Figure 2 As shown, the upper and lower surfaces of the first adapter board are the first surface and the second surface respectively. In the subsequent preparation of the co-package structure, the thermal sensitive chip and the optical isolation chip are placed on the side of the first surface. The first adapter board 100 can be a silicon-based adapter board.

[0064] Step S102, determining a first position on the first adapter board where the heat-sensitive chip is to be placed, and preparing a thermal isolation structure around the first position, wherein the thermal isolation structure includes: a first through-hole structure and a second through-hole structure filled with polyparaxylene, wherein the distance between the first through-hole structure and the second through-hole structure is less than the first distance.

[0065] In the embodiment of the present application, the heat sensitive chip refers to a light detection device, such as an APD (avalanche photodiode), which is used to receive a laser signal emitted by a light emitting device. The optical isolation chip refers to a light emitting device, such as a VCSEL (vertical cavity surface emitting laser), which is used to emit a laser signal.

[0066] In this embodiment, before installing the heat-sensitive chip, the position (first position) where the heat-sensitive chip is placed on the first surface is predetermined, so that the position of the heat-isolating structure to be prepared is determined according to the first position, that is, the heat-isolating structure is prepared around the first position so that the heat-isolating structure surrounds the heat-sensitive chip to isolate heat conduction. Figure 3 , Figure 3 A schematic diagram of the structure of a thermal isolation structure formed in a method for preparing a co-packaging structure is shown. Figure 3 As shown, the thermal isolation structure is a double-layer isolation structure composed of a first through-hole structure and a second through-hole structure, wherein the first through-hole structure 101 is an inner layer and the second through-hole structure 102 is an outer layer. The first through-hole structure 101 and the second through-hole structure 102 are through-hole structures filled with polyparaxylene material, and the distance between the two is less than the first distance (for example, 10 μm), forming a Figure 3 The thermal isolation layer shown is polyparaxylene-adapter plate material (eg, silicon-based material)-polyparaxylene. The specific value of the first distance can be set according to actual process requirements.

[0067] In a possible implementation, the first through-hole structure is at least 200 μm away from the thermal-sensitive chip, and the second through-hole structure is farther away from the thermal-sensitive chip than the first through-hole structure. That is, the position of the first through-hole structure is first determined at a distance of at least 200 μm from the first position according to the first position of the thermal-sensitive chip, and then the position of the second through-hole structure is determined according to the position of the first through-hole structure and the first distance.

[0068] Reference Figure 4 , Figure 4 A top view of a thermal isolation structure on a first adapter plate is shown. Figure 4 As shown, in this embodiment, the prepared thermal isolation structure can be formed into a ring around the first position (thermal sensitive chip) (at least 200μm away), and an inner ring composed of a first through-hole structure and an outer ring composed of a second through-hole structure are formed at least 200μm away from the first position (thermal sensitive chip), thereby realizing a thermal isolation design. The specific shapes of the first through-hole structure and the second through-hole structure in the thermal isolation structure are not limited in the embodiment of the present application. For example, the first through-hole structure and the second through-hole structure can be Figure 4 The ring shape shown.

[0069] VCSEL generates a certain amount of heat when working, especially when running at high power, the temperature may rise significantly. As a highly sensitive light detector, APD is very sensitive to temperature, and temperature changes will affect its gain, response speed and noise characteristics. If heat is transferred to APD, its performance will be reduced, which will manifest as problems such as reduced detection efficiency, longer response time, and increased dark current. The design of the thermal isolation structure proposed in the embodiment of the present application (such as Figure 3 As shown in the figure, effective thermal management can be achieved by using materials with low thermal conductivity (polyparaxylene) or dedicated thermal isolation areas to prevent the heat generated by the VCSEL from being transferred to the APD. This can not only improve the stability of the APD, but also extend the service life of the entire optoelectronic system.

[0070] In a possible implementation manner, step S102, preparing a thermal isolation structure around the first position, includes:

[0071] Step S1021, performing image etching around the first position on the first surface of the first adapter plate to obtain a first blind hole and a second blind hole, wherein the distance between the first blind hole and the second blind hole is less than the first distance; and the etching depth of the first blind hole and the second blind hole is greater than the thickness of the optical isolation chip.

[0072] Specifically, refer to Figure 5 , Figure 5A schematic diagram of the structure of a blind hole formed in a method for preparing a co-packaging structure is shown. Figure 5 As shown, pattern etching is performed around the predefined area where the thermal sensitive chip (APD) is to be placed to obtain a first blind hole 103 and a second blind hole 104. The position of the first blind hole is the position of the first through-hole structure, and the position of the second blind hole is the position of the second through-hole structure. The first blind hole is located in the inner layer, and the second blind hole is located in the outer layer, so that the first blind hole is closer to the first position. The etching depth of the first blind hole and the second blind hole is greater than the thickness of the optical isolation chip, that is, the overall thickness of the buried trench of the optical isolation chip (VSCEL).

[0073] Step S1022, depositing Parylene on the first surface of the first adapter plate, so that the first blind hole and the second blind hole are completely filled with Parylene. Specifically, the deposition thickness should be greater than half of the width of the blind hole pattern.

[0074] Step S1023, removing excess polyparaxylene on the first surface by oxygen plasma etching or chemical mechanical polishing (CMP).

[0075] Reference Figure 6 , Figure 6 FIG. 1 shows a schematic diagram of a structure of a blind hole filled with polyparaxylene material formed in a method for preparing a co-packaging structure. Figure 6 As shown, the deposited polyparaxylene material will not only fill the first blind hole and the second blind hole, but also cause excess polyparaxylene material to be present on the first surface. The polyparaxylene material on the first surface is selectively removed by oxygen plasma etching or chemical mechanical polishing (CMP) to obtain the first blind hole and the second blind hole filled with polyparaxylene.

[0076] Step S1024, thinning the surface of the first adapter plate away from the first surface until the polyparaxylene in the first blind hole and the second blind hole is exposed, thereby obtaining the first through hole structure and the second through hole structure filled with polyparaxylene.

[0077] Specifically, the back side of the first adapter plate is thinned, and a multi-step thinning method can be used to thin the surface of the first adapter plate away from the first surface (i.e., the second surface) until the polyparaxylene material in the first blind hole and the second blind hole is exposed to obtain a thermal isolation structure (a first through-hole structure and a second through-hole structure). Figure 3 As shown, the thermal isolation structure includes: a first through-hole structure 101 and a second through-hole structure 102. In this case, the thinned first adapter plate 100 and the first through-hole structure 101 and the second through-hole structure 102 embedded in the first adapter plate have the same height.

[0078] In a possible implementation, the method further includes:

[0079] The first adapter plate material between the first through-hole structure and the second through-hole structure is removed by etching.

[0080] Specifically, in this embodiment, there are two possibilities for the prepared thermal isolation structure:

[0081] A thermal isolation structure is a thermal isolation structure in which a thermal isolation layer such as polyparaxylene-adapter board material-polyparaxylene is prepared through steps S1021-S1024 as a thermal isolation structure. Figure 3 As shown, the remaining transfer board substrate of the first transfer board is between the first through hole structure and the second through hole structure.

[0082] Reference Figure 7 , Figure 7 A schematic diagram of another thermal isolation structure is shown. Figure 7 As shown, another case is that after executing step S1024, the first adapter plate is etched again to remove the silicon groove (i.e., the first adapter plate material) between the first through-hole structure and the second through-hole structure, and form a thermal isolation layer such as polyparaxylene-air-polyparaxylene as a thermal isolation structure. Thus, the lower thermal conductivity of air is utilized to further improve the thermal insulation effect of the thermal isolation structure.

[0083] Step S103 , defining a first interconnect metal electrode and a second interconnect metal electrode on the first surface of the first adapter plate by photolithography-stripping.

[0084] In this embodiment, the interconnected metal electrodes can be defined on the first surface by photolithography-stripping. Specifically, the pattern is first defined on the first surface by photoresist. Figure 8 , Figure 8 A schematic diagram of a photoresist formed in a method for preparing a co-encapsulation structure is shown, Figure 8 As shown, the electrode pattern is defined on the first surface by using the photoresist 105, and the area not covered by the photoresist 105 on the first surface is the location of the first interconnection metal electrode and the second interconnection metal electrode. Figure 8 The photoresist pattern shown is only an example, and the pattern defined by the photoresist can be set according to actual application requirements, which is not limited in this embodiment.

[0085] When using photoresist to define the electrode pattern, it is necessary to predetermine the position of each interconnected metal electrode on the first surface. In a possible implementation, the method further includes:

[0086] Determine the position of the first interconnected metal electrode on the first surface; the position of the first interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the first interconnected metal electrode is farther from the thermal sensitive chip than the second through-hole structure. Determine the position of the second interconnected metal electrode on the first surface; the position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the second interconnected metal electrode is farther from the thermal sensitive chip than the second through-hole structure.

[0087] Reference Fig. 9 , Fig. 9 A schematic diagram of interconnected metal electrodes formed in a method for preparing a co-packaging structure is shown, Fig. 9 As shown, according to the electrode pattern defined by the photoresist, a first interconnecting metal electrode 106 and a second interconnecting metal electrode 107 are prepared on the first surface, and the photoresist material on the first surface is removed. The first interconnecting metal electrode is used to connect the optical isolation chip, and the second interconnecting metal electrode is used to connect the thermal sensitive chip. Whether the first interconnecting metal electrode 106 and the second interconnecting metal electrode 107 are connected can be determined according to the actual process requirements. It should be noted that in this embodiment Fig. 9 The first interconnect metal electrode and the second interconnect metal electrode shown in the figure are only examples. The first interconnect metal electrode and the second interconnect metal electrode may be configured according to actual application requirements, and this embodiment does not limit them.

[0088] Step S104: embedding an optical isolation chip in the first adapter plate, and connecting electrodes of the optical isolation chip to the first interconnecting metal electrodes on the first surface.

[0089] The optical signal interference problem of the existing co-packaging technology mainly stems from the fact that the scattered light and reflected light in the packaging structure are not fully isolated. Especially in a simple co-packaging design, the light of the VCSEL may directly irradiate or reflect to the detection area of ​​the APD. Even if a multi-layer package is used, the complex optical path can easily cause scattered light to affect the detection accuracy of the APD. The embodiment of the present application utilizes a special optical isolation design to bury the VSCEL in the optical isolation structure in the silicon cavity (in the chip embedding groove of the first adapter board), effectively blocking the scattered light or other interfering light from the VCSEL, simplifying the optical path inside the package, and avoiding light reflection and scattering, thereby ensuring that the APD only receives the target optical signal and improving the accuracy and reliability of detection.

[0090] In a possible implementation manner, embedding the optical isolation chip in the first adapter board includes:

[0091] Step S1041, etching a chip embedding groove on the first surface of the first adapter plate, wherein the width of the chip embedding groove is 10-30 um greater than the width of the optical isolation chip.

[0092] Reference Fig.10 , Fig.10 A schematic diagram of the structure of a chip buried groove formed in a method for preparing a co-packaging structure is shown. Fig.10 As shown, according to the size of the optical isolation chip to be buried, a chip embedding groove 108 is prepared by etching on the first surface of the first adapter plate 100. Among them, the position of the chip embedding groove 108 (that is, the position of the optical isolation chip) can be determined according to the actual application requirements, and is not limited in this embodiment. In this embodiment, the height (that is, the depth) of the chip embedding groove is the same as the height of the optical isolation chip, and the width of the chip embedding groove is 10-30um longer than the width of the optical isolation chip. In order to ensure that the first chip can be accurately placed in the embedding groove, a certain width can be reserved when etching the chip embedding groove, that is, the chip embedding groove is designed to be 10-30um wider than the optical isolation chip.

[0093] Step S1042, embed the optical isolation chip in the chip embedding groove. Specifically, the optical isolation chip can be bonded to the bottom of the chip embedding groove by using a DAF film or other bonding adhesive. Fig.11 , Fig.11 A schematic diagram of a first intermediate structure formed in a method for preparing a co-packaging structure is shown. Fig.11 As shown, an optical isolation chip 109 is placed in the chip buried groove 108 .

[0094] Step S1043, filling the gap between the optical isolation chip and the chip buried groove by depositing polyparaxylene or dry film lamination process.

[0095] Specifically, since the etched chip embedding groove is wider than the optical isolation chip, there is a gap between the optical isolation chip and the chip embedding groove. In this embodiment, a layer of polyparaxylene can be deposited on the first surface by room temperature chemical vapor deposition (or dry film lamination process) so that the polyparaxylene film completely fills the gap between the optical isolation chip and the inner wall of the chip embedding groove (that is, the thickness of the polyparaxylene film should be greater than the maximum value of the gap between the optical isolation chip and the chip embedding groove). Fig.12 , Fig.12 A schematic diagram of a second intermediate structure formed in a method for preparing a co-packaging structure is shown. Fig.12As shown, an optical isolation chip 109 is placed in the chip embedding groove 108, and polyparaxylene is filled in the gap between the optical isolation chip 109 and the chip embedding groove 108. In order to make the polyparaxylene material completely fill the gap in the chip embedding groove, a polyparaxylene layer 110 of a certain thickness is deposited on the first surface.

[0096] Then, the electrodes on the optical isolation chip 109 are connected to the first interconnected metal electrodes 106 on the first surface, and then the excess polyparaxylene material on the first surface is removed by etching (for example, oxygen plasma etching). Fig.13 , Fig.13 A schematic diagram of an optical isolation structure formed in a method for preparing a co-packaging structure is shown. Fig.13 As shown, an optical isolation chip 109 is placed in the chip buried groove 108, and the electrodes on the optical isolation chip 109 are interconnected with the first interconnection metal electrodes 106 on the first surface.

[0097] In a possible implementation, connecting the electrode of the optical isolation chip to the first interconnected metal electrode on the first surface includes:

[0098] The electrodes of the optical isolation chip are connected to the first interconnection metal electrodes on the first surface through a Damascene process.

[0099] In the existing co-packaging solution, the laser emitted by the VCSEL may be scattered or reflected to the light receiving area of ​​the APD, generating optical noise. This interference will significantly affect the detection accuracy of the APD, resulting in increased signal error or noise. In order to solve the above-mentioned optical interference problem, the embodiment of the present application effectively blocks the scattered light or other interference light from the VCSEL by burying the VSCEL in the optical isolation structure in the silicon cavity (in the chip embedding groove of the first adapter board), thereby ensuring that the APD only receives the target optical signal and improving the accuracy and reliability of detection.

[0100] Step S105 , fixing the heat sensitive chip at the first position, and connecting the heat sensitive chip to the second interconnected metal electrodes on the first surface by a wire bonding process to obtain a heat sensitive chip-optical isolation chip co-packaging structure.

[0101] Reference Fig.14 , Fig.14 A schematic diagram of a thermal sensitive chip-optical isolation chip co-packaging structure is shown. Fig.14As shown, the electrode of the heat-sensitive chip 111 is connected to the second interconnected metal electrode 107 on the first surface by a wire bonding process. The thermal isolation structure (the first through-hole structure 101 and the second through-hole structure 102) separates the optical isolation chip 109 from the heat-sensitive chip 111, so that the heat generated by the optical isolation chip will not be transferred to the heat-sensitive chip, thereby improving the stability of system performance.

[0102] In the embodiment of the present application, a co-package structure of a thermal sensitive chip and an optical isolation chip is prepared according to the above method (steps S101-S105), that is, APD-VSCEL co-package is realized. The beneficial effects of the co-package structure are: 1. Improving integration and reducing device volume: By co-packaging APD and VCSEL, the number of discrete components in the optoelectronic communication system can be significantly reduced, and the volume and weight of the overall device can be reduced. This highly integrated design is particularly important for modern communication equipment (such as 5G base stations, optical fiber transmission modules, etc.), which helps to improve the integration of the system. 2. Improving system performance: The co-package structure can shorten the optical transmission distance between the optical emitting device (VCSEL) and the optical detection device (APD), reduce signal loss, and improve the response speed of the system and the reliability of signal transmission. At the same time, through optical isolation and thermal isolation technology, the detection accuracy of APD and the luminous stability of VCSEL can be improved. 3. Reducing production costs and simplifying processes: In the manufacturing process, co-packaging APD and VCSEL can reduce the complex process of separate packaging and reduce material and manufacturing costs. In addition, the co-package structure simplifies the optical path design, reduces the difficulty of system debugging, and helps improve production efficiency. 4. Support high-speed optical communication and optical sensing: This co-package structure is particularly suitable for high-speed optical communication systems, such as data centers, 5G networks, etc., and can provide an efficient and stable combination of light sources and detectors during high-speed transmission. At the same time, it can also be used in the field of optical sensing, such as laser radar, medical imaging and other high-precision scenarios.

[0103] The second aspect of the embodiment of the present application further provides a co-packaging structure, wherein the co-packaging structure is prepared by the method for preparing the light-heat-isolated co-packaging structure according to the first aspect of the embodiment of the present application;

[0104] like Fig.14 As shown, the co-packaging structure includes:

[0105] The first adapter board, the thermal sensitive chip and the optical isolation chip;

[0106] The heat sensitive chip is located at a first position on the first surface of the first adapter plate; a heat isolation structure is prepared around the heat sensitive chip, and the heat isolation structure includes: a first through hole structure and a second through hole structure filled with polyparaxylene, and the distance between the first through hole structure and the second through hole structure is less than the first distance;

[0107] The optical isolation chip is buried in the first adapter board;

[0108] The heat sensitive chip is connected to the second interconnected metal electrode on the first surface through a metal wire prepared by a wire bonding process, and the electrode of the optical isolation chip is connected to the first interconnected metal electrode on the first surface.

[0109] In a possible implementation manner, the position of the first interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; the first interconnected metal electrode is farther from the thermal sensitive chip than the second through-hole structure;

[0110] The position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; and the second interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure.

[0111] In a possible implementation manner, the first through-hole structure is at least 200 μm away from the thermal sensitive chip, and the second through-hole structure is farther away from the thermal sensitive chip than the first through-hole structure.

[0112] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0113] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0116] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0117] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0118] The above is a detailed introduction to the preparation method of a light-thermal isolation co-packaging structure and a co-packaging structure provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing a light-heat-isolated co-packaging structure, characterized in that: The method comprises: Obtaining a first adapter plate required for packaging; Determine a first position where the heat-sensitive chip is to be placed on the first adapter board, and prepare a thermal isolation structure around the first position, wherein the thermal isolation structure includes: a first through-hole structure and a second through-hole structure filled with polyparaxylene, wherein the distance between the first through-hole structure and the second through-hole structure is less than the first distance; the thermal isolation structure is surrounded in a ring shape, wherein the first through-hole structure constitutes an inner ring, and the second through-hole structure constitutes an outer ring; defining a first interconnect metal electrode and a second interconnect metal electrode on the first surface of the first interposer by photolithography-lift-off; embedding an optical isolation chip in the chip embedding groove of the first adapter plate, and connecting the electrode of the optical isolation chip to the first interconnecting metal electrode on the first surface; The heat sensitive chip is fixed on the first position of the first surface, and the heat sensitive chip is connected to the second interconnected metal electrode on the first surface by a wire bonding process to obtain a heat sensitive chip-optical isolation chip co-package structure; wherein the optical isolation chip is a light emitting device VCSEL, which is used to emit a laser signal; and the heat sensitive chip is a light detection device APD, which is used to receive the laser signal emitted by the light emitting device; A thermal insulation structure is prepared around the first position, comprising: Performing image etching around the first position on the first surface of the first adapter plate to obtain a first blind hole and a second blind hole, wherein the distance between the first blind hole and the second blind hole is less than the first distance; and the etching depth of the first blind hole and the second blind hole is greater than the thickness of the optical isolation chip; Depositing polyparaxylene on the first surface of the first adapter plate so that the first blind hole and the second blind hole are completely filled with polyparaxylene; Removing excess polyparaxylene on the first surface by oxygen plasma etching or chemical mechanical polishing; Thinning the surface of the first adapter plate on the side away from the first surface until the poly-para-xylene in the first blind hole and the second blind hole is exposed, thereby obtaining the first through-hole structure and the second through-hole structure filled with poly-para-xylene; The method further comprises: The first adapter plate material between the first through-hole structure and the second through-hole structure is removed by etching to form a polyparaxylene-air-polyparaxylene thermal isolation layer as the thermal isolation structure.

2. The method for preparing a co-packaging structure according to claim 1, characterized in that: The step of embedding the optical isolation chip into the chip embedding groove of the first adapter board comprises: Etching the chip embedding groove on the first surface of the first adapter plate, wherein the width of the chip embedding groove is 10-30 um greater than the width of the optical isolation chip; embedding the optical isolation chip in the chip embedding groove; The gap between the optical isolation chip and the chip buried groove is filled by depositing polyparaxylene or by dry film lamination process.

3. The method for preparing a co-packaging structure according to claim 1, characterized in that: The method further comprises: Determine the position of the first interconnection metal electrode on the first surface; the position of the first interconnection metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the first interconnection metal electrode is farther from the heat-sensitive chip than the second through-hole structure; The position of the second interconnected metal electrode on the first surface is determined; the position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure, and the second interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure.

4. The method for preparing a co-packaging structure according to claim 1, characterized in that: The first through-hole structure is at least 200 μm away from the thermal-sensitive chip, and the second through-hole structure is farther away from the thermal-sensitive chip than the first through-hole structure.

5. The method for preparing a co-packaging structure according to claim 1, characterized in that: Connecting the electrode of the optical isolation chip to the first interconnect metal electrode on the first surface comprises: The electrodes of the optical isolation chip are connected to the first interconnection metal electrodes on the first surface through a Damascene process.

6. A co-packaging structure, characterized in that: The co-packaging structure is prepared by the method for preparing a light-heat-isolated co-packaging structure according to any one of claims 1 to 5; The co-packaging structure comprises: The first adapter board, the thermal sensitive chip and the optical isolation chip; The heat-sensitive chip is located at a first position on the first surface of the first adapter plate; a heat-insulating structure is prepared around the heat-sensitive chip, and the heat-insulating structure includes: a first through-hole structure and a second through-hole structure filled with polyparaxylene, and the distance between the first through-hole structure and the second through-hole structure is less than the first distance; the heat-insulating structure is surrounded in a ring shape, the first through-hole structure constitutes an inner ring, and the second through-hole structure constitutes an outer ring; The optical isolation chip is buried in the first adapter board; The heat sensitive chip is connected to the second interconnected metal electrode on the first surface through a metal wire prepared by a wire bonding process, and the electrode of the optical isolation chip is connected to the first interconnected metal electrode on the first surface; Wherein, the thermal isolation structure is a thermal isolation layer of polyparaxylene-air-polyparaxylene.

7. The co-packaging structure according to claim 6, characterized in that: The position of the first interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; the first interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure; The position of the second interconnected metal electrode does not overlap with the position of the first through-hole structure or the second through-hole structure; and the second interconnected metal electrode is farther from the heat-sensitive chip than the second through-hole structure.

8. The co-packaging structure according to claim 6, characterized in that: The first through-hole structure is at least 200 μm away from the thermal-sensitive chip, and the second through-hole structure is farther away from the thermal-sensitive chip than the first through-hole structure.

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